src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/u_slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define ATI_VENDOR_ID 0x1002
  47
  48 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  49 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  50 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  51
  52 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  53 /* Pipeline & streamout query controls. */
  54 #define R600_CONTEXT_START_PIPELINE_STATS       (1u << 1)
  55 #define R600_CONTEXT_STOP_PIPELINE_STATS        (1u << 2)
  56 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 3)
  57
  58 /* special primitive types */
  59 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  60
  61 /* Debug flags. */
  62 /* logging */
  63 #define DBG_TEX                 (1 << 0)
  64 /* gap - reuse */
  65 #define DBG_COMPUTE             (1 << 2)
  66 #define DBG_VM                  (1 << 3)
  67 /* gap - reuse */
  68 /* shader logging */
  69 #define DBG_FS                  (1 << 5)
  70 #define DBG_VS                  (1 << 6)
  71 #define DBG_GS                  (1 << 7)
  72 #define DBG_PS                  (1 << 8)
  73 #define DBG_CS                  (1 << 9)
  74 #define DBG_TCS                 (1 << 10)
  75 #define DBG_TES                 (1 << 11)
  76 #define DBG_NO_IR               (1 << 12)
  77 #define DBG_NO_TGSI             (1 << 13)
  78 #define DBG_NO_ASM              (1 << 14)
  79 #define DBG_PREOPT_IR           (1 << 15)
  80 /* Bits 21-31 are reserved for the r600g driver. */
  81 /* features */
  82 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  83 #define DBG_NO_HYPERZ           (1llu << 33)
  84 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  85 #define DBG_NO_2D_TILING        (1llu << 35)
  86 #define DBG_NO_TILING           (1llu << 36)
  87 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  88 #define DBG_FORCE_DMA           (1llu << 38)
  89 #define DBG_PRECOMPILE          (1llu << 39)
  90 #define DBG_INFO                (1llu << 40)
  91 #define DBG_NO_WC               (1llu << 41)
  92 #define DBG_CHECK_VM            (1llu << 42)
  93 #define DBG_NO_DCC              (1llu << 43)
  94 #define DBG_NO_DCC_CLEAR        (1llu << 44)
  95 #define DBG_NO_RB_PLUS          (1llu << 45)
  96 #define DBG_SI_SCHED            (1llu << 46)
  97 #define DBG_MONOLITHIC_SHADERS  (1llu << 47)
  98
  99 #define R600_MAP_BUFFER_ALIGNMENT 64
 100
 101 struct r600_common_context;
 102 struct r600_perfcounters;
 103
 104 struct radeon_shader_reloc {
 105         char name[32];
 106         uint64_t offset;
 107 };
 108
 109 struct radeon_shader_binary {
 110         /** Shader code */
 111         unsigned char *code;
 112         unsigned code_size;
 113
 114         /** Config/Context register state that accompanies this shader.
 115          * This is a stream of dword pairs.  First dword contains the
 116          * register address, the second dword contains the value.*/
 117         unsigned char *config;
 118         unsigned config_size;
 119
 120         /** The number of bytes of config information for each global symbol.
 121          */
 122         unsigned config_size_per_symbol;
 123
 124         /** Constant data accessed by the shader.  This will be uploaded
 125          * into a constant buffer. */
 126         unsigned char *rodata;
 127         unsigned rodata_size;
 128
 129         /** List of symbol offsets for the shader */
 130         uint64_t *global_symbol_offsets;
 131         unsigned global_symbol_count;
 132
 133         struct radeon_shader_reloc *relocs;
 134         unsigned reloc_count;
 135
 136         /** Disassembled shader in a string. */
 137         char *disasm_string;
 138 };
 139
 140 void radeon_shader_binary_init(struct radeon_shader_binary *b);
 141 void radeon_shader_binary_clean(struct radeon_shader_binary *b);
 142
 143 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
 144  * at the moment.
 145  */
 146 struct r600_resource {
 147         struct u_resource               b;
 148
 149         /* Winsys objects. */
 150         struct pb_buffer                *buf;
 151         uint64_t                        gpu_address;
 152
 153         /* Resource state. */
 154         enum radeon_bo_domain           domains;
 155
 156         /* The buffer range which is initialized (with a write transfer,
 157          * streamout, DMA, or as a random access target). The rest of
 158          * the buffer is considered invalid and can be mapped unsynchronized.
 159          *
 160          * This allows unsychronized mapping of a buffer range which hasn't
 161          * been used yet. It's for applications which forget to use
 162          * the unsynchronized map flag and expect the driver to figure it out.
 163          */
 164         struct util_range               valid_buffer_range;
 165
 166         /* For buffers only. This indicates that a write operation has been
 167          * performed by TC L2, but the cache hasn't been flushed.
 168          * Any hw block which doesn't use or bypasses TC L2 should check this
 169          * flag and flush the cache before using the buffer.
 170          *
 171          * For example, TC L2 must be flushed if a buffer which has been
 172          * modified by a shader store instruction is about to be used as
 173          * an index buffer. The reason is that VGT DMA index fetching doesn't
 174          * use TC L2.
 175          */
 176         bool                            TC_L2_dirty;
 177
 178         /* Whether the resource has been exported via resource_get_handle. */
 179         bool                            is_shared;
 180         unsigned                        external_usage; /* PIPE_HANDLE_USAGE_* */
 181 };
 182
 183 struct r600_transfer {
 184         struct pipe_transfer            transfer;
 185         struct r600_resource            *staging;
 186         unsigned                        offset;
 187 };
 188
 189 struct r600_fmask_info {
 190         uint64_t offset;
 191         uint64_t size;
 192         unsigned alignment;
 193         unsigned pitch_in_pixels;
 194         unsigned bank_height;
 195         unsigned slice_tile_max;
 196         unsigned tile_mode_index;
 197 };
 198
 199 struct r600_cmask_info {
 200         uint64_t offset;
 201         uint64_t size;
 202         unsigned alignment;
 203         unsigned pitch;
 204         unsigned height;
 205         unsigned xalign;
 206         unsigned yalign;
 207         unsigned slice_tile_max;
 208         unsigned base_address_reg;
 209 };
 210
 211 struct r600_htile_info {
 212         unsigned pitch;
 213         unsigned height;
 214         unsigned xalign;
 215         unsigned yalign;
 216 };
 217
 218 struct r600_texture {
 219         struct r600_resource            resource;
 220
 221         uint64_t                        size;
 222         bool                            is_depth;
 223         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 224         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 225         struct r600_texture             *flushed_depth_texture;
 226         boolean                         is_flushing_texture;
 227         struct radeon_surf              surface;
 228
 229         /* Colorbuffer compression and fast clear. */
 230         struct r600_fmask_info          fmask;
 231         struct r600_cmask_info          cmask;
 232         struct r600_resource            *cmask_buffer;
 233         uint64_t                        dcc_offset; /* 0 = disabled */
 234         unsigned                        cb_color_info; /* fast clear enable bit */
 235         unsigned                        color_clear_value[2];
 236
 237         /* Depth buffer compression and fast clear. */
 238         struct r600_htile_info          htile;
 239         struct r600_resource            *htile_buffer;
 240         bool                            depth_cleared; /* if it was cleared at least once */
 241         float                           depth_clear_value;
 242         bool                            stencil_cleared; /* if it was cleared at least once */
 243         uint8_t                         stencil_clear_value;
 244
 245         bool                            non_disp_tiling; /* R600-Cayman only */
 246 };
 247
 248 struct r600_surface {
 249         struct pipe_surface             base;
 250
 251         bool color_initialized;
 252         bool depth_initialized;
 253
 254         /* Misc. color flags. */
 255         bool alphatest_bypass;
 256         bool export_16bpc;
 257         bool color_is_int8;
 258
 259         /* Color registers. */
 260         unsigned cb_color_info;
 261         unsigned cb_color_base;
 262         unsigned cb_color_view;
 263         unsigned cb_color_size;         /* R600 only */
 264         unsigned cb_color_dim;          /* EG only */
 265         unsigned cb_color_pitch;        /* EG and later */
 266         unsigned cb_color_slice;        /* EG and later */
 267         unsigned cb_dcc_base;           /* VI and later */
 268         unsigned cb_color_attrib;       /* EG and later */
 269         unsigned cb_dcc_control;        /* VI and later */
 270         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 271         unsigned cb_color_fmask_slice;  /* EG and later */
 272         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 273         unsigned cb_color_mask;         /* R600 only */
 274         unsigned spi_shader_col_format;         /* SI+, no blending, no alpha-to-coverage. */
 275         unsigned spi_shader_col_format_alpha;   /* SI+, alpha-to-coverage */
 276         unsigned spi_shader_col_format_blend;   /* SI+, blending without alpha. */
 277         unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
 278         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 279         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 280
 281         /* DB registers. */
 282         unsigned db_depth_info;         /* R600 only, then SI and later */
 283         unsigned db_z_info;             /* EG and later */
 284         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 285         unsigned db_depth_view;
 286         unsigned db_depth_size;
 287         unsigned db_depth_slice;        /* EG and later */
 288         unsigned db_stencil_base;       /* EG and later */
 289         unsigned db_stencil_info;       /* EG and later */
 290         unsigned db_prefetch_limit;     /* R600 only */
 291         unsigned db_htile_surface;
 292         unsigned db_htile_data_base;
 293         unsigned db_preload_control;    /* EG and later */
 294         unsigned pa_su_poly_offset_db_fmt_cntl;
 295 };
 296
 297 struct r600_common_screen {
 298         struct pipe_screen              b;
 299         struct radeon_winsys            *ws;
 300         enum radeon_family              family;
 301         enum chip_class                 chip_class;
 302         struct radeon_info              info;
 303         uint64_t                        debug_flags;
 304         bool                            has_cp_dma;
 305         bool                            has_streamout;
 306
 307         /* Auxiliary context. Mainly used to initialize resources.
 308          * It must be locked prior to using and flushed before unlocking. */
 309         struct pipe_context             *aux_context;
 310         pipe_mutex                      aux_context_lock;
 311
 312         /* This must be in the screen, because UE4 uses one context for
 313          * compilation and another one for rendering.
 314          */
 315         unsigned                        num_compilations;
 316         /* Along with ST_DEBUG=precompile, this should show if applications
 317          * are loading shaders on demand. This is a monotonic counter.
 318          */
 319         unsigned                        num_shaders_created;
 320
 321         /* GPU load thread. */
 322         pipe_mutex                      gpu_load_mutex;
 323         pipe_thread                     gpu_load_thread;
 324         unsigned                        gpu_load_counter_busy;
 325         unsigned                        gpu_load_counter_idle;
 326         volatile unsigned               gpu_load_stop_thread; /* bool */
 327
 328         char                            renderer_string[64];
 329
 330         /* Performance counters. */
 331         struct r600_perfcounters        *perfcounters;
 332
 333         /* If pipe_screen wants to re-emit the framebuffer state of all
 334          * contexts, it should atomically increment this. Each context will
 335          * compare this with its own last known value of the counter before
 336          * drawing and re-emit the framebuffer state accordingly.
 337          */
 338         unsigned                        dirty_fb_counter;
 339
 340         /* Atomically increment this counter when an existing texture's
 341          * metadata is enabled or disabled in a way that requires changing
 342          * contexts' compressed texture binding masks.
 343          */
 344         unsigned                        compressed_colortex_counter;
 345
 346         void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
 347                                       struct r600_texture *rtex,
 348                                       struct radeon_bo_metadata *md);
 349 };
 350
 351 /* This encapsulates a state or an operation which can emitted into the GPU
 352  * command stream. */
 353 struct r600_atom {
 354         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 355         unsigned                num_dw;
 356         unsigned short          id;
 357 };
 358
 359 struct r600_so_target {
 360         struct pipe_stream_output_target b;
 361
 362         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 363         struct r600_resource    *buf_filled_size;
 364         unsigned                buf_filled_size_offset;
 365         bool                    buf_filled_size_valid;
 366
 367         unsigned                stride_in_dw;
 368 };
 369
 370 struct r600_streamout {
 371         struct r600_atom                begin_atom;
 372         bool                            begin_emitted;
 373         unsigned                        num_dw_for_end;
 374
 375         unsigned                        enabled_mask;
 376         unsigned                        num_targets;
 377         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 378
 379         unsigned                        append_bitmask;
 380         bool                            suspended;
 381
 382         /* External state which comes from the vertex shader,
 383          * it must be set explicitly when binding a shader. */
 384         unsigned                        *stride_in_dw;
 385         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 386
 387         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 388         unsigned                        hw_enabled_mask;
 389
 390         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 391         struct r600_atom                enable_atom;
 392         bool                            streamout_enabled;
 393         bool                            prims_gen_query_enabled;
 394         int                             num_prims_gen_queries;
 395 };
 396
 397 struct r600_ring {
 398         struct radeon_winsys_cs         *cs;
 399         void (*flush)(void *ctx, unsigned flags,
 400                       struct pipe_fence_handle **fence);
 401 };
 402
 403 struct r600_common_context {
 404         struct pipe_context b; /* base class */
 405
 406         struct r600_common_screen       *screen;
 407         struct radeon_winsys            *ws;
 408         struct radeon_winsys_ctx        *ctx;
 409         enum radeon_family              family;
 410         enum chip_class                 chip_class;
 411         struct r600_ring                gfx;
 412         struct r600_ring                dma;
 413         struct pipe_fence_handle        *last_sdma_fence;
 414         unsigned                        initial_gfx_cs_size;
 415         unsigned                        gpu_reset_counter;
 416         unsigned                        last_dirty_fb_counter;
 417         unsigned                        last_compressed_colortex_counter;
 418
 419         struct u_upload_mgr             *uploader;
 420         struct u_suballocator           *allocator_so_filled_size;
 421         struct util_slab_mempool        pool_transfers;
 422
 423         /* Current unaccounted memory usage. */
 424         uint64_t                        vram;
 425         uint64_t                        gtt;
 426
 427         /* States. */
 428         struct r600_streamout           streamout;
 429
 430         /* Additional context states. */
 431         unsigned flags; /* flush flags */
 432
 433         /* Queries. */
 434         /* Maintain the list of active queries for pausing between IBs. */
 435         int                             num_occlusion_queries;
 436         int                             num_perfect_occlusion_queries;
 437         struct list_head                active_queries;
 438         unsigned                        num_cs_dw_queries_suspend;
 439         /* Additional hardware info. */
 440         unsigned                        backend_mask;
 441         unsigned                        max_db; /* for OQ */
 442         /* Misc stats. */
 443         unsigned                        num_draw_calls;
 444
 445         /* Render condition. */
 446         struct r600_atom                render_cond_atom;
 447         struct pipe_query               *render_cond;
 448         unsigned                        render_cond_mode;
 449         boolean                         render_cond_invert;
 450         bool                            render_cond_force_off; /* for u_blitter */
 451
 452         /* MSAA sample locations.
 453          * The first index is the sample index.
 454          * The second index is the coordinate: X, Y. */
 455         float                           sample_locations_1x[1][2];
 456         float                           sample_locations_2x[2][2];
 457         float                           sample_locations_4x[4][2];
 458         float                           sample_locations_8x[8][2];
 459         float                           sample_locations_16x[16][2];
 460
 461         /* The list of all texture buffer objects in this context.
 462          * This list is walked when a buffer is invalidated/reallocated and
 463          * the GPU addresses are updated. */
 464         struct list_head                texture_buffers;
 465
 466         struct pipe_debug_callback      debug;
 467
 468         /* Copy one resource to another using async DMA. */
 469         void (*dma_copy)(struct pipe_context *ctx,
 470                          struct pipe_resource *dst,
 471                          unsigned dst_level,
 472                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 473                          struct pipe_resource *src,
 474                          unsigned src_level,
 475                          const struct pipe_box *src_box);
 476
 477         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 478                              uint64_t offset, uint64_t size, unsigned value,
 479                              bool is_framebuffer);
 480
 481         void (*blit_decompress_depth)(struct pipe_context *ctx,
 482                                       struct r600_texture *texture,
 483                                       struct r600_texture *staging,
 484                                       unsigned first_level, unsigned last_level,
 485                                       unsigned first_layer, unsigned last_layer,
 486                                       unsigned first_sample, unsigned last_sample);
 487
 488         void (*decompress_dcc)(struct pipe_context *ctx,
 489                                struct r600_texture *rtex);
 490
 491         /* Reallocate the buffer and update all resource bindings where
 492          * the buffer is bound, including all resource descriptors. */
 493         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 494
 495         /* Enable or disable occlusion queries. */
 496         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 497
 498         /* This ensures there is enough space in the command stream. */
 499         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 500                                   bool include_draw_vbo);
 501
 502         void (*set_atom_dirty)(struct r600_common_context *ctx,
 503                                struct r600_atom *atom, bool dirty);
 504 };
 505
 506 /* r600_buffer.c */
 507 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 508                                         struct pb_buffer *buf,
 509                                         enum radeon_bo_usage usage);
 510 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 511                                       struct r600_resource *resource,
 512                                       unsigned usage);
 513 bool r600_init_resource(struct r600_common_screen *rscreen,
 514                         struct r600_resource *res,
 515                         uint64_t size, unsigned alignment,
 516                         bool use_reusable_pool);
 517 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 518                                          const struct pipe_resource *templ,
 519                                          unsigned alignment);
 520 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
 521                                                   unsigned bind,
 522                                                   unsigned usage,
 523                                                   unsigned size,
 524                                                   unsigned alignment);
 525 struct pipe_resource *
 526 r600_buffer_from_user_memory(struct pipe_screen *screen,
 527                              const struct pipe_resource *templ,
 528                              void *user_memory);
 529 void
 530 r600_invalidate_resource(struct pipe_context *ctx,
 531                          struct pipe_resource *resource);
 532
 533 /* r600_common_pipe.c */
 534 void r600_draw_rectangle(struct blitter_context *blitter,
 535                          int x1, int y1, int x2, int y2, float depth,
 536                          enum blitter_attrib_type type,
 537                          const union pipe_color_union *attrib);
 538 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 539                              struct radeon_winsys *ws);
 540 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 541 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 542 void r600_postflush_resume_features(struct r600_common_context *ctx);
 543 bool r600_common_context_init(struct r600_common_context *rctx,
 544                               struct r600_common_screen *rscreen);
 545 void r600_common_context_cleanup(struct r600_common_context *rctx);
 546 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 547 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 548                           unsigned processor);
 549 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 550                               uint64_t offset, uint64_t size, unsigned value,
 551                               bool is_framebuffer);
 552 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 553                                                   const struct pipe_resource *templ);
 554 const char *r600_get_llvm_processor_name(enum radeon_family family);
 555 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw);
 556
 557 /* r600_gpu_load.c */
 558 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 559 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 560 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 561
 562 /* r600_perfcounters.c */
 563 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
 564
 565 /* r600_query.c */
 566 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
 567 void r600_query_init(struct r600_common_context *rctx);
 568 void r600_suspend_queries(struct r600_common_context *ctx);
 569 void r600_resume_queries(struct r600_common_context *ctx);
 570 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 571
 572 /* r600_streamout.c */
 573 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 574 void r600_set_streamout_targets(struct pipe_context *ctx,
 575                                 unsigned num_targets,
 576                                 struct pipe_stream_output_target **targets,
 577                                 const unsigned *offset);
 578 void r600_emit_streamout_end(struct r600_common_context *rctx);
 579 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 580                                              unsigned type, int diff);
 581 void r600_streamout_init(struct r600_common_context *rctx);
 582
 583 /* r600_texture.c */
 584 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 585                                  struct r600_texture *rtex,
 586                                  unsigned nr_samples,
 587                                  struct r600_fmask_info *out);
 588 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 589                                  struct r600_texture *rtex,
 590                                  struct r600_cmask_info *out);
 591 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 592                                      struct pipe_resource *texture,
 593                                      struct r600_texture **staging);
 594 void r600_print_texture_info(struct r600_texture *rtex, FILE *f);
 595 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 596                                         const struct pipe_resource *templ);
 597 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 598                                                 struct pipe_resource *texture,
 599                                                 const struct pipe_surface *templ,
 600                                                 unsigned width, unsigned height);
 601 unsigned r600_translate_colorswap(enum pipe_format format);
 602 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 603                                    struct pipe_framebuffer_state *fb,
 604                                    struct r600_atom *fb_state,
 605                                    unsigned *buffers, unsigned *dirty_cbufs,
 606                                    const union pipe_color_union *color);
 607 void r600_texture_disable_dcc(struct r600_common_screen *rscreen,
 608                               struct r600_texture *rtex);
 609 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 610 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 611
 612 /* cayman_msaa.c */
 613 extern const uint32_t eg_sample_locs_2x[4];
 614 extern const unsigned eg_max_dist_2x;
 615 extern const uint32_t eg_sample_locs_4x[4];
 616 extern const unsigned eg_max_dist_4x;
 617 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 618                                 unsigned sample_index, float *out_value);
 619 void cayman_init_msaa(struct pipe_context *ctx);
 620 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 621 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 622                              int ps_iter_samples, int overrast_samples);
 623
 624
 625 /* Inline helpers. */
 626
 627 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 628 {
 629         return (struct r600_resource*)r;
 630 }
 631
 632 static inline void
 633 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 634 {
 635         pipe_resource_reference((struct pipe_resource **)ptr,
 636                                 (struct pipe_resource *)res);
 637 }
 638
 639 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
 640 {
 641         return rctx->streamout.streamout_enabled ||
 642                rctx->streamout.prims_gen_query_enabled;
 643 }
 644
 645 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 646 {
 647         if (filter <= 1)   return 0;
 648         if (filter <= 2)   return 1;
 649         if (filter <= 4)   return 2;
 650         if (filter <= 8)   return 3;
 651          /* else */        return 4;
 652 }
 653
 654 static inline unsigned r600_wavefront_size(enum radeon_family family)
 655 {
 656         switch (family) {
 657         case CHIP_RV610:
 658         case CHIP_RS780:
 659         case CHIP_RV620:
 660         case CHIP_RS880:
 661                 return 16;
 662         case CHIP_RV630:
 663         case CHIP_RV635:
 664         case CHIP_RV730:
 665         case CHIP_RV710:
 666         case CHIP_PALM:
 667         case CHIP_CEDAR:
 668                 return 32;
 669         default:
 670                 return 64;
 671         }
 672 }
 673
 674 static inline enum radeon_bo_priority
 675 r600_get_sampler_view_priority(struct r600_resource *res)
 676 {
 677         if (res->b.b.target == PIPE_BUFFER)
 678                 return RADEON_PRIO_SAMPLER_BUFFER;
 679
 680         if (res->b.b.nr_samples > 1)
 681                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 682
 683         return RADEON_PRIO_SAMPLER_TEXTURE;
 684 }
 685
 686 #define COMPUTE_DBG(rscreen, fmt, args...) \
 687         do { \
 688                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 689         } while (0);
 690
 691 #define R600_ERR(fmt, args...) \
 692         fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 693
 694 /* For MSAA sample positions. */
 695 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 696         (((s0x) & 0xf) | (((s0y) & 0xf) << 4) |            \
 697         (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |     \
 698         (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |    \
 699          (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
 700
 701 #endif