src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "amd/common/ac_binary.h"
  38
  39 #include "radeon/radeon_winsys.h"
  40
  41 #include "util/disk_cache.h"
  42 #include "util/u_blitter.h"
  43 #include "util/list.h"
  44 #include "util/u_range.h"
  45 #include "util/slab.h"
  46 #include "util/u_suballoc.h"
  47 #include "util/u_transfer.h"
  48 #include "util/u_threaded_context.h"
  49
  50 #define ATI_VENDOR_ID 0x1002
  51
  52 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  53 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  54 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  55 #define R600_RESOURCE_FLAG_DISABLE_DCC          (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
  56 #define R600_RESOURCE_FLAG_UNMAPPABLE           (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
  57
  58 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  59 /* Pipeline & streamout query controls. */
  60 #define R600_CONTEXT_START_PIPELINE_STATS       (1u << 1)
  61 #define R600_CONTEXT_STOP_PIPELINE_STATS        (1u << 2)
  62 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 3)
  63
  64 /* special primitive types */
  65 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  66
  67 /* Debug flags. */
  68 /* logging */
  69 #define DBG_TEX                 (1 << 0)
  70 /* gap - reuse */
  71 #define DBG_COMPUTE             (1 << 2)
  72 #define DBG_VM                  (1 << 3)
  73 /* gap - reuse */
  74 /* shader logging */
  75 #define DBG_FS                  (1 << 5)
  76 #define DBG_VS                  (1 << 6)
  77 #define DBG_GS                  (1 << 7)
  78 #define DBG_PS                  (1 << 8)
  79 #define DBG_CS                  (1 << 9)
  80 #define DBG_TCS                 (1 << 10)
  81 #define DBG_TES                 (1 << 11)
  82 #define DBG_NO_IR               (1 << 12)
  83 #define DBG_NO_TGSI             (1 << 13)
  84 #define DBG_NO_ASM              (1 << 14)
  85 #define DBG_PREOPT_IR           (1 << 15)
  86 #define DBG_CHECK_IR            (1 << 16)
  87 #define DBG_NO_OPT_VARIANT      (1 << 17)
  88 /* gaps */
  89 #define DBG_TEST_DMA            (1 << 20)
  90 /* Bits 21-31 are reserved for the r600g driver. */
  91 /* features */
  92 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  93 #define DBG_NO_HYPERZ           (1llu << 33)
  94 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  95 #define DBG_NO_2D_TILING        (1llu << 35)
  96 #define DBG_NO_TILING           (1llu << 36)
  97 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  98 #define DBG_FORCE_DMA           (1llu << 38)
  99 #define DBG_PRECOMPILE          (1llu << 39)
 100 #define DBG_INFO                (1llu << 40)
 101 #define DBG_NO_WC               (1llu << 41)
 102 #define DBG_CHECK_VM            (1llu << 42)
 103 #define DBG_NO_DCC              (1llu << 43)
 104 #define DBG_NO_DCC_CLEAR        (1llu << 44)
 105 #define DBG_NO_RB_PLUS          (1llu << 45)
 106 #define DBG_SI_SCHED            (1llu << 46)
 107 #define DBG_MONOLITHIC_SHADERS  (1llu << 47)
 108 #define DBG_NO_CE               (1llu << 48)
 109 #define DBG_UNSAFE_MATH         (1llu << 49)
 110 #define DBG_NO_DCC_FB           (1llu << 50)
 111 #define DBG_TEST_VMFAULT_CP     (1llu << 51)
 112 #define DBG_TEST_VMFAULT_SDMA   (1llu << 52)
 113 #define DBG_TEST_VMFAULT_SHADER (1llu << 53)
 114
 115 #define R600_MAP_BUFFER_ALIGNMENT 64
 116 #define R600_MAX_VIEWPORTS        16
 117
 118 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
 119
 120 enum r600_coherency {
 121         R600_COHERENCY_NONE, /* no cache flushes needed */
 122         R600_COHERENCY_SHADER,
 123         R600_COHERENCY_CB_META,
 124 };
 125
 126 #ifdef PIPE_ARCH_BIG_ENDIAN
 127 #define R600_BIG_ENDIAN 1
 128 #else
 129 #define R600_BIG_ENDIAN 0
 130 #endif
 131
 132 struct r600_common_context;
 133 struct r600_perfcounters;
 134 struct tgsi_shader_info;
 135 struct r600_qbo_state;
 136
 137 void radeon_shader_binary_init(struct ac_shader_binary *b);
 138 void radeon_shader_binary_clean(struct ac_shader_binary *b);
 139
 140 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
 141  * at the moment.
 142  */
 143 struct r600_resource {
 144         struct threaded_resource        b;
 145
 146         /* Winsys objects. */
 147         struct pb_buffer                *buf;
 148         uint64_t                        gpu_address;
 149         /* Memory usage if the buffer placement is optimal. */
 150         uint64_t                        vram_usage;
 151         uint64_t                        gart_usage;
 152
 153         /* Resource properties. */
 154         uint64_t                        bo_size;
 155         unsigned                        bo_alignment;
 156         enum radeon_bo_domain           domains;
 157         enum radeon_bo_flag             flags;
 158         unsigned                        bind_history;
 159
 160         /* The buffer range which is initialized (with a write transfer,
 161          * streamout, DMA, or as a random access target). The rest of
 162          * the buffer is considered invalid and can be mapped unsynchronized.
 163          *
 164          * This allows unsychronized mapping of a buffer range which hasn't
 165          * been used yet. It's for applications which forget to use
 166          * the unsynchronized map flag and expect the driver to figure it out.
 167          */
 168         struct util_range               valid_buffer_range;
 169
 170         /* For buffers only. This indicates that a write operation has been
 171          * performed by TC L2, but the cache hasn't been flushed.
 172          * Any hw block which doesn't use or bypasses TC L2 should check this
 173          * flag and flush the cache before using the buffer.
 174          *
 175          * For example, TC L2 must be flushed if a buffer which has been
 176          * modified by a shader store instruction is about to be used as
 177          * an index buffer. The reason is that VGT DMA index fetching doesn't
 178          * use TC L2.
 179          */
 180         bool                            TC_L2_dirty;
 181
 182         /* Whether the resource has been exported via resource_get_handle. */
 183         unsigned                        external_usage; /* PIPE_HANDLE_USAGE_* */
 184
 185         /* Whether this resource is referenced by bindless handles. */
 186         bool                            texture_handle_allocated;
 187         bool                            image_handle_allocated;
 188 };
 189
 190 struct r600_transfer {
 191         struct threaded_transfer        b;
 192         struct r600_resource            *staging;
 193         unsigned                        offset;
 194 };
 195
 196 struct r600_fmask_info {
 197         uint64_t offset;
 198         uint64_t size;
 199         unsigned alignment;
 200         unsigned pitch_in_pixels;
 201         unsigned bank_height;
 202         unsigned slice_tile_max;
 203         unsigned tile_mode_index;
 204 };
 205
 206 struct r600_cmask_info {
 207         uint64_t offset;
 208         uint64_t size;
 209         unsigned alignment;
 210         unsigned slice_tile_max;
 211         uint64_t base_address_reg;
 212 };
 213
 214 struct r600_texture {
 215         struct r600_resource            resource;
 216
 217         uint64_t                        size;
 218         unsigned                        num_level0_transfers;
 219         enum pipe_format                db_render_format;
 220         bool                            is_depth;
 221         bool                            db_compatible;
 222         bool                            can_sample_z;
 223         bool                            can_sample_s;
 224         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 225         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 226         struct r600_texture             *flushed_depth_texture;
 227         struct radeon_surf              surface;
 228
 229         /* Colorbuffer compression and fast clear. */
 230         struct r600_fmask_info          fmask;
 231         struct r600_cmask_info          cmask;
 232         struct r600_resource            *cmask_buffer;
 233         uint64_t                        dcc_offset; /* 0 = disabled */
 234         unsigned                        cb_color_info; /* fast clear enable bit */
 235         unsigned                        color_clear_value[2];
 236         unsigned                        last_msaa_resolve_target_micro_mode;
 237
 238         /* Depth buffer compression and fast clear. */
 239         uint64_t                        htile_offset;
 240         bool                            tc_compatible_htile;
 241         bool                            depth_cleared; /* if it was cleared at least once */
 242         float                           depth_clear_value;
 243         bool                            stencil_cleared; /* if it was cleared at least once */
 244         uint8_t                         stencil_clear_value;
 245
 246         bool                            non_disp_tiling; /* R600-Cayman only */
 247
 248         /* Whether the texture is a displayable back buffer and needs DCC
 249          * decompression, which is expensive. Therefore, it's enabled only
 250          * if statistics suggest that it will pay off and it's allocated
 251          * separately. It can't be bound as a sampler by apps. Limited to
 252          * target == 2D and last_level == 0. If enabled, dcc_offset contains
 253          * the absolute GPUVM address, not the relative one.
 254          */
 255         struct r600_resource            *dcc_separate_buffer;
 256         /* When DCC is temporarily disabled, the separate buffer is here. */
 257         struct r600_resource            *last_dcc_separate_buffer;
 258         /* We need to track DCC dirtiness, because st/dri usually calls
 259          * flush_resource twice per frame (not a bug) and we don't wanna
 260          * decompress DCC twice. Also, the dirty tracking must be done even
 261          * if DCC isn't used, because it's required by the DCC usage analysis
 262          * for a possible future enablement.
 263          */
 264         bool                            separate_dcc_dirty;
 265         /* Statistics gathering for the DCC enablement heuristic. */
 266         bool                            dcc_gather_statistics;
 267         /* Estimate of how much this color buffer is written to in units of
 268          * full-screen draws: ps_invocations / (width * height)
 269          * Shader kills, late Z, and blending with trivial discards make it
 270          * inaccurate (we need to count CB updates, not PS invocations).
 271          */
 272         unsigned                        ps_draw_ratio;
 273         /* The number of clears since the last DCC usage analysis. */
 274         unsigned                        num_slow_clears;
 275
 276         /* Counter that should be non-zero if the texture is bound to a
 277          * framebuffer. Implemented in radeonsi only.
 278          */
 279         uint32_t                        framebuffers_bound;
 280 };
 281
 282 struct r600_surface {
 283         struct pipe_surface             base;
 284
 285         /* These can vary with block-compressed textures. */
 286         unsigned width0;
 287         unsigned height0;
 288
 289         bool color_initialized;
 290         bool depth_initialized;
 291
 292         /* Misc. color flags. */
 293         bool alphatest_bypass;
 294         bool export_16bpc;
 295         bool color_is_int8;
 296         bool color_is_int10;
 297         bool dcc_incompatible;
 298
 299         /* Color registers. */
 300         unsigned cb_color_info;
 301         unsigned cb_color_base;
 302         unsigned cb_color_view;
 303         unsigned cb_color_size;         /* R600 only */
 304         unsigned cb_color_dim;          /* EG only */
 305         unsigned cb_color_pitch;        /* EG and later */
 306         unsigned cb_color_slice;        /* EG and later */
 307         unsigned cb_color_attrib;       /* EG and later */
 308         unsigned cb_color_attrib2;      /* GFX9 and later */
 309         unsigned cb_dcc_control;        /* VI and later */
 310         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 311         unsigned cb_color_fmask_slice;  /* EG and later */
 312         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 313         unsigned cb_color_mask;         /* R600 only */
 314         unsigned spi_shader_col_format;         /* SI+, no blending, no alpha-to-coverage. */
 315         unsigned spi_shader_col_format_alpha;   /* SI+, alpha-to-coverage */
 316         unsigned spi_shader_col_format_blend;   /* SI+, blending without alpha. */
 317         unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
 318         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 319         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 320
 321         /* DB registers. */
 322         uint64_t db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 323         uint64_t db_stencil_base;       /* EG and later */
 324         uint64_t db_htile_data_base;
 325         unsigned db_depth_info;         /* R600 only, then SI and later */
 326         unsigned db_z_info;             /* EG and later */
 327         unsigned db_z_info2;            /* GFX9+ */
 328         unsigned db_depth_view;
 329         unsigned db_depth_size;
 330         unsigned db_depth_slice;        /* EG and later */
 331         unsigned db_stencil_info;       /* EG and later */
 332         unsigned db_stencil_info2;      /* GFX9+ */
 333         unsigned db_prefetch_limit;     /* R600 only */
 334         unsigned db_htile_surface;
 335         unsigned db_preload_control;    /* EG and later */
 336 };
 337
 338 struct r600_mmio_counter {
 339         unsigned busy;
 340         unsigned idle;
 341 };
 342
 343 union r600_mmio_counters {
 344         struct {
 345                 /* For global GPU load including SDMA. */
 346                 struct r600_mmio_counter gpu;
 347
 348                 /* GRBM_STATUS */
 349                 struct r600_mmio_counter spi;
 350                 struct r600_mmio_counter gui;
 351                 struct r600_mmio_counter ta;
 352                 struct r600_mmio_counter gds;
 353                 struct r600_mmio_counter vgt;
 354                 struct r600_mmio_counter ia;
 355                 struct r600_mmio_counter sx;
 356                 struct r600_mmio_counter wd;
 357                 struct r600_mmio_counter bci;
 358                 struct r600_mmio_counter sc;
 359                 struct r600_mmio_counter pa;
 360                 struct r600_mmio_counter db;
 361                 struct r600_mmio_counter cp;
 362                 struct r600_mmio_counter cb;
 363
 364                 /* SRBM_STATUS2 */
 365                 struct r600_mmio_counter sdma;
 366
 367                 /* CP_STAT */
 368                 struct r600_mmio_counter pfp;
 369                 struct r600_mmio_counter meq;
 370                 struct r600_mmio_counter me;
 371                 struct r600_mmio_counter surf_sync;
 372                 struct r600_mmio_counter dma;
 373                 struct r600_mmio_counter scratch_ram;
 374                 struct r600_mmio_counter ce;
 375         } named;
 376         unsigned array[0];
 377 };
 378
 379 struct r600_common_screen {
 380         struct pipe_screen              b;
 381         struct radeon_winsys            *ws;
 382         enum radeon_family              family;
 383         enum chip_class                 chip_class;
 384         struct radeon_info              info;
 385         uint64_t                        debug_flags;
 386         bool                            has_cp_dma;
 387         bool                            has_streamout;
 388         bool                            has_rbplus;     /* if RB+ registers exist */
 389         bool                            rbplus_allowed; /* if RB+ is allowed */
 390
 391         struct disk_cache               *disk_shader_cache;
 392
 393         struct slab_parent_pool         pool_transfers;
 394
 395         /* Texture filter settings. */
 396         int                             force_aniso; /* -1 = disabled */
 397
 398         /* Auxiliary context. Mainly used to initialize resources.
 399          * It must be locked prior to using and flushed before unlocking. */
 400         struct pipe_context             *aux_context;
 401         mtx_t                           aux_context_lock;
 402
 403         /* This must be in the screen, because UE4 uses one context for
 404          * compilation and another one for rendering.
 405          */
 406         unsigned                        num_compilations;
 407         /* Along with ST_DEBUG=precompile, this should show if applications
 408          * are loading shaders on demand. This is a monotonic counter.
 409          */
 410         unsigned                        num_shaders_created;
 411         unsigned                        num_shader_cache_hits;
 412
 413         /* GPU load thread. */
 414         mtx_t                           gpu_load_mutex;
 415         thrd_t                          gpu_load_thread;
 416         union r600_mmio_counters        mmio_counters;
 417         volatile unsigned               gpu_load_stop_thread; /* bool */
 418
 419         char                            renderer_string[100];
 420
 421         /* Performance counters. */
 422         struct r600_perfcounters        *perfcounters;
 423
 424         /* If pipe_screen wants to recompute and re-emit the framebuffer,
 425          * sampler, and image states of all contexts, it should atomically
 426          * increment this.
 427          *
 428          * Each context will compare this with its own last known value of
 429          * the counter before drawing and re-emit the states accordingly.
 430          */
 431         unsigned                        dirty_tex_counter;
 432
 433         /* Atomically increment this counter when an existing texture's
 434          * metadata is enabled or disabled in a way that requires changing
 435          * contexts' compressed texture binding masks.
 436          */
 437         unsigned                        compressed_colortex_counter;
 438
 439         struct {
 440                 /* Context flags to set so that all writes from earlier jobs
 441                  * in the CP are seen by L2 clients.
 442                  */
 443                 unsigned cp_to_L2;
 444
 445                 /* Context flags to set so that all writes from earlier
 446                  * compute jobs are seen by L2 clients.
 447                  */
 448                 unsigned compute_to_L2;
 449         } barrier_flags;
 450
 451         void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
 452                                       struct r600_texture *rtex,
 453                                       struct radeon_bo_metadata *md);
 454
 455         void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
 456                                     struct r600_texture *rtex,
 457                                     struct radeon_bo_metadata *md);
 458 };
 459
 460 /* This encapsulates a state or an operation which can emitted into the GPU
 461  * command stream. */
 462 struct r600_atom {
 463         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 464         unsigned                num_dw;
 465         unsigned short          id;
 466 };
 467
 468 struct r600_so_target {
 469         struct pipe_stream_output_target b;
 470
 471         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 472         struct r600_resource    *buf_filled_size;
 473         unsigned                buf_filled_size_offset;
 474         bool                    buf_filled_size_valid;
 475
 476         unsigned                stride_in_dw;
 477 };
 478
 479 struct r600_streamout {
 480         struct r600_atom                begin_atom;
 481         bool                            begin_emitted;
 482         unsigned                        num_dw_for_end;
 483
 484         unsigned                        enabled_mask;
 485         unsigned                        num_targets;
 486         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 487
 488         unsigned                        append_bitmask;
 489         bool                            suspended;
 490
 491         /* External state which comes from the vertex shader,
 492          * it must be set explicitly when binding a shader. */
 493         uint16_t                        *stride_in_dw;
 494         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 495
 496         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 497         unsigned                        hw_enabled_mask;
 498
 499         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 500         struct r600_atom                enable_atom;
 501         bool                            streamout_enabled;
 502         bool                            prims_gen_query_enabled;
 503         int                             num_prims_gen_queries;
 504 };
 505
 506 struct r600_signed_scissor {
 507         int minx;
 508         int miny;
 509         int maxx;
 510         int maxy;
 511 };
 512
 513 struct r600_scissors {
 514         struct r600_atom                atom;
 515         unsigned                        dirty_mask;
 516         struct pipe_scissor_state       states[R600_MAX_VIEWPORTS];
 517 };
 518
 519 struct r600_viewports {
 520         struct r600_atom                atom;
 521         unsigned                        dirty_mask;
 522         unsigned                        depth_range_dirty_mask;
 523         struct pipe_viewport_state      states[R600_MAX_VIEWPORTS];
 524         struct r600_signed_scissor      as_scissor[R600_MAX_VIEWPORTS];
 525 };
 526
 527 struct r600_ring {
 528         struct radeon_winsys_cs         *cs;
 529         void (*flush)(void *ctx, unsigned flags,
 530                       struct pipe_fence_handle **fence);
 531 };
 532
 533 /* Saved CS data for debugging features. */
 534 struct radeon_saved_cs {
 535         uint32_t                        *ib;
 536         unsigned                        num_dw;
 537
 538         struct radeon_bo_list_item      *bo_list;
 539         unsigned                        bo_count;
 540 };
 541
 542 struct r600_common_context {
 543         struct pipe_context b; /* base class */
 544
 545         struct r600_common_screen       *screen;
 546         struct radeon_winsys            *ws;
 547         struct radeon_winsys_ctx        *ctx;
 548         enum radeon_family              family;
 549         enum chip_class                 chip_class;
 550         struct r600_ring                gfx;
 551         struct r600_ring                dma;
 552         struct pipe_fence_handle        *last_gfx_fence;
 553         struct pipe_fence_handle        *last_sdma_fence;
 554         unsigned                        num_gfx_cs_flushes;
 555         unsigned                        initial_gfx_cs_size;
 556         unsigned                        gpu_reset_counter;
 557         unsigned                        last_dirty_tex_counter;
 558         unsigned                        last_compressed_colortex_counter;
 559
 560         struct threaded_context         *tc;
 561         struct u_suballocator           *allocator_zeroed_memory;
 562         struct slab_child_pool          pool_transfers;
 563         struct slab_child_pool          pool_transfers_unsync; /* for threaded_context */
 564
 565         /* Current unaccounted memory usage. */
 566         uint64_t                        vram;
 567         uint64_t                        gtt;
 568
 569         /* States. */
 570         struct r600_streamout           streamout;
 571         struct r600_scissors            scissors;
 572         struct r600_viewports           viewports;
 573         bool                            scissor_enabled;
 574         bool                            clip_halfz;
 575         bool                            vs_writes_viewport_index;
 576         bool                            vs_disables_clipping_viewport;
 577
 578         /* Additional context states. */
 579         unsigned flags; /* flush flags */
 580
 581         /* Queries. */
 582         /* Maintain the list of active queries for pausing between IBs. */
 583         int                             num_occlusion_queries;
 584         int                             num_perfect_occlusion_queries;
 585         struct list_head                active_queries;
 586         unsigned                        num_cs_dw_queries_suspend;
 587         /* Misc stats. */
 588         unsigned                        num_draw_calls;
 589         unsigned                        num_prim_restart_calls;
 590         unsigned                        num_spill_draw_calls;
 591         unsigned                        num_compute_calls;
 592         unsigned                        num_spill_compute_calls;
 593         unsigned                        num_dma_calls;
 594         unsigned                        num_cp_dma_calls;
 595         unsigned                        num_vs_flushes;
 596         unsigned                        num_ps_flushes;
 597         unsigned                        num_cs_flushes;
 598         unsigned                        num_fb_cache_flushes;
 599         unsigned                        num_L2_invalidates;
 600         unsigned                        num_L2_writebacks;
 601         unsigned                        num_resident_handles;
 602         uint64_t                        num_alloc_tex_transfer_bytes;
 603         unsigned                        last_tex_ps_draw_ratio; /* for query */
 604
 605         /* Render condition. */
 606         struct r600_atom                render_cond_atom;
 607         struct pipe_query               *render_cond;
 608         unsigned                        render_cond_mode;
 609         bool                            render_cond_invert;
 610         bool                            render_cond_force_off; /* for u_blitter */
 611
 612         /* MSAA sample locations.
 613          * The first index is the sample index.
 614          * The second index is the coordinate: X, Y. */
 615         float                           sample_locations_1x[1][2];
 616         float                           sample_locations_2x[2][2];
 617         float                           sample_locations_4x[4][2];
 618         float                           sample_locations_8x[8][2];
 619         float                           sample_locations_16x[16][2];
 620
 621         /* Statistics gathering for the DCC enablement heuristic. It can't be
 622          * in r600_texture because r600_texture can be shared by multiple
 623          * contexts. This is for back buffers only. We shouldn't get too many
 624          * of those.
 625          *
 626          * X11 DRI3 rotates among a finite set of back buffers. They should
 627          * all fit in this array. If they don't, separate DCC might never be
 628          * enabled by DCC stat gathering.
 629          */
 630         struct {
 631                 struct r600_texture             *tex;
 632                 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
 633                 struct pipe_query               *ps_stats[3];
 634                 /* If all slots are used and another slot is needed,
 635                  * the least recently used slot is evicted based on this. */
 636                 int64_t                         last_use_timestamp;
 637                 bool                            query_active;
 638         } dcc_stats[5];
 639
 640         struct pipe_debug_callback      debug;
 641         struct pipe_device_reset_callback device_reset_callback;
 642
 643         void                            *query_result_shader;
 644
 645         /* Copy one resource to another using async DMA. */
 646         void (*dma_copy)(struct pipe_context *ctx,
 647                          struct pipe_resource *dst,
 648                          unsigned dst_level,
 649                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 650                          struct pipe_resource *src,
 651                          unsigned src_level,
 652                          const struct pipe_box *src_box);
 653
 654         void (*dma_clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 655                                  uint64_t offset, uint64_t size, unsigned value);
 656
 657         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 658                              uint64_t offset, uint64_t size, unsigned value,
 659                              enum r600_coherency coher);
 660
 661         void (*blit_decompress_depth)(struct pipe_context *ctx,
 662                                       struct r600_texture *texture,
 663                                       struct r600_texture *staging,
 664                                       unsigned first_level, unsigned last_level,
 665                                       unsigned first_layer, unsigned last_layer,
 666                                       unsigned first_sample, unsigned last_sample);
 667
 668         void (*decompress_dcc)(struct pipe_context *ctx,
 669                                struct r600_texture *rtex);
 670
 671         /* Reallocate the buffer and update all resource bindings where
 672          * the buffer is bound, including all resource descriptors. */
 673         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 674
 675         /* Update all resource bindings where the buffer is bound, including
 676          * all resource descriptors. This is invalidate_buffer without
 677          * the invalidation. */
 678         void (*rebind_buffer)(struct pipe_context *ctx, struct pipe_resource *buf,
 679                               uint64_t old_gpu_address);
 680
 681         /* Enable or disable occlusion queries. */
 682         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 683
 684         void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state *st);
 685
 686         /* This ensures there is enough space in the command stream. */
 687         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 688                                   bool include_draw_vbo);
 689
 690         void (*set_atom_dirty)(struct r600_common_context *ctx,
 691                                struct r600_atom *atom, bool dirty);
 692
 693         void (*check_vm_faults)(struct r600_common_context *ctx,
 694                                 struct radeon_saved_cs *saved,
 695                                 enum ring_type ring);
 696 };
 697
 698 /* r600_buffer_common.c */
 699 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 700                                      struct pb_buffer *buf,
 701                                      enum radeon_bo_usage usage);
 702 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 703                                       struct r600_resource *resource,
 704                                       unsigned usage);
 705 void r600_buffer_subdata(struct pipe_context *ctx,
 706                          struct pipe_resource *buffer,
 707                          unsigned usage, unsigned offset,
 708                          unsigned size, const void *data);
 709 void r600_init_resource_fields(struct r600_common_screen *rscreen,
 710                                struct r600_resource *res,
 711                                uint64_t size, unsigned alignment);
 712 bool r600_alloc_resource(struct r600_common_screen *rscreen,
 713                          struct r600_resource *res);
 714 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 715                                          const struct pipe_resource *templ,
 716                                          unsigned alignment);
 717 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
 718                                                   unsigned flags,
 719                                                   unsigned usage,
 720                                                   unsigned size,
 721                                                   unsigned alignment);
 722 struct pipe_resource *
 723 r600_buffer_from_user_memory(struct pipe_screen *screen,
 724                              const struct pipe_resource *templ,
 725                              void *user_memory);
 726 void
 727 r600_invalidate_resource(struct pipe_context *ctx,
 728                          struct pipe_resource *resource);
 729 void r600_replace_buffer_storage(struct pipe_context *ctx,
 730                                  struct pipe_resource *dst,
 731                                  struct pipe_resource *src);
 732
 733 /* r600_common_pipe.c */
 734 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
 735                               unsigned event, unsigned event_flags,
 736                               unsigned data_sel,
 737                               struct r600_resource *buf, uint64_t va,
 738                               uint32_t old_fence, uint32_t new_fence);
 739 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen);
 740 void r600_gfx_wait_fence(struct r600_common_context *ctx,
 741                          uint64_t va, uint32_t ref, uint32_t mask);
 742 void r600_draw_rectangle(struct blitter_context *blitter,
 743                          int x1, int y1, int x2, int y2, float depth,
 744                          enum blitter_attrib_type type,
 745                          const union pipe_color_union *attrib);
 746 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 747                              struct radeon_winsys *ws);
 748 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 749 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 750 void r600_postflush_resume_features(struct r600_common_context *ctx);
 751 bool r600_common_context_init(struct r600_common_context *rctx,
 752                               struct r600_common_screen *rscreen,
 753                               unsigned context_flags);
 754 void r600_common_context_cleanup(struct r600_common_context *rctx);
 755 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 756                           unsigned processor);
 757 bool r600_extra_shader_checks(struct r600_common_screen *rscreen,
 758                               unsigned processor);
 759 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 760                               uint64_t offset, uint64_t size, unsigned value);
 761 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 762                                                   const struct pipe_resource *templ);
 763 const char *r600_get_llvm_processor_name(enum radeon_family family);
 764 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
 765                          struct r600_resource *dst, struct r600_resource *src);
 766 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
 767                     struct radeon_saved_cs *saved);
 768 void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
 769 bool r600_check_device_reset(struct r600_common_context *rctx);
 770
 771 /* r600_gpu_load.c */
 772 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 773 uint64_t r600_begin_counter(struct r600_common_screen *rscreen, unsigned type);
 774 unsigned r600_end_counter(struct r600_common_screen *rscreen, unsigned type,
 775                           uint64_t begin);
 776
 777 /* r600_perfcounters.c */
 778 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
 779
 780 /* r600_query.c */
 781 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
 782 void r600_query_init(struct r600_common_context *rctx);
 783 void r600_suspend_queries(struct r600_common_context *ctx);
 784 void r600_resume_queries(struct r600_common_context *ctx);
 785 void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen);
 786
 787 /* r600_streamout.c */
 788 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 789 void r600_set_streamout_targets(struct pipe_context *ctx,
 790                                 unsigned num_targets,
 791                                 struct pipe_stream_output_target **targets,
 792                                 const unsigned *offset);
 793 void r600_emit_streamout_end(struct r600_common_context *rctx);
 794 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 795                                              unsigned type, int diff);
 796 void r600_streamout_init(struct r600_common_context *rctx);
 797
 798 /* r600_test_dma.c */
 799 void r600_test_dma(struct r600_common_screen *rscreen);
 800
 801 /* r600_texture.c */
 802 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
 803                                 struct r600_texture *rdst,
 804                                 unsigned dst_level, unsigned dstx,
 805                                 unsigned dsty, unsigned dstz,
 806                                 struct r600_texture *rsrc,
 807                                 unsigned src_level,
 808                                 const struct pipe_box *src_box);
 809 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 810                                  struct r600_texture *rtex,
 811                                  unsigned nr_samples,
 812                                  struct r600_fmask_info *out);
 813 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 814                                  struct r600_texture *rtex,
 815                                  struct r600_cmask_info *out);
 816 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 817                                      struct pipe_resource *texture,
 818                                      struct r600_texture **staging);
 819 void r600_print_texture_info(struct r600_common_screen *rscreen,
 820                              struct r600_texture *rtex, FILE *f);
 821 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 822                                         const struct pipe_resource *templ);
 823 bool vi_dcc_formats_compatible(enum pipe_format format1,
 824                                enum pipe_format format2);
 825 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
 826                                      unsigned level,
 827                                      enum pipe_format view_format);
 828 void vi_disable_dcc_if_incompatible_format(struct r600_common_context *rctx,
 829                                            struct pipe_resource *tex,
 830                                            unsigned level,
 831                                            enum pipe_format view_format);
 832 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 833                                                 struct pipe_resource *texture,
 834                                                 const struct pipe_surface *templ,
 835                                                 unsigned width0, unsigned height0,
 836                                                 unsigned width, unsigned height);
 837 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
 838 void vi_separate_dcc_start_query(struct pipe_context *ctx,
 839                                  struct r600_texture *tex);
 840 void vi_separate_dcc_stop_query(struct pipe_context *ctx,
 841                                 struct r600_texture *tex);
 842 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
 843                                              struct r600_texture *tex);
 844 void vi_dcc_clear_level(struct r600_common_context *rctx,
 845                         struct r600_texture *rtex,
 846                         unsigned level, unsigned clear_value);
 847 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 848                                    struct pipe_framebuffer_state *fb,
 849                                    struct r600_atom *fb_state,
 850                                    unsigned *buffers, ubyte *dirty_cbufs,
 851                                    const union pipe_color_union *color);
 852 bool r600_texture_disable_dcc(struct r600_common_context *rctx,
 853                               struct r600_texture *rtex);
 854 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 855 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 856
 857 /* r600_viewport.c */
 858 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
 859                                             struct pipe_scissor_state *scissor);
 860 void r600_viewport_set_rast_deps(struct r600_common_context *rctx,
 861                                  bool scissor_enable, bool clip_halfz);
 862 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
 863                                           struct tgsi_shader_info *info);
 864 void r600_init_viewport_functions(struct r600_common_context *rctx);
 865
 866 /* cayman_msaa.c */
 867 extern const uint32_t eg_sample_locs_2x[4];
 868 extern const unsigned eg_max_dist_2x;
 869 extern const uint32_t eg_sample_locs_4x[4];
 870 extern const unsigned eg_max_dist_4x;
 871 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 872                                 unsigned sample_index, float *out_value);
 873 void cayman_init_msaa(struct pipe_context *ctx);
 874 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 875 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 876                              int ps_iter_samples, int overrast_samples,
 877                              unsigned sc_mode_cntl_1);
 878
 879
 880 /* Inline helpers. */
 881
 882 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 883 {
 884         return (struct r600_resource*)r;
 885 }
 886
 887 static inline void
 888 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 889 {
 890         pipe_resource_reference((struct pipe_resource **)ptr,
 891                                 (struct pipe_resource *)res);
 892 }
 893
 894 static inline void
 895 r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
 896 {
 897         pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
 898 }
 899
 900 static inline void
 901 r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 902 {
 903         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 904         struct r600_resource *res = (struct r600_resource *)r;
 905
 906         if (res) {
 907                 /* Add memory usage for need_gfx_cs_space */
 908                 rctx->vram += res->vram_usage;
 909                 rctx->gtt += res->gart_usage;
 910         }
 911 }
 912
 913 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
 914 {
 915         return rctx->streamout.streamout_enabled ||
 916                rctx->streamout.prims_gen_query_enabled;
 917 }
 918
 919 #define     SQ_TEX_XY_FILTER_POINT                         0x00
 920 #define     SQ_TEX_XY_FILTER_BILINEAR                      0x01
 921 #define     SQ_TEX_XY_FILTER_ANISO_POINT                   0x02
 922 #define     SQ_TEX_XY_FILTER_ANISO_BILINEAR                0x03
 923
 924 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
 925 {
 926         if (filter == PIPE_TEX_FILTER_LINEAR)
 927                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
 928                                      : SQ_TEX_XY_FILTER_BILINEAR;
 929         else
 930                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
 931                                      : SQ_TEX_XY_FILTER_POINT;
 932 }
 933
 934 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 935 {
 936         if (filter < 2)
 937                 return 0;
 938         if (filter < 4)
 939                 return 1;
 940         if (filter < 8)
 941                 return 2;
 942         if (filter < 16)
 943                 return 3;
 944         return 4;
 945 }
 946
 947 static inline unsigned r600_wavefront_size(enum radeon_family family)
 948 {
 949         switch (family) {
 950         case CHIP_RV610:
 951         case CHIP_RS780:
 952         case CHIP_RV620:
 953         case CHIP_RS880:
 954                 return 16;
 955         case CHIP_RV630:
 956         case CHIP_RV635:
 957         case CHIP_RV730:
 958         case CHIP_RV710:
 959         case CHIP_PALM:
 960         case CHIP_CEDAR:
 961                 return 32;
 962         default:
 963                 return 64;
 964         }
 965 }
 966
 967 static inline enum radeon_bo_priority
 968 r600_get_sampler_view_priority(struct r600_resource *res)
 969 {
 970         if (res->b.b.target == PIPE_BUFFER)
 971                 return RADEON_PRIO_SAMPLER_BUFFER;
 972
 973         if (res->b.b.nr_samples > 1)
 974                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 975
 976         return RADEON_PRIO_SAMPLER_TEXTURE;
 977 }
 978
 979 static inline bool
 980 r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
 981 {
 982         return (stencil_sampler && tex->can_sample_s) ||
 983                (!stencil_sampler && tex->can_sample_z);
 984 }
 985
 986 static inline bool
 987 vi_dcc_enabled(struct r600_texture *tex, unsigned level)
 988 {
 989         return tex->dcc_offset && level < tex->surface.num_dcc_levels;
 990 }
 991
 992 #define COMPUTE_DBG(rscreen, fmt, args...) \
 993         do { \
 994                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 995         } while (0);
 996
 997 #define R600_ERR(fmt, args...) \
 998         fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 999
1000 /* For MSAA sample positions. */
1001 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
1002         (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) |                  \
1003         (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) |         \
1004         (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) |        \
1005          (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
1006
1007 #endif