src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "amd/common/ac_binary.h"
  38
  39 #include "radeon/radeon_winsys.h"
  40
  41 #include "util/disk_cache.h"
  42 #include "util/u_blitter.h"
  43 #include "util/list.h"
  44 #include "util/u_range.h"
  45 #include "util/slab.h"
  46 #include "util/u_suballoc.h"
  47 #include "util/u_transfer.h"
  48
  49 #define ATI_VENDOR_ID 0x1002
  50
  51 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  52 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  53 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  54 #define R600_RESOURCE_FLAG_DISABLE_DCC          (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
  55 #define R600_RESOURCE_FLAG_UNMAPPABLE           (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
  56
  57 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  58 /* Pipeline & streamout query controls. */
  59 #define R600_CONTEXT_START_PIPELINE_STATS       (1u << 1)
  60 #define R600_CONTEXT_STOP_PIPELINE_STATS        (1u << 2)
  61 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 3)
  62
  63 /* special primitive types */
  64 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  65
  66 /* Debug flags. */
  67 /* logging */
  68 #define DBG_TEX                 (1 << 0)
  69 /* gap - reuse */
  70 #define DBG_COMPUTE             (1 << 2)
  71 #define DBG_VM                  (1 << 3)
  72 /* gap - reuse */
  73 /* shader logging */
  74 #define DBG_FS                  (1 << 5)
  75 #define DBG_VS                  (1 << 6)
  76 #define DBG_GS                  (1 << 7)
  77 #define DBG_PS                  (1 << 8)
  78 #define DBG_CS                  (1 << 9)
  79 #define DBG_TCS                 (1 << 10)
  80 #define DBG_TES                 (1 << 11)
  81 #define DBG_NO_IR               (1 << 12)
  82 #define DBG_NO_TGSI             (1 << 13)
  83 #define DBG_NO_ASM              (1 << 14)
  84 #define DBG_PREOPT_IR           (1 << 15)
  85 #define DBG_CHECK_IR            (1 << 16)
  86 #define DBG_NO_OPT_VARIANT      (1 << 17)
  87 /* gaps */
  88 #define DBG_TEST_DMA            (1 << 20)
  89 /* Bits 21-31 are reserved for the r600g driver. */
  90 /* features */
  91 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  92 #define DBG_NO_HYPERZ           (1llu << 33)
  93 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  94 #define DBG_NO_2D_TILING        (1llu << 35)
  95 #define DBG_NO_TILING           (1llu << 36)
  96 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  97 #define DBG_FORCE_DMA           (1llu << 38)
  98 #define DBG_PRECOMPILE          (1llu << 39)
  99 #define DBG_INFO                (1llu << 40)
 100 #define DBG_NO_WC               (1llu << 41)
 101 #define DBG_CHECK_VM            (1llu << 42)
 102 #define DBG_NO_DCC              (1llu << 43)
 103 #define DBG_NO_DCC_CLEAR        (1llu << 44)
 104 #define DBG_NO_RB_PLUS          (1llu << 45)
 105 #define DBG_SI_SCHED            (1llu << 46)
 106 #define DBG_MONOLITHIC_SHADERS  (1llu << 47)
 107 #define DBG_NO_CE               (1llu << 48)
 108 #define DBG_UNSAFE_MATH         (1llu << 49)
 109 #define DBG_NO_DCC_FB           (1llu << 50)
 110
 111 #define R600_MAP_BUFFER_ALIGNMENT 64
 112 #define R600_MAX_VIEWPORTS        16
 113
 114 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
 115
 116 enum r600_coherency {
 117         R600_COHERENCY_NONE, /* no cache flushes needed */
 118         R600_COHERENCY_SHADER,
 119         R600_COHERENCY_CB_META,
 120 };
 121
 122 #ifdef PIPE_ARCH_BIG_ENDIAN
 123 #define R600_BIG_ENDIAN 1
 124 #else
 125 #define R600_BIG_ENDIAN 0
 126 #endif
 127
 128 struct r600_common_context;
 129 struct r600_perfcounters;
 130 struct tgsi_shader_info;
 131 struct r600_qbo_state;
 132
 133 void radeon_shader_binary_init(struct ac_shader_binary *b);
 134 void radeon_shader_binary_clean(struct ac_shader_binary *b);
 135
 136 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
 137  * at the moment.
 138  */
 139 struct r600_resource {
 140         struct u_resource               b;
 141
 142         /* Winsys objects. */
 143         struct pb_buffer                *buf;
 144         uint64_t                        gpu_address;
 145         /* Memory usage if the buffer placement is optimal. */
 146         uint64_t                        vram_usage;
 147         uint64_t                        gart_usage;
 148
 149         /* Resource properties. */
 150         uint64_t                        bo_size;
 151         unsigned                        bo_alignment;
 152         enum radeon_bo_domain           domains;
 153         enum radeon_bo_flag             flags;
 154         unsigned                        bind_history;
 155
 156         /* The buffer range which is initialized (with a write transfer,
 157          * streamout, DMA, or as a random access target). The rest of
 158          * the buffer is considered invalid and can be mapped unsynchronized.
 159          *
 160          * This allows unsychronized mapping of a buffer range which hasn't
 161          * been used yet. It's for applications which forget to use
 162          * the unsynchronized map flag and expect the driver to figure it out.
 163          */
 164         struct util_range               valid_buffer_range;
 165
 166         /* For buffers only. This indicates that a write operation has been
 167          * performed by TC L2, but the cache hasn't been flushed.
 168          * Any hw block which doesn't use or bypasses TC L2 should check this
 169          * flag and flush the cache before using the buffer.
 170          *
 171          * For example, TC L2 must be flushed if a buffer which has been
 172          * modified by a shader store instruction is about to be used as
 173          * an index buffer. The reason is that VGT DMA index fetching doesn't
 174          * use TC L2.
 175          */
 176         bool                            TC_L2_dirty;
 177
 178         /* Whether the resource has been exported via resource_get_handle. */
 179         bool                            is_shared;
 180         unsigned                        external_usage; /* PIPE_HANDLE_USAGE_* */
 181 };
 182
 183 struct r600_transfer {
 184         struct pipe_transfer            transfer;
 185         struct r600_resource            *staging;
 186         unsigned                        offset;
 187 };
 188
 189 struct r600_fmask_info {
 190         uint64_t offset;
 191         uint64_t size;
 192         unsigned alignment;
 193         unsigned pitch_in_pixels;
 194         unsigned bank_height;
 195         unsigned slice_tile_max;
 196         unsigned tile_mode_index;
 197 };
 198
 199 struct r600_cmask_info {
 200         uint64_t offset;
 201         uint64_t size;
 202         unsigned alignment;
 203         unsigned slice_tile_max;
 204         unsigned base_address_reg;
 205 };
 206
 207 struct r600_texture {
 208         struct r600_resource            resource;
 209
 210         uint64_t                        size;
 211         unsigned                        num_level0_transfers;
 212         enum pipe_format                db_render_format;
 213         bool                            is_depth;
 214         bool                            db_compatible;
 215         bool                            can_sample_z;
 216         bool                            can_sample_s;
 217         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 218         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 219         struct r600_texture             *flushed_depth_texture;
 220         struct radeon_surf              surface;
 221
 222         /* Colorbuffer compression and fast clear. */
 223         struct r600_fmask_info          fmask;
 224         struct r600_cmask_info          cmask;
 225         struct r600_resource            *cmask_buffer;
 226         uint64_t                        dcc_offset; /* 0 = disabled */
 227         unsigned                        cb_color_info; /* fast clear enable bit */
 228         unsigned                        color_clear_value[2];
 229         unsigned                        last_msaa_resolve_target_micro_mode;
 230
 231         /* Depth buffer compression and fast clear. */
 232         struct r600_resource            *htile_buffer;
 233         bool                            tc_compatible_htile;
 234         bool                            depth_cleared; /* if it was cleared at least once */
 235         float                           depth_clear_value;
 236         bool                            stencil_cleared; /* if it was cleared at least once */
 237         uint8_t                         stencil_clear_value;
 238
 239         bool                            non_disp_tiling; /* R600-Cayman only */
 240
 241         /* Whether the texture is a displayable back buffer and needs DCC
 242          * decompression, which is expensive. Therefore, it's enabled only
 243          * if statistics suggest that it will pay off and it's allocated
 244          * separately. It can't be bound as a sampler by apps. Limited to
 245          * target == 2D and last_level == 0. If enabled, dcc_offset contains
 246          * the absolute GPUVM address, not the relative one.
 247          */
 248         struct r600_resource            *dcc_separate_buffer;
 249         /* When DCC is temporarily disabled, the separate buffer is here. */
 250         struct r600_resource            *last_dcc_separate_buffer;
 251         /* We need to track DCC dirtiness, because st/dri usually calls
 252          * flush_resource twice per frame (not a bug) and we don't wanna
 253          * decompress DCC twice. Also, the dirty tracking must be done even
 254          * if DCC isn't used, because it's required by the DCC usage analysis
 255          * for a possible future enablement.
 256          */
 257         bool                            separate_dcc_dirty;
 258         /* Statistics gathering for the DCC enablement heuristic. */
 259         bool                            dcc_gather_statistics;
 260         /* Estimate of how much this color buffer is written to in units of
 261          * full-screen draws: ps_invocations / (width * height)
 262          * Shader kills, late Z, and blending with trivial discards make it
 263          * inaccurate (we need to count CB updates, not PS invocations).
 264          */
 265         unsigned                        ps_draw_ratio;
 266         /* The number of clears since the last DCC usage analysis. */
 267         unsigned                        num_slow_clears;
 268
 269         /* Counter that should be non-zero if the texture is bound to a
 270          * framebuffer. Implemented in radeonsi only.
 271          */
 272         uint32_t                        framebuffers_bound;
 273 };
 274
 275 struct r600_surface {
 276         struct pipe_surface             base;
 277
 278         bool color_initialized;
 279         bool depth_initialized;
 280
 281         /* Misc. color flags. */
 282         bool alphatest_bypass;
 283         bool export_16bpc;
 284         bool color_is_int8;
 285         bool color_is_int10;
 286
 287         /* Color registers. */
 288         unsigned cb_color_info;
 289         unsigned cb_color_base;
 290         unsigned cb_color_view;
 291         unsigned cb_color_size;         /* R600 only */
 292         unsigned cb_color_dim;          /* EG only */
 293         unsigned cb_color_pitch;        /* EG and later */
 294         unsigned cb_color_slice;        /* EG and later */
 295         unsigned cb_color_attrib;       /* EG and later */
 296         unsigned cb_dcc_control;        /* VI and later */
 297         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 298         unsigned cb_color_fmask_slice;  /* EG and later */
 299         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 300         unsigned cb_color_mask;         /* R600 only */
 301         unsigned spi_shader_col_format;         /* SI+, no blending, no alpha-to-coverage. */
 302         unsigned spi_shader_col_format_alpha;   /* SI+, alpha-to-coverage */
 303         unsigned spi_shader_col_format_blend;   /* SI+, blending without alpha. */
 304         unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
 305         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 306         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 307
 308         /* DB registers. */
 309         unsigned db_depth_info;         /* R600 only, then SI and later */
 310         unsigned db_z_info;             /* EG and later */
 311         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 312         unsigned db_depth_view;
 313         unsigned db_depth_size;
 314         unsigned db_depth_slice;        /* EG and later */
 315         unsigned db_stencil_base;       /* EG and later */
 316         unsigned db_stencil_info;       /* EG and later */
 317         unsigned db_prefetch_limit;     /* R600 only */
 318         unsigned db_htile_surface;
 319         unsigned db_htile_data_base;
 320         unsigned db_preload_control;    /* EG and later */
 321 };
 322
 323 struct r600_mmio_counter {
 324         unsigned busy;
 325         unsigned idle;
 326 };
 327
 328 union r600_mmio_counters {
 329         struct {
 330                 /* For global GPU load including SDMA. */
 331                 struct r600_mmio_counter gpu;
 332
 333                 /* GRBM_STATUS */
 334                 struct r600_mmio_counter spi;
 335                 struct r600_mmio_counter gui;
 336                 struct r600_mmio_counter ta;
 337                 struct r600_mmio_counter gds;
 338                 struct r600_mmio_counter vgt;
 339                 struct r600_mmio_counter ia;
 340                 struct r600_mmio_counter sx;
 341                 struct r600_mmio_counter wd;
 342                 struct r600_mmio_counter bci;
 343                 struct r600_mmio_counter sc;
 344                 struct r600_mmio_counter pa;
 345                 struct r600_mmio_counter db;
 346                 struct r600_mmio_counter cp;
 347                 struct r600_mmio_counter cb;
 348
 349                 /* SRBM_STATUS2 */
 350                 struct r600_mmio_counter sdma;
 351
 352                 /* CP_STAT */
 353                 struct r600_mmio_counter pfp;
 354                 struct r600_mmio_counter meq;
 355                 struct r600_mmio_counter me;
 356                 struct r600_mmio_counter surf_sync;
 357                 struct r600_mmio_counter dma;
 358                 struct r600_mmio_counter scratch_ram;
 359                 struct r600_mmio_counter ce;
 360         } named;
 361         unsigned array[0];
 362 };
 363
 364 struct r600_common_screen {
 365         struct pipe_screen              b;
 366         struct radeon_winsys            *ws;
 367         enum radeon_family              family;
 368         enum chip_class                 chip_class;
 369         struct radeon_info              info;
 370         uint64_t                        debug_flags;
 371         bool                            has_cp_dma;
 372         bool                            has_streamout;
 373         bool                            has_rbplus;     /* if RB+ registers exist */
 374         bool                            rbplus_allowed; /* if RB+ is allowed */
 375
 376         struct disk_cache               *disk_shader_cache;
 377
 378         struct slab_parent_pool         pool_transfers;
 379
 380         /* Texture filter settings. */
 381         int                             force_aniso; /* -1 = disabled */
 382
 383         /* Auxiliary context. Mainly used to initialize resources.
 384          * It must be locked prior to using and flushed before unlocking. */
 385         struct pipe_context             *aux_context;
 386         mtx_t                           aux_context_lock;
 387
 388         /* This must be in the screen, because UE4 uses one context for
 389          * compilation and another one for rendering.
 390          */
 391         unsigned                        num_compilations;
 392         /* Along with ST_DEBUG=precompile, this should show if applications
 393          * are loading shaders on demand. This is a monotonic counter.
 394          */
 395         unsigned                        num_shaders_created;
 396         unsigned                        num_shader_cache_hits;
 397
 398         /* GPU load thread. */
 399         mtx_t                           gpu_load_mutex;
 400         thrd_t                          gpu_load_thread;
 401         union r600_mmio_counters        mmio_counters;
 402         volatile unsigned               gpu_load_stop_thread; /* bool */
 403
 404         char                            renderer_string[100];
 405
 406         /* Performance counters. */
 407         struct r600_perfcounters        *perfcounters;
 408
 409         /* If pipe_screen wants to recompute and re-emit the framebuffer,
 410          * sampler, and image states of all contexts, it should atomically
 411          * increment this.
 412          *
 413          * Each context will compare this with its own last known value of
 414          * the counter before drawing and re-emit the states accordingly.
 415          */
 416         unsigned                        dirty_tex_counter;
 417
 418         /* Atomically increment this counter when an existing texture's
 419          * metadata is enabled or disabled in a way that requires changing
 420          * contexts' compressed texture binding masks.
 421          */
 422         unsigned                        compressed_colortex_counter;
 423
 424         struct {
 425                 /* Context flags to set so that all writes from earlier jobs
 426                  * in the CP are seen by L2 clients.
 427                  */
 428                 unsigned cp_to_L2;
 429
 430                 /* Context flags to set so that all writes from earlier
 431                  * compute jobs are seen by L2 clients.
 432                  */
 433                 unsigned compute_to_L2;
 434         } barrier_flags;
 435
 436         void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
 437                                       struct r600_texture *rtex,
 438                                       struct radeon_bo_metadata *md);
 439
 440         void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
 441                                     struct r600_texture *rtex,
 442                                     struct radeon_bo_metadata *md);
 443 };
 444
 445 /* This encapsulates a state or an operation which can emitted into the GPU
 446  * command stream. */
 447 struct r600_atom {
 448         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 449         unsigned                num_dw;
 450         unsigned short          id;
 451 };
 452
 453 struct r600_so_target {
 454         struct pipe_stream_output_target b;
 455
 456         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 457         struct r600_resource    *buf_filled_size;
 458         unsigned                buf_filled_size_offset;
 459         bool                    buf_filled_size_valid;
 460
 461         unsigned                stride_in_dw;
 462 };
 463
 464 struct r600_streamout {
 465         struct r600_atom                begin_atom;
 466         bool                            begin_emitted;
 467         unsigned                        num_dw_for_end;
 468
 469         unsigned                        enabled_mask;
 470         unsigned                        num_targets;
 471         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 472
 473         unsigned                        append_bitmask;
 474         bool                            suspended;
 475
 476         /* External state which comes from the vertex shader,
 477          * it must be set explicitly when binding a shader. */
 478         unsigned                        *stride_in_dw;
 479         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 480
 481         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 482         unsigned                        hw_enabled_mask;
 483
 484         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 485         struct r600_atom                enable_atom;
 486         bool                            streamout_enabled;
 487         bool                            prims_gen_query_enabled;
 488         int                             num_prims_gen_queries;
 489 };
 490
 491 struct r600_signed_scissor {
 492         int minx;
 493         int miny;
 494         int maxx;
 495         int maxy;
 496 };
 497
 498 struct r600_scissors {
 499         struct r600_atom                atom;
 500         unsigned                        dirty_mask;
 501         struct pipe_scissor_state       states[R600_MAX_VIEWPORTS];
 502 };
 503
 504 struct r600_viewports {
 505         struct r600_atom                atom;
 506         unsigned                        dirty_mask;
 507         unsigned                        depth_range_dirty_mask;
 508         struct pipe_viewport_state      states[R600_MAX_VIEWPORTS];
 509         struct r600_signed_scissor      as_scissor[R600_MAX_VIEWPORTS];
 510 };
 511
 512 struct r600_ring {
 513         struct radeon_winsys_cs         *cs;
 514         void (*flush)(void *ctx, unsigned flags,
 515                       struct pipe_fence_handle **fence);
 516 };
 517
 518 /* Saved CS data for debugging features. */
 519 struct radeon_saved_cs {
 520         uint32_t                        *ib;
 521         unsigned                        num_dw;
 522
 523         struct radeon_bo_list_item      *bo_list;
 524         unsigned                        bo_count;
 525 };
 526
 527 struct r600_common_context {
 528         struct pipe_context b; /* base class */
 529
 530         struct r600_common_screen       *screen;
 531         struct radeon_winsys            *ws;
 532         struct radeon_winsys_ctx        *ctx;
 533         enum radeon_family              family;
 534         enum chip_class                 chip_class;
 535         struct r600_ring                gfx;
 536         struct r600_ring                dma;
 537         struct pipe_fence_handle        *last_gfx_fence;
 538         struct pipe_fence_handle        *last_sdma_fence;
 539         unsigned                        num_gfx_cs_flushes;
 540         unsigned                        initial_gfx_cs_size;
 541         unsigned                        gpu_reset_counter;
 542         unsigned                        last_dirty_tex_counter;
 543         unsigned                        last_compressed_colortex_counter;
 544
 545         struct u_suballocator           *allocator_zeroed_memory;
 546         struct slab_child_pool          pool_transfers;
 547
 548         /* Current unaccounted memory usage. */
 549         uint64_t                        vram;
 550         uint64_t                        gtt;
 551
 552         /* States. */
 553         struct r600_streamout           streamout;
 554         struct r600_scissors            scissors;
 555         struct r600_viewports           viewports;
 556         bool                            scissor_enabled;
 557         bool                            clip_halfz;
 558         bool                            vs_writes_viewport_index;
 559         bool                            vs_disables_clipping_viewport;
 560
 561         /* Additional context states. */
 562         unsigned flags; /* flush flags */
 563
 564         /* Queries. */
 565         /* Maintain the list of active queries for pausing between IBs. */
 566         int                             num_occlusion_queries;
 567         int                             num_perfect_occlusion_queries;
 568         struct list_head                active_queries;
 569         unsigned                        num_cs_dw_queries_suspend;
 570         /* Misc stats. */
 571         unsigned                        num_draw_calls;
 572         unsigned                        num_spill_draw_calls;
 573         unsigned                        num_compute_calls;
 574         unsigned                        num_spill_compute_calls;
 575         unsigned                        num_dma_calls;
 576         unsigned                        num_cp_dma_calls;
 577         unsigned                        num_vs_flushes;
 578         unsigned                        num_ps_flushes;
 579         unsigned                        num_cs_flushes;
 580         unsigned                        num_fb_cache_flushes;
 581         unsigned                        num_L2_invalidates;
 582         unsigned                        num_L2_writebacks;
 583         uint64_t                        num_alloc_tex_transfer_bytes;
 584         unsigned                        last_tex_ps_draw_ratio; /* for query */
 585
 586         /* Render condition. */
 587         struct r600_atom                render_cond_atom;
 588         struct pipe_query               *render_cond;
 589         unsigned                        render_cond_mode;
 590         bool                            render_cond_invert;
 591         bool                            render_cond_force_off; /* for u_blitter */
 592
 593         /* MSAA sample locations.
 594          * The first index is the sample index.
 595          * The second index is the coordinate: X, Y. */
 596         float                           sample_locations_1x[1][2];
 597         float                           sample_locations_2x[2][2];
 598         float                           sample_locations_4x[4][2];
 599         float                           sample_locations_8x[8][2];
 600         float                           sample_locations_16x[16][2];
 601
 602         /* Statistics gathering for the DCC enablement heuristic. It can't be
 603          * in r600_texture because r600_texture can be shared by multiple
 604          * contexts. This is for back buffers only. We shouldn't get too many
 605          * of those.
 606          *
 607          * X11 DRI3 rotates among a finite set of back buffers. They should
 608          * all fit in this array. If they don't, separate DCC might never be
 609          * enabled by DCC stat gathering.
 610          */
 611         struct {
 612                 struct r600_texture             *tex;
 613                 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
 614                 struct pipe_query               *ps_stats[3];
 615                 /* If all slots are used and another slot is needed,
 616                  * the least recently used slot is evicted based on this. */
 617                 int64_t                         last_use_timestamp;
 618                 bool                            query_active;
 619         } dcc_stats[5];
 620
 621         struct pipe_debug_callback      debug;
 622         struct pipe_device_reset_callback device_reset_callback;
 623
 624         void                            *query_result_shader;
 625
 626         /* Copy one resource to another using async DMA. */
 627         void (*dma_copy)(struct pipe_context *ctx,
 628                          struct pipe_resource *dst,
 629                          unsigned dst_level,
 630                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 631                          struct pipe_resource *src,
 632                          unsigned src_level,
 633                          const struct pipe_box *src_box);
 634
 635         void (*dma_clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 636                                  uint64_t offset, uint64_t size, unsigned value);
 637
 638         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 639                              uint64_t offset, uint64_t size, unsigned value,
 640                              enum r600_coherency coher);
 641
 642         void (*blit_decompress_depth)(struct pipe_context *ctx,
 643                                       struct r600_texture *texture,
 644                                       struct r600_texture *staging,
 645                                       unsigned first_level, unsigned last_level,
 646                                       unsigned first_layer, unsigned last_layer,
 647                                       unsigned first_sample, unsigned last_sample);
 648
 649         void (*decompress_dcc)(struct pipe_context *ctx,
 650                                struct r600_texture *rtex);
 651
 652         /* Reallocate the buffer and update all resource bindings where
 653          * the buffer is bound, including all resource descriptors. */
 654         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 655
 656         /* Enable or disable occlusion queries. */
 657         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 658
 659         void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state *st);
 660
 661         /* This ensures there is enough space in the command stream. */
 662         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 663                                   bool include_draw_vbo);
 664
 665         void (*set_atom_dirty)(struct r600_common_context *ctx,
 666                                struct r600_atom *atom, bool dirty);
 667
 668         void (*check_vm_faults)(struct r600_common_context *ctx,
 669                                 struct radeon_saved_cs *saved,
 670                                 enum ring_type ring);
 671 };
 672
 673 /* r600_buffer.c */
 674 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 675                                      struct pb_buffer *buf,
 676                                      enum radeon_bo_usage usage);
 677 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 678                                       struct r600_resource *resource,
 679                                       unsigned usage);
 680 void r600_buffer_subdata(struct pipe_context *ctx,
 681                          struct pipe_resource *buffer,
 682                          unsigned usage, unsigned offset,
 683                          unsigned size, const void *data);
 684 void r600_init_resource_fields(struct r600_common_screen *rscreen,
 685                                struct r600_resource *res,
 686                                uint64_t size, unsigned alignment);
 687 bool r600_alloc_resource(struct r600_common_screen *rscreen,
 688                          struct r600_resource *res);
 689 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 690                                          const struct pipe_resource *templ,
 691                                          unsigned alignment);
 692 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
 693                                                   unsigned flags,
 694                                                   unsigned usage,
 695                                                   unsigned size,
 696                                                   unsigned alignment);
 697 struct pipe_resource *
 698 r600_buffer_from_user_memory(struct pipe_screen *screen,
 699                              const struct pipe_resource *templ,
 700                              void *user_memory);
 701 void
 702 r600_invalidate_resource(struct pipe_context *ctx,
 703                          struct pipe_resource *resource);
 704
 705 /* r600_common_pipe.c */
 706 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
 707                               unsigned event, unsigned event_flags,
 708                               unsigned data_sel,
 709                               struct r600_resource *buf, uint64_t va,
 710                               uint32_t old_fence, uint32_t new_fence);
 711 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen);
 712 void r600_gfx_wait_fence(struct r600_common_context *ctx,
 713                          uint64_t va, uint32_t ref, uint32_t mask);
 714 void r600_draw_rectangle(struct blitter_context *blitter,
 715                          int x1, int y1, int x2, int y2, float depth,
 716                          enum blitter_attrib_type type,
 717                          const union pipe_color_union *attrib);
 718 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 719                              struct radeon_winsys *ws);
 720 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 721 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 722 void r600_postflush_resume_features(struct r600_common_context *ctx);
 723 bool r600_common_context_init(struct r600_common_context *rctx,
 724                               struct r600_common_screen *rscreen,
 725                               unsigned context_flags);
 726 void r600_common_context_cleanup(struct r600_common_context *rctx);
 727 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 728                           unsigned processor);
 729 bool r600_extra_shader_checks(struct r600_common_screen *rscreen,
 730                               unsigned processor);
 731 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 732                               uint64_t offset, uint64_t size, unsigned value);
 733 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 734                                                   const struct pipe_resource *templ);
 735 const char *r600_get_llvm_processor_name(enum radeon_family family);
 736 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
 737                          struct r600_resource *dst, struct r600_resource *src);
 738 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
 739                     struct radeon_saved_cs *saved);
 740 void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
 741 bool r600_check_device_reset(struct r600_common_context *rctx);
 742
 743 /* r600_gpu_load.c */
 744 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 745 uint64_t r600_begin_counter(struct r600_common_screen *rscreen, unsigned type);
 746 unsigned r600_end_counter(struct r600_common_screen *rscreen, unsigned type,
 747                           uint64_t begin);
 748
 749 /* r600_perfcounters.c */
 750 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
 751
 752 /* r600_query.c */
 753 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
 754 void r600_query_init(struct r600_common_context *rctx);
 755 void r600_suspend_queries(struct r600_common_context *ctx);
 756 void r600_resume_queries(struct r600_common_context *ctx);
 757 void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen);
 758
 759 /* r600_streamout.c */
 760 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 761 void r600_set_streamout_targets(struct pipe_context *ctx,
 762                                 unsigned num_targets,
 763                                 struct pipe_stream_output_target **targets,
 764                                 const unsigned *offset);
 765 void r600_emit_streamout_end(struct r600_common_context *rctx);
 766 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 767                                              unsigned type, int diff);
 768 void r600_streamout_init(struct r600_common_context *rctx);
 769
 770 /* r600_test_dma.c */
 771 void r600_test_dma(struct r600_common_screen *rscreen);
 772
 773 /* r600_texture.c */
 774 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
 775                                 struct r600_texture *rdst,
 776                                 unsigned dst_level, unsigned dstx,
 777                                 unsigned dsty, unsigned dstz,
 778                                 struct r600_texture *rsrc,
 779                                 unsigned src_level,
 780                                 const struct pipe_box *src_box);
 781 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 782                                  struct r600_texture *rtex,
 783                                  unsigned nr_samples,
 784                                  struct r600_fmask_info *out);
 785 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 786                                  struct r600_texture *rtex,
 787                                  struct r600_cmask_info *out);
 788 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 789                                      struct pipe_resource *texture,
 790                                      struct r600_texture **staging);
 791 void r600_print_texture_info(struct r600_common_screen *rscreen,
 792                              struct r600_texture *rtex, FILE *f);
 793 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 794                                         const struct pipe_resource *templ);
 795 bool vi_dcc_formats_compatible(enum pipe_format format1,
 796                                enum pipe_format format2);
 797 void vi_dcc_disable_if_incompatible_format(struct r600_common_context *rctx,
 798                                            struct pipe_resource *tex,
 799                                            unsigned level,
 800                                            enum pipe_format view_format);
 801 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 802                                                 struct pipe_resource *texture,
 803                                                 const struct pipe_surface *templ,
 804                                                 unsigned width, unsigned height);
 805 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
 806 void vi_separate_dcc_start_query(struct pipe_context *ctx,
 807                                  struct r600_texture *tex);
 808 void vi_separate_dcc_stop_query(struct pipe_context *ctx,
 809                                 struct r600_texture *tex);
 810 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
 811                                              struct r600_texture *tex);
 812 void vi_dcc_clear_level(struct r600_common_context *rctx,
 813                         struct r600_texture *rtex,
 814                         unsigned level, unsigned clear_value);
 815 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 816                                    struct pipe_framebuffer_state *fb,
 817                                    struct r600_atom *fb_state,
 818                                    unsigned *buffers, unsigned *dirty_cbufs,
 819                                    const union pipe_color_union *color);
 820 bool r600_texture_disable_dcc(struct r600_common_context *rctx,
 821                               struct r600_texture *rtex);
 822 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 823 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 824
 825 /* r600_viewport.c */
 826 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
 827                                             struct pipe_scissor_state *scissor);
 828 void r600_viewport_set_rast_deps(struct r600_common_context *rctx,
 829                                  bool scissor_enable, bool clip_halfz);
 830 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
 831                                           struct tgsi_shader_info *info);
 832 void r600_init_viewport_functions(struct r600_common_context *rctx);
 833
 834 /* cayman_msaa.c */
 835 extern const uint32_t eg_sample_locs_2x[4];
 836 extern const unsigned eg_max_dist_2x;
 837 extern const uint32_t eg_sample_locs_4x[4];
 838 extern const unsigned eg_max_dist_4x;
 839 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 840                                 unsigned sample_index, float *out_value);
 841 void cayman_init_msaa(struct pipe_context *ctx);
 842 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 843 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 844                              int ps_iter_samples, int overrast_samples,
 845                              unsigned sc_mode_cntl_1);
 846
 847
 848 /* Inline helpers. */
 849
 850 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 851 {
 852         return (struct r600_resource*)r;
 853 }
 854
 855 static inline void
 856 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 857 {
 858         pipe_resource_reference((struct pipe_resource **)ptr,
 859                                 (struct pipe_resource *)res);
 860 }
 861
 862 static inline void
 863 r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
 864 {
 865         pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
 866 }
 867
 868 static inline void
 869 r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 870 {
 871         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 872         struct r600_resource *res = (struct r600_resource *)r;
 873
 874         if (res) {
 875                 /* Add memory usage for need_gfx_cs_space */
 876                 rctx->vram += res->vram_usage;
 877                 rctx->gtt += res->gart_usage;
 878         }
 879 }
 880
 881 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
 882 {
 883         return rctx->streamout.streamout_enabled ||
 884                rctx->streamout.prims_gen_query_enabled;
 885 }
 886
 887 #define     SQ_TEX_XY_FILTER_POINT                         0x00
 888 #define     SQ_TEX_XY_FILTER_BILINEAR                      0x01
 889 #define     SQ_TEX_XY_FILTER_ANISO_POINT                   0x02
 890 #define     SQ_TEX_XY_FILTER_ANISO_BILINEAR                0x03
 891
 892 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
 893 {
 894         if (filter == PIPE_TEX_FILTER_LINEAR)
 895                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
 896                                      : SQ_TEX_XY_FILTER_BILINEAR;
 897         else
 898                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
 899                                      : SQ_TEX_XY_FILTER_POINT;
 900 }
 901
 902 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 903 {
 904         if (filter < 2)
 905                 return 0;
 906         if (filter < 4)
 907                 return 1;
 908         if (filter < 8)
 909                 return 2;
 910         if (filter < 16)
 911                 return 3;
 912         return 4;
 913 }
 914
 915 static inline unsigned r600_wavefront_size(enum radeon_family family)
 916 {
 917         switch (family) {
 918         case CHIP_RV610:
 919         case CHIP_RS780:
 920         case CHIP_RV620:
 921         case CHIP_RS880:
 922                 return 16;
 923         case CHIP_RV630:
 924         case CHIP_RV635:
 925         case CHIP_RV730:
 926         case CHIP_RV710:
 927         case CHIP_PALM:
 928         case CHIP_CEDAR:
 929                 return 32;
 930         default:
 931                 return 64;
 932         }
 933 }
 934
 935 static inline enum radeon_bo_priority
 936 r600_get_sampler_view_priority(struct r600_resource *res)
 937 {
 938         if (res->b.b.target == PIPE_BUFFER)
 939                 return RADEON_PRIO_SAMPLER_BUFFER;
 940
 941         if (res->b.b.nr_samples > 1)
 942                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 943
 944         return RADEON_PRIO_SAMPLER_TEXTURE;
 945 }
 946
 947 static inline bool
 948 r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
 949 {
 950         return (stencil_sampler && tex->can_sample_s) ||
 951                (!stencil_sampler && tex->can_sample_z);
 952 }
 953
 954 #define COMPUTE_DBG(rscreen, fmt, args...) \
 955         do { \
 956                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 957         } while (0);
 958
 959 #define R600_ERR(fmt, args...) \
 960         fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 961
 962 /* For MSAA sample positions. */
 963 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 964         (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) |                  \
 965         (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) |         \
 966         (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) |        \
 967          (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
 968
 969 #endif