src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/u_slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define ATI_VENDOR_ID 0x1002
  47
  48 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  49 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  50 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  51 #define R600_RESOURCE_FLAG_DISABLE_DCC          (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
  52
  53 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  54 /* Pipeline & streamout query controls. */
  55 #define R600_CONTEXT_START_PIPELINE_STATS       (1u << 1)
  56 #define R600_CONTEXT_STOP_PIPELINE_STATS        (1u << 2)
  57 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 3)
  58
  59 /* special primitive types */
  60 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  61
  62 /* Debug flags. */
  63 /* logging */
  64 #define DBG_TEX                 (1 << 0)
  65 /* gap - reuse */
  66 #define DBG_COMPUTE             (1 << 2)
  67 #define DBG_VM                  (1 << 3)
  68 /* gap - reuse */
  69 /* shader logging */
  70 #define DBG_FS                  (1 << 5)
  71 #define DBG_VS                  (1 << 6)
  72 #define DBG_GS                  (1 << 7)
  73 #define DBG_PS                  (1 << 8)
  74 #define DBG_CS                  (1 << 9)
  75 #define DBG_TCS                 (1 << 10)
  76 #define DBG_TES                 (1 << 11)
  77 #define DBG_NO_IR               (1 << 12)
  78 #define DBG_NO_TGSI             (1 << 13)
  79 #define DBG_NO_ASM              (1 << 14)
  80 #define DBG_PREOPT_IR           (1 << 15)
  81 /* gaps */
  82 #define DBG_TEST_DMA            (1 << 20)
  83 /* Bits 21-31 are reserved for the r600g driver. */
  84 /* features */
  85 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  86 #define DBG_NO_HYPERZ           (1llu << 33)
  87 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  88 #define DBG_NO_2D_TILING        (1llu << 35)
  89 #define DBG_NO_TILING           (1llu << 36)
  90 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  91 #define DBG_FORCE_DMA           (1llu << 38)
  92 #define DBG_PRECOMPILE          (1llu << 39)
  93 #define DBG_INFO                (1llu << 40)
  94 #define DBG_NO_WC               (1llu << 41)
  95 #define DBG_CHECK_VM            (1llu << 42)
  96 #define DBG_NO_DCC              (1llu << 43)
  97 #define DBG_NO_DCC_CLEAR        (1llu << 44)
  98 #define DBG_NO_RB_PLUS          (1llu << 45)
  99 #define DBG_SI_SCHED            (1llu << 46)
 100 #define DBG_MONOLITHIC_SHADERS  (1llu << 47)
 101 #define DBG_NO_CE               (1llu << 48)
 102 #define DBG_UNSAFE_MATH         (1llu << 49)
 103 #define DBG_NO_DCC_FB           (1llu << 50)
 104
 105 #define R600_MAP_BUFFER_ALIGNMENT 64
 106 #define R600_MAX_VIEWPORTS        16
 107
 108 enum r600_coherency {
 109         R600_COHERENCY_NONE, /* no cache flushes needed */
 110         R600_COHERENCY_SHADER,
 111         R600_COHERENCY_CB_META,
 112 };
 113
 114 #ifdef PIPE_ARCH_BIG_ENDIAN
 115 #define R600_BIG_ENDIAN 1
 116 #else
 117 #define R600_BIG_ENDIAN 0
 118 #endif
 119
 120 struct r600_common_context;
 121 struct r600_perfcounters;
 122 struct tgsi_shader_info;
 123
 124 struct radeon_shader_reloc {
 125         char name[32];
 126         uint64_t offset;
 127 };
 128
 129 struct radeon_shader_binary {
 130         /** Shader code */
 131         unsigned char *code;
 132         unsigned code_size;
 133
 134         /** Config/Context register state that accompanies this shader.
 135          * This is a stream of dword pairs.  First dword contains the
 136          * register address, the second dword contains the value.*/
 137         unsigned char *config;
 138         unsigned config_size;
 139
 140         /** The number of bytes of config information for each global symbol.
 141          */
 142         unsigned config_size_per_symbol;
 143
 144         /** Constant data accessed by the shader.  This will be uploaded
 145          * into a constant buffer. */
 146         unsigned char *rodata;
 147         unsigned rodata_size;
 148
 149         /** List of symbol offsets for the shader */
 150         uint64_t *global_symbol_offsets;
 151         unsigned global_symbol_count;
 152
 153         struct radeon_shader_reloc *relocs;
 154         unsigned reloc_count;
 155
 156         /** Disassembled shader in a string. */
 157         char *disasm_string;
 158         char *llvm_ir_string;
 159 };
 160
 161 void radeon_shader_binary_init(struct radeon_shader_binary *b);
 162 void radeon_shader_binary_clean(struct radeon_shader_binary *b);
 163
 164 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
 165  * at the moment.
 166  */
 167 struct r600_resource {
 168         struct u_resource               b;
 169
 170         /* Winsys objects. */
 171         struct pb_buffer                *buf;
 172         uint64_t                        gpu_address;
 173         /* Memory usage if the buffer placement is optimal. */
 174         uint64_t                        vram_usage;
 175         uint64_t                        gart_usage;
 176
 177         /* Resource state. */
 178         enum radeon_bo_domain           domains;
 179
 180         /* The buffer range which is initialized (with a write transfer,
 181          * streamout, DMA, or as a random access target). The rest of
 182          * the buffer is considered invalid and can be mapped unsynchronized.
 183          *
 184          * This allows unsychronized mapping of a buffer range which hasn't
 185          * been used yet. It's for applications which forget to use
 186          * the unsynchronized map flag and expect the driver to figure it out.
 187          */
 188         struct util_range               valid_buffer_range;
 189
 190         /* For buffers only. This indicates that a write operation has been
 191          * performed by TC L2, but the cache hasn't been flushed.
 192          * Any hw block which doesn't use or bypasses TC L2 should check this
 193          * flag and flush the cache before using the buffer.
 194          *
 195          * For example, TC L2 must be flushed if a buffer which has been
 196          * modified by a shader store instruction is about to be used as
 197          * an index buffer. The reason is that VGT DMA index fetching doesn't
 198          * use TC L2.
 199          */
 200         bool                            TC_L2_dirty;
 201
 202         /* Whether the resource has been exported via resource_get_handle. */
 203         bool                            is_shared;
 204         unsigned                        external_usage; /* PIPE_HANDLE_USAGE_* */
 205 };
 206
 207 struct r600_transfer {
 208         struct pipe_transfer            transfer;
 209         struct r600_resource            *staging;
 210         unsigned                        offset;
 211 };
 212
 213 struct r600_fmask_info {
 214         uint64_t offset;
 215         uint64_t size;
 216         unsigned alignment;
 217         unsigned pitch_in_pixels;
 218         unsigned bank_height;
 219         unsigned slice_tile_max;
 220         unsigned tile_mode_index;
 221 };
 222
 223 struct r600_cmask_info {
 224         uint64_t offset;
 225         uint64_t size;
 226         unsigned alignment;
 227         unsigned pitch;
 228         unsigned height;
 229         unsigned xalign;
 230         unsigned yalign;
 231         unsigned slice_tile_max;
 232         unsigned base_address_reg;
 233 };
 234
 235 struct r600_htile_info {
 236         unsigned pitch;
 237         unsigned height;
 238         unsigned xalign;
 239         unsigned yalign;
 240 };
 241
 242 struct r600_texture {
 243         struct r600_resource            resource;
 244
 245         uint64_t                        size;
 246         unsigned                        num_level0_transfers;
 247         bool                            is_depth;
 248         bool                            db_compatible;
 249         bool                            can_sample_z;
 250         bool                            can_sample_s;
 251         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 252         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 253         struct r600_texture             *flushed_depth_texture;
 254         struct radeon_surf              surface;
 255
 256         /* Colorbuffer compression and fast clear. */
 257         struct r600_fmask_info          fmask;
 258         struct r600_cmask_info          cmask;
 259         struct r600_resource            *cmask_buffer;
 260         uint64_t                        dcc_offset; /* 0 = disabled */
 261         unsigned                        cb_color_info; /* fast clear enable bit */
 262         unsigned                        color_clear_value[2];
 263         unsigned                        last_msaa_resolve_target_micro_mode;
 264
 265         /* Depth buffer compression and fast clear. */
 266         struct r600_htile_info          htile;
 267         struct r600_resource            *htile_buffer;
 268         bool                            depth_cleared; /* if it was cleared at least once */
 269         float                           depth_clear_value;
 270         bool                            stencil_cleared; /* if it was cleared at least once */
 271         uint8_t                         stencil_clear_value;
 272
 273         bool                            non_disp_tiling; /* R600-Cayman only */
 274
 275         /* Whether the texture is a displayable back buffer and needs DCC
 276          * decompression, which is expensive. Therefore, it's enabled only
 277          * if statistics suggest that it will pay off and it's allocated
 278          * separately. It can't be bound as a sampler by apps. Limited to
 279          * target == 2D and last_level == 0. If enabled, dcc_offset contains
 280          * the absolute GPUVM address, not the relative one.
 281          */
 282         struct r600_resource            *dcc_separate_buffer;
 283         /* When DCC is temporarily disabled, the separate buffer is here. */
 284         struct r600_resource            *last_dcc_separate_buffer;
 285         /* We need to track DCC dirtiness, because st/dri usually calls
 286          * flush_resource twice per frame (not a bug) and we don't wanna
 287          * decompress DCC twice. Also, the dirty tracking must be done even
 288          * if DCC isn't used, because it's required by the DCC usage analysis
 289          * for a possible future enablement.
 290          */
 291         bool                            separate_dcc_dirty;
 292         /* Statistics gathering for the DCC enablement heuristic. */
 293         bool                            dcc_gather_statistics;
 294         /* Estimate of how much this color buffer is written to in units of
 295          * full-screen draws: ps_invocations / (width * height)
 296          * Shader kills, late Z, and blending with trivial discards make it
 297          * inaccurate (we need to count CB updates, not PS invocations).
 298          */
 299         unsigned                        ps_draw_ratio;
 300         /* The number of clears since the last DCC usage analysis. */
 301         unsigned                        num_slow_clears;
 302
 303         /* Counter that should be non-zero if the texture is bound to a
 304          * framebuffer. Implemented in radeonsi only.
 305          */
 306         uint32_t                        framebuffers_bound;
 307 };
 308
 309 struct r600_surface {
 310         struct pipe_surface             base;
 311         const struct radeon_surf_level  *level_info;
 312
 313         bool color_initialized;
 314         bool depth_initialized;
 315
 316         /* Misc. color flags. */
 317         bool alphatest_bypass;
 318         bool export_16bpc;
 319         bool color_is_int8;
 320
 321         /* Color registers. */
 322         unsigned cb_color_info;
 323         unsigned cb_color_base;
 324         unsigned cb_color_view;
 325         unsigned cb_color_size;         /* R600 only */
 326         unsigned cb_color_dim;          /* EG only */
 327         unsigned cb_color_pitch;        /* EG and later */
 328         unsigned cb_color_slice;        /* EG and later */
 329         unsigned cb_color_attrib;       /* EG and later */
 330         unsigned cb_dcc_control;        /* VI and later */
 331         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 332         unsigned cb_color_fmask_slice;  /* EG and later */
 333         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 334         unsigned cb_color_mask;         /* R600 only */
 335         unsigned spi_shader_col_format;         /* SI+, no blending, no alpha-to-coverage. */
 336         unsigned spi_shader_col_format_alpha;   /* SI+, alpha-to-coverage */
 337         unsigned spi_shader_col_format_blend;   /* SI+, blending without alpha. */
 338         unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
 339         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 340         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 341
 342         /* DB registers. */
 343         unsigned db_depth_info;         /* R600 only, then SI and later */
 344         unsigned db_z_info;             /* EG and later */
 345         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 346         unsigned db_depth_view;
 347         unsigned db_depth_size;
 348         unsigned db_depth_slice;        /* EG and later */
 349         unsigned db_stencil_base;       /* EG and later */
 350         unsigned db_stencil_info;       /* EG and later */
 351         unsigned db_prefetch_limit;     /* R600 only */
 352         unsigned db_htile_surface;
 353         unsigned db_htile_data_base;
 354         unsigned db_preload_control;    /* EG and later */
 355 };
 356
 357 struct r600_common_screen {
 358         struct pipe_screen              b;
 359         struct radeon_winsys            *ws;
 360         enum radeon_family              family;
 361         enum chip_class                 chip_class;
 362         struct radeon_info              info;
 363         uint64_t                        debug_flags;
 364         bool                            has_cp_dma;
 365         bool                            has_streamout;
 366
 367         /* Texture filter settings. */
 368         int                             force_aniso; /* -1 = disabled */
 369
 370         /* Auxiliary context. Mainly used to initialize resources.
 371          * It must be locked prior to using and flushed before unlocking. */
 372         struct pipe_context             *aux_context;
 373         pipe_mutex                      aux_context_lock;
 374
 375         /* This must be in the screen, because UE4 uses one context for
 376          * compilation and another one for rendering.
 377          */
 378         unsigned                        num_compilations;
 379         /* Along with ST_DEBUG=precompile, this should show if applications
 380          * are loading shaders on demand. This is a monotonic counter.
 381          */
 382         unsigned                        num_shaders_created;
 383
 384         /* GPU load thread. */
 385         pipe_mutex                      gpu_load_mutex;
 386         pipe_thread                     gpu_load_thread;
 387         unsigned                        gpu_load_counter_busy;
 388         unsigned                        gpu_load_counter_idle;
 389         volatile unsigned               gpu_load_stop_thread; /* bool */
 390
 391         char                            renderer_string[100];
 392
 393         /* Performance counters. */
 394         struct r600_perfcounters        *perfcounters;
 395
 396         /* If pipe_screen wants to re-emit the framebuffer state of all
 397          * contexts, it should atomically increment this. Each context will
 398          * compare this with its own last known value of the counter before
 399          * drawing and re-emit the framebuffer state accordingly.
 400          */
 401         unsigned                        dirty_fb_counter;
 402
 403         /* Atomically increment this counter when an existing texture's
 404          * metadata is enabled or disabled in a way that requires changing
 405          * contexts' compressed texture binding masks.
 406          */
 407         unsigned                        compressed_colortex_counter;
 408
 409         /* Atomically increment this counter when an existing texture's
 410          * backing buffer or tile mode parameters have changed that requires
 411          * recomputation of shader descriptors.
 412          */
 413         unsigned                        dirty_tex_descriptor_counter;
 414
 415         void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
 416                                       struct r600_texture *rtex,
 417                                       struct radeon_bo_metadata *md);
 418
 419         void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
 420                                     struct r600_texture *rtex,
 421                                     struct radeon_bo_metadata *md);
 422 };
 423
 424 /* This encapsulates a state or an operation which can emitted into the GPU
 425  * command stream. */
 426 struct r600_atom {
 427         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 428         unsigned                num_dw;
 429         unsigned short          id;
 430 };
 431
 432 struct r600_so_target {
 433         struct pipe_stream_output_target b;
 434
 435         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 436         struct r600_resource    *buf_filled_size;
 437         unsigned                buf_filled_size_offset;
 438         bool                    buf_filled_size_valid;
 439
 440         unsigned                stride_in_dw;
 441 };
 442
 443 struct r600_streamout {
 444         struct r600_atom                begin_atom;
 445         bool                            begin_emitted;
 446         unsigned                        num_dw_for_end;
 447
 448         unsigned                        enabled_mask;
 449         unsigned                        num_targets;
 450         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 451
 452         unsigned                        append_bitmask;
 453         bool                            suspended;
 454
 455         /* External state which comes from the vertex shader,
 456          * it must be set explicitly when binding a shader. */
 457         unsigned                        *stride_in_dw;
 458         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 459
 460         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 461         unsigned                        hw_enabled_mask;
 462
 463         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 464         struct r600_atom                enable_atom;
 465         bool                            streamout_enabled;
 466         bool                            prims_gen_query_enabled;
 467         int                             num_prims_gen_queries;
 468 };
 469
 470 struct r600_signed_scissor {
 471         int minx;
 472         int miny;
 473         int maxx;
 474         int maxy;
 475 };
 476
 477 struct r600_scissors {
 478         struct r600_atom                atom;
 479         unsigned                        dirty_mask;
 480         struct pipe_scissor_state       states[R600_MAX_VIEWPORTS];
 481 };
 482
 483 struct r600_viewports {
 484         struct r600_atom                atom;
 485         unsigned                        dirty_mask;
 486         struct pipe_viewport_state      states[R600_MAX_VIEWPORTS];
 487         struct r600_signed_scissor      as_scissor[R600_MAX_VIEWPORTS];
 488 };
 489
 490 struct r600_ring {
 491         struct radeon_winsys_cs         *cs;
 492         void (*flush)(void *ctx, unsigned flags,
 493                       struct pipe_fence_handle **fence);
 494 };
 495
 496 /* Saved CS data for debugging features. */
 497 struct radeon_saved_cs {
 498         uint32_t                        *ib;
 499         unsigned                        num_dw;
 500
 501         struct radeon_bo_list_item      *bo_list;
 502         unsigned                        bo_count;
 503 };
 504
 505 struct r600_common_context {
 506         struct pipe_context b; /* base class */
 507
 508         struct r600_common_screen       *screen;
 509         struct radeon_winsys            *ws;
 510         struct radeon_winsys_ctx        *ctx;
 511         enum radeon_family              family;
 512         enum chip_class                 chip_class;
 513         struct r600_ring                gfx;
 514         struct r600_ring                dma;
 515         struct pipe_fence_handle        *last_gfx_fence;
 516         struct pipe_fence_handle        *last_sdma_fence;
 517         unsigned                        num_gfx_cs_flushes;
 518         unsigned                        initial_gfx_cs_size;
 519         unsigned                        gpu_reset_counter;
 520         unsigned                        last_dirty_fb_counter;
 521         unsigned                        last_compressed_colortex_counter;
 522         unsigned                        last_dirty_tex_descriptor_counter;
 523
 524         struct u_upload_mgr             *uploader;
 525         struct u_suballocator           *allocator_zeroed_memory;
 526         struct util_slab_mempool        pool_transfers;
 527
 528         /* Current unaccounted memory usage. */
 529         uint64_t                        vram;
 530         uint64_t                        gtt;
 531
 532         /* States. */
 533         struct r600_streamout           streamout;
 534         struct r600_scissors            scissors;
 535         struct r600_viewports           viewports;
 536         bool                            scissor_enabled;
 537         bool                            vs_writes_viewport_index;
 538         bool                            vs_disables_clipping_viewport;
 539
 540         /* Additional context states. */
 541         unsigned flags; /* flush flags */
 542
 543         /* Queries. */
 544         /* Maintain the list of active queries for pausing between IBs. */
 545         int                             num_occlusion_queries;
 546         int                             num_perfect_occlusion_queries;
 547         struct list_head                active_queries;
 548         unsigned                        num_cs_dw_queries_suspend;
 549         /* Additional hardware info. */
 550         unsigned                        backend_mask;
 551         unsigned                        max_db; /* for OQ */
 552         /* Misc stats. */
 553         unsigned                        num_draw_calls;
 554         unsigned                        num_spill_draw_calls;
 555         unsigned                        num_compute_calls;
 556         unsigned                        num_spill_compute_calls;
 557         unsigned                        num_dma_calls;
 558         uint64_t                        num_alloc_tex_transfer_bytes;
 559         unsigned                        last_tex_ps_draw_ratio; /* for query */
 560
 561         /* Render condition. */
 562         struct r600_atom                render_cond_atom;
 563         struct pipe_query               *render_cond;
 564         unsigned                        render_cond_mode;
 565         bool                            render_cond_invert;
 566         bool                            render_cond_force_off; /* for u_blitter */
 567
 568         /* MSAA sample locations.
 569          * The first index is the sample index.
 570          * The second index is the coordinate: X, Y. */
 571         float                           sample_locations_1x[1][2];
 572         float                           sample_locations_2x[2][2];
 573         float                           sample_locations_4x[4][2];
 574         float                           sample_locations_8x[8][2];
 575         float                           sample_locations_16x[16][2];
 576
 577         /* Statistics gathering for the DCC enablement heuristic. It can't be
 578          * in r600_texture because r600_texture can be shared by multiple
 579          * contexts. This is for back buffers only. We shouldn't get too many
 580          * of those.
 581          *
 582          * X11 DRI3 rotates among a finite set of back buffers. They should
 583          * all fit in this array. If they don't, separate DCC might never be
 584          * enabled by DCC stat gathering.
 585          */
 586         struct {
 587                 struct r600_texture             *tex;
 588                 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
 589                 struct pipe_query               *ps_stats[3];
 590                 /* If all slots are used and another slot is needed,
 591                  * the least recently used slot is evicted based on this. */
 592                 int64_t                         last_use_timestamp;
 593                 bool                            query_active;
 594         } dcc_stats[5];
 595
 596         /* The list of all texture buffer objects in this context.
 597          * This list is walked when a buffer is invalidated/reallocated and
 598          * the GPU addresses are updated. */
 599         struct list_head                texture_buffers;
 600
 601         struct pipe_debug_callback      debug;
 602
 603         /* Copy one resource to another using async DMA. */
 604         void (*dma_copy)(struct pipe_context *ctx,
 605                          struct pipe_resource *dst,
 606                          unsigned dst_level,
 607                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 608                          struct pipe_resource *src,
 609                          unsigned src_level,
 610                          const struct pipe_box *src_box);
 611
 612         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 613                              uint64_t offset, uint64_t size, unsigned value,
 614                              enum r600_coherency coher);
 615
 616         void (*blit_decompress_depth)(struct pipe_context *ctx,
 617                                       struct r600_texture *texture,
 618                                       struct r600_texture *staging,
 619                                       unsigned first_level, unsigned last_level,
 620                                       unsigned first_layer, unsigned last_layer,
 621                                       unsigned first_sample, unsigned last_sample);
 622
 623         void (*decompress_dcc)(struct pipe_context *ctx,
 624                                struct r600_texture *rtex);
 625
 626         /* Reallocate the buffer and update all resource bindings where
 627          * the buffer is bound, including all resource descriptors. */
 628         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 629
 630         /* Enable or disable occlusion queries. */
 631         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 632
 633         /* This ensures there is enough space in the command stream. */
 634         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 635                                   bool include_draw_vbo);
 636
 637         void (*set_atom_dirty)(struct r600_common_context *ctx,
 638                                struct r600_atom *atom, bool dirty);
 639
 640         void (*check_vm_faults)(struct r600_common_context *ctx,
 641                                 struct radeon_saved_cs *saved,
 642                                 enum ring_type ring);
 643 };
 644
 645 /* r600_buffer.c */
 646 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 647                                      struct pb_buffer *buf,
 648                                      enum radeon_bo_usage usage);
 649 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 650                                       struct r600_resource *resource,
 651                                       unsigned usage);
 652 void r600_buffer_subdata(struct pipe_context *ctx,
 653                          struct pipe_resource *buffer,
 654                          unsigned usage, unsigned offset,
 655                          unsigned size, const void *data);
 656 bool r600_init_resource(struct r600_common_screen *rscreen,
 657                         struct r600_resource *res,
 658                         uint64_t size, unsigned alignment);
 659 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 660                                          const struct pipe_resource *templ,
 661                                          unsigned alignment);
 662 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
 663                                                   unsigned bind,
 664                                                   unsigned usage,
 665                                                   unsigned size,
 666                                                   unsigned alignment);
 667 struct pipe_resource *
 668 r600_buffer_from_user_memory(struct pipe_screen *screen,
 669                              const struct pipe_resource *templ,
 670                              void *user_memory);
 671 void
 672 r600_invalidate_resource(struct pipe_context *ctx,
 673                          struct pipe_resource *resource);
 674
 675 /* r600_common_pipe.c */
 676 void r600_draw_rectangle(struct blitter_context *blitter,
 677                          int x1, int y1, int x2, int y2, float depth,
 678                          enum blitter_attrib_type type,
 679                          const union pipe_color_union *attrib);
 680 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 681                              struct radeon_winsys *ws);
 682 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 683 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 684 void r600_postflush_resume_features(struct r600_common_context *ctx);
 685 bool r600_common_context_init(struct r600_common_context *rctx,
 686                               struct r600_common_screen *rscreen,
 687                               unsigned context_flags);
 688 void r600_common_context_cleanup(struct r600_common_context *rctx);
 689 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 690 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 691                           unsigned processor);
 692 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 693                               uint64_t offset, uint64_t size, unsigned value,
 694                               enum r600_coherency coher);
 695 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 696                                                   const struct pipe_resource *templ);
 697 const char *r600_get_llvm_processor_name(enum radeon_family family);
 698 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
 699                          struct r600_resource *dst, struct r600_resource *src);
 700 void r600_dma_emit_wait_idle(struct r600_common_context *rctx);
 701 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
 702                     struct radeon_saved_cs *saved);
 703 void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
 704
 705 /* r600_gpu_load.c */
 706 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 707 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 708 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 709
 710 /* r600_perfcounters.c */
 711 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
 712
 713 /* r600_query.c */
 714 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
 715 void r600_query_init(struct r600_common_context *rctx);
 716 void r600_suspend_queries(struct r600_common_context *ctx);
 717 void r600_resume_queries(struct r600_common_context *ctx);
 718 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 719
 720 /* r600_streamout.c */
 721 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 722 void r600_set_streamout_targets(struct pipe_context *ctx,
 723                                 unsigned num_targets,
 724                                 struct pipe_stream_output_target **targets,
 725                                 const unsigned *offset);
 726 void r600_emit_streamout_end(struct r600_common_context *rctx);
 727 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 728                                              unsigned type, int diff);
 729 void r600_streamout_init(struct r600_common_context *rctx);
 730
 731 /* r600_test_dma.c */
 732 void r600_test_dma(struct r600_common_screen *rscreen);
 733
 734 /* r600_texture.c */
 735 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
 736                                 struct r600_texture *rdst,
 737                                 unsigned dst_level, unsigned dstx,
 738                                 unsigned dsty, unsigned dstz,
 739                                 struct r600_texture *rsrc,
 740                                 unsigned src_level,
 741                                 const struct pipe_box *src_box);
 742 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 743                                  struct r600_texture *rtex,
 744                                  unsigned nr_samples,
 745                                  struct r600_fmask_info *out);
 746 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 747                                  struct r600_texture *rtex,
 748                                  struct r600_cmask_info *out);
 749 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 750                                      struct pipe_resource *texture,
 751                                      struct r600_texture **staging);
 752 void r600_print_texture_info(struct r600_texture *rtex, FILE *f);
 753 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 754                                         const struct pipe_resource *templ);
 755 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 756                                                 struct pipe_resource *texture,
 757                                                 const struct pipe_surface *templ,
 758                                                 unsigned width, unsigned height);
 759 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
 760 void vi_separate_dcc_start_query(struct pipe_context *ctx,
 761                                  struct r600_texture *tex);
 762 void vi_separate_dcc_stop_query(struct pipe_context *ctx,
 763                                 struct r600_texture *tex);
 764 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
 765                                              struct r600_texture *tex);
 766 void vi_dcc_clear_level(struct r600_common_context *rctx,
 767                         struct r600_texture *rtex,
 768                         unsigned level, unsigned clear_value);
 769 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 770                                    struct pipe_framebuffer_state *fb,
 771                                    struct r600_atom *fb_state,
 772                                    unsigned *buffers, unsigned *dirty_cbufs,
 773                                    const union pipe_color_union *color);
 774 bool r600_texture_disable_dcc(struct r600_common_context *rctx,
 775                               struct r600_texture *rtex);
 776 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 777 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 778
 779 /* r600_viewport.c */
 780 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
 781                                             struct pipe_scissor_state *scissor);
 782 void r600_set_scissor_enable(struct r600_common_context *rctx, bool enable);
 783 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
 784                                           struct tgsi_shader_info *info);
 785 void r600_init_viewport_functions(struct r600_common_context *rctx);
 786
 787 /* cayman_msaa.c */
 788 extern const uint32_t eg_sample_locs_2x[4];
 789 extern const unsigned eg_max_dist_2x;
 790 extern const uint32_t eg_sample_locs_4x[4];
 791 extern const unsigned eg_max_dist_4x;
 792 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 793                                 unsigned sample_index, float *out_value);
 794 void cayman_init_msaa(struct pipe_context *ctx);
 795 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 796 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 797                              int ps_iter_samples, int overrast_samples,
 798                              unsigned sc_mode_cntl_1);
 799
 800
 801 /* Inline helpers. */
 802
 803 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 804 {
 805         return (struct r600_resource*)r;
 806 }
 807
 808 static inline void
 809 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 810 {
 811         pipe_resource_reference((struct pipe_resource **)ptr,
 812                                 (struct pipe_resource *)res);
 813 }
 814
 815 static inline void
 816 r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
 817 {
 818         pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
 819 }
 820
 821 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
 822 {
 823         return rctx->streamout.streamout_enabled ||
 824                rctx->streamout.prims_gen_query_enabled;
 825 }
 826
 827 #define     SQ_TEX_XY_FILTER_POINT                         0x00
 828 #define     SQ_TEX_XY_FILTER_BILINEAR                      0x01
 829 #define     SQ_TEX_XY_FILTER_ANISO_POINT                   0x02
 830 #define     SQ_TEX_XY_FILTER_ANISO_BILINEAR                0x03
 831
 832 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
 833 {
 834         if (filter == PIPE_TEX_FILTER_LINEAR)
 835                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
 836                                      : SQ_TEX_XY_FILTER_BILINEAR;
 837         else
 838                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
 839                                      : SQ_TEX_XY_FILTER_POINT;
 840 }
 841
 842 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 843 {
 844         if (filter < 2)
 845                 return 0;
 846         if (filter < 4)
 847                 return 1;
 848         if (filter < 8)
 849                 return 2;
 850         if (filter < 16)
 851                 return 3;
 852         return 4;
 853 }
 854
 855 static inline unsigned r600_wavefront_size(enum radeon_family family)
 856 {
 857         switch (family) {
 858         case CHIP_RV610:
 859         case CHIP_RS780:
 860         case CHIP_RV620:
 861         case CHIP_RS880:
 862                 return 16;
 863         case CHIP_RV630:
 864         case CHIP_RV635:
 865         case CHIP_RV730:
 866         case CHIP_RV710:
 867         case CHIP_PALM:
 868         case CHIP_CEDAR:
 869                 return 32;
 870         default:
 871                 return 64;
 872         }
 873 }
 874
 875 static inline enum radeon_bo_priority
 876 r600_get_sampler_view_priority(struct r600_resource *res)
 877 {
 878         if (res->b.b.target == PIPE_BUFFER)
 879                 return RADEON_PRIO_SAMPLER_BUFFER;
 880
 881         if (res->b.b.nr_samples > 1)
 882                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 883
 884         return RADEON_PRIO_SAMPLER_TEXTURE;
 885 }
 886
 887 static inline bool
 888 r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
 889 {
 890         return (stencil_sampler && tex->can_sample_s) ||
 891                (!stencil_sampler && tex->can_sample_z);
 892 }
 893
 894 #define COMPUTE_DBG(rscreen, fmt, args...) \
 895         do { \
 896                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 897         } while (0);
 898
 899 #define R600_ERR(fmt, args...) \
 900         fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 901
 902 /* For MSAA sample positions. */
 903 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 904         (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) |                  \
 905         (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) |         \
 906         (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) |        \
 907          (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
 908
 909 #endif