src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define ATI_VENDOR_ID 0x1002
  47
  48 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  49 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  50 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  51 #define R600_RESOURCE_FLAG_DISABLE_DCC          (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
  52
  53 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  54 /* Pipeline & streamout query controls. */
  55 #define R600_CONTEXT_START_PIPELINE_STATS       (1u << 1)
  56 #define R600_CONTEXT_STOP_PIPELINE_STATS        (1u << 2)
  57 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 3)
  58
  59 /* special primitive types */
  60 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  61
  62 /* Debug flags. */
  63 /* logging */
  64 #define DBG_TEX                 (1 << 0)
  65 /* gap - reuse */
  66 #define DBG_COMPUTE             (1 << 2)
  67 #define DBG_VM                  (1 << 3)
  68 /* gap - reuse */
  69 /* shader logging */
  70 #define DBG_FS                  (1 << 5)
  71 #define DBG_VS                  (1 << 6)
  72 #define DBG_GS                  (1 << 7)
  73 #define DBG_PS                  (1 << 8)
  74 #define DBG_CS                  (1 << 9)
  75 #define DBG_TCS                 (1 << 10)
  76 #define DBG_TES                 (1 << 11)
  77 #define DBG_NO_IR               (1 << 12)
  78 #define DBG_NO_TGSI             (1 << 13)
  79 #define DBG_NO_ASM              (1 << 14)
  80 #define DBG_PREOPT_IR           (1 << 15)
  81 #define DBG_CHECK_IR            (1 << 16)
  82 #define DBG_NO_OPT_VARIANT      (1 << 17)
  83 /* gaps */
  84 #define DBG_TEST_DMA            (1 << 20)
  85 /* Bits 21-31 are reserved for the r600g driver. */
  86 /* features */
  87 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  88 #define DBG_NO_HYPERZ           (1llu << 33)
  89 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  90 #define DBG_NO_2D_TILING        (1llu << 35)
  91 #define DBG_NO_TILING           (1llu << 36)
  92 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  93 #define DBG_FORCE_DMA           (1llu << 38)
  94 #define DBG_PRECOMPILE          (1llu << 39)
  95 #define DBG_INFO                (1llu << 40)
  96 #define DBG_NO_WC               (1llu << 41)
  97 #define DBG_CHECK_VM            (1llu << 42)
  98 #define DBG_NO_DCC              (1llu << 43)
  99 #define DBG_NO_DCC_CLEAR        (1llu << 44)
 100 #define DBG_NO_RB_PLUS          (1llu << 45)
 101 #define DBG_SI_SCHED            (1llu << 46)
 102 #define DBG_MONOLITHIC_SHADERS  (1llu << 47)
 103 #define DBG_NO_CE               (1llu << 48)
 104 #define DBG_UNSAFE_MATH         (1llu << 49)
 105 #define DBG_NO_DCC_FB           (1llu << 50)
 106
 107 #define R600_MAP_BUFFER_ALIGNMENT 64
 108 #define R600_MAX_VIEWPORTS        16
 109
 110 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
 111
 112 enum r600_coherency {
 113         R600_COHERENCY_NONE, /* no cache flushes needed */
 114         R600_COHERENCY_SHADER,
 115         R600_COHERENCY_CB_META,
 116 };
 117
 118 #ifdef PIPE_ARCH_BIG_ENDIAN
 119 #define R600_BIG_ENDIAN 1
 120 #else
 121 #define R600_BIG_ENDIAN 0
 122 #endif
 123
 124 struct r600_common_context;
 125 struct r600_perfcounters;
 126 struct tgsi_shader_info;
 127 struct r600_qbo_state;
 128
 129 struct radeon_shader_reloc {
 130         char name[32];
 131         uint64_t offset;
 132 };
 133
 134 struct radeon_shader_binary {
 135         /** Shader code */
 136         unsigned char *code;
 137         unsigned code_size;
 138
 139         /** Config/Context register state that accompanies this shader.
 140          * This is a stream of dword pairs.  First dword contains the
 141          * register address, the second dword contains the value.*/
 142         unsigned char *config;
 143         unsigned config_size;
 144
 145         /** The number of bytes of config information for each global symbol.
 146          */
 147         unsigned config_size_per_symbol;
 148
 149         /** Constant data accessed by the shader.  This will be uploaded
 150          * into a constant buffer. */
 151         unsigned char *rodata;
 152         unsigned rodata_size;
 153
 154         /** List of symbol offsets for the shader */
 155         uint64_t *global_symbol_offsets;
 156         unsigned global_symbol_count;
 157
 158         struct radeon_shader_reloc *relocs;
 159         unsigned reloc_count;
 160
 161         /** Disassembled shader in a string. */
 162         char *disasm_string;
 163         char *llvm_ir_string;
 164 };
 165
 166 void radeon_shader_binary_init(struct radeon_shader_binary *b);
 167 void radeon_shader_binary_clean(struct radeon_shader_binary *b);
 168
 169 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
 170  * at the moment.
 171  */
 172 struct r600_resource {
 173         struct u_resource               b;
 174
 175         /* Winsys objects. */
 176         struct pb_buffer                *buf;
 177         uint64_t                        gpu_address;
 178         /* Memory usage if the buffer placement is optimal. */
 179         uint64_t                        vram_usage;
 180         uint64_t                        gart_usage;
 181
 182         /* Resource properties. */
 183         uint64_t                        bo_size;
 184         unsigned                        bo_alignment;
 185         enum radeon_bo_domain           domains;
 186         enum radeon_bo_flag             flags;
 187         unsigned                        bind_history;
 188
 189         /* The buffer range which is initialized (with a write transfer,
 190          * streamout, DMA, or as a random access target). The rest of
 191          * the buffer is considered invalid and can be mapped unsynchronized.
 192          *
 193          * This allows unsychronized mapping of a buffer range which hasn't
 194          * been used yet. It's for applications which forget to use
 195          * the unsynchronized map flag and expect the driver to figure it out.
 196          */
 197         struct util_range               valid_buffer_range;
 198
 199         /* For buffers only. This indicates that a write operation has been
 200          * performed by TC L2, but the cache hasn't been flushed.
 201          * Any hw block which doesn't use or bypasses TC L2 should check this
 202          * flag and flush the cache before using the buffer.
 203          *
 204          * For example, TC L2 must be flushed if a buffer which has been
 205          * modified by a shader store instruction is about to be used as
 206          * an index buffer. The reason is that VGT DMA index fetching doesn't
 207          * use TC L2.
 208          */
 209         bool                            TC_L2_dirty;
 210
 211         /* Whether the resource has been exported via resource_get_handle. */
 212         bool                            is_shared;
 213         unsigned                        external_usage; /* PIPE_HANDLE_USAGE_* */
 214 };
 215
 216 struct r600_transfer {
 217         struct pipe_transfer            transfer;
 218         struct r600_resource            *staging;
 219         unsigned                        offset;
 220 };
 221
 222 struct r600_fmask_info {
 223         uint64_t offset;
 224         uint64_t size;
 225         unsigned alignment;
 226         unsigned pitch_in_pixels;
 227         unsigned bank_height;
 228         unsigned slice_tile_max;
 229         unsigned tile_mode_index;
 230 };
 231
 232 struct r600_cmask_info {
 233         uint64_t offset;
 234         uint64_t size;
 235         unsigned alignment;
 236         unsigned slice_tile_max;
 237         unsigned base_address_reg;
 238 };
 239
 240 struct r600_texture {
 241         struct r600_resource            resource;
 242
 243         uint64_t                        size;
 244         unsigned                        num_level0_transfers;
 245         enum pipe_format                db_render_format;
 246         bool                            is_depth;
 247         bool                            db_compatible;
 248         bool                            can_sample_z;
 249         bool                            can_sample_s;
 250         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 251         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 252         struct r600_texture             *flushed_depth_texture;
 253         struct radeon_surf              surface;
 254
 255         /* Colorbuffer compression and fast clear. */
 256         struct r600_fmask_info          fmask;
 257         struct r600_cmask_info          cmask;
 258         struct r600_resource            *cmask_buffer;
 259         uint64_t                        dcc_offset; /* 0 = disabled */
 260         unsigned                        cb_color_info; /* fast clear enable bit */
 261         unsigned                        color_clear_value[2];
 262         unsigned                        last_msaa_resolve_target_micro_mode;
 263
 264         /* Depth buffer compression and fast clear. */
 265         struct r600_resource            *htile_buffer;
 266         bool                            tc_compatible_htile;
 267         bool                            depth_cleared; /* if it was cleared at least once */
 268         float                           depth_clear_value;
 269         bool                            stencil_cleared; /* if it was cleared at least once */
 270         uint8_t                         stencil_clear_value;
 271
 272         bool                            non_disp_tiling; /* R600-Cayman only */
 273
 274         /* Whether the texture is a displayable back buffer and needs DCC
 275          * decompression, which is expensive. Therefore, it's enabled only
 276          * if statistics suggest that it will pay off and it's allocated
 277          * separately. It can't be bound as a sampler by apps. Limited to
 278          * target == 2D and last_level == 0. If enabled, dcc_offset contains
 279          * the absolute GPUVM address, not the relative one.
 280          */
 281         struct r600_resource            *dcc_separate_buffer;
 282         /* When DCC is temporarily disabled, the separate buffer is here. */
 283         struct r600_resource            *last_dcc_separate_buffer;
 284         /* We need to track DCC dirtiness, because st/dri usually calls
 285          * flush_resource twice per frame (not a bug) and we don't wanna
 286          * decompress DCC twice. Also, the dirty tracking must be done even
 287          * if DCC isn't used, because it's required by the DCC usage analysis
 288          * for a possible future enablement.
 289          */
 290         bool                            separate_dcc_dirty;
 291         /* Statistics gathering for the DCC enablement heuristic. */
 292         bool                            dcc_gather_statistics;
 293         /* Estimate of how much this color buffer is written to in units of
 294          * full-screen draws: ps_invocations / (width * height)
 295          * Shader kills, late Z, and blending with trivial discards make it
 296          * inaccurate (we need to count CB updates, not PS invocations).
 297          */
 298         unsigned                        ps_draw_ratio;
 299         /* The number of clears since the last DCC usage analysis. */
 300         unsigned                        num_slow_clears;
 301
 302         /* Counter that should be non-zero if the texture is bound to a
 303          * framebuffer. Implemented in radeonsi only.
 304          */
 305         uint32_t                        framebuffers_bound;
 306 };
 307
 308 struct r600_surface {
 309         struct pipe_surface             base;
 310
 311         bool color_initialized;
 312         bool depth_initialized;
 313
 314         /* Misc. color flags. */
 315         bool alphatest_bypass;
 316         bool export_16bpc;
 317         bool color_is_int8;
 318
 319         /* Color registers. */
 320         unsigned cb_color_info;
 321         unsigned cb_color_base;
 322         unsigned cb_color_view;
 323         unsigned cb_color_size;         /* R600 only */
 324         unsigned cb_color_dim;          /* EG only */
 325         unsigned cb_color_pitch;        /* EG and later */
 326         unsigned cb_color_slice;        /* EG and later */
 327         unsigned cb_color_attrib;       /* EG and later */
 328         unsigned cb_dcc_control;        /* VI and later */
 329         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 330         unsigned cb_color_fmask_slice;  /* EG and later */
 331         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 332         unsigned cb_color_mask;         /* R600 only */
 333         unsigned spi_shader_col_format;         /* SI+, no blending, no alpha-to-coverage. */
 334         unsigned spi_shader_col_format_alpha;   /* SI+, alpha-to-coverage */
 335         unsigned spi_shader_col_format_blend;   /* SI+, blending without alpha. */
 336         unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
 337         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 338         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 339
 340         /* DB registers. */
 341         unsigned db_depth_info;         /* R600 only, then SI and later */
 342         unsigned db_z_info;             /* EG and later */
 343         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 344         unsigned db_depth_view;
 345         unsigned db_depth_size;
 346         unsigned db_depth_slice;        /* EG and later */
 347         unsigned db_stencil_base;       /* EG and later */
 348         unsigned db_stencil_info;       /* EG and later */
 349         unsigned db_prefetch_limit;     /* R600 only */
 350         unsigned db_htile_surface;
 351         unsigned db_htile_data_base;
 352         unsigned db_preload_control;    /* EG and later */
 353 };
 354
 355 struct r600_mmio_counter {
 356         unsigned busy;
 357         unsigned idle;
 358 };
 359
 360 union r600_mmio_counters {
 361         struct {
 362                 /* GRBM_STATUS */
 363                 struct r600_mmio_counter spi;
 364                 struct r600_mmio_counter gui;
 365                 struct r600_mmio_counter ta;
 366                 struct r600_mmio_counter gds;
 367                 struct r600_mmio_counter vgt;
 368                 struct r600_mmio_counter ia;
 369                 struct r600_mmio_counter sx;
 370                 struct r600_mmio_counter wd;
 371                 struct r600_mmio_counter bci;
 372                 struct r600_mmio_counter sc;
 373                 struct r600_mmio_counter pa;
 374                 struct r600_mmio_counter db;
 375                 struct r600_mmio_counter cp;
 376                 struct r600_mmio_counter cb;
 377         } named;
 378         unsigned array[0];
 379 };
 380
 381 struct r600_common_screen {
 382         struct pipe_screen              b;
 383         struct radeon_winsys            *ws;
 384         enum radeon_family              family;
 385         enum chip_class                 chip_class;
 386         struct radeon_info              info;
 387         uint64_t                        debug_flags;
 388         bool                            has_cp_dma;
 389         bool                            has_streamout;
 390
 391         struct slab_parent_pool         pool_transfers;
 392
 393         /* Texture filter settings. */
 394         int                             force_aniso; /* -1 = disabled */
 395
 396         /* Auxiliary context. Mainly used to initialize resources.
 397          * It must be locked prior to using and flushed before unlocking. */
 398         struct pipe_context             *aux_context;
 399         pipe_mutex                      aux_context_lock;
 400
 401         /* This must be in the screen, because UE4 uses one context for
 402          * compilation and another one for rendering.
 403          */
 404         unsigned                        num_compilations;
 405         /* Along with ST_DEBUG=precompile, this should show if applications
 406          * are loading shaders on demand. This is a monotonic counter.
 407          */
 408         unsigned                        num_shaders_created;
 409         unsigned                        num_shader_cache_hits;
 410
 411         /* GPU load thread. */
 412         pipe_mutex                      gpu_load_mutex;
 413         pipe_thread                     gpu_load_thread;
 414         union r600_mmio_counters        mmio_counters;
 415         volatile unsigned               gpu_load_stop_thread; /* bool */
 416
 417         char                            renderer_string[100];
 418
 419         /* Performance counters. */
 420         struct r600_perfcounters        *perfcounters;
 421
 422         /* If pipe_screen wants to re-emit the framebuffer state of all
 423          * contexts, it should atomically increment this. Each context will
 424          * compare this with its own last known value of the counter before
 425          * drawing and re-emit the framebuffer state accordingly.
 426          */
 427         unsigned                        dirty_fb_counter;
 428
 429         /* Atomically increment this counter when an existing texture's
 430          * metadata is enabled or disabled in a way that requires changing
 431          * contexts' compressed texture binding masks.
 432          */
 433         unsigned                        compressed_colortex_counter;
 434
 435         /* Atomically increment this counter when an existing texture's
 436          * backing buffer or tile mode parameters have changed that requires
 437          * recomputation of shader descriptors.
 438          */
 439         unsigned                        dirty_tex_descriptor_counter;
 440
 441         struct {
 442                 /* Context flags to set so that all writes from earlier jobs
 443                  * in the CP are seen by L2 clients.
 444                  */
 445                 unsigned cp_to_L2;
 446
 447                 /* Context flags to set so that all writes from earlier
 448                  * compute jobs are seen by L2 clients.
 449                  */
 450                 unsigned compute_to_L2;
 451         } barrier_flags;
 452
 453         void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
 454                                       struct r600_texture *rtex,
 455                                       struct radeon_bo_metadata *md);
 456
 457         void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
 458                                     struct r600_texture *rtex,
 459                                     struct radeon_bo_metadata *md);
 460 };
 461
 462 /* This encapsulates a state or an operation which can emitted into the GPU
 463  * command stream. */
 464 struct r600_atom {
 465         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 466         unsigned                num_dw;
 467         unsigned short          id;
 468 };
 469
 470 struct r600_so_target {
 471         struct pipe_stream_output_target b;
 472
 473         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 474         struct r600_resource    *buf_filled_size;
 475         unsigned                buf_filled_size_offset;
 476         bool                    buf_filled_size_valid;
 477
 478         unsigned                stride_in_dw;
 479 };
 480
 481 struct r600_streamout {
 482         struct r600_atom                begin_atom;
 483         bool                            begin_emitted;
 484         unsigned                        num_dw_for_end;
 485
 486         unsigned                        enabled_mask;
 487         unsigned                        num_targets;
 488         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 489
 490         unsigned                        append_bitmask;
 491         bool                            suspended;
 492
 493         /* External state which comes from the vertex shader,
 494          * it must be set explicitly when binding a shader. */
 495         unsigned                        *stride_in_dw;
 496         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 497
 498         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 499         unsigned                        hw_enabled_mask;
 500
 501         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 502         struct r600_atom                enable_atom;
 503         bool                            streamout_enabled;
 504         bool                            prims_gen_query_enabled;
 505         int                             num_prims_gen_queries;
 506 };
 507
 508 struct r600_signed_scissor {
 509         int minx;
 510         int miny;
 511         int maxx;
 512         int maxy;
 513 };
 514
 515 struct r600_scissors {
 516         struct r600_atom                atom;
 517         unsigned                        dirty_mask;
 518         struct pipe_scissor_state       states[R600_MAX_VIEWPORTS];
 519 };
 520
 521 struct r600_viewports {
 522         struct r600_atom                atom;
 523         unsigned                        dirty_mask;
 524         unsigned                        depth_range_dirty_mask;
 525         struct pipe_viewport_state      states[R600_MAX_VIEWPORTS];
 526         struct r600_signed_scissor      as_scissor[R600_MAX_VIEWPORTS];
 527 };
 528
 529 struct r600_ring {
 530         struct radeon_winsys_cs         *cs;
 531         void (*flush)(void *ctx, unsigned flags,
 532                       struct pipe_fence_handle **fence);
 533 };
 534
 535 /* Saved CS data for debugging features. */
 536 struct radeon_saved_cs {
 537         uint32_t                        *ib;
 538         unsigned                        num_dw;
 539
 540         struct radeon_bo_list_item      *bo_list;
 541         unsigned                        bo_count;
 542 };
 543
 544 struct r600_common_context {
 545         struct pipe_context b; /* base class */
 546
 547         struct r600_common_screen       *screen;
 548         struct radeon_winsys            *ws;
 549         struct radeon_winsys_ctx        *ctx;
 550         enum radeon_family              family;
 551         enum chip_class                 chip_class;
 552         struct r600_ring                gfx;
 553         struct r600_ring                dma;
 554         struct pipe_fence_handle        *last_gfx_fence;
 555         struct pipe_fence_handle        *last_sdma_fence;
 556         unsigned                        num_gfx_cs_flushes;
 557         unsigned                        initial_gfx_cs_size;
 558         unsigned                        gpu_reset_counter;
 559         unsigned                        last_dirty_fb_counter;
 560         unsigned                        last_compressed_colortex_counter;
 561         unsigned                        last_dirty_tex_descriptor_counter;
 562
 563         struct u_upload_mgr             *uploader;
 564         struct u_suballocator           *allocator_zeroed_memory;
 565         struct slab_child_pool          pool_transfers;
 566
 567         /* Current unaccounted memory usage. */
 568         uint64_t                        vram;
 569         uint64_t                        gtt;
 570
 571         /* States. */
 572         struct r600_streamout           streamout;
 573         struct r600_scissors            scissors;
 574         struct r600_viewports           viewports;
 575         bool                            scissor_enabled;
 576         bool                            clip_halfz;
 577         bool                            vs_writes_viewport_index;
 578         bool                            vs_disables_clipping_viewport;
 579
 580         /* Additional context states. */
 581         unsigned flags; /* flush flags */
 582
 583         /* Queries. */
 584         /* Maintain the list of active queries for pausing between IBs. */
 585         int                             num_occlusion_queries;
 586         int                             num_perfect_occlusion_queries;
 587         struct list_head                active_queries;
 588         unsigned                        num_cs_dw_queries_suspend;
 589         /* Misc stats. */
 590         unsigned                        num_draw_calls;
 591         unsigned                        num_spill_draw_calls;
 592         unsigned                        num_compute_calls;
 593         unsigned                        num_spill_compute_calls;
 594         unsigned                        num_dma_calls;
 595         unsigned                        num_cp_dma_calls;
 596         unsigned                        num_vs_flushes;
 597         unsigned                        num_ps_flushes;
 598         unsigned                        num_cs_flushes;
 599         unsigned                        num_fb_cache_flushes;
 600         unsigned                        num_L2_invalidates;
 601         unsigned                        num_L2_writebacks;
 602         uint64_t                        num_alloc_tex_transfer_bytes;
 603         unsigned                        last_tex_ps_draw_ratio; /* for query */
 604
 605         /* Render condition. */
 606         struct r600_atom                render_cond_atom;
 607         struct pipe_query               *render_cond;
 608         unsigned                        render_cond_mode;
 609         bool                            render_cond_invert;
 610         bool                            render_cond_force_off; /* for u_blitter */
 611
 612         /* MSAA sample locations.
 613          * The first index is the sample index.
 614          * The second index is the coordinate: X, Y. */
 615         float                           sample_locations_1x[1][2];
 616         float                           sample_locations_2x[2][2];
 617         float                           sample_locations_4x[4][2];
 618         float                           sample_locations_8x[8][2];
 619         float                           sample_locations_16x[16][2];
 620
 621         /* Statistics gathering for the DCC enablement heuristic. It can't be
 622          * in r600_texture because r600_texture can be shared by multiple
 623          * contexts. This is for back buffers only. We shouldn't get too many
 624          * of those.
 625          *
 626          * X11 DRI3 rotates among a finite set of back buffers. They should
 627          * all fit in this array. If they don't, separate DCC might never be
 628          * enabled by DCC stat gathering.
 629          */
 630         struct {
 631                 struct r600_texture             *tex;
 632                 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
 633                 struct pipe_query               *ps_stats[3];
 634                 /* If all slots are used and another slot is needed,
 635                  * the least recently used slot is evicted based on this. */
 636                 int64_t                         last_use_timestamp;
 637                 bool                            query_active;
 638         } dcc_stats[5];
 639
 640         struct pipe_debug_callback      debug;
 641         struct pipe_device_reset_callback device_reset_callback;
 642
 643         void                            *query_result_shader;
 644
 645         /* Copy one resource to another using async DMA. */
 646         void (*dma_copy)(struct pipe_context *ctx,
 647                          struct pipe_resource *dst,
 648                          unsigned dst_level,
 649                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 650                          struct pipe_resource *src,
 651                          unsigned src_level,
 652                          const struct pipe_box *src_box);
 653
 654         void (*dma_clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 655                                  uint64_t offset, uint64_t size, unsigned value);
 656
 657         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 658                              uint64_t offset, uint64_t size, unsigned value,
 659                              enum r600_coherency coher);
 660
 661         void (*blit_decompress_depth)(struct pipe_context *ctx,
 662                                       struct r600_texture *texture,
 663                                       struct r600_texture *staging,
 664                                       unsigned first_level, unsigned last_level,
 665                                       unsigned first_layer, unsigned last_layer,
 666                                       unsigned first_sample, unsigned last_sample);
 667
 668         void (*decompress_dcc)(struct pipe_context *ctx,
 669                                struct r600_texture *rtex);
 670
 671         /* Reallocate the buffer and update all resource bindings where
 672          * the buffer is bound, including all resource descriptors. */
 673         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 674
 675         /* Enable or disable occlusion queries. */
 676         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 677
 678         void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state *st);
 679
 680         /* This ensures there is enough space in the command stream. */
 681         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 682                                   bool include_draw_vbo);
 683
 684         void (*set_atom_dirty)(struct r600_common_context *ctx,
 685                                struct r600_atom *atom, bool dirty);
 686
 687         void (*check_vm_faults)(struct r600_common_context *ctx,
 688                                 struct radeon_saved_cs *saved,
 689                                 enum ring_type ring);
 690 };
 691
 692 /* r600_buffer.c */
 693 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 694                                      struct pb_buffer *buf,
 695                                      enum radeon_bo_usage usage);
 696 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 697                                       struct r600_resource *resource,
 698                                       unsigned usage);
 699 void r600_buffer_subdata(struct pipe_context *ctx,
 700                          struct pipe_resource *buffer,
 701                          unsigned usage, unsigned offset,
 702                          unsigned size, const void *data);
 703 void r600_init_resource_fields(struct r600_common_screen *rscreen,
 704                                struct r600_resource *res,
 705                                uint64_t size, unsigned alignment);
 706 bool r600_alloc_resource(struct r600_common_screen *rscreen,
 707                          struct r600_resource *res);
 708 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 709                                          const struct pipe_resource *templ,
 710                                          unsigned alignment);
 711 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
 712                                                   unsigned bind,
 713                                                   unsigned usage,
 714                                                   unsigned size,
 715                                                   unsigned alignment);
 716 struct pipe_resource *
 717 r600_buffer_from_user_memory(struct pipe_screen *screen,
 718                              const struct pipe_resource *templ,
 719                              void *user_memory);
 720 void
 721 r600_invalidate_resource(struct pipe_context *ctx,
 722                          struct pipe_resource *resource);
 723
 724 /* r600_common_pipe.c */
 725 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
 726                               unsigned event, unsigned event_flags,
 727                               unsigned data_sel,
 728                               struct r600_resource *buf, uint64_t va,
 729                               uint32_t old_fence, uint32_t new_fence);
 730 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen);
 731 void r600_gfx_wait_fence(struct r600_common_context *ctx,
 732                          uint64_t va, uint32_t ref, uint32_t mask);
 733 void r600_draw_rectangle(struct blitter_context *blitter,
 734                          int x1, int y1, int x2, int y2, float depth,
 735                          enum blitter_attrib_type type,
 736                          const union pipe_color_union *attrib);
 737 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 738                              struct radeon_winsys *ws);
 739 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 740 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 741 void r600_postflush_resume_features(struct r600_common_context *ctx);
 742 bool r600_common_context_init(struct r600_common_context *rctx,
 743                               struct r600_common_screen *rscreen,
 744                               unsigned context_flags);
 745 void r600_common_context_cleanup(struct r600_common_context *rctx);
 746 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 747                           unsigned processor);
 748 bool r600_extra_shader_checks(struct r600_common_screen *rscreen,
 749                               unsigned processor);
 750 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 751                               uint64_t offset, uint64_t size, unsigned value);
 752 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 753                                                   const struct pipe_resource *templ);
 754 const char *r600_get_llvm_processor_name(enum radeon_family family);
 755 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
 756                          struct r600_resource *dst, struct r600_resource *src);
 757 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
 758                     struct radeon_saved_cs *saved);
 759 void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
 760 bool r600_check_device_reset(struct r600_common_context *rctx);
 761
 762 /* r600_gpu_load.c */
 763 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 764 uint64_t r600_begin_counter(struct r600_common_screen *rscreen, unsigned type);
 765 unsigned r600_end_counter(struct r600_common_screen *rscreen, unsigned type,
 766                           uint64_t begin);
 767
 768 /* r600_perfcounters.c */
 769 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
 770
 771 /* r600_query.c */
 772 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
 773 void r600_query_init(struct r600_common_context *rctx);
 774 void r600_suspend_queries(struct r600_common_context *ctx);
 775 void r600_resume_queries(struct r600_common_context *ctx);
 776 void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen);
 777
 778 /* r600_streamout.c */
 779 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 780 void r600_set_streamout_targets(struct pipe_context *ctx,
 781                                 unsigned num_targets,
 782                                 struct pipe_stream_output_target **targets,
 783                                 const unsigned *offset);
 784 void r600_emit_streamout_end(struct r600_common_context *rctx);
 785 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 786                                              unsigned type, int diff);
 787 void r600_streamout_init(struct r600_common_context *rctx);
 788
 789 /* r600_test_dma.c */
 790 void r600_test_dma(struct r600_common_screen *rscreen);
 791
 792 /* r600_texture.c */
 793 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
 794                                 struct r600_texture *rdst,
 795                                 unsigned dst_level, unsigned dstx,
 796                                 unsigned dsty, unsigned dstz,
 797                                 struct r600_texture *rsrc,
 798                                 unsigned src_level,
 799                                 const struct pipe_box *src_box);
 800 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 801                                  struct r600_texture *rtex,
 802                                  unsigned nr_samples,
 803                                  struct r600_fmask_info *out);
 804 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 805                                  struct r600_texture *rtex,
 806                                  struct r600_cmask_info *out);
 807 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 808                                      struct pipe_resource *texture,
 809                                      struct r600_texture **staging);
 810 void r600_print_texture_info(struct r600_texture *rtex, FILE *f);
 811 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 812                                         const struct pipe_resource *templ);
 813 bool vi_dcc_formats_compatible(enum pipe_format format1,
 814                                enum pipe_format format2);
 815 void vi_dcc_disable_if_incompatible_format(struct r600_common_context *rctx,
 816                                            struct pipe_resource *tex,
 817                                            unsigned level,
 818                                            enum pipe_format view_format);
 819 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 820                                                 struct pipe_resource *texture,
 821                                                 const struct pipe_surface *templ,
 822                                                 unsigned width, unsigned height);
 823 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
 824 void vi_separate_dcc_start_query(struct pipe_context *ctx,
 825                                  struct r600_texture *tex);
 826 void vi_separate_dcc_stop_query(struct pipe_context *ctx,
 827                                 struct r600_texture *tex);
 828 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
 829                                              struct r600_texture *tex);
 830 void vi_dcc_clear_level(struct r600_common_context *rctx,
 831                         struct r600_texture *rtex,
 832                         unsigned level, unsigned clear_value);
 833 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 834                                    struct pipe_framebuffer_state *fb,
 835                                    struct r600_atom *fb_state,
 836                                    unsigned *buffers, unsigned *dirty_cbufs,
 837                                    const union pipe_color_union *color);
 838 bool r600_texture_disable_dcc(struct r600_common_context *rctx,
 839                               struct r600_texture *rtex);
 840 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 841 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 842
 843 /* r600_viewport.c */
 844 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
 845                                             struct pipe_scissor_state *scissor);
 846 void r600_viewport_set_rast_deps(struct r600_common_context *rctx,
 847                                  bool scissor_enable, bool clip_halfz);
 848 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
 849                                           struct tgsi_shader_info *info);
 850 void r600_init_viewport_functions(struct r600_common_context *rctx);
 851
 852 /* cayman_msaa.c */
 853 extern const uint32_t eg_sample_locs_2x[4];
 854 extern const unsigned eg_max_dist_2x;
 855 extern const uint32_t eg_sample_locs_4x[4];
 856 extern const unsigned eg_max_dist_4x;
 857 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 858                                 unsigned sample_index, float *out_value);
 859 void cayman_init_msaa(struct pipe_context *ctx);
 860 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 861 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 862                              int ps_iter_samples, int overrast_samples,
 863                              unsigned sc_mode_cntl_1);
 864
 865
 866 /* Inline helpers. */
 867
 868 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 869 {
 870         return (struct r600_resource*)r;
 871 }
 872
 873 static inline void
 874 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 875 {
 876         pipe_resource_reference((struct pipe_resource **)ptr,
 877                                 (struct pipe_resource *)res);
 878 }
 879
 880 static inline void
 881 r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
 882 {
 883         pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
 884 }
 885
 886 static inline void
 887 r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 888 {
 889         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 890         struct r600_resource *res = (struct r600_resource *)r;
 891
 892         if (res) {
 893                 /* Add memory usage for need_gfx_cs_space */
 894                 rctx->vram += res->vram_usage;
 895                 rctx->gtt += res->gart_usage;
 896         }
 897 }
 898
 899 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
 900 {
 901         return rctx->streamout.streamout_enabled ||
 902                rctx->streamout.prims_gen_query_enabled;
 903 }
 904
 905 #define     SQ_TEX_XY_FILTER_POINT                         0x00
 906 #define     SQ_TEX_XY_FILTER_BILINEAR                      0x01
 907 #define     SQ_TEX_XY_FILTER_ANISO_POINT                   0x02
 908 #define     SQ_TEX_XY_FILTER_ANISO_BILINEAR                0x03
 909
 910 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
 911 {
 912         if (filter == PIPE_TEX_FILTER_LINEAR)
 913                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
 914                                      : SQ_TEX_XY_FILTER_BILINEAR;
 915         else
 916                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
 917                                      : SQ_TEX_XY_FILTER_POINT;
 918 }
 919
 920 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 921 {
 922         if (filter < 2)
 923                 return 0;
 924         if (filter < 4)
 925                 return 1;
 926         if (filter < 8)
 927                 return 2;
 928         if (filter < 16)
 929                 return 3;
 930         return 4;
 931 }
 932
 933 static inline unsigned r600_wavefront_size(enum radeon_family family)
 934 {
 935         switch (family) {
 936         case CHIP_RV610:
 937         case CHIP_RS780:
 938         case CHIP_RV620:
 939         case CHIP_RS880:
 940                 return 16;
 941         case CHIP_RV630:
 942         case CHIP_RV635:
 943         case CHIP_RV730:
 944         case CHIP_RV710:
 945         case CHIP_PALM:
 946         case CHIP_CEDAR:
 947                 return 32;
 948         default:
 949                 return 64;
 950         }
 951 }
 952
 953 static inline enum radeon_bo_priority
 954 r600_get_sampler_view_priority(struct r600_resource *res)
 955 {
 956         if (res->b.b.target == PIPE_BUFFER)
 957                 return RADEON_PRIO_SAMPLER_BUFFER;
 958
 959         if (res->b.b.nr_samples > 1)
 960                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 961
 962         return RADEON_PRIO_SAMPLER_TEXTURE;
 963 }
 964
 965 static inline bool
 966 r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
 967 {
 968         return (stencil_sampler && tex->can_sample_s) ||
 969                (!stencil_sampler && tex->can_sample_z);
 970 }
 971
 972 #define COMPUTE_DBG(rscreen, fmt, args...) \
 973         do { \
 974                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 975         } while (0);
 976
 977 #define R600_ERR(fmt, args...) \
 978         fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 979
 980 /* For MSAA sample positions. */
 981 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 982         (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) |                  \
 983         (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) |         \
 984         (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) |        \
 985          (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
 986
 987 #endif