src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/u_slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define ATI_VENDOR_ID 0x1002
  47
  48 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  49 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  50 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  51 #define R600_RESOURCE_FLAG_DISABLE_DCC          (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
  52
  53 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  54 /* Pipeline & streamout query controls. */
  55 #define R600_CONTEXT_START_PIPELINE_STATS       (1u << 1)
  56 #define R600_CONTEXT_STOP_PIPELINE_STATS        (1u << 2)
  57 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 3)
  58
  59 /* special primitive types */
  60 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  61
  62 /* Debug flags. */
  63 /* logging */
  64 #define DBG_TEX                 (1 << 0)
  65 /* gap - reuse */
  66 #define DBG_COMPUTE             (1 << 2)
  67 #define DBG_VM                  (1 << 3)
  68 /* gap - reuse */
  69 /* shader logging */
  70 #define DBG_FS                  (1 << 5)
  71 #define DBG_VS                  (1 << 6)
  72 #define DBG_GS                  (1 << 7)
  73 #define DBG_PS                  (1 << 8)
  74 #define DBG_CS                  (1 << 9)
  75 #define DBG_TCS                 (1 << 10)
  76 #define DBG_TES                 (1 << 11)
  77 #define DBG_NO_IR               (1 << 12)
  78 #define DBG_NO_TGSI             (1 << 13)
  79 #define DBG_NO_ASM              (1 << 14)
  80 #define DBG_PREOPT_IR           (1 << 15)
  81 /* gaps */
  82 #define DBG_TEST_DMA            (1 << 20)
  83 /* Bits 21-31 are reserved for the r600g driver. */
  84 /* features */
  85 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  86 #define DBG_NO_HYPERZ           (1llu << 33)
  87 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  88 #define DBG_NO_2D_TILING        (1llu << 35)
  89 #define DBG_NO_TILING           (1llu << 36)
  90 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  91 #define DBG_FORCE_DMA           (1llu << 38)
  92 #define DBG_PRECOMPILE          (1llu << 39)
  93 #define DBG_INFO                (1llu << 40)
  94 #define DBG_NO_WC               (1llu << 41)
  95 #define DBG_CHECK_VM            (1llu << 42)
  96 #define DBG_NO_DCC              (1llu << 43)
  97 #define DBG_NO_DCC_CLEAR        (1llu << 44)
  98 #define DBG_NO_RB_PLUS          (1llu << 45)
  99 #define DBG_SI_SCHED            (1llu << 46)
 100 #define DBG_MONOLITHIC_SHADERS  (1llu << 47)
 101 #define DBG_NO_CE               (1llu << 48)
 102 #define DBG_UNSAFE_MATH         (1llu << 49)
 103
 104 #define R600_MAP_BUFFER_ALIGNMENT 64
 105 #define R600_MAX_VIEWPORTS        16
 106
 107 enum r600_coherency {
 108         R600_COHERENCY_NONE, /* no cache flushes needed */
 109         R600_COHERENCY_SHADER,
 110         R600_COHERENCY_CB_META,
 111 };
 112
 113 #ifdef PIPE_ARCH_BIG_ENDIAN
 114 #define R600_BIG_ENDIAN 1
 115 #else
 116 #define R600_BIG_ENDIAN 0
 117 #endif
 118
 119 struct r600_common_context;
 120 struct r600_perfcounters;
 121 struct tgsi_shader_info;
 122
 123 struct radeon_shader_reloc {
 124         char name[32];
 125         uint64_t offset;
 126 };
 127
 128 struct radeon_shader_binary {
 129         /** Shader code */
 130         unsigned char *code;
 131         unsigned code_size;
 132
 133         /** Config/Context register state that accompanies this shader.
 134          * This is a stream of dword pairs.  First dword contains the
 135          * register address, the second dword contains the value.*/
 136         unsigned char *config;
 137         unsigned config_size;
 138
 139         /** The number of bytes of config information for each global symbol.
 140          */
 141         unsigned config_size_per_symbol;
 142
 143         /** Constant data accessed by the shader.  This will be uploaded
 144          * into a constant buffer. */
 145         unsigned char *rodata;
 146         unsigned rodata_size;
 147
 148         /** List of symbol offsets for the shader */
 149         uint64_t *global_symbol_offsets;
 150         unsigned global_symbol_count;
 151
 152         struct radeon_shader_reloc *relocs;
 153         unsigned reloc_count;
 154
 155         /** Disassembled shader in a string. */
 156         char *disasm_string;
 157 };
 158
 159 void radeon_shader_binary_init(struct radeon_shader_binary *b);
 160 void radeon_shader_binary_clean(struct radeon_shader_binary *b);
 161
 162 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
 163  * at the moment.
 164  */
 165 struct r600_resource {
 166         struct u_resource               b;
 167
 168         /* Winsys objects. */
 169         struct pb_buffer                *buf;
 170         uint64_t                        gpu_address;
 171
 172         /* Resource state. */
 173         enum radeon_bo_domain           domains;
 174
 175         /* The buffer range which is initialized (with a write transfer,
 176          * streamout, DMA, or as a random access target). The rest of
 177          * the buffer is considered invalid and can be mapped unsynchronized.
 178          *
 179          * This allows unsychronized mapping of a buffer range which hasn't
 180          * been used yet. It's for applications which forget to use
 181          * the unsynchronized map flag and expect the driver to figure it out.
 182          */
 183         struct util_range               valid_buffer_range;
 184
 185         /* For buffers only. This indicates that a write operation has been
 186          * performed by TC L2, but the cache hasn't been flushed.
 187          * Any hw block which doesn't use or bypasses TC L2 should check this
 188          * flag and flush the cache before using the buffer.
 189          *
 190          * For example, TC L2 must be flushed if a buffer which has been
 191          * modified by a shader store instruction is about to be used as
 192          * an index buffer. The reason is that VGT DMA index fetching doesn't
 193          * use TC L2.
 194          */
 195         bool                            TC_L2_dirty;
 196
 197         /* Whether the resource has been exported via resource_get_handle. */
 198         bool                            is_shared;
 199         unsigned                        external_usage; /* PIPE_HANDLE_USAGE_* */
 200 };
 201
 202 struct r600_transfer {
 203         struct pipe_transfer            transfer;
 204         struct r600_resource            *staging;
 205         unsigned                        offset;
 206 };
 207
 208 struct r600_fmask_info {
 209         uint64_t offset;
 210         uint64_t size;
 211         unsigned alignment;
 212         unsigned pitch_in_pixels;
 213         unsigned bank_height;
 214         unsigned slice_tile_max;
 215         unsigned tile_mode_index;
 216 };
 217
 218 struct r600_cmask_info {
 219         uint64_t offset;
 220         uint64_t size;
 221         unsigned alignment;
 222         unsigned pitch;
 223         unsigned height;
 224         unsigned xalign;
 225         unsigned yalign;
 226         unsigned slice_tile_max;
 227         unsigned base_address_reg;
 228 };
 229
 230 struct r600_htile_info {
 231         unsigned pitch;
 232         unsigned height;
 233         unsigned xalign;
 234         unsigned yalign;
 235 };
 236
 237 struct r600_texture {
 238         struct r600_resource            resource;
 239
 240         uint64_t                        size;
 241         unsigned                        num_level0_transfers;
 242         bool                            is_depth;
 243         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 244         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 245         struct r600_texture             *flushed_depth_texture;
 246         boolean                         is_flushing_texture;
 247         struct radeon_surf              surface;
 248
 249         /* Colorbuffer compression and fast clear. */
 250         struct r600_fmask_info          fmask;
 251         struct r600_cmask_info          cmask;
 252         struct r600_resource            *cmask_buffer;
 253         uint64_t                        dcc_offset; /* 0 = disabled */
 254         unsigned                        cb_color_info; /* fast clear enable bit */
 255         unsigned                        color_clear_value[2];
 256         unsigned                        last_msaa_resolve_target_micro_mode;
 257
 258         /* Depth buffer compression and fast clear. */
 259         struct r600_htile_info          htile;
 260         struct r600_resource            *htile_buffer;
 261         bool                            depth_cleared; /* if it was cleared at least once */
 262         float                           depth_clear_value;
 263         bool                            stencil_cleared; /* if it was cleared at least once */
 264         uint8_t                         stencil_clear_value;
 265
 266         bool                            non_disp_tiling; /* R600-Cayman only */
 267
 268         /* Counter that should be non-zero if the texture is bound to a
 269          * framebuffer. Implemented in radeonsi only.
 270          */
 271         uint32_t                        framebuffers_bound;
 272 };
 273
 274 struct r600_surface {
 275         struct pipe_surface             base;
 276         const struct radeon_surf_level  *level_info;
 277
 278         bool color_initialized;
 279         bool depth_initialized;
 280
 281         /* Misc. color flags. */
 282         bool alphatest_bypass;
 283         bool export_16bpc;
 284         bool color_is_int8;
 285
 286         /* Color registers. */
 287         unsigned cb_color_info;
 288         unsigned cb_color_base;
 289         unsigned cb_color_view;
 290         unsigned cb_color_size;         /* R600 only */
 291         unsigned cb_color_dim;          /* EG only */
 292         unsigned cb_color_pitch;        /* EG and later */
 293         unsigned cb_color_slice;        /* EG and later */
 294         unsigned cb_color_attrib;       /* EG and later */
 295         unsigned cb_dcc_control;        /* VI and later */
 296         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 297         unsigned cb_color_fmask_slice;  /* EG and later */
 298         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 299         unsigned cb_color_mask;         /* R600 only */
 300         unsigned spi_shader_col_format;         /* SI+, no blending, no alpha-to-coverage. */
 301         unsigned spi_shader_col_format_alpha;   /* SI+, alpha-to-coverage */
 302         unsigned spi_shader_col_format_blend;   /* SI+, blending without alpha. */
 303         unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
 304         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 305         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 306
 307         /* DB registers. */
 308         unsigned db_depth_info;         /* R600 only, then SI and later */
 309         unsigned db_z_info;             /* EG and later */
 310         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 311         unsigned db_depth_view;
 312         unsigned db_depth_size;
 313         unsigned db_depth_slice;        /* EG and later */
 314         unsigned db_stencil_base;       /* EG and later */
 315         unsigned db_stencil_info;       /* EG and later */
 316         unsigned db_prefetch_limit;     /* R600 only */
 317         unsigned db_htile_surface;
 318         unsigned db_htile_data_base;
 319         unsigned db_preload_control;    /* EG and later */
 320         unsigned pa_su_poly_offset_db_fmt_cntl;
 321 };
 322
 323 struct r600_common_screen {
 324         struct pipe_screen              b;
 325         struct radeon_winsys            *ws;
 326         enum radeon_family              family;
 327         enum chip_class                 chip_class;
 328         struct radeon_info              info;
 329         uint64_t                        debug_flags;
 330         bool                            has_cp_dma;
 331         bool                            has_streamout;
 332
 333         /* Texture filter settings. */
 334         int                             force_aniso; /* -1 = disabled */
 335
 336         /* Auxiliary context. Mainly used to initialize resources.
 337          * It must be locked prior to using and flushed before unlocking. */
 338         struct pipe_context             *aux_context;
 339         pipe_mutex                      aux_context_lock;
 340
 341         /* This must be in the screen, because UE4 uses one context for
 342          * compilation and another one for rendering.
 343          */
 344         unsigned                        num_compilations;
 345         /* Along with ST_DEBUG=precompile, this should show if applications
 346          * are loading shaders on demand. This is a monotonic counter.
 347          */
 348         unsigned                        num_shaders_created;
 349
 350         /* GPU load thread. */
 351         pipe_mutex                      gpu_load_mutex;
 352         pipe_thread                     gpu_load_thread;
 353         unsigned                        gpu_load_counter_busy;
 354         unsigned                        gpu_load_counter_idle;
 355         volatile unsigned               gpu_load_stop_thread; /* bool */
 356
 357         char                            renderer_string[64];
 358
 359         /* Performance counters. */
 360         struct r600_perfcounters        *perfcounters;
 361
 362         /* If pipe_screen wants to re-emit the framebuffer state of all
 363          * contexts, it should atomically increment this. Each context will
 364          * compare this with its own last known value of the counter before
 365          * drawing and re-emit the framebuffer state accordingly.
 366          */
 367         unsigned                        dirty_fb_counter;
 368
 369         /* Atomically increment this counter when an existing texture's
 370          * metadata is enabled or disabled in a way that requires changing
 371          * contexts' compressed texture binding masks.
 372          */
 373         unsigned                        compressed_colortex_counter;
 374
 375         /* Atomically increment this counter when an existing texture's
 376          * backing buffer or tile mode parameters have changed that requires
 377          * recomputation of shader descriptors.
 378          */
 379         unsigned                        dirty_tex_descriptor_counter;
 380
 381         void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
 382                                       struct r600_texture *rtex,
 383                                       struct radeon_bo_metadata *md);
 384
 385         void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
 386                                     struct r600_texture *rtex,
 387                                     struct radeon_bo_metadata *md);
 388 };
 389
 390 /* This encapsulates a state or an operation which can emitted into the GPU
 391  * command stream. */
 392 struct r600_atom {
 393         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 394         unsigned                num_dw;
 395         unsigned short          id;
 396 };
 397
 398 struct r600_so_target {
 399         struct pipe_stream_output_target b;
 400
 401         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 402         struct r600_resource    *buf_filled_size;
 403         unsigned                buf_filled_size_offset;
 404         bool                    buf_filled_size_valid;
 405
 406         unsigned                stride_in_dw;
 407 };
 408
 409 struct r600_streamout {
 410         struct r600_atom                begin_atom;
 411         bool                            begin_emitted;
 412         unsigned                        num_dw_for_end;
 413
 414         unsigned                        enabled_mask;
 415         unsigned                        num_targets;
 416         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 417
 418         unsigned                        append_bitmask;
 419         bool                            suspended;
 420
 421         /* External state which comes from the vertex shader,
 422          * it must be set explicitly when binding a shader. */
 423         unsigned                        *stride_in_dw;
 424         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 425
 426         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 427         unsigned                        hw_enabled_mask;
 428
 429         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 430         struct r600_atom                enable_atom;
 431         bool                            streamout_enabled;
 432         bool                            prims_gen_query_enabled;
 433         int                             num_prims_gen_queries;
 434 };
 435
 436 struct r600_signed_scissor {
 437         int minx;
 438         int miny;
 439         int maxx;
 440         int maxy;
 441 };
 442
 443 struct r600_scissors {
 444         struct r600_atom                atom;
 445         unsigned                        dirty_mask;
 446         struct pipe_scissor_state       states[R600_MAX_VIEWPORTS];
 447 };
 448
 449 struct r600_viewports {
 450         struct r600_atom                atom;
 451         unsigned                        dirty_mask;
 452         struct pipe_viewport_state      states[R600_MAX_VIEWPORTS];
 453         struct r600_signed_scissor      as_scissor[R600_MAX_VIEWPORTS];
 454 };
 455
 456 struct r600_ring {
 457         struct radeon_winsys_cs         *cs;
 458         void (*flush)(void *ctx, unsigned flags,
 459                       struct pipe_fence_handle **fence);
 460 };
 461
 462 struct r600_common_context {
 463         struct pipe_context b; /* base class */
 464
 465         struct r600_common_screen       *screen;
 466         struct radeon_winsys            *ws;
 467         struct radeon_winsys_ctx        *ctx;
 468         enum radeon_family              family;
 469         enum chip_class                 chip_class;
 470         struct r600_ring                gfx;
 471         struct r600_ring                dma;
 472         struct pipe_fence_handle        *last_sdma_fence;
 473         unsigned                        initial_gfx_cs_size;
 474         unsigned                        gpu_reset_counter;
 475         unsigned                        last_dirty_fb_counter;
 476         unsigned                        last_compressed_colortex_counter;
 477         unsigned                        last_dirty_tex_descriptor_counter;
 478
 479         struct u_upload_mgr             *uploader;
 480         struct u_suballocator           *allocator_zeroed_memory;
 481         struct util_slab_mempool        pool_transfers;
 482
 483         /* Current unaccounted memory usage. */
 484         uint64_t                        vram;
 485         uint64_t                        gtt;
 486
 487         /* States. */
 488         struct r600_streamout           streamout;
 489         struct r600_scissors            scissors;
 490         struct r600_viewports           viewports;
 491         bool                            scissor_enabled;
 492         bool                            vs_writes_viewport_index;
 493         bool                            vs_disables_clipping_viewport;
 494
 495         /* Additional context states. */
 496         unsigned flags; /* flush flags */
 497
 498         /* Queries. */
 499         /* Maintain the list of active queries for pausing between IBs. */
 500         int                             num_occlusion_queries;
 501         int                             num_perfect_occlusion_queries;
 502         struct list_head                active_queries;
 503         unsigned                        num_cs_dw_queries_suspend;
 504         /* Additional hardware info. */
 505         unsigned                        backend_mask;
 506         unsigned                        max_db; /* for OQ */
 507         /* Misc stats. */
 508         unsigned                        num_draw_calls;
 509         unsigned                        num_spill_draw_calls;
 510         unsigned                        num_compute_calls;
 511         unsigned                        num_spill_compute_calls;
 512         unsigned                        num_dma_calls;
 513         uint64_t                        num_alloc_tex_transfer_bytes;
 514
 515         /* Render condition. */
 516         struct r600_atom                render_cond_atom;
 517         struct pipe_query               *render_cond;
 518         unsigned                        render_cond_mode;
 519         boolean                         render_cond_invert;
 520         bool                            render_cond_force_off; /* for u_blitter */
 521
 522         /* MSAA sample locations.
 523          * The first index is the sample index.
 524          * The second index is the coordinate: X, Y. */
 525         float                           sample_locations_1x[1][2];
 526         float                           sample_locations_2x[2][2];
 527         float                           sample_locations_4x[4][2];
 528         float                           sample_locations_8x[8][2];
 529         float                           sample_locations_16x[16][2];
 530
 531         /* The list of all texture buffer objects in this context.
 532          * This list is walked when a buffer is invalidated/reallocated and
 533          * the GPU addresses are updated. */
 534         struct list_head                texture_buffers;
 535
 536         struct pipe_debug_callback      debug;
 537
 538         /* Copy one resource to another using async DMA. */
 539         void (*dma_copy)(struct pipe_context *ctx,
 540                          struct pipe_resource *dst,
 541                          unsigned dst_level,
 542                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 543                          struct pipe_resource *src,
 544                          unsigned src_level,
 545                          const struct pipe_box *src_box);
 546
 547         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 548                              uint64_t offset, uint64_t size, unsigned value,
 549                              enum r600_coherency coher);
 550
 551         void (*blit_decompress_depth)(struct pipe_context *ctx,
 552                                       struct r600_texture *texture,
 553                                       struct r600_texture *staging,
 554                                       unsigned first_level, unsigned last_level,
 555                                       unsigned first_layer, unsigned last_layer,
 556                                       unsigned first_sample, unsigned last_sample);
 557
 558         void (*decompress_dcc)(struct pipe_context *ctx,
 559                                struct r600_texture *rtex);
 560
 561         /* Reallocate the buffer and update all resource bindings where
 562          * the buffer is bound, including all resource descriptors. */
 563         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 564
 565         /* Enable or disable occlusion queries. */
 566         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 567
 568         /* This ensures there is enough space in the command stream. */
 569         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 570                                   bool include_draw_vbo);
 571
 572         void (*set_atom_dirty)(struct r600_common_context *ctx,
 573                                struct r600_atom *atom, bool dirty);
 574 };
 575
 576 /* r600_buffer.c */
 577 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 578                                         struct pb_buffer *buf,
 579                                         enum radeon_bo_usage usage);
 580 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 581                                       struct r600_resource *resource,
 582                                       unsigned usage);
 583 bool r600_init_resource(struct r600_common_screen *rscreen,
 584                         struct r600_resource *res,
 585                         uint64_t size, unsigned alignment);
 586 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 587                                          const struct pipe_resource *templ,
 588                                          unsigned alignment);
 589 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
 590                                                   unsigned bind,
 591                                                   unsigned usage,
 592                                                   unsigned size,
 593                                                   unsigned alignment);
 594 struct pipe_resource *
 595 r600_buffer_from_user_memory(struct pipe_screen *screen,
 596                              const struct pipe_resource *templ,
 597                              void *user_memory);
 598 void
 599 r600_invalidate_resource(struct pipe_context *ctx,
 600                          struct pipe_resource *resource);
 601
 602 /* r600_common_pipe.c */
 603 void r600_draw_rectangle(struct blitter_context *blitter,
 604                          int x1, int y1, int x2, int y2, float depth,
 605                          enum blitter_attrib_type type,
 606                          const union pipe_color_union *attrib);
 607 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 608                              struct radeon_winsys *ws);
 609 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 610 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 611 void r600_postflush_resume_features(struct r600_common_context *ctx);
 612 bool r600_common_context_init(struct r600_common_context *rctx,
 613                               struct r600_common_screen *rscreen);
 614 void r600_common_context_cleanup(struct r600_common_context *rctx);
 615 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 616 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 617                           unsigned processor);
 618 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 619                               uint64_t offset, uint64_t size, unsigned value,
 620                               enum r600_coherency coher);
 621 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 622                                                   const struct pipe_resource *templ);
 623 const char *r600_get_llvm_processor_name(enum radeon_family family);
 624 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
 625                          struct r600_resource *dst, struct r600_resource *src);
 626 void r600_dma_emit_wait_idle(struct r600_common_context *rctx);
 627
 628 /* r600_gpu_load.c */
 629 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 630 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 631 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 632
 633 /* r600_perfcounters.c */
 634 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
 635
 636 /* r600_query.c */
 637 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
 638 void r600_query_init(struct r600_common_context *rctx);
 639 void r600_suspend_queries(struct r600_common_context *ctx);
 640 void r600_resume_queries(struct r600_common_context *ctx);
 641 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 642
 643 /* r600_streamout.c */
 644 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 645 void r600_set_streamout_targets(struct pipe_context *ctx,
 646                                 unsigned num_targets,
 647                                 struct pipe_stream_output_target **targets,
 648                                 const unsigned *offset);
 649 void r600_emit_streamout_end(struct r600_common_context *rctx);
 650 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 651                                              unsigned type, int diff);
 652 void r600_streamout_init(struct r600_common_context *rctx);
 653
 654 /* r600_test_dma.c */
 655 void r600_test_dma(struct r600_common_screen *rscreen);
 656
 657 /* r600_texture.c */
 658 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
 659                                 struct r600_texture *rdst,
 660                                 unsigned dst_level, unsigned dstx,
 661                                 unsigned dsty, unsigned dstz,
 662                                 struct r600_texture *rsrc,
 663                                 unsigned src_level,
 664                                 const struct pipe_box *src_box);
 665 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 666                                  struct r600_texture *rtex,
 667                                  unsigned nr_samples,
 668                                  struct r600_fmask_info *out);
 669 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 670                                  struct r600_texture *rtex,
 671                                  struct r600_cmask_info *out);
 672 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 673                                      struct pipe_resource *texture,
 674                                      struct r600_texture **staging);
 675 void r600_print_texture_info(struct r600_texture *rtex, FILE *f);
 676 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 677                                         const struct pipe_resource *templ);
 678 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 679                                                 struct pipe_resource *texture,
 680                                                 const struct pipe_surface *templ,
 681                                                 unsigned width, unsigned height);
 682 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
 683 void vi_dcc_clear_level(struct r600_common_context *rctx,
 684                         struct r600_texture *rtex,
 685                         unsigned level, unsigned clear_value);
 686 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 687                                    struct pipe_framebuffer_state *fb,
 688                                    struct r600_atom *fb_state,
 689                                    unsigned *buffers, unsigned *dirty_cbufs,
 690                                    const union pipe_color_union *color);
 691 bool r600_texture_disable_dcc(struct r600_common_screen *rscreen,
 692                               struct r600_texture *rtex);
 693 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 694 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 695
 696 /* r600_viewport.c */
 697 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
 698                                             struct pipe_scissor_state *scissor);
 699 void r600_set_scissor_enable(struct r600_common_context *rctx, bool enable);
 700 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
 701                                           struct tgsi_shader_info *info);
 702 void r600_init_viewport_functions(struct r600_common_context *rctx);
 703
 704 /* cayman_msaa.c */
 705 extern const uint32_t eg_sample_locs_2x[4];
 706 extern const unsigned eg_max_dist_2x;
 707 extern const uint32_t eg_sample_locs_4x[4];
 708 extern const unsigned eg_max_dist_4x;
 709 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 710                                 unsigned sample_index, float *out_value);
 711 void cayman_init_msaa(struct pipe_context *ctx);
 712 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 713 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 714                              int ps_iter_samples, int overrast_samples);
 715
 716
 717 /* Inline helpers. */
 718
 719 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 720 {
 721         return (struct r600_resource*)r;
 722 }
 723
 724 static inline void
 725 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 726 {
 727         pipe_resource_reference((struct pipe_resource **)ptr,
 728                                 (struct pipe_resource *)res);
 729 }
 730
 731 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
 732 {
 733         return rctx->streamout.streamout_enabled ||
 734                rctx->streamout.prims_gen_query_enabled;
 735 }
 736
 737 #define     SQ_TEX_XY_FILTER_POINT                         0x00
 738 #define     SQ_TEX_XY_FILTER_BILINEAR                      0x01
 739 #define     SQ_TEX_XY_FILTER_ANISO_POINT                   0x02
 740 #define     SQ_TEX_XY_FILTER_ANISO_BILINEAR                0x03
 741
 742 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
 743 {
 744         if (filter == PIPE_TEX_FILTER_LINEAR)
 745                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
 746                                      : SQ_TEX_XY_FILTER_BILINEAR;
 747         else
 748                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
 749                                      : SQ_TEX_XY_FILTER_POINT;
 750 }
 751
 752 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 753 {
 754         if (filter < 2)
 755                 return 0;
 756         if (filter < 4)
 757                 return 1;
 758         if (filter < 8)
 759                 return 2;
 760         if (filter < 16)
 761                 return 3;
 762         return 4;
 763 }
 764
 765 static inline unsigned r600_wavefront_size(enum radeon_family family)
 766 {
 767         switch (family) {
 768         case CHIP_RV610:
 769         case CHIP_RS780:
 770         case CHIP_RV620:
 771         case CHIP_RS880:
 772                 return 16;
 773         case CHIP_RV630:
 774         case CHIP_RV635:
 775         case CHIP_RV730:
 776         case CHIP_RV710:
 777         case CHIP_PALM:
 778         case CHIP_CEDAR:
 779                 return 32;
 780         default:
 781                 return 64;
 782         }
 783 }
 784
 785 static inline enum radeon_bo_priority
 786 r600_get_sampler_view_priority(struct r600_resource *res)
 787 {
 788         if (res->b.b.target == PIPE_BUFFER)
 789                 return RADEON_PRIO_SAMPLER_BUFFER;
 790
 791         if (res->b.b.nr_samples > 1)
 792                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 793
 794         return RADEON_PRIO_SAMPLER_TEXTURE;
 795 }
 796
 797 #define COMPUTE_DBG(rscreen, fmt, args...) \
 798         do { \
 799                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 800         } while (0);
 801
 802 #define R600_ERR(fmt, args...) \
 803         fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 804
 805 /* For MSAA sample positions. */
 806 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 807         (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) |                  \
 808         (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) |         \
 809         (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) |        \
 810          (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
 811
 812 #endif