2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
37 #include "amd/common/ac_binary.h"
39 #include "radeon/radeon_winsys.h"
41 #include "util/disk_cache.h"
42 #include "util/u_blitter.h"
43 #include "util/list.h"
44 #include "util/u_range.h"
45 #include "util/slab.h"
46 #include "util/u_suballoc.h"
47 #include "util/u_transfer.h"
48 #include "util/u_threaded_context.h"
50 #define ATI_VENDOR_ID 0x1002
52 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
53 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
54 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
55 #define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
56 #define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
58 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
59 /* Pipeline & streamout query controls. */
60 #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
61 #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
62 #define R600_CONTEXT_PRIVATE_FLAG (1u << 3)
64 /* special primitive types */
65 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
69 #define DBG_TEX (1 << 0)
71 #define DBG_COMPUTE (1 << 2)
72 #define DBG_VM (1 << 3)
75 #define DBG_FS (1 << 5)
76 #define DBG_VS (1 << 6)
77 #define DBG_GS (1 << 7)
78 #define DBG_PS (1 << 8)
79 #define DBG_CS (1 << 9)
80 #define DBG_TCS (1 << 10)
81 #define DBG_TES (1 << 11)
82 #define DBG_NO_IR (1 << 12)
83 #define DBG_NO_TGSI (1 << 13)
84 #define DBG_NO_ASM (1 << 14)
85 #define DBG_PREOPT_IR (1 << 15)
86 #define DBG_CHECK_IR (1 << 16)
87 #define DBG_NO_OPT_VARIANT (1 << 17)
89 #define DBG_TEST_DMA (1 << 20)
90 /* Bits 21-31 are reserved for the r600g driver. */
92 #define DBG_NO_ASYNC_DMA (1llu << 32)
93 #define DBG_NO_HYPERZ (1llu << 33)
94 #define DBG_NO_DISCARD_RANGE (1llu << 34)
95 #define DBG_NO_2D_TILING (1llu << 35)
96 #define DBG_NO_TILING (1llu << 36)
97 #define DBG_SWITCH_ON_EOP (1llu << 37)
98 #define DBG_FORCE_DMA (1llu << 38)
99 #define DBG_PRECOMPILE (1llu << 39)
100 #define DBG_INFO (1llu << 40)
101 #define DBG_NO_WC (1llu << 41)
102 #define DBG_CHECK_VM (1llu << 42)
103 #define DBG_NO_DCC (1llu << 43)
104 #define DBG_NO_DCC_CLEAR (1llu << 44)
105 #define DBG_NO_RB_PLUS (1llu << 45)
106 #define DBG_SI_SCHED (1llu << 46)
107 #define DBG_MONOLITHIC_SHADERS (1llu << 47)
108 #define DBG_NO_CE (1llu << 48)
109 #define DBG_UNSAFE_MATH (1llu << 49)
110 #define DBG_NO_DCC_FB (1llu << 50)
111 #define DBG_TEST_VMFAULT_CP (1llu << 51)
112 #define DBG_TEST_VMFAULT_SDMA (1llu << 52)
113 #define DBG_TEST_VMFAULT_SHADER (1llu << 53)
115 #define R600_MAP_BUFFER_ALIGNMENT 64
116 #define R600_MAX_VIEWPORTS 16
118 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
120 enum r600_coherency
{
121 R600_COHERENCY_NONE
, /* no cache flushes needed */
122 R600_COHERENCY_SHADER
,
123 R600_COHERENCY_CB_META
,
126 #ifdef PIPE_ARCH_BIG_ENDIAN
127 #define R600_BIG_ENDIAN 1
129 #define R600_BIG_ENDIAN 0
132 struct r600_common_context
;
133 struct r600_perfcounters
;
134 struct tgsi_shader_info
;
135 struct r600_qbo_state
;
137 void radeon_shader_binary_init(struct ac_shader_binary
*b
);
138 void radeon_shader_binary_clean(struct ac_shader_binary
*b
);
140 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
143 struct r600_resource
{
144 struct threaded_resource b
;
146 /* Winsys objects. */
147 struct pb_buffer
*buf
;
148 uint64_t gpu_address
;
149 /* Memory usage if the buffer placement is optimal. */
153 /* Resource properties. */
155 unsigned bo_alignment
;
156 enum radeon_bo_domain domains
;
157 enum radeon_bo_flag flags
;
158 unsigned bind_history
;
160 /* The buffer range which is initialized (with a write transfer,
161 * streamout, DMA, or as a random access target). The rest of
162 * the buffer is considered invalid and can be mapped unsynchronized.
164 * This allows unsychronized mapping of a buffer range which hasn't
165 * been used yet. It's for applications which forget to use
166 * the unsynchronized map flag and expect the driver to figure it out.
168 struct util_range valid_buffer_range
;
170 /* For buffers only. This indicates that a write operation has been
171 * performed by TC L2, but the cache hasn't been flushed.
172 * Any hw block which doesn't use or bypasses TC L2 should check this
173 * flag and flush the cache before using the buffer.
175 * For example, TC L2 must be flushed if a buffer which has been
176 * modified by a shader store instruction is about to be used as
177 * an index buffer. The reason is that VGT DMA index fetching doesn't
182 /* Whether the resource has been exported via resource_get_handle. */
183 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
186 struct r600_transfer
{
187 struct pipe_transfer transfer
;
188 struct r600_resource
*staging
;
192 struct r600_fmask_info
{
196 unsigned pitch_in_pixels
;
197 unsigned bank_height
;
198 unsigned slice_tile_max
;
199 unsigned tile_mode_index
;
202 struct r600_cmask_info
{
206 unsigned slice_tile_max
;
207 uint64_t base_address_reg
;
210 struct r600_texture
{
211 struct r600_resource resource
;
214 unsigned num_level0_transfers
;
215 enum pipe_format db_render_format
;
220 unsigned dirty_level_mask
; /* each bit says if that mipmap is compressed */
221 unsigned stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
222 struct r600_texture
*flushed_depth_texture
;
223 struct radeon_surf surface
;
225 /* Colorbuffer compression and fast clear. */
226 struct r600_fmask_info fmask
;
227 struct r600_cmask_info cmask
;
228 struct r600_resource
*cmask_buffer
;
229 uint64_t dcc_offset
; /* 0 = disabled */
230 unsigned cb_color_info
; /* fast clear enable bit */
231 unsigned color_clear_value
[2];
232 unsigned last_msaa_resolve_target_micro_mode
;
234 /* Depth buffer compression and fast clear. */
235 struct r600_resource
*htile_buffer
;
236 bool tc_compatible_htile
;
237 bool depth_cleared
; /* if it was cleared at least once */
238 float depth_clear_value
;
239 bool stencil_cleared
; /* if it was cleared at least once */
240 uint8_t stencil_clear_value
;
242 bool non_disp_tiling
; /* R600-Cayman only */
244 /* Whether the texture is a displayable back buffer and needs DCC
245 * decompression, which is expensive. Therefore, it's enabled only
246 * if statistics suggest that it will pay off and it's allocated
247 * separately. It can't be bound as a sampler by apps. Limited to
248 * target == 2D and last_level == 0. If enabled, dcc_offset contains
249 * the absolute GPUVM address, not the relative one.
251 struct r600_resource
*dcc_separate_buffer
;
252 /* When DCC is temporarily disabled, the separate buffer is here. */
253 struct r600_resource
*last_dcc_separate_buffer
;
254 /* We need to track DCC dirtiness, because st/dri usually calls
255 * flush_resource twice per frame (not a bug) and we don't wanna
256 * decompress DCC twice. Also, the dirty tracking must be done even
257 * if DCC isn't used, because it's required by the DCC usage analysis
258 * for a possible future enablement.
260 bool separate_dcc_dirty
;
261 /* Statistics gathering for the DCC enablement heuristic. */
262 bool dcc_gather_statistics
;
263 /* Estimate of how much this color buffer is written to in units of
264 * full-screen draws: ps_invocations / (width * height)
265 * Shader kills, late Z, and blending with trivial discards make it
266 * inaccurate (we need to count CB updates, not PS invocations).
268 unsigned ps_draw_ratio
;
269 /* The number of clears since the last DCC usage analysis. */
270 unsigned num_slow_clears
;
272 /* Counter that should be non-zero if the texture is bound to a
273 * framebuffer. Implemented in radeonsi only.
275 uint32_t framebuffers_bound
;
278 struct r600_surface
{
279 struct pipe_surface base
;
281 /* These can vary with block-compressed textures. */
285 bool color_initialized
;
286 bool depth_initialized
;
288 /* Misc. color flags. */
289 bool alphatest_bypass
;
293 bool dcc_incompatible
;
295 /* Color registers. */
296 unsigned cb_color_info
;
297 unsigned cb_color_base
;
298 unsigned cb_color_view
;
299 unsigned cb_color_size
; /* R600 only */
300 unsigned cb_color_dim
; /* EG only */
301 unsigned cb_color_pitch
; /* EG and later */
302 unsigned cb_color_slice
; /* EG and later */
303 unsigned cb_color_attrib
; /* EG and later */
304 unsigned cb_color_attrib2
; /* GFX9 and later */
305 unsigned cb_dcc_control
; /* VI and later */
306 unsigned cb_color_fmask
; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
307 unsigned cb_color_fmask_slice
; /* EG and later */
308 unsigned cb_color_cmask
; /* CB_COLORn_TILE (r600 only) */
309 unsigned cb_color_mask
; /* R600 only */
310 unsigned spi_shader_col_format
; /* SI+, no blending, no alpha-to-coverage. */
311 unsigned spi_shader_col_format_alpha
; /* SI+, alpha-to-coverage */
312 unsigned spi_shader_col_format_blend
; /* SI+, blending without alpha. */
313 unsigned spi_shader_col_format_blend_alpha
; /* SI+, blending with alpha. */
314 struct r600_resource
*cb_buffer_fmask
; /* Used for FMASK relocations. R600 only */
315 struct r600_resource
*cb_buffer_cmask
; /* Used for CMASK relocations. R600 only */
318 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
319 uint64_t db_stencil_base
; /* EG and later */
320 uint64_t db_htile_data_base
;
321 unsigned db_depth_info
; /* R600 only, then SI and later */
322 unsigned db_z_info
; /* EG and later */
323 unsigned db_z_info2
; /* GFX9+ */
324 unsigned db_depth_view
;
325 unsigned db_depth_size
;
326 unsigned db_depth_slice
; /* EG and later */
327 unsigned db_stencil_info
; /* EG and later */
328 unsigned db_stencil_info2
; /* GFX9+ */
329 unsigned db_prefetch_limit
; /* R600 only */
330 unsigned db_htile_surface
;
331 unsigned db_preload_control
; /* EG and later */
334 struct r600_mmio_counter
{
339 union r600_mmio_counters
{
341 /* For global GPU load including SDMA. */
342 struct r600_mmio_counter gpu
;
345 struct r600_mmio_counter spi
;
346 struct r600_mmio_counter gui
;
347 struct r600_mmio_counter ta
;
348 struct r600_mmio_counter gds
;
349 struct r600_mmio_counter vgt
;
350 struct r600_mmio_counter ia
;
351 struct r600_mmio_counter sx
;
352 struct r600_mmio_counter wd
;
353 struct r600_mmio_counter bci
;
354 struct r600_mmio_counter sc
;
355 struct r600_mmio_counter pa
;
356 struct r600_mmio_counter db
;
357 struct r600_mmio_counter cp
;
358 struct r600_mmio_counter cb
;
361 struct r600_mmio_counter sdma
;
364 struct r600_mmio_counter pfp
;
365 struct r600_mmio_counter meq
;
366 struct r600_mmio_counter me
;
367 struct r600_mmio_counter surf_sync
;
368 struct r600_mmio_counter dma
;
369 struct r600_mmio_counter scratch_ram
;
370 struct r600_mmio_counter ce
;
375 struct r600_common_screen
{
376 struct pipe_screen b
;
377 struct radeon_winsys
*ws
;
378 enum radeon_family family
;
379 enum chip_class chip_class
;
380 struct radeon_info info
;
381 uint64_t debug_flags
;
384 bool has_rbplus
; /* if RB+ registers exist */
385 bool rbplus_allowed
; /* if RB+ is allowed */
387 struct disk_cache
*disk_shader_cache
;
389 struct slab_parent_pool pool_transfers
;
391 /* Texture filter settings. */
392 int force_aniso
; /* -1 = disabled */
394 /* Auxiliary context. Mainly used to initialize resources.
395 * It must be locked prior to using and flushed before unlocking. */
396 struct pipe_context
*aux_context
;
397 mtx_t aux_context_lock
;
399 /* This must be in the screen, because UE4 uses one context for
400 * compilation and another one for rendering.
402 unsigned num_compilations
;
403 /* Along with ST_DEBUG=precompile, this should show if applications
404 * are loading shaders on demand. This is a monotonic counter.
406 unsigned num_shaders_created
;
407 unsigned num_shader_cache_hits
;
409 /* GPU load thread. */
410 mtx_t gpu_load_mutex
;
411 thrd_t gpu_load_thread
;
412 union r600_mmio_counters mmio_counters
;
413 volatile unsigned gpu_load_stop_thread
; /* bool */
415 char renderer_string
[100];
417 /* Performance counters. */
418 struct r600_perfcounters
*perfcounters
;
420 /* If pipe_screen wants to recompute and re-emit the framebuffer,
421 * sampler, and image states of all contexts, it should atomically
424 * Each context will compare this with its own last known value of
425 * the counter before drawing and re-emit the states accordingly.
427 unsigned dirty_tex_counter
;
429 /* Atomically increment this counter when an existing texture's
430 * metadata is enabled or disabled in a way that requires changing
431 * contexts' compressed texture binding masks.
433 unsigned compressed_colortex_counter
;
436 /* Context flags to set so that all writes from earlier jobs
437 * in the CP are seen by L2 clients.
441 /* Context flags to set so that all writes from earlier
442 * compute jobs are seen by L2 clients.
444 unsigned compute_to_L2
;
447 void (*query_opaque_metadata
)(struct r600_common_screen
*rscreen
,
448 struct r600_texture
*rtex
,
449 struct radeon_bo_metadata
*md
);
451 void (*apply_opaque_metadata
)(struct r600_common_screen
*rscreen
,
452 struct r600_texture
*rtex
,
453 struct radeon_bo_metadata
*md
);
456 /* This encapsulates a state or an operation which can emitted into the GPU
459 void (*emit
)(struct r600_common_context
*ctx
, struct r600_atom
*state
);
464 struct r600_so_target
{
465 struct pipe_stream_output_target b
;
467 /* The buffer where BUFFER_FILLED_SIZE is stored. */
468 struct r600_resource
*buf_filled_size
;
469 unsigned buf_filled_size_offset
;
470 bool buf_filled_size_valid
;
472 unsigned stride_in_dw
;
475 struct r600_streamout
{
476 struct r600_atom begin_atom
;
478 unsigned num_dw_for_end
;
480 unsigned enabled_mask
;
481 unsigned num_targets
;
482 struct r600_so_target
*targets
[PIPE_MAX_SO_BUFFERS
];
484 unsigned append_bitmask
;
487 /* External state which comes from the vertex shader,
488 * it must be set explicitly when binding a shader. */
489 uint16_t *stride_in_dw
;
490 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
492 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
493 unsigned hw_enabled_mask
;
495 /* The state of VGT_STRMOUT_(CONFIG|EN). */
496 struct r600_atom enable_atom
;
497 bool streamout_enabled
;
498 bool prims_gen_query_enabled
;
499 int num_prims_gen_queries
;
502 struct r600_signed_scissor
{
509 struct r600_scissors
{
510 struct r600_atom atom
;
512 struct pipe_scissor_state states
[R600_MAX_VIEWPORTS
];
515 struct r600_viewports
{
516 struct r600_atom atom
;
518 unsigned depth_range_dirty_mask
;
519 struct pipe_viewport_state states
[R600_MAX_VIEWPORTS
];
520 struct r600_signed_scissor as_scissor
[R600_MAX_VIEWPORTS
];
524 struct radeon_winsys_cs
*cs
;
525 void (*flush
)(void *ctx
, unsigned flags
,
526 struct pipe_fence_handle
**fence
);
529 /* Saved CS data for debugging features. */
530 struct radeon_saved_cs
{
534 struct radeon_bo_list_item
*bo_list
;
538 struct r600_common_context
{
539 struct pipe_context b
; /* base class */
541 struct r600_common_screen
*screen
;
542 struct radeon_winsys
*ws
;
543 struct radeon_winsys_ctx
*ctx
;
544 enum radeon_family family
;
545 enum chip_class chip_class
;
546 struct r600_ring gfx
;
547 struct r600_ring dma
;
548 struct pipe_fence_handle
*last_gfx_fence
;
549 struct pipe_fence_handle
*last_sdma_fence
;
550 unsigned num_gfx_cs_flushes
;
551 unsigned initial_gfx_cs_size
;
552 unsigned gpu_reset_counter
;
553 unsigned last_dirty_tex_counter
;
554 unsigned last_compressed_colortex_counter
;
556 struct u_suballocator
*allocator_zeroed_memory
;
557 struct slab_child_pool pool_transfers
;
558 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
560 /* Current unaccounted memory usage. */
565 struct r600_streamout streamout
;
566 struct r600_scissors scissors
;
567 struct r600_viewports viewports
;
568 bool scissor_enabled
;
570 bool vs_writes_viewport_index
;
571 bool vs_disables_clipping_viewport
;
573 /* Additional context states. */
574 unsigned flags
; /* flush flags */
577 /* Maintain the list of active queries for pausing between IBs. */
578 int num_occlusion_queries
;
579 int num_perfect_occlusion_queries
;
580 struct list_head active_queries
;
581 unsigned num_cs_dw_queries_suspend
;
583 unsigned num_draw_calls
;
584 unsigned num_prim_restart_calls
;
585 unsigned num_spill_draw_calls
;
586 unsigned num_compute_calls
;
587 unsigned num_spill_compute_calls
;
588 unsigned num_dma_calls
;
589 unsigned num_cp_dma_calls
;
590 unsigned num_vs_flushes
;
591 unsigned num_ps_flushes
;
592 unsigned num_cs_flushes
;
593 unsigned num_fb_cache_flushes
;
594 unsigned num_L2_invalidates
;
595 unsigned num_L2_writebacks
;
596 uint64_t num_alloc_tex_transfer_bytes
;
597 unsigned last_tex_ps_draw_ratio
; /* for query */
599 /* Render condition. */
600 struct r600_atom render_cond_atom
;
601 struct pipe_query
*render_cond
;
602 unsigned render_cond_mode
;
603 bool render_cond_invert
;
604 bool render_cond_force_off
; /* for u_blitter */
606 /* MSAA sample locations.
607 * The first index is the sample index.
608 * The second index is the coordinate: X, Y. */
609 float sample_locations_1x
[1][2];
610 float sample_locations_2x
[2][2];
611 float sample_locations_4x
[4][2];
612 float sample_locations_8x
[8][2];
613 float sample_locations_16x
[16][2];
615 /* Statistics gathering for the DCC enablement heuristic. It can't be
616 * in r600_texture because r600_texture can be shared by multiple
617 * contexts. This is for back buffers only. We shouldn't get too many
620 * X11 DRI3 rotates among a finite set of back buffers. They should
621 * all fit in this array. If they don't, separate DCC might never be
622 * enabled by DCC stat gathering.
625 struct r600_texture
*tex
;
626 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
627 struct pipe_query
*ps_stats
[3];
628 /* If all slots are used and another slot is needed,
629 * the least recently used slot is evicted based on this. */
630 int64_t last_use_timestamp
;
634 struct pipe_debug_callback debug
;
635 struct pipe_device_reset_callback device_reset_callback
;
637 void *query_result_shader
;
639 /* Copy one resource to another using async DMA. */
640 void (*dma_copy
)(struct pipe_context
*ctx
,
641 struct pipe_resource
*dst
,
643 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
644 struct pipe_resource
*src
,
646 const struct pipe_box
*src_box
);
648 void (*dma_clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
649 uint64_t offset
, uint64_t size
, unsigned value
);
651 void (*clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
652 uint64_t offset
, uint64_t size
, unsigned value
,
653 enum r600_coherency coher
);
655 void (*blit_decompress_depth
)(struct pipe_context
*ctx
,
656 struct r600_texture
*texture
,
657 struct r600_texture
*staging
,
658 unsigned first_level
, unsigned last_level
,
659 unsigned first_layer
, unsigned last_layer
,
660 unsigned first_sample
, unsigned last_sample
);
662 void (*decompress_dcc
)(struct pipe_context
*ctx
,
663 struct r600_texture
*rtex
);
665 /* Reallocate the buffer and update all resource bindings where
666 * the buffer is bound, including all resource descriptors. */
667 void (*invalidate_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
);
669 /* Enable or disable occlusion queries. */
670 void (*set_occlusion_query_state
)(struct pipe_context
*ctx
, bool enable
);
672 void (*save_qbo_state
)(struct pipe_context
*ctx
, struct r600_qbo_state
*st
);
674 /* This ensures there is enough space in the command stream. */
675 void (*need_gfx_cs_space
)(struct pipe_context
*ctx
, unsigned num_dw
,
676 bool include_draw_vbo
);
678 void (*set_atom_dirty
)(struct r600_common_context
*ctx
,
679 struct r600_atom
*atom
, bool dirty
);
681 void (*check_vm_faults
)(struct r600_common_context
*ctx
,
682 struct radeon_saved_cs
*saved
,
683 enum ring_type ring
);
687 bool r600_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
688 struct pb_buffer
*buf
,
689 enum radeon_bo_usage usage
);
690 void *r600_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
691 struct r600_resource
*resource
,
693 void r600_buffer_subdata(struct pipe_context
*ctx
,
694 struct pipe_resource
*buffer
,
695 unsigned usage
, unsigned offset
,
696 unsigned size
, const void *data
);
697 void r600_init_resource_fields(struct r600_common_screen
*rscreen
,
698 struct r600_resource
*res
,
699 uint64_t size
, unsigned alignment
);
700 bool r600_alloc_resource(struct r600_common_screen
*rscreen
,
701 struct r600_resource
*res
);
702 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
703 const struct pipe_resource
*templ
,
705 struct pipe_resource
* r600_aligned_buffer_create(struct pipe_screen
*screen
,
710 struct pipe_resource
*
711 r600_buffer_from_user_memory(struct pipe_screen
*screen
,
712 const struct pipe_resource
*templ
,
715 r600_invalidate_resource(struct pipe_context
*ctx
,
716 struct pipe_resource
*resource
);
718 /* r600_common_pipe.c */
719 void r600_gfx_write_event_eop(struct r600_common_context
*ctx
,
720 unsigned event
, unsigned event_flags
,
722 struct r600_resource
*buf
, uint64_t va
,
723 uint32_t old_fence
, uint32_t new_fence
);
724 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen
*screen
);
725 void r600_gfx_wait_fence(struct r600_common_context
*ctx
,
726 uint64_t va
, uint32_t ref
, uint32_t mask
);
727 void r600_draw_rectangle(struct blitter_context
*blitter
,
728 int x1
, int y1
, int x2
, int y2
, float depth
,
729 enum blitter_attrib_type type
,
730 const union pipe_color_union
*attrib
);
731 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
732 struct radeon_winsys
*ws
);
733 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
);
734 void r600_preflush_suspend_features(struct r600_common_context
*ctx
);
735 void r600_postflush_resume_features(struct r600_common_context
*ctx
);
736 bool r600_common_context_init(struct r600_common_context
*rctx
,
737 struct r600_common_screen
*rscreen
,
738 unsigned context_flags
);
739 void r600_common_context_cleanup(struct r600_common_context
*rctx
);
740 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
742 bool r600_extra_shader_checks(struct r600_common_screen
*rscreen
,
744 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
745 uint64_t offset
, uint64_t size
, unsigned value
);
746 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
747 const struct pipe_resource
*templ
);
748 const char *r600_get_llvm_processor_name(enum radeon_family family
);
749 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
,
750 struct r600_resource
*dst
, struct r600_resource
*src
);
751 void radeon_save_cs(struct radeon_winsys
*ws
, struct radeon_winsys_cs
*cs
,
752 struct radeon_saved_cs
*saved
);
753 void radeon_clear_saved_cs(struct radeon_saved_cs
*saved
);
754 bool r600_check_device_reset(struct r600_common_context
*rctx
);
756 /* r600_gpu_load.c */
757 void r600_gpu_load_kill_thread(struct r600_common_screen
*rscreen
);
758 uint64_t r600_begin_counter(struct r600_common_screen
*rscreen
, unsigned type
);
759 unsigned r600_end_counter(struct r600_common_screen
*rscreen
, unsigned type
,
762 /* r600_perfcounters.c */
763 void r600_perfcounters_destroy(struct r600_common_screen
*rscreen
);
766 void r600_init_screen_query_functions(struct r600_common_screen
*rscreen
);
767 void r600_query_init(struct r600_common_context
*rctx
);
768 void r600_suspend_queries(struct r600_common_context
*ctx
);
769 void r600_resume_queries(struct r600_common_context
*ctx
);
770 void r600_query_fix_enabled_rb_mask(struct r600_common_screen
*rscreen
);
772 /* r600_streamout.c */
773 void r600_streamout_buffers_dirty(struct r600_common_context
*rctx
);
774 void r600_set_streamout_targets(struct pipe_context
*ctx
,
775 unsigned num_targets
,
776 struct pipe_stream_output_target
**targets
,
777 const unsigned *offset
);
778 void r600_emit_streamout_end(struct r600_common_context
*rctx
);
779 void r600_update_prims_generated_query_state(struct r600_common_context
*rctx
,
780 unsigned type
, int diff
);
781 void r600_streamout_init(struct r600_common_context
*rctx
);
783 /* r600_test_dma.c */
784 void r600_test_dma(struct r600_common_screen
*rscreen
);
787 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
788 struct r600_texture
*rdst
,
789 unsigned dst_level
, unsigned dstx
,
790 unsigned dsty
, unsigned dstz
,
791 struct r600_texture
*rsrc
,
793 const struct pipe_box
*src_box
);
794 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
795 struct r600_texture
*rtex
,
797 struct r600_fmask_info
*out
);
798 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
799 struct r600_texture
*rtex
,
800 struct r600_cmask_info
*out
);
801 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
802 struct pipe_resource
*texture
,
803 struct r600_texture
**staging
);
804 void r600_print_texture_info(struct r600_common_screen
*rscreen
,
805 struct r600_texture
*rtex
, FILE *f
);
806 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
807 const struct pipe_resource
*templ
);
808 bool vi_dcc_formats_compatible(enum pipe_format format1
,
809 enum pipe_format format2
);
810 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
812 enum pipe_format view_format
);
813 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
814 struct pipe_resource
*tex
,
816 enum pipe_format view_format
);
817 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
818 struct pipe_resource
*texture
,
819 const struct pipe_surface
*templ
,
820 unsigned width0
, unsigned height0
,
821 unsigned width
, unsigned height
);
822 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
823 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
824 struct r600_texture
*tex
);
825 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
826 struct r600_texture
*tex
);
827 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
828 struct r600_texture
*tex
);
829 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
830 struct r600_texture
*rtex
,
831 unsigned level
, unsigned clear_value
);
832 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
833 struct pipe_framebuffer_state
*fb
,
834 struct r600_atom
*fb_state
,
835 unsigned *buffers
, unsigned *dirty_cbufs
,
836 const union pipe_color_union
*color
);
837 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
838 struct r600_texture
*rtex
);
839 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
);
840 void r600_init_context_texture_functions(struct r600_common_context
*rctx
);
842 /* r600_viewport.c */
843 void evergreen_apply_scissor_bug_workaround(struct r600_common_context
*rctx
,
844 struct pipe_scissor_state
*scissor
);
845 void r600_viewport_set_rast_deps(struct r600_common_context
*rctx
,
846 bool scissor_enable
, bool clip_halfz
);
847 void r600_update_vs_writes_viewport_index(struct r600_common_context
*rctx
,
848 struct tgsi_shader_info
*info
);
849 void r600_init_viewport_functions(struct r600_common_context
*rctx
);
852 extern const uint32_t eg_sample_locs_2x
[4];
853 extern const unsigned eg_max_dist_2x
;
854 extern const uint32_t eg_sample_locs_4x
[4];
855 extern const unsigned eg_max_dist_4x
;
856 void cayman_get_sample_position(struct pipe_context
*ctx
, unsigned sample_count
,
857 unsigned sample_index
, float *out_value
);
858 void cayman_init_msaa(struct pipe_context
*ctx
);
859 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
860 void cayman_emit_msaa_config(struct radeon_winsys_cs
*cs
, int nr_samples
,
861 int ps_iter_samples
, int overrast_samples
,
862 unsigned sc_mode_cntl_1
);
865 /* Inline helpers. */
867 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
869 return (struct r600_resource
*)r
;
873 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
875 pipe_resource_reference((struct pipe_resource
**)ptr
,
876 (struct pipe_resource
*)res
);
880 r600_texture_reference(struct r600_texture
**ptr
, struct r600_texture
*res
)
882 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->resource
.b
.b
);
886 r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
888 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
889 struct r600_resource
*res
= (struct r600_resource
*)r
;
892 /* Add memory usage for need_gfx_cs_space */
893 rctx
->vram
+= res
->vram_usage
;
894 rctx
->gtt
+= res
->gart_usage
;
898 static inline bool r600_get_strmout_en(struct r600_common_context
*rctx
)
900 return rctx
->streamout
.streamout_enabled
||
901 rctx
->streamout
.prims_gen_query_enabled
;
904 #define SQ_TEX_XY_FILTER_POINT 0x00
905 #define SQ_TEX_XY_FILTER_BILINEAR 0x01
906 #define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
907 #define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
909 static inline unsigned eg_tex_filter(unsigned filter
, unsigned max_aniso
)
911 if (filter
== PIPE_TEX_FILTER_LINEAR
)
912 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
913 : SQ_TEX_XY_FILTER_BILINEAR
;
915 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
916 : SQ_TEX_XY_FILTER_POINT
;
919 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
932 static inline unsigned r600_wavefront_size(enum radeon_family family
)
952 static inline enum radeon_bo_priority
953 r600_get_sampler_view_priority(struct r600_resource
*res
)
955 if (res
->b
.b
.target
== PIPE_BUFFER
)
956 return RADEON_PRIO_SAMPLER_BUFFER
;
958 if (res
->b
.b
.nr_samples
> 1)
959 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
961 return RADEON_PRIO_SAMPLER_TEXTURE
;
965 r600_can_sample_zs(struct r600_texture
*tex
, bool stencil_sampler
)
967 return (stencil_sampler
&& tex
->can_sample_s
) ||
968 (!stencil_sampler
&& tex
->can_sample_z
);
972 vi_dcc_enabled(struct r600_texture
*tex
, unsigned level
)
974 return tex
->dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
977 #define COMPUTE_DBG(rscreen, fmt, args...) \
979 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
982 #define R600_ERR(fmt, args...) \
983 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
985 /* For MSAA sample positions. */
986 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
987 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
988 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
989 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
990 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))