2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * This file contains common screen and context structures and functions
26 * for r600g and radeonsi.
29 #ifndef R600_PIPE_COMMON_H
30 #define R600_PIPE_COMMON_H
34 #include "amd/common/ac_binary.h"
36 #include "radeon/radeon_winsys.h"
38 #include "util/disk_cache.h"
39 #include "util/u_blitter.h"
40 #include "util/list.h"
41 #include "util/u_range.h"
42 #include "util/slab.h"
43 #include "util/u_suballoc.h"
44 #include "util/u_transfer.h"
45 #include "util/u_threaded_context.h"
51 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
52 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
53 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
54 #define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
55 #define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
59 /* Shader logging options: */
60 DBG_VS
= PIPE_SHADER_VERTEX
,
61 DBG_PS
= PIPE_SHADER_FRAGMENT
,
62 DBG_GS
= PIPE_SHADER_GEOMETRY
,
63 DBG_TCS
= PIPE_SHADER_TESS_CTRL
,
64 DBG_TES
= PIPE_SHADER_TESS_EVAL
,
65 DBG_CS
= PIPE_SHADER_COMPUTE
,
71 /* Shader compiler options the shader cache should be aware of: */
72 DBG_FS_CORRECT_DERIVS_AFTER_KILL
,
76 /* Shader compiler options (with no effect on the shader cache): */
80 DBG_MONOLITHIC_SHADERS
,
83 /* Information logging options: */
96 /* 3D engine options: */
116 DBG_TEST_VMFAULT_SDMA
,
117 DBG_TEST_VMFAULT_SHADER
,
120 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
121 #define DBG(name) (1ull << DBG_##name)
123 #define R600_MAP_BUFFER_ALIGNMENT 64
125 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
127 struct r600_common_context
;
128 struct r600_perfcounters
;
129 struct tgsi_shader_info
;
130 struct r600_qbo_state
;
132 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
135 struct r600_resource
{
136 struct threaded_resource b
;
138 /* Winsys objects. */
139 struct pb_buffer
*buf
;
140 uint64_t gpu_address
;
141 /* Memory usage if the buffer placement is optimal. */
145 /* Resource properties. */
147 unsigned bo_alignment
;
148 enum radeon_bo_domain domains
;
149 enum radeon_bo_flag flags
;
150 unsigned bind_history
;
151 int max_forced_staging_uploads
;
153 /* The buffer range which is initialized (with a write transfer,
154 * streamout, DMA, or as a random access target). The rest of
155 * the buffer is considered invalid and can be mapped unsynchronized.
157 * This allows unsychronized mapping of a buffer range which hasn't
158 * been used yet. It's for applications which forget to use
159 * the unsynchronized map flag and expect the driver to figure it out.
161 struct util_range valid_buffer_range
;
163 /* For buffers only. This indicates that a write operation has been
164 * performed by TC L2, but the cache hasn't been flushed.
165 * Any hw block which doesn't use or bypasses TC L2 should check this
166 * flag and flush the cache before using the buffer.
168 * For example, TC L2 must be flushed if a buffer which has been
169 * modified by a shader store instruction is about to be used as
170 * an index buffer. The reason is that VGT DMA index fetching doesn't
175 /* Whether the resource has been exported via resource_get_handle. */
176 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
178 /* Whether this resource is referenced by bindless handles. */
179 bool texture_handle_allocated
;
180 bool image_handle_allocated
;
183 struct r600_transfer
{
184 struct threaded_transfer b
;
185 struct r600_resource
*staging
;
189 struct r600_fmask_info
{
193 unsigned pitch_in_pixels
;
194 unsigned bank_height
;
195 unsigned slice_tile_max
;
196 unsigned tile_mode_index
;
197 unsigned tile_swizzle
;
200 struct r600_cmask_info
{
204 unsigned slice_tile_max
;
205 uint64_t base_address_reg
;
208 struct r600_texture
{
209 struct r600_resource resource
;
211 struct radeon_surf surface
;
213 struct r600_texture
*flushed_depth_texture
;
215 /* Colorbuffer compression and fast clear. */
216 struct r600_fmask_info fmask
;
217 struct r600_cmask_info cmask
;
218 struct r600_resource
*cmask_buffer
;
219 uint64_t dcc_offset
; /* 0 = disabled */
220 unsigned cb_color_info
; /* fast clear enable bit */
221 unsigned color_clear_value
[2];
222 unsigned last_msaa_resolve_target_micro_mode
;
223 unsigned num_level0_transfers
;
225 /* Depth buffer compression and fast clear. */
226 uint64_t htile_offset
;
227 float depth_clear_value
;
228 uint16_t dirty_level_mask
; /* each bit says if that mipmap is compressed */
229 uint16_t stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
230 enum pipe_format db_render_format
:16;
231 uint8_t stencil_clear_value
;
232 bool tc_compatible_htile
:1;
233 bool depth_cleared
:1; /* if it was cleared at least once */
234 bool stencil_cleared
:1; /* if it was cleared at least once */
235 bool upgraded_depth
:1; /* upgraded from unorm to Z32_FLOAT */
237 bool db_compatible
:1;
241 /* We need to track DCC dirtiness, because st/dri usually calls
242 * flush_resource twice per frame (not a bug) and we don't wanna
243 * decompress DCC twice. Also, the dirty tracking must be done even
244 * if DCC isn't used, because it's required by the DCC usage analysis
245 * for a possible future enablement.
247 bool separate_dcc_dirty
:1;
248 /* Statistics gathering for the DCC enablement heuristic. */
249 bool dcc_gather_statistics
:1;
250 /* Counter that should be non-zero if the texture is bound to a
253 unsigned framebuffers_bound
;
254 /* Whether the texture is a displayable back buffer and needs DCC
255 * decompression, which is expensive. Therefore, it's enabled only
256 * if statistics suggest that it will pay off and it's allocated
257 * separately. It can't be bound as a sampler by apps. Limited to
258 * target == 2D and last_level == 0. If enabled, dcc_offset contains
259 * the absolute GPUVM address, not the relative one.
261 struct r600_resource
*dcc_separate_buffer
;
262 /* When DCC is temporarily disabled, the separate buffer is here. */
263 struct r600_resource
*last_dcc_separate_buffer
;
264 /* Estimate of how much this color buffer is written to in units of
265 * full-screen draws: ps_invocations / (width * height)
266 * Shader kills, late Z, and blending with trivial discards make it
267 * inaccurate (we need to count CB updates, not PS invocations).
269 unsigned ps_draw_ratio
;
270 /* The number of clears since the last DCC usage analysis. */
271 unsigned num_slow_clears
;
274 struct r600_surface
{
275 struct pipe_surface base
;
277 /* These can vary with block-compressed textures. */
281 bool color_initialized
:1;
282 bool depth_initialized
:1;
284 /* Misc. color flags. */
285 bool color_is_int8
:1;
286 bool color_is_int10
:1;
287 bool dcc_incompatible
:1;
289 /* Color registers. */
290 unsigned cb_color_info
;
291 unsigned cb_color_view
;
292 unsigned cb_color_attrib
;
293 unsigned cb_color_attrib2
; /* GFX9 and later */
294 unsigned cb_dcc_control
; /* VI and later */
295 unsigned spi_shader_col_format
:8; /* no blending, no alpha-to-coverage. */
296 unsigned spi_shader_col_format_alpha
:8; /* alpha-to-coverage */
297 unsigned spi_shader_col_format_blend
:8; /* blending without alpha. */
298 unsigned spi_shader_col_format_blend_alpha
:8; /* blending with alpha. */
301 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE */
302 uint64_t db_stencil_base
;
303 uint64_t db_htile_data_base
;
304 unsigned db_depth_info
;
306 unsigned db_z_info2
; /* GFX9+ */
307 unsigned db_depth_view
;
308 unsigned db_depth_size
;
309 unsigned db_depth_slice
;
310 unsigned db_stencil_info
;
311 unsigned db_stencil_info2
; /* GFX9+ */
312 unsigned db_htile_surface
;
315 struct r600_mmio_counter
{
320 union r600_mmio_counters
{
322 /* For global GPU load including SDMA. */
323 struct r600_mmio_counter gpu
;
326 struct r600_mmio_counter spi
;
327 struct r600_mmio_counter gui
;
328 struct r600_mmio_counter ta
;
329 struct r600_mmio_counter gds
;
330 struct r600_mmio_counter vgt
;
331 struct r600_mmio_counter ia
;
332 struct r600_mmio_counter sx
;
333 struct r600_mmio_counter wd
;
334 struct r600_mmio_counter bci
;
335 struct r600_mmio_counter sc
;
336 struct r600_mmio_counter pa
;
337 struct r600_mmio_counter db
;
338 struct r600_mmio_counter cp
;
339 struct r600_mmio_counter cb
;
342 struct r600_mmio_counter sdma
;
345 struct r600_mmio_counter pfp
;
346 struct r600_mmio_counter meq
;
347 struct r600_mmio_counter me
;
348 struct r600_mmio_counter surf_sync
;
349 struct r600_mmio_counter cp_dma
;
350 struct r600_mmio_counter scratch_ram
;
355 struct r600_memory_object
{
356 struct pipe_memory_object b
;
357 struct pb_buffer
*buf
;
362 struct r600_common_screen
{
363 struct pipe_screen b
;
364 struct radeon_winsys
*ws
;
365 enum radeon_family family
;
366 enum chip_class chip_class
;
367 struct radeon_info info
;
368 uint64_t debug_flags
;
369 bool has_rbplus
; /* if RB+ registers exist */
370 bool rbplus_allowed
; /* if RB+ is allowed */
371 bool dcc_msaa_allowed
;
373 struct disk_cache
*disk_shader_cache
;
375 struct slab_parent_pool pool_transfers
;
377 /* Texture filter settings. */
378 int force_aniso
; /* -1 = disabled */
380 /* Auxiliary context. Mainly used to initialize resources.
381 * It must be locked prior to using and flushed before unlocking. */
382 struct pipe_context
*aux_context
;
383 mtx_t aux_context_lock
;
385 /* This must be in the screen, because UE4 uses one context for
386 * compilation and another one for rendering.
388 unsigned num_compilations
;
389 /* Along with ST_DEBUG=precompile, this should show if applications
390 * are loading shaders on demand. This is a monotonic counter.
392 unsigned num_shaders_created
;
393 unsigned num_shader_cache_hits
;
395 /* GPU load thread. */
396 mtx_t gpu_load_mutex
;
397 thrd_t gpu_load_thread
;
398 union r600_mmio_counters mmio_counters
;
399 volatile unsigned gpu_load_stop_thread
; /* bool */
401 char renderer_string
[100];
403 /* Performance counters. */
404 struct r600_perfcounters
*perfcounters
;
406 /* If pipe_screen wants to recompute and re-emit the framebuffer,
407 * sampler, and image states of all contexts, it should atomically
410 * Each context will compare this with its own last known value of
411 * the counter before drawing and re-emit the states accordingly.
413 unsigned dirty_tex_counter
;
415 /* Atomically increment this counter when an existing texture's
416 * metadata is enabled or disabled in a way that requires changing
417 * contexts' compressed texture binding masks.
419 unsigned compressed_colortex_counter
;
422 /* Context flags to set so that all writes from earlier jobs
423 * in the CP are seen by L2 clients.
427 /* Context flags to set so that all writes from earlier jobs
428 * that end in L2 are seen by CP.
432 /* Context flags to set so that all writes from earlier
433 * compute jobs are seen by L2 clients.
435 unsigned compute_to_L2
;
439 /* This encapsulates a state or an operation which can emitted into the GPU
442 void (*emit
)(struct r600_common_context
*ctx
, struct r600_atom
*state
);
447 struct radeon_winsys_cs
*cs
;
448 void (*flush
)(void *ctx
, unsigned flags
,
449 struct pipe_fence_handle
**fence
);
452 /* Saved CS data for debugging features. */
453 struct radeon_saved_cs
{
457 struct radeon_bo_list_item
*bo_list
;
461 struct r600_common_context
{
462 struct pipe_context b
; /* base class */
464 struct r600_common_screen
*screen
;
465 struct radeon_winsys
*ws
;
466 struct radeon_winsys_ctx
*ctx
;
467 enum radeon_family family
;
468 enum chip_class chip_class
;
469 struct r600_ring gfx
;
470 struct r600_ring dma
;
471 struct pipe_fence_handle
*last_gfx_fence
;
472 struct pipe_fence_handle
*last_sdma_fence
;
473 struct r600_resource
*eop_bug_scratch
;
474 unsigned num_gfx_cs_flushes
;
475 unsigned initial_gfx_cs_size
;
476 unsigned gpu_reset_counter
;
477 unsigned last_dirty_tex_counter
;
478 unsigned last_compressed_colortex_counter
;
479 unsigned last_num_draw_calls
;
481 struct threaded_context
*tc
;
482 struct u_suballocator
*allocator_zeroed_memory
;
483 struct slab_child_pool pool_transfers
;
484 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
486 /* Current unaccounted memory usage. */
490 /* Additional context states. */
491 unsigned flags
; /* flush flags */
494 /* Maintain the list of active queries for pausing between IBs. */
495 int num_occlusion_queries
;
496 int num_perfect_occlusion_queries
;
497 struct list_head active_queries
;
498 unsigned num_cs_dw_queries_suspend
;
500 unsigned num_draw_calls
;
501 unsigned num_decompress_calls
;
502 unsigned num_mrt_draw_calls
;
503 unsigned num_prim_restart_calls
;
504 unsigned num_spill_draw_calls
;
505 unsigned num_compute_calls
;
506 unsigned num_spill_compute_calls
;
507 unsigned num_dma_calls
;
508 unsigned num_cp_dma_calls
;
509 unsigned num_vs_flushes
;
510 unsigned num_ps_flushes
;
511 unsigned num_cs_flushes
;
512 unsigned num_cb_cache_flushes
;
513 unsigned num_db_cache_flushes
;
514 unsigned num_L2_invalidates
;
515 unsigned num_L2_writebacks
;
516 unsigned num_resident_handles
;
517 uint64_t num_alloc_tex_transfer_bytes
;
518 unsigned last_tex_ps_draw_ratio
; /* for query */
520 /* Render condition. */
521 struct r600_atom render_cond_atom
;
522 struct pipe_query
*render_cond
;
523 unsigned render_cond_mode
;
524 bool render_cond_invert
;
525 bool render_cond_force_off
; /* for u_blitter */
527 /* Statistics gathering for the DCC enablement heuristic. It can't be
528 * in r600_texture because r600_texture can be shared by multiple
529 * contexts. This is for back buffers only. We shouldn't get too many
532 * X11 DRI3 rotates among a finite set of back buffers. They should
533 * all fit in this array. If they don't, separate DCC might never be
534 * enabled by DCC stat gathering.
537 struct r600_texture
*tex
;
538 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
539 struct pipe_query
*ps_stats
[3];
540 /* If all slots are used and another slot is needed,
541 * the least recently used slot is evicted based on this. */
542 int64_t last_use_timestamp
;
546 struct pipe_device_reset_callback device_reset_callback
;
547 struct u_log_context
*log
;
549 void *query_result_shader
;
551 /* Copy one resource to another using async DMA. */
552 void (*dma_copy
)(struct pipe_context
*ctx
,
553 struct pipe_resource
*dst
,
555 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
556 struct pipe_resource
*src
,
558 const struct pipe_box
*src_box
);
560 void (*dma_clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
561 uint64_t offset
, uint64_t size
, unsigned value
);
563 void (*blit_decompress_depth
)(struct pipe_context
*ctx
,
564 struct r600_texture
*texture
,
565 struct r600_texture
*staging
,
566 unsigned first_level
, unsigned last_level
,
567 unsigned first_layer
, unsigned last_layer
,
568 unsigned first_sample
, unsigned last_sample
);
570 void (*decompress_dcc
)(struct pipe_context
*ctx
,
571 struct r600_texture
*rtex
);
573 /* Reallocate the buffer and update all resource bindings where
574 * the buffer is bound, including all resource descriptors. */
575 void (*invalidate_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
);
577 /* Update all resource bindings where the buffer is bound, including
578 * all resource descriptors. This is invalidate_buffer without
579 * the invalidation. */
580 void (*rebind_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
581 uint64_t old_gpu_address
);
583 /* Enable or disable occlusion queries. */
584 void (*set_occlusion_query_state
)(struct pipe_context
*ctx
,
586 bool old_perfect_enable
);
588 void (*save_qbo_state
)(struct pipe_context
*ctx
, struct r600_qbo_state
*st
);
590 /* This ensures there is enough space in the command stream. */
591 void (*need_gfx_cs_space
)(struct pipe_context
*ctx
, unsigned num_dw
,
592 bool include_draw_vbo
);
594 void (*set_atom_dirty
)(struct r600_common_context
*ctx
,
595 struct r600_atom
*atom
, bool dirty
);
597 void (*check_vm_faults
)(struct r600_common_context
*ctx
,
598 struct radeon_saved_cs
*saved
,
599 enum ring_type ring
);
602 /* r600_buffer_common.c */
603 bool si_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
604 struct pb_buffer
*buf
,
605 enum radeon_bo_usage usage
);
606 void *si_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
607 struct r600_resource
*resource
,
609 void si_init_resource_fields(struct r600_common_screen
*rscreen
,
610 struct r600_resource
*res
,
611 uint64_t size
, unsigned alignment
);
612 bool si_alloc_resource(struct r600_common_screen
*rscreen
,
613 struct r600_resource
*res
);
614 struct pipe_resource
*si_aligned_buffer_create(struct pipe_screen
*screen
,
619 void si_replace_buffer_storage(struct pipe_context
*ctx
,
620 struct pipe_resource
*dst
,
621 struct pipe_resource
*src
);
622 void si_init_screen_buffer_functions(struct si_screen
*sscreen
);
623 void si_init_buffer_functions(struct si_context
*sctx
);
625 /* r600_common_pipe.c */
626 void si_gfx_write_event_eop(struct r600_common_context
*ctx
,
627 unsigned event
, unsigned event_flags
,
629 struct r600_resource
*buf
, uint64_t va
,
630 uint32_t new_fence
, unsigned query_type
);
631 unsigned si_gfx_write_fence_dwords(struct r600_common_screen
*screen
);
632 void si_gfx_wait_fence(struct r600_common_context
*ctx
,
633 uint64_t va
, uint32_t ref
, uint32_t mask
);
634 bool si_common_context_init(struct r600_common_context
*rctx
,
635 struct r600_common_screen
*rscreen
,
636 unsigned context_flags
);
637 void si_common_context_cleanup(struct r600_common_context
*rctx
);
638 void si_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
639 uint64_t offset
, uint64_t size
, unsigned value
);
640 void si_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
,
641 struct r600_resource
*dst
, struct r600_resource
*src
);
642 void si_save_cs(struct radeon_winsys
*ws
, struct radeon_winsys_cs
*cs
,
643 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
644 void si_clear_saved_cs(struct radeon_saved_cs
*saved
);
645 bool si_check_device_reset(struct r600_common_context
*rctx
);
647 /* r600_gpu_load.c */
648 void si_gpu_load_kill_thread(struct r600_common_screen
*rscreen
);
649 uint64_t si_begin_counter(struct r600_common_screen
*rscreen
, unsigned type
);
650 unsigned si_end_counter(struct r600_common_screen
*rscreen
, unsigned type
,
653 /* r600_perfcounters.c */
654 void si_perfcounters_destroy(struct r600_common_screen
*rscreen
);
657 void si_init_screen_query_functions(struct r600_common_screen
*rscreen
);
658 void si_init_query_functions(struct r600_common_context
*rctx
);
659 void si_suspend_queries(struct r600_common_context
*ctx
);
660 void si_resume_queries(struct r600_common_context
*ctx
);
663 bool si_prepare_for_dma_blit(struct r600_common_context
*rctx
,
664 struct r600_texture
*rdst
,
665 unsigned dst_level
, unsigned dstx
,
666 unsigned dsty
, unsigned dstz
,
667 struct r600_texture
*rsrc
,
669 const struct pipe_box
*src_box
);
670 void si_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
671 struct r600_texture
*rtex
,
673 struct r600_fmask_info
*out
);
674 void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
675 struct r600_texture
*rtex
,
676 struct r600_cmask_info
*out
);
677 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
678 struct pipe_resource
*texture
,
679 struct r600_texture
**staging
);
680 void si_print_texture_info(struct r600_common_screen
*rscreen
,
681 struct r600_texture
*rtex
, struct u_log_context
*log
);
682 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
683 const struct pipe_resource
*templ
);
684 bool vi_dcc_formats_compatible(enum pipe_format format1
,
685 enum pipe_format format2
);
686 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
688 enum pipe_format view_format
);
689 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
690 struct pipe_resource
*tex
,
692 enum pipe_format view_format
);
693 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
694 struct pipe_resource
*texture
,
695 const struct pipe_surface
*templ
,
696 unsigned width0
, unsigned height0
,
697 unsigned width
, unsigned height
);
698 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
699 void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
700 struct r600_texture
*tex
);
701 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
702 struct r600_texture
*tex
);
703 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
704 struct r600_texture
*tex
);
705 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
706 struct r600_texture
*tex
);
707 bool si_texture_disable_dcc(struct r600_common_context
*rctx
,
708 struct r600_texture
*rtex
);
709 void si_init_screen_texture_functions(struct r600_common_screen
*rscreen
);
710 void si_init_context_texture_functions(struct r600_common_context
*rctx
);
713 /* Inline helpers. */
715 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
717 return (struct r600_resource
*)r
;
721 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
723 pipe_resource_reference((struct pipe_resource
**)ptr
,
724 (struct pipe_resource
*)res
);
728 r600_texture_reference(struct r600_texture
**ptr
, struct r600_texture
*res
)
730 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->resource
.b
.b
);
734 vi_dcc_enabled(struct r600_texture
*tex
, unsigned level
)
736 return tex
->dcc_offset
&& level
< tex
->surface
.num_dcc_levels
;
739 #define R600_ERR(fmt, args...) \
740 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)