2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
37 #include "radeon/radeon_winsys.h"
39 #include "util/u_blitter.h"
40 #include "util/list.h"
41 #include "util/u_range.h"
42 #include "util/slab.h"
43 #include "util/u_suballoc.h"
44 #include "util/u_transfer.h"
46 #define ATI_VENDOR_ID 0x1002
48 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
49 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
50 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
51 #define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
53 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
54 /* Pipeline & streamout query controls. */
55 #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
56 #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
57 #define R600_CONTEXT_PRIVATE_FLAG (1u << 3)
59 /* special primitive types */
60 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
64 #define DBG_TEX (1 << 0)
66 #define DBG_COMPUTE (1 << 2)
67 #define DBG_VM (1 << 3)
70 #define DBG_FS (1 << 5)
71 #define DBG_VS (1 << 6)
72 #define DBG_GS (1 << 7)
73 #define DBG_PS (1 << 8)
74 #define DBG_CS (1 << 9)
75 #define DBG_TCS (1 << 10)
76 #define DBG_TES (1 << 11)
77 #define DBG_NO_IR (1 << 12)
78 #define DBG_NO_TGSI (1 << 13)
79 #define DBG_NO_ASM (1 << 14)
80 #define DBG_PREOPT_IR (1 << 15)
81 #define DBG_CHECK_IR (1 << 16)
83 #define DBG_TEST_DMA (1 << 20)
84 /* Bits 21-31 are reserved for the r600g driver. */
86 #define DBG_NO_ASYNC_DMA (1llu << 32)
87 #define DBG_NO_HYPERZ (1llu << 33)
88 #define DBG_NO_DISCARD_RANGE (1llu << 34)
89 #define DBG_NO_2D_TILING (1llu << 35)
90 #define DBG_NO_TILING (1llu << 36)
91 #define DBG_SWITCH_ON_EOP (1llu << 37)
92 #define DBG_FORCE_DMA (1llu << 38)
93 #define DBG_PRECOMPILE (1llu << 39)
94 #define DBG_INFO (1llu << 40)
95 #define DBG_NO_WC (1llu << 41)
96 #define DBG_CHECK_VM (1llu << 42)
97 #define DBG_NO_DCC (1llu << 43)
98 #define DBG_NO_DCC_CLEAR (1llu << 44)
99 #define DBG_NO_RB_PLUS (1llu << 45)
100 #define DBG_SI_SCHED (1llu << 46)
101 #define DBG_MONOLITHIC_SHADERS (1llu << 47)
102 #define DBG_NO_CE (1llu << 48)
103 #define DBG_UNSAFE_MATH (1llu << 49)
104 #define DBG_NO_DCC_FB (1llu << 50)
106 #define R600_MAP_BUFFER_ALIGNMENT 64
107 #define R600_MAX_VIEWPORTS 16
109 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
111 enum r600_coherency
{
112 R600_COHERENCY_NONE
, /* no cache flushes needed */
113 R600_COHERENCY_SHADER
,
114 R600_COHERENCY_CB_META
,
117 #ifdef PIPE_ARCH_BIG_ENDIAN
118 #define R600_BIG_ENDIAN 1
120 #define R600_BIG_ENDIAN 0
123 struct r600_common_context
;
124 struct r600_perfcounters
;
125 struct tgsi_shader_info
;
126 struct r600_qbo_state
;
128 struct radeon_shader_reloc
{
133 struct radeon_shader_binary
{
138 /** Config/Context register state that accompanies this shader.
139 * This is a stream of dword pairs. First dword contains the
140 * register address, the second dword contains the value.*/
141 unsigned char *config
;
142 unsigned config_size
;
144 /** The number of bytes of config information for each global symbol.
146 unsigned config_size_per_symbol
;
148 /** Constant data accessed by the shader. This will be uploaded
149 * into a constant buffer. */
150 unsigned char *rodata
;
151 unsigned rodata_size
;
153 /** List of symbol offsets for the shader */
154 uint64_t *global_symbol_offsets
;
155 unsigned global_symbol_count
;
157 struct radeon_shader_reloc
*relocs
;
158 unsigned reloc_count
;
160 /** Disassembled shader in a string. */
162 char *llvm_ir_string
;
165 void radeon_shader_binary_init(struct radeon_shader_binary
*b
);
166 void radeon_shader_binary_clean(struct radeon_shader_binary
*b
);
168 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
171 struct r600_resource
{
174 /* Winsys objects. */
175 struct pb_buffer
*buf
;
176 uint64_t gpu_address
;
177 /* Memory usage if the buffer placement is optimal. */
181 /* Resource properties. */
183 unsigned bo_alignment
;
184 enum radeon_bo_domain domains
;
185 enum radeon_bo_flag flags
;
186 unsigned bind_history
;
188 /* The buffer range which is initialized (with a write transfer,
189 * streamout, DMA, or as a random access target). The rest of
190 * the buffer is considered invalid and can be mapped unsynchronized.
192 * This allows unsychronized mapping of a buffer range which hasn't
193 * been used yet. It's for applications which forget to use
194 * the unsynchronized map flag and expect the driver to figure it out.
196 struct util_range valid_buffer_range
;
198 /* For buffers only. This indicates that a write operation has been
199 * performed by TC L2, but the cache hasn't been flushed.
200 * Any hw block which doesn't use or bypasses TC L2 should check this
201 * flag and flush the cache before using the buffer.
203 * For example, TC L2 must be flushed if a buffer which has been
204 * modified by a shader store instruction is about to be used as
205 * an index buffer. The reason is that VGT DMA index fetching doesn't
210 /* Whether the resource has been exported via resource_get_handle. */
212 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
215 struct r600_transfer
{
216 struct pipe_transfer transfer
;
217 struct r600_resource
*staging
;
221 struct r600_fmask_info
{
225 unsigned pitch_in_pixels
;
226 unsigned bank_height
;
227 unsigned slice_tile_max
;
228 unsigned tile_mode_index
;
231 struct r600_cmask_info
{
235 unsigned slice_tile_max
;
236 unsigned base_address_reg
;
239 struct r600_texture
{
240 struct r600_resource resource
;
243 unsigned num_level0_transfers
;
244 enum pipe_format db_render_format
;
249 unsigned dirty_level_mask
; /* each bit says if that mipmap is compressed */
250 unsigned stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
251 struct r600_texture
*flushed_depth_texture
;
252 struct radeon_surf surface
;
254 /* Colorbuffer compression and fast clear. */
255 struct r600_fmask_info fmask
;
256 struct r600_cmask_info cmask
;
257 struct r600_resource
*cmask_buffer
;
258 uint64_t dcc_offset
; /* 0 = disabled */
259 unsigned cb_color_info
; /* fast clear enable bit */
260 unsigned color_clear_value
[2];
261 unsigned last_msaa_resolve_target_micro_mode
;
263 /* Depth buffer compression and fast clear. */
264 struct r600_resource
*htile_buffer
;
265 bool tc_compatible_htile
;
266 bool depth_cleared
; /* if it was cleared at least once */
267 float depth_clear_value
;
268 bool stencil_cleared
; /* if it was cleared at least once */
269 uint8_t stencil_clear_value
;
271 bool non_disp_tiling
; /* R600-Cayman only */
273 /* Whether the texture is a displayable back buffer and needs DCC
274 * decompression, which is expensive. Therefore, it's enabled only
275 * if statistics suggest that it will pay off and it's allocated
276 * separately. It can't be bound as a sampler by apps. Limited to
277 * target == 2D and last_level == 0. If enabled, dcc_offset contains
278 * the absolute GPUVM address, not the relative one.
280 struct r600_resource
*dcc_separate_buffer
;
281 /* When DCC is temporarily disabled, the separate buffer is here. */
282 struct r600_resource
*last_dcc_separate_buffer
;
283 /* We need to track DCC dirtiness, because st/dri usually calls
284 * flush_resource twice per frame (not a bug) and we don't wanna
285 * decompress DCC twice. Also, the dirty tracking must be done even
286 * if DCC isn't used, because it's required by the DCC usage analysis
287 * for a possible future enablement.
289 bool separate_dcc_dirty
;
290 /* Statistics gathering for the DCC enablement heuristic. */
291 bool dcc_gather_statistics
;
292 /* Estimate of how much this color buffer is written to in units of
293 * full-screen draws: ps_invocations / (width * height)
294 * Shader kills, late Z, and blending with trivial discards make it
295 * inaccurate (we need to count CB updates, not PS invocations).
297 unsigned ps_draw_ratio
;
298 /* The number of clears since the last DCC usage analysis. */
299 unsigned num_slow_clears
;
301 /* Counter that should be non-zero if the texture is bound to a
302 * framebuffer. Implemented in radeonsi only.
304 uint32_t framebuffers_bound
;
307 struct r600_surface
{
308 struct pipe_surface base
;
309 const struct radeon_surf_level
*level_info
;
311 bool color_initialized
;
312 bool depth_initialized
;
314 /* Misc. color flags. */
315 bool alphatest_bypass
;
319 /* Color registers. */
320 unsigned cb_color_info
;
321 unsigned cb_color_base
;
322 unsigned cb_color_view
;
323 unsigned cb_color_size
; /* R600 only */
324 unsigned cb_color_dim
; /* EG only */
325 unsigned cb_color_pitch
; /* EG and later */
326 unsigned cb_color_slice
; /* EG and later */
327 unsigned cb_color_attrib
; /* EG and later */
328 unsigned cb_dcc_control
; /* VI and later */
329 unsigned cb_color_fmask
; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
330 unsigned cb_color_fmask_slice
; /* EG and later */
331 unsigned cb_color_cmask
; /* CB_COLORn_TILE (r600 only) */
332 unsigned cb_color_mask
; /* R600 only */
333 unsigned spi_shader_col_format
; /* SI+, no blending, no alpha-to-coverage. */
334 unsigned spi_shader_col_format_alpha
; /* SI+, alpha-to-coverage */
335 unsigned spi_shader_col_format_blend
; /* SI+, blending without alpha. */
336 unsigned spi_shader_col_format_blend_alpha
; /* SI+, blending with alpha. */
337 struct r600_resource
*cb_buffer_fmask
; /* Used for FMASK relocations. R600 only */
338 struct r600_resource
*cb_buffer_cmask
; /* Used for CMASK relocations. R600 only */
341 unsigned db_depth_info
; /* R600 only, then SI and later */
342 unsigned db_z_info
; /* EG and later */
343 unsigned db_depth_base
; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
344 unsigned db_depth_view
;
345 unsigned db_depth_size
;
346 unsigned db_depth_slice
; /* EG and later */
347 unsigned db_stencil_base
; /* EG and later */
348 unsigned db_stencil_info
; /* EG and later */
349 unsigned db_prefetch_limit
; /* R600 only */
350 unsigned db_htile_surface
;
351 unsigned db_htile_data_base
;
352 unsigned db_preload_control
; /* EG and later */
355 struct r600_common_screen
{
356 struct pipe_screen b
;
357 struct radeon_winsys
*ws
;
358 enum radeon_family family
;
359 enum chip_class chip_class
;
360 struct radeon_info info
;
361 uint64_t debug_flags
;
365 struct slab_parent_pool pool_transfers
;
367 /* Texture filter settings. */
368 int force_aniso
; /* -1 = disabled */
370 /* Auxiliary context. Mainly used to initialize resources.
371 * It must be locked prior to using and flushed before unlocking. */
372 struct pipe_context
*aux_context
;
373 pipe_mutex aux_context_lock
;
375 /* This must be in the screen, because UE4 uses one context for
376 * compilation and another one for rendering.
378 unsigned num_compilations
;
379 /* Along with ST_DEBUG=precompile, this should show if applications
380 * are loading shaders on demand. This is a monotonic counter.
382 unsigned num_shaders_created
;
383 unsigned num_shader_cache_hits
;
385 /* GPU load thread. */
386 pipe_mutex gpu_load_mutex
;
387 pipe_thread gpu_load_thread
;
388 unsigned gpu_load_counter_busy
;
389 unsigned gpu_load_counter_idle
;
390 volatile unsigned gpu_load_stop_thread
; /* bool */
392 char renderer_string
[100];
394 /* Performance counters. */
395 struct r600_perfcounters
*perfcounters
;
397 /* If pipe_screen wants to re-emit the framebuffer state of all
398 * contexts, it should atomically increment this. Each context will
399 * compare this with its own last known value of the counter before
400 * drawing and re-emit the framebuffer state accordingly.
402 unsigned dirty_fb_counter
;
404 /* Atomically increment this counter when an existing texture's
405 * metadata is enabled or disabled in a way that requires changing
406 * contexts' compressed texture binding masks.
408 unsigned compressed_colortex_counter
;
410 /* Atomically increment this counter when an existing texture's
411 * backing buffer or tile mode parameters have changed that requires
412 * recomputation of shader descriptors.
414 unsigned dirty_tex_descriptor_counter
;
417 /* Context flags to set so that all writes from earlier jobs
418 * in the CP are seen by L2 clients.
422 /* Context flags to set so that all writes from earlier
423 * compute jobs are seen by L2 clients.
425 unsigned compute_to_L2
;
428 void (*query_opaque_metadata
)(struct r600_common_screen
*rscreen
,
429 struct r600_texture
*rtex
,
430 struct radeon_bo_metadata
*md
);
432 void (*apply_opaque_metadata
)(struct r600_common_screen
*rscreen
,
433 struct r600_texture
*rtex
,
434 struct radeon_bo_metadata
*md
);
437 /* This encapsulates a state or an operation which can emitted into the GPU
440 void (*emit
)(struct r600_common_context
*ctx
, struct r600_atom
*state
);
445 struct r600_so_target
{
446 struct pipe_stream_output_target b
;
448 /* The buffer where BUFFER_FILLED_SIZE is stored. */
449 struct r600_resource
*buf_filled_size
;
450 unsigned buf_filled_size_offset
;
451 bool buf_filled_size_valid
;
453 unsigned stride_in_dw
;
456 struct r600_streamout
{
457 struct r600_atom begin_atom
;
459 unsigned num_dw_for_end
;
461 unsigned enabled_mask
;
462 unsigned num_targets
;
463 struct r600_so_target
*targets
[PIPE_MAX_SO_BUFFERS
];
465 unsigned append_bitmask
;
468 /* External state which comes from the vertex shader,
469 * it must be set explicitly when binding a shader. */
470 unsigned *stride_in_dw
;
471 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
473 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
474 unsigned hw_enabled_mask
;
476 /* The state of VGT_STRMOUT_(CONFIG|EN). */
477 struct r600_atom enable_atom
;
478 bool streamout_enabled
;
479 bool prims_gen_query_enabled
;
480 int num_prims_gen_queries
;
483 struct r600_signed_scissor
{
490 struct r600_scissors
{
491 struct r600_atom atom
;
493 struct pipe_scissor_state states
[R600_MAX_VIEWPORTS
];
496 struct r600_viewports
{
497 struct r600_atom atom
;
499 unsigned depth_range_dirty_mask
;
500 struct pipe_viewport_state states
[R600_MAX_VIEWPORTS
];
501 struct r600_signed_scissor as_scissor
[R600_MAX_VIEWPORTS
];
505 struct radeon_winsys_cs
*cs
;
506 void (*flush
)(void *ctx
, unsigned flags
,
507 struct pipe_fence_handle
**fence
);
510 /* Saved CS data for debugging features. */
511 struct radeon_saved_cs
{
515 struct radeon_bo_list_item
*bo_list
;
519 struct r600_common_context
{
520 struct pipe_context b
; /* base class */
522 struct r600_common_screen
*screen
;
523 struct radeon_winsys
*ws
;
524 struct radeon_winsys_ctx
*ctx
;
525 enum radeon_family family
;
526 enum chip_class chip_class
;
527 struct r600_ring gfx
;
528 struct r600_ring dma
;
529 struct pipe_fence_handle
*last_gfx_fence
;
530 struct pipe_fence_handle
*last_sdma_fence
;
531 unsigned num_gfx_cs_flushes
;
532 unsigned initial_gfx_cs_size
;
533 unsigned gpu_reset_counter
;
534 unsigned last_dirty_fb_counter
;
535 unsigned last_compressed_colortex_counter
;
536 unsigned last_dirty_tex_descriptor_counter
;
538 struct u_upload_mgr
*uploader
;
539 struct u_suballocator
*allocator_zeroed_memory
;
540 struct slab_child_pool pool_transfers
;
542 /* Current unaccounted memory usage. */
547 struct r600_streamout streamout
;
548 struct r600_scissors scissors
;
549 struct r600_viewports viewports
;
550 bool scissor_enabled
;
552 bool vs_writes_viewport_index
;
553 bool vs_disables_clipping_viewport
;
555 /* Additional context states. */
556 unsigned flags
; /* flush flags */
559 /* Maintain the list of active queries for pausing between IBs. */
560 int num_occlusion_queries
;
561 int num_perfect_occlusion_queries
;
562 struct list_head active_queries
;
563 unsigned num_cs_dw_queries_suspend
;
564 /* Additional hardware info. */
565 unsigned backend_mask
;
566 unsigned max_db
; /* for OQ */
568 unsigned num_draw_calls
;
569 unsigned num_spill_draw_calls
;
570 unsigned num_compute_calls
;
571 unsigned num_spill_compute_calls
;
572 unsigned num_dma_calls
;
573 unsigned num_vs_flushes
;
574 unsigned num_ps_flushes
;
575 unsigned num_cs_flushes
;
576 uint64_t num_alloc_tex_transfer_bytes
;
577 unsigned last_tex_ps_draw_ratio
; /* for query */
579 /* Render condition. */
580 struct r600_atom render_cond_atom
;
581 struct pipe_query
*render_cond
;
582 unsigned render_cond_mode
;
583 bool render_cond_invert
;
584 bool render_cond_force_off
; /* for u_blitter */
586 /* MSAA sample locations.
587 * The first index is the sample index.
588 * The second index is the coordinate: X, Y. */
589 float sample_locations_1x
[1][2];
590 float sample_locations_2x
[2][2];
591 float sample_locations_4x
[4][2];
592 float sample_locations_8x
[8][2];
593 float sample_locations_16x
[16][2];
595 /* Statistics gathering for the DCC enablement heuristic. It can't be
596 * in r600_texture because r600_texture can be shared by multiple
597 * contexts. This is for back buffers only. We shouldn't get too many
600 * X11 DRI3 rotates among a finite set of back buffers. They should
601 * all fit in this array. If they don't, separate DCC might never be
602 * enabled by DCC stat gathering.
605 struct r600_texture
*tex
;
606 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
607 struct pipe_query
*ps_stats
[3];
608 /* If all slots are used and another slot is needed,
609 * the least recently used slot is evicted based on this. */
610 int64_t last_use_timestamp
;
614 struct pipe_debug_callback debug
;
615 struct pipe_device_reset_callback device_reset_callback
;
617 void *query_result_shader
;
619 /* Copy one resource to another using async DMA. */
620 void (*dma_copy
)(struct pipe_context
*ctx
,
621 struct pipe_resource
*dst
,
623 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
624 struct pipe_resource
*src
,
626 const struct pipe_box
*src_box
);
628 void (*clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
629 uint64_t offset
, uint64_t size
, unsigned value
,
630 enum r600_coherency coher
);
632 void (*blit_decompress_depth
)(struct pipe_context
*ctx
,
633 struct r600_texture
*texture
,
634 struct r600_texture
*staging
,
635 unsigned first_level
, unsigned last_level
,
636 unsigned first_layer
, unsigned last_layer
,
637 unsigned first_sample
, unsigned last_sample
);
639 void (*decompress_dcc
)(struct pipe_context
*ctx
,
640 struct r600_texture
*rtex
);
642 /* Reallocate the buffer and update all resource bindings where
643 * the buffer is bound, including all resource descriptors. */
644 void (*invalidate_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
);
646 /* Enable or disable occlusion queries. */
647 void (*set_occlusion_query_state
)(struct pipe_context
*ctx
, bool enable
);
649 void (*save_qbo_state
)(struct pipe_context
*ctx
, struct r600_qbo_state
*st
);
651 /* This ensures there is enough space in the command stream. */
652 void (*need_gfx_cs_space
)(struct pipe_context
*ctx
, unsigned num_dw
,
653 bool include_draw_vbo
);
655 void (*set_atom_dirty
)(struct r600_common_context
*ctx
,
656 struct r600_atom
*atom
, bool dirty
);
658 void (*check_vm_faults
)(struct r600_common_context
*ctx
,
659 struct radeon_saved_cs
*saved
,
660 enum ring_type ring
);
664 bool r600_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
665 struct pb_buffer
*buf
,
666 enum radeon_bo_usage usage
);
667 void *r600_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
668 struct r600_resource
*resource
,
670 void r600_buffer_subdata(struct pipe_context
*ctx
,
671 struct pipe_resource
*buffer
,
672 unsigned usage
, unsigned offset
,
673 unsigned size
, const void *data
);
674 void r600_init_resource_fields(struct r600_common_screen
*rscreen
,
675 struct r600_resource
*res
,
676 uint64_t size
, unsigned alignment
);
677 bool r600_alloc_resource(struct r600_common_screen
*rscreen
,
678 struct r600_resource
*res
);
679 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
680 const struct pipe_resource
*templ
,
682 struct pipe_resource
* r600_aligned_buffer_create(struct pipe_screen
*screen
,
687 struct pipe_resource
*
688 r600_buffer_from_user_memory(struct pipe_screen
*screen
,
689 const struct pipe_resource
*templ
,
692 r600_invalidate_resource(struct pipe_context
*ctx
,
693 struct pipe_resource
*resource
);
695 /* r600_common_pipe.c */
696 void r600_gfx_write_event_eop(struct r600_common_context
*ctx
,
697 unsigned event
, unsigned event_flags
,
699 struct r600_resource
*buf
, uint64_t va
,
700 uint32_t old_fence
, uint32_t new_fence
);
701 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen
*screen
);
702 void r600_gfx_wait_fence(struct r600_common_context
*ctx
,
703 uint64_t va
, uint32_t ref
, uint32_t mask
);
704 void r600_draw_rectangle(struct blitter_context
*blitter
,
705 int x1
, int y1
, int x2
, int y2
, float depth
,
706 enum blitter_attrib_type type
,
707 const union pipe_color_union
*attrib
);
708 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
709 struct radeon_winsys
*ws
);
710 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
);
711 void r600_preflush_suspend_features(struct r600_common_context
*ctx
);
712 void r600_postflush_resume_features(struct r600_common_context
*ctx
);
713 bool r600_common_context_init(struct r600_common_context
*rctx
,
714 struct r600_common_screen
*rscreen
,
715 unsigned context_flags
);
716 void r600_common_context_cleanup(struct r600_common_context
*rctx
);
717 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
719 bool r600_extra_shader_checks(struct r600_common_screen
*rscreen
,
721 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
722 uint64_t offset
, uint64_t size
, unsigned value
,
723 enum r600_coherency coher
);
724 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
725 const struct pipe_resource
*templ
);
726 const char *r600_get_llvm_processor_name(enum radeon_family family
);
727 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
,
728 struct r600_resource
*dst
, struct r600_resource
*src
);
729 void r600_dma_emit_wait_idle(struct r600_common_context
*rctx
);
730 void radeon_save_cs(struct radeon_winsys
*ws
, struct radeon_winsys_cs
*cs
,
731 struct radeon_saved_cs
*saved
);
732 void radeon_clear_saved_cs(struct radeon_saved_cs
*saved
);
733 bool r600_check_device_reset(struct r600_common_context
*rctx
);
735 /* r600_gpu_load.c */
736 void r600_gpu_load_kill_thread(struct r600_common_screen
*rscreen
);
737 uint64_t r600_gpu_load_begin(struct r600_common_screen
*rscreen
);
738 unsigned r600_gpu_load_end(struct r600_common_screen
*rscreen
, uint64_t begin
);
740 /* r600_perfcounters.c */
741 void r600_perfcounters_destroy(struct r600_common_screen
*rscreen
);
744 void r600_init_screen_query_functions(struct r600_common_screen
*rscreen
);
745 void r600_query_init(struct r600_common_context
*rctx
);
746 void r600_suspend_queries(struct r600_common_context
*ctx
);
747 void r600_resume_queries(struct r600_common_context
*ctx
);
748 void r600_query_init_backend_mask(struct r600_common_context
*ctx
);
750 /* r600_streamout.c */
751 void r600_streamout_buffers_dirty(struct r600_common_context
*rctx
);
752 void r600_set_streamout_targets(struct pipe_context
*ctx
,
753 unsigned num_targets
,
754 struct pipe_stream_output_target
**targets
,
755 const unsigned *offset
);
756 void r600_emit_streamout_end(struct r600_common_context
*rctx
);
757 void r600_update_prims_generated_query_state(struct r600_common_context
*rctx
,
758 unsigned type
, int diff
);
759 void r600_streamout_init(struct r600_common_context
*rctx
);
761 /* r600_test_dma.c */
762 void r600_test_dma(struct r600_common_screen
*rscreen
);
765 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
766 struct r600_texture
*rdst
,
767 unsigned dst_level
, unsigned dstx
,
768 unsigned dsty
, unsigned dstz
,
769 struct r600_texture
*rsrc
,
771 const struct pipe_box
*src_box
);
772 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
773 struct r600_texture
*rtex
,
775 struct r600_fmask_info
*out
);
776 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
777 struct r600_texture
*rtex
,
778 struct r600_cmask_info
*out
);
779 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
780 struct pipe_resource
*texture
,
781 struct r600_texture
**staging
);
782 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
);
783 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
784 const struct pipe_resource
*templ
);
785 bool vi_dcc_formats_compatible(enum pipe_format format1
,
786 enum pipe_format format2
);
787 void vi_dcc_disable_if_incompatible_format(struct r600_common_context
*rctx
,
788 struct pipe_resource
*tex
,
790 enum pipe_format view_format
);
791 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
792 struct pipe_resource
*texture
,
793 const struct pipe_surface
*templ
,
794 unsigned width
, unsigned height
);
795 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
796 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
797 struct r600_texture
*tex
);
798 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
799 struct r600_texture
*tex
);
800 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
801 struct r600_texture
*tex
);
802 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
803 struct r600_texture
*rtex
,
804 unsigned level
, unsigned clear_value
);
805 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
806 struct pipe_framebuffer_state
*fb
,
807 struct r600_atom
*fb_state
,
808 unsigned *buffers
, unsigned *dirty_cbufs
,
809 const union pipe_color_union
*color
);
810 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
811 struct r600_texture
*rtex
);
812 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
);
813 void r600_init_context_texture_functions(struct r600_common_context
*rctx
);
815 /* r600_viewport.c */
816 void evergreen_apply_scissor_bug_workaround(struct r600_common_context
*rctx
,
817 struct pipe_scissor_state
*scissor
);
818 void r600_viewport_set_rast_deps(struct r600_common_context
*rctx
,
819 bool scissor_enable
, bool clip_halfz
);
820 void r600_update_vs_writes_viewport_index(struct r600_common_context
*rctx
,
821 struct tgsi_shader_info
*info
);
822 void r600_init_viewport_functions(struct r600_common_context
*rctx
);
825 extern const uint32_t eg_sample_locs_2x
[4];
826 extern const unsigned eg_max_dist_2x
;
827 extern const uint32_t eg_sample_locs_4x
[4];
828 extern const unsigned eg_max_dist_4x
;
829 void cayman_get_sample_position(struct pipe_context
*ctx
, unsigned sample_count
,
830 unsigned sample_index
, float *out_value
);
831 void cayman_init_msaa(struct pipe_context
*ctx
);
832 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
833 void cayman_emit_msaa_config(struct radeon_winsys_cs
*cs
, int nr_samples
,
834 int ps_iter_samples
, int overrast_samples
,
835 unsigned sc_mode_cntl_1
);
838 /* Inline helpers. */
840 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
842 return (struct r600_resource
*)r
;
846 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
848 pipe_resource_reference((struct pipe_resource
**)ptr
,
849 (struct pipe_resource
*)res
);
853 r600_texture_reference(struct r600_texture
**ptr
, struct r600_texture
*res
)
855 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->resource
.b
.b
);
859 r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
861 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
862 struct r600_resource
*res
= (struct r600_resource
*)r
;
865 /* Add memory usage for need_gfx_cs_space */
866 rctx
->vram
+= res
->vram_usage
;
867 rctx
->gtt
+= res
->gart_usage
;
871 static inline bool r600_get_strmout_en(struct r600_common_context
*rctx
)
873 return rctx
->streamout
.streamout_enabled
||
874 rctx
->streamout
.prims_gen_query_enabled
;
877 #define SQ_TEX_XY_FILTER_POINT 0x00
878 #define SQ_TEX_XY_FILTER_BILINEAR 0x01
879 #define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
880 #define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
882 static inline unsigned eg_tex_filter(unsigned filter
, unsigned max_aniso
)
884 if (filter
== PIPE_TEX_FILTER_LINEAR
)
885 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
886 : SQ_TEX_XY_FILTER_BILINEAR
;
888 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
889 : SQ_TEX_XY_FILTER_POINT
;
892 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
905 static inline unsigned r600_wavefront_size(enum radeon_family family
)
925 static inline enum radeon_bo_priority
926 r600_get_sampler_view_priority(struct r600_resource
*res
)
928 if (res
->b
.b
.target
== PIPE_BUFFER
)
929 return RADEON_PRIO_SAMPLER_BUFFER
;
931 if (res
->b
.b
.nr_samples
> 1)
932 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
934 return RADEON_PRIO_SAMPLER_TEXTURE
;
938 r600_can_sample_zs(struct r600_texture
*tex
, bool stencil_sampler
)
940 return (stencil_sampler
&& tex
->can_sample_s
) ||
941 (!stencil_sampler
&& tex
->can_sample_z
);
944 #define COMPUTE_DBG(rscreen, fmt, args...) \
946 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
949 #define R600_ERR(fmt, args...) \
950 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
952 /* For MSAA sample positions. */
953 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
954 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
955 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
956 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
957 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))