src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include "../../winsys/radeon/drm/radeon_winsys.h"
  36
  37 #include "util/u_range.h"
  38 #include "util/u_suballoc.h"
  39 #include "util/u_transfer.h"
  40
  41 /* read caches */
  42 #define R600_CONTEXT_INV_VERTEX_CACHE           (1 << 0)
  43 #define R600_CONTEXT_INV_TEX_CACHE              (1 << 1)
  44 #define R600_CONTEXT_INV_CONST_CACHE            (1 << 2)
  45 /* read-write caches */
  46 #define R600_CONTEXT_STREAMOUT_FLUSH            (1 << 8)
  47 #define R600_CONTEXT_FLUSH_AND_INV              (1 << 9)
  48 #define R600_CONTEXT_FLUSH_AND_INV_CB_META      (1 << 10)
  49 #define R600_CONTEXT_FLUSH_AND_INV_DB_META      (1 << 11)
  50 #define R600_CONTEXT_FLUSH_AND_INV_DB           (1 << 12)
  51 #define R600_CONTEXT_FLUSH_AND_INV_CB           (1 << 13)
  52 /* engine synchronization */
  53 #define R600_CONTEXT_PS_PARTIAL_FLUSH           (1 << 16)
  54 #define R600_CONTEXT_WAIT_3D_IDLE               (1 << 17)
  55 #define R600_CONTEXT_WAIT_CP_DMA_IDLE           (1 << 18)
  56
  57 struct r600_common_context;
  58
  59 struct r600_resource {
  60         struct u_resource               b;
  61
  62         /* Winsys objects. */
  63         struct pb_buffer                *buf;
  64         struct radeon_winsys_cs_handle  *cs_buf;
  65
  66         /* Resource state. */
  67         enum radeon_bo_domain           domains;
  68
  69         /* The buffer range which is initialized (with a write transfer,
  70          * streamout, DMA, or as a random access target). The rest of
  71          * the buffer is considered invalid and can be mapped unsynchronized.
  72          *
  73          * This allows unsychronized mapping of a buffer range which hasn't
  74          * been used yet. It's for applications which forget to use
  75          * the unsynchronized map flag and expect the driver to figure it out.
  76          */
  77         struct util_range               valid_buffer_range;
  78 };
  79
  80 struct r600_common_screen {
  81         struct pipe_screen              b;
  82         struct radeon_winsys            *ws;
  83         enum radeon_family              family;
  84         enum chip_class                 chip_class;
  85         struct radeon_info              info;
  86 };
  87
  88 /* This encapsulates a state or an operation which can emitted into the GPU
  89  * command stream. */
  90 struct r600_atom {
  91         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
  92         unsigned                num_dw;
  93         bool                    dirty;
  94 };
  95
  96 struct r600_so_target {
  97         struct pipe_stream_output_target b;
  98
  99         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 100         struct r600_resource    *buf_filled_size;
 101         unsigned                buf_filled_size_offset;
 102
 103         unsigned                stride_in_dw;
 104 };
 105
 106 struct r600_streamout {
 107         struct r600_atom                begin_atom;
 108         bool                            begin_emitted;
 109         unsigned                        num_dw_for_end;
 110
 111         unsigned                        enabled_mask;
 112         unsigned                        num_targets;
 113         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 114
 115         unsigned                        append_bitmask;
 116         bool                            suspended;
 117
 118         /* External state which comes from the vertex shader,
 119          * it must be set explicitly when binding a shader. */
 120         unsigned                        *stride_in_dw;
 121 };
 122
 123 struct r600_ring {
 124         struct radeon_winsys_cs         *cs;
 125         bool                            flushing;
 126         void (*flush)(void *ctx, unsigned flags);
 127 };
 128
 129 struct r600_rings {
 130         struct r600_ring                gfx;
 131         struct r600_ring                dma;
 132 };
 133
 134 struct r600_common_context {
 135         struct pipe_context b; /* base class */
 136
 137         struct radeon_winsys            *ws;
 138         enum radeon_family              family;
 139         enum chip_class                 chip_class;
 140         struct r600_rings               rings;
 141
 142         struct u_suballocator           *allocator_so_filled_size;
 143
 144         /* Current unaccounted memory usage. */
 145         uint64_t                        vram;
 146         uint64_t                        gtt;
 147
 148         /* States. */
 149         struct r600_streamout           streamout;
 150
 151         /* Additional context states. */
 152         unsigned flags; /* flush flags */
 153 };
 154
 155 /* r600_common_pipe.c */
 156 void r600_common_screen_init(struct r600_common_screen *rscreen,
 157                              struct radeon_winsys *ws);
 158 bool r600_common_context_init(struct r600_common_context *rctx,
 159                               struct r600_common_screen *rscreen);
 160 void r600_common_context_cleanup(struct r600_common_context *rctx);
 161 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 162
 163 /* r600_streamout.c */
 164 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 165 void r600_set_streamout_targets(struct pipe_context *ctx,
 166                                 unsigned num_targets,
 167                                 struct pipe_stream_output_target **targets,
 168                                 unsigned append_bitmask);
 169 void r600_emit_streamout_end(struct r600_common_context *rctx);
 170 void r600_streamout_init(struct r600_common_context *rctx);
 171
 172 /* Inline helpers. */
 173
 174 static INLINE struct r600_resource *r600_resource(struct pipe_resource *r)
 175 {
 176         return (struct r600_resource*)r;
 177 }
 178
 179 #endif