src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define ATI_VENDOR_ID 0x1002
  47
  48 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  49 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  50 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  51 #define R600_RESOURCE_FLAG_DISABLE_DCC          (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
  52
  53 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  54 /* Pipeline & streamout query controls. */
  55 #define R600_CONTEXT_START_PIPELINE_STATS       (1u << 1)
  56 #define R600_CONTEXT_STOP_PIPELINE_STATS        (1u << 2)
  57 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 3)
  58
  59 /* special primitive types */
  60 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  61
  62 /* Debug flags. */
  63 /* logging */
  64 #define DBG_TEX                 (1 << 0)
  65 /* gap - reuse */
  66 #define DBG_COMPUTE             (1 << 2)
  67 #define DBG_VM                  (1 << 3)
  68 /* gap - reuse */
  69 /* shader logging */
  70 #define DBG_FS                  (1 << 5)
  71 #define DBG_VS                  (1 << 6)
  72 #define DBG_GS                  (1 << 7)
  73 #define DBG_PS                  (1 << 8)
  74 #define DBG_CS                  (1 << 9)
  75 #define DBG_TCS                 (1 << 10)
  76 #define DBG_TES                 (1 << 11)
  77 #define DBG_NO_IR               (1 << 12)
  78 #define DBG_NO_TGSI             (1 << 13)
  79 #define DBG_NO_ASM              (1 << 14)
  80 #define DBG_PREOPT_IR           (1 << 15)
  81 #define DBG_CHECK_IR            (1 << 16)
  82 /* gaps */
  83 #define DBG_TEST_DMA            (1 << 20)
  84 /* Bits 21-31 are reserved for the r600g driver. */
  85 /* features */
  86 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  87 #define DBG_NO_HYPERZ           (1llu << 33)
  88 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  89 #define DBG_NO_2D_TILING        (1llu << 35)
  90 #define DBG_NO_TILING           (1llu << 36)
  91 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  92 #define DBG_FORCE_DMA           (1llu << 38)
  93 #define DBG_PRECOMPILE          (1llu << 39)
  94 #define DBG_INFO                (1llu << 40)
  95 #define DBG_NO_WC               (1llu << 41)
  96 #define DBG_CHECK_VM            (1llu << 42)
  97 #define DBG_NO_DCC              (1llu << 43)
  98 #define DBG_NO_DCC_CLEAR        (1llu << 44)
  99 #define DBG_NO_RB_PLUS          (1llu << 45)
 100 #define DBG_SI_SCHED            (1llu << 46)
 101 #define DBG_MONOLITHIC_SHADERS  (1llu << 47)
 102 #define DBG_NO_CE               (1llu << 48)
 103 #define DBG_UNSAFE_MATH         (1llu << 49)
 104 #define DBG_NO_DCC_FB           (1llu << 50)
 105
 106 #define R600_MAP_BUFFER_ALIGNMENT 64
 107 #define R600_MAX_VIEWPORTS        16
 108
 109 enum r600_coherency {
 110         R600_COHERENCY_NONE, /* no cache flushes needed */
 111         R600_COHERENCY_SHADER,
 112         R600_COHERENCY_CB_META,
 113 };
 114
 115 #ifdef PIPE_ARCH_BIG_ENDIAN
 116 #define R600_BIG_ENDIAN 1
 117 #else
 118 #define R600_BIG_ENDIAN 0
 119 #endif
 120
 121 struct r600_common_context;
 122 struct r600_perfcounters;
 123 struct tgsi_shader_info;
 124 struct r600_qbo_state;
 125
 126 struct radeon_shader_reloc {
 127         char name[32];
 128         uint64_t offset;
 129 };
 130
 131 struct radeon_shader_binary {
 132         /** Shader code */
 133         unsigned char *code;
 134         unsigned code_size;
 135
 136         /** Config/Context register state that accompanies this shader.
 137          * This is a stream of dword pairs.  First dword contains the
 138          * register address, the second dword contains the value.*/
 139         unsigned char *config;
 140         unsigned config_size;
 141
 142         /** The number of bytes of config information for each global symbol.
 143          */
 144         unsigned config_size_per_symbol;
 145
 146         /** Constant data accessed by the shader.  This will be uploaded
 147          * into a constant buffer. */
 148         unsigned char *rodata;
 149         unsigned rodata_size;
 150
 151         /** List of symbol offsets for the shader */
 152         uint64_t *global_symbol_offsets;
 153         unsigned global_symbol_count;
 154
 155         struct radeon_shader_reloc *relocs;
 156         unsigned reloc_count;
 157
 158         /** Disassembled shader in a string. */
 159         char *disasm_string;
 160         char *llvm_ir_string;
 161 };
 162
 163 void radeon_shader_binary_init(struct radeon_shader_binary *b);
 164 void radeon_shader_binary_clean(struct radeon_shader_binary *b);
 165
 166 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
 167  * at the moment.
 168  */
 169 struct r600_resource {
 170         struct u_resource               b;
 171
 172         /* Winsys objects. */
 173         struct pb_buffer                *buf;
 174         uint64_t                        gpu_address;
 175         /* Memory usage if the buffer placement is optimal. */
 176         uint64_t                        vram_usage;
 177         uint64_t                        gart_usage;
 178
 179         /* Resource properties. */
 180         uint64_t                        bo_size;
 181         unsigned                        bo_alignment;
 182         enum radeon_bo_domain           domains;
 183         enum radeon_bo_flag             flags;
 184         unsigned                        bind_history;
 185
 186         /* The buffer range which is initialized (with a write transfer,
 187          * streamout, DMA, or as a random access target). The rest of
 188          * the buffer is considered invalid and can be mapped unsynchronized.
 189          *
 190          * This allows unsychronized mapping of a buffer range which hasn't
 191          * been used yet. It's for applications which forget to use
 192          * the unsynchronized map flag and expect the driver to figure it out.
 193          */
 194         struct util_range               valid_buffer_range;
 195
 196         /* For buffers only. This indicates that a write operation has been
 197          * performed by TC L2, but the cache hasn't been flushed.
 198          * Any hw block which doesn't use or bypasses TC L2 should check this
 199          * flag and flush the cache before using the buffer.
 200          *
 201          * For example, TC L2 must be flushed if a buffer which has been
 202          * modified by a shader store instruction is about to be used as
 203          * an index buffer. The reason is that VGT DMA index fetching doesn't
 204          * use TC L2.
 205          */
 206         bool                            TC_L2_dirty;
 207
 208         /* Whether the resource has been exported via resource_get_handle. */
 209         bool                            is_shared;
 210         unsigned                        external_usage; /* PIPE_HANDLE_USAGE_* */
 211 };
 212
 213 struct r600_transfer {
 214         struct pipe_transfer            transfer;
 215         struct r600_resource            *staging;
 216         unsigned                        offset;
 217 };
 218
 219 struct r600_fmask_info {
 220         uint64_t offset;
 221         uint64_t size;
 222         unsigned alignment;
 223         unsigned pitch_in_pixels;
 224         unsigned bank_height;
 225         unsigned slice_tile_max;
 226         unsigned tile_mode_index;
 227 };
 228
 229 struct r600_cmask_info {
 230         uint64_t offset;
 231         uint64_t size;
 232         unsigned alignment;
 233         unsigned pitch;
 234         unsigned height;
 235         unsigned xalign;
 236         unsigned yalign;
 237         unsigned slice_tile_max;
 238         unsigned base_address_reg;
 239 };
 240
 241 struct r600_htile_info {
 242         unsigned pitch;
 243         unsigned height;
 244         unsigned xalign;
 245         unsigned yalign;
 246 };
 247
 248 struct r600_texture {
 249         struct r600_resource            resource;
 250
 251         uint64_t                        size;
 252         unsigned                        num_level0_transfers;
 253         bool                            is_depth;
 254         bool                            db_compatible;
 255         bool                            can_sample_z;
 256         bool                            can_sample_s;
 257         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 258         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 259         struct r600_texture             *flushed_depth_texture;
 260         struct radeon_surf              surface;
 261
 262         /* Colorbuffer compression and fast clear. */
 263         struct r600_fmask_info          fmask;
 264         struct r600_cmask_info          cmask;
 265         struct r600_resource            *cmask_buffer;
 266         uint64_t                        dcc_offset; /* 0 = disabled */
 267         unsigned                        cb_color_info; /* fast clear enable bit */
 268         unsigned                        color_clear_value[2];
 269         unsigned                        last_msaa_resolve_target_micro_mode;
 270
 271         /* Depth buffer compression and fast clear. */
 272         struct r600_htile_info          htile;
 273         struct r600_resource            *htile_buffer;
 274         bool                            depth_cleared; /* if it was cleared at least once */
 275         float                           depth_clear_value;
 276         bool                            stencil_cleared; /* if it was cleared at least once */
 277         uint8_t                         stencil_clear_value;
 278
 279         bool                            non_disp_tiling; /* R600-Cayman only */
 280
 281         /* Whether the texture is a displayable back buffer and needs DCC
 282          * decompression, which is expensive. Therefore, it's enabled only
 283          * if statistics suggest that it will pay off and it's allocated
 284          * separately. It can't be bound as a sampler by apps. Limited to
 285          * target == 2D and last_level == 0. If enabled, dcc_offset contains
 286          * the absolute GPUVM address, not the relative one.
 287          */
 288         struct r600_resource            *dcc_separate_buffer;
 289         /* When DCC is temporarily disabled, the separate buffer is here. */
 290         struct r600_resource            *last_dcc_separate_buffer;
 291         /* We need to track DCC dirtiness, because st/dri usually calls
 292          * flush_resource twice per frame (not a bug) and we don't wanna
 293          * decompress DCC twice. Also, the dirty tracking must be done even
 294          * if DCC isn't used, because it's required by the DCC usage analysis
 295          * for a possible future enablement.
 296          */
 297         bool                            separate_dcc_dirty;
 298         /* Statistics gathering for the DCC enablement heuristic. */
 299         bool                            dcc_gather_statistics;
 300         /* Estimate of how much this color buffer is written to in units of
 301          * full-screen draws: ps_invocations / (width * height)
 302          * Shader kills, late Z, and blending with trivial discards make it
 303          * inaccurate (we need to count CB updates, not PS invocations).
 304          */
 305         unsigned                        ps_draw_ratio;
 306         /* The number of clears since the last DCC usage analysis. */
 307         unsigned                        num_slow_clears;
 308
 309         /* Counter that should be non-zero if the texture is bound to a
 310          * framebuffer. Implemented in radeonsi only.
 311          */
 312         uint32_t                        framebuffers_bound;
 313 };
 314
 315 struct r600_surface {
 316         struct pipe_surface             base;
 317         const struct radeon_surf_level  *level_info;
 318
 319         bool color_initialized;
 320         bool depth_initialized;
 321
 322         /* Misc. color flags. */
 323         bool alphatest_bypass;
 324         bool export_16bpc;
 325         bool color_is_int8;
 326
 327         /* Color registers. */
 328         unsigned cb_color_info;
 329         unsigned cb_color_base;
 330         unsigned cb_color_view;
 331         unsigned cb_color_size;         /* R600 only */
 332         unsigned cb_color_dim;          /* EG only */
 333         unsigned cb_color_pitch;        /* EG and later */
 334         unsigned cb_color_slice;        /* EG and later */
 335         unsigned cb_color_attrib;       /* EG and later */
 336         unsigned cb_dcc_control;        /* VI and later */
 337         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 338         unsigned cb_color_fmask_slice;  /* EG and later */
 339         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 340         unsigned cb_color_mask;         /* R600 only */
 341         unsigned spi_shader_col_format;         /* SI+, no blending, no alpha-to-coverage. */
 342         unsigned spi_shader_col_format_alpha;   /* SI+, alpha-to-coverage */
 343         unsigned spi_shader_col_format_blend;   /* SI+, blending without alpha. */
 344         unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
 345         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 346         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 347
 348         /* DB registers. */
 349         unsigned db_depth_info;         /* R600 only, then SI and later */
 350         unsigned db_z_info;             /* EG and later */
 351         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 352         unsigned db_depth_view;
 353         unsigned db_depth_size;
 354         unsigned db_depth_slice;        /* EG and later */
 355         unsigned db_stencil_base;       /* EG and later */
 356         unsigned db_stencil_info;       /* EG and later */
 357         unsigned db_prefetch_limit;     /* R600 only */
 358         unsigned db_htile_surface;
 359         unsigned db_htile_data_base;
 360         unsigned db_preload_control;    /* EG and later */
 361 };
 362
 363 struct r600_common_screen {
 364         struct pipe_screen              b;
 365         struct radeon_winsys            *ws;
 366         enum radeon_family              family;
 367         enum chip_class                 chip_class;
 368         struct radeon_info              info;
 369         uint64_t                        debug_flags;
 370         bool                            has_cp_dma;
 371         bool                            has_streamout;
 372
 373         struct slab_parent_pool         pool_transfers;
 374
 375         /* Texture filter settings. */
 376         int                             force_aniso; /* -1 = disabled */
 377
 378         /* Auxiliary context. Mainly used to initialize resources.
 379          * It must be locked prior to using and flushed before unlocking. */
 380         struct pipe_context             *aux_context;
 381         pipe_mutex                      aux_context_lock;
 382
 383         /* This must be in the screen, because UE4 uses one context for
 384          * compilation and another one for rendering.
 385          */
 386         unsigned                        num_compilations;
 387         /* Along with ST_DEBUG=precompile, this should show if applications
 388          * are loading shaders on demand. This is a monotonic counter.
 389          */
 390         unsigned                        num_shaders_created;
 391
 392         /* GPU load thread. */
 393         pipe_mutex                      gpu_load_mutex;
 394         pipe_thread                     gpu_load_thread;
 395         unsigned                        gpu_load_counter_busy;
 396         unsigned                        gpu_load_counter_idle;
 397         volatile unsigned               gpu_load_stop_thread; /* bool */
 398
 399         char                            renderer_string[100];
 400
 401         /* Performance counters. */
 402         struct r600_perfcounters        *perfcounters;
 403
 404         /* If pipe_screen wants to re-emit the framebuffer state of all
 405          * contexts, it should atomically increment this. Each context will
 406          * compare this with its own last known value of the counter before
 407          * drawing and re-emit the framebuffer state accordingly.
 408          */
 409         unsigned                        dirty_fb_counter;
 410
 411         /* Atomically increment this counter when an existing texture's
 412          * metadata is enabled or disabled in a way that requires changing
 413          * contexts' compressed texture binding masks.
 414          */
 415         unsigned                        compressed_colortex_counter;
 416
 417         /* Atomically increment this counter when an existing texture's
 418          * backing buffer or tile mode parameters have changed that requires
 419          * recomputation of shader descriptors.
 420          */
 421         unsigned                        dirty_tex_descriptor_counter;
 422
 423         struct {
 424                 /* Context flags to set so that all writes from earlier jobs
 425                  * in the CP are seen by L2 clients.
 426                  */
 427                 unsigned cp_to_L2;
 428
 429                 /* Context flags to set so that all writes from earlier
 430                  * compute jobs are seen by L2 clients.
 431                  */
 432                 unsigned compute_to_L2;
 433         } barrier_flags;
 434
 435         void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
 436                                       struct r600_texture *rtex,
 437                                       struct radeon_bo_metadata *md);
 438
 439         void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
 440                                     struct r600_texture *rtex,
 441                                     struct radeon_bo_metadata *md);
 442 };
 443
 444 /* This encapsulates a state or an operation which can emitted into the GPU
 445  * command stream. */
 446 struct r600_atom {
 447         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 448         unsigned                num_dw;
 449         unsigned short          id;
 450 };
 451
 452 struct r600_so_target {
 453         struct pipe_stream_output_target b;
 454
 455         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 456         struct r600_resource    *buf_filled_size;
 457         unsigned                buf_filled_size_offset;
 458         bool                    buf_filled_size_valid;
 459
 460         unsigned                stride_in_dw;
 461 };
 462
 463 struct r600_streamout {
 464         struct r600_atom                begin_atom;
 465         bool                            begin_emitted;
 466         unsigned                        num_dw_for_end;
 467
 468         unsigned                        enabled_mask;
 469         unsigned                        num_targets;
 470         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 471
 472         unsigned                        append_bitmask;
 473         bool                            suspended;
 474
 475         /* External state which comes from the vertex shader,
 476          * it must be set explicitly when binding a shader. */
 477         unsigned                        *stride_in_dw;
 478         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 479
 480         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 481         unsigned                        hw_enabled_mask;
 482
 483         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 484         struct r600_atom                enable_atom;
 485         bool                            streamout_enabled;
 486         bool                            prims_gen_query_enabled;
 487         int                             num_prims_gen_queries;
 488 };
 489
 490 struct r600_signed_scissor {
 491         int minx;
 492         int miny;
 493         int maxx;
 494         int maxy;
 495 };
 496
 497 struct r600_scissors {
 498         struct r600_atom                atom;
 499         unsigned                        dirty_mask;
 500         struct pipe_scissor_state       states[R600_MAX_VIEWPORTS];
 501 };
 502
 503 struct r600_viewports {
 504         struct r600_atom                atom;
 505         unsigned                        dirty_mask;
 506         unsigned                        depth_range_dirty_mask;
 507         struct pipe_viewport_state      states[R600_MAX_VIEWPORTS];
 508         struct r600_signed_scissor      as_scissor[R600_MAX_VIEWPORTS];
 509 };
 510
 511 struct r600_ring {
 512         struct radeon_winsys_cs         *cs;
 513         void (*flush)(void *ctx, unsigned flags,
 514                       struct pipe_fence_handle **fence);
 515 };
 516
 517 /* Saved CS data for debugging features. */
 518 struct radeon_saved_cs {
 519         uint32_t                        *ib;
 520         unsigned                        num_dw;
 521
 522         struct radeon_bo_list_item      *bo_list;
 523         unsigned                        bo_count;
 524 };
 525
 526 struct r600_common_context {
 527         struct pipe_context b; /* base class */
 528
 529         struct r600_common_screen       *screen;
 530         struct radeon_winsys            *ws;
 531         struct radeon_winsys_ctx        *ctx;
 532         enum radeon_family              family;
 533         enum chip_class                 chip_class;
 534         struct r600_ring                gfx;
 535         struct r600_ring                dma;
 536         struct pipe_fence_handle        *last_gfx_fence;
 537         struct pipe_fence_handle        *last_sdma_fence;
 538         unsigned                        num_gfx_cs_flushes;
 539         unsigned                        initial_gfx_cs_size;
 540         unsigned                        gpu_reset_counter;
 541         unsigned                        last_dirty_fb_counter;
 542         unsigned                        last_compressed_colortex_counter;
 543         unsigned                        last_dirty_tex_descriptor_counter;
 544
 545         struct u_upload_mgr             *uploader;
 546         struct u_suballocator           *allocator_zeroed_memory;
 547         struct slab_child_pool          pool_transfers;
 548
 549         /* Current unaccounted memory usage. */
 550         uint64_t                        vram;
 551         uint64_t                        gtt;
 552
 553         /* States. */
 554         struct r600_streamout           streamout;
 555         struct r600_scissors            scissors;
 556         struct r600_viewports           viewports;
 557         bool                            scissor_enabled;
 558         bool                            clip_halfz;
 559         bool                            vs_writes_viewport_index;
 560         bool                            vs_disables_clipping_viewport;
 561
 562         /* Additional context states. */
 563         unsigned flags; /* flush flags */
 564
 565         /* Queries. */
 566         /* Maintain the list of active queries for pausing between IBs. */
 567         int                             num_occlusion_queries;
 568         int                             num_perfect_occlusion_queries;
 569         struct list_head                active_queries;
 570         unsigned                        num_cs_dw_queries_suspend;
 571         /* Additional hardware info. */
 572         unsigned                        backend_mask;
 573         unsigned                        max_db; /* for OQ */
 574         /* Misc stats. */
 575         unsigned                        num_draw_calls;
 576         unsigned                        num_spill_draw_calls;
 577         unsigned                        num_compute_calls;
 578         unsigned                        num_spill_compute_calls;
 579         unsigned                        num_dma_calls;
 580         unsigned                        num_vs_flushes;
 581         unsigned                        num_ps_flushes;
 582         unsigned                        num_cs_flushes;
 583         uint64_t                        num_alloc_tex_transfer_bytes;
 584         unsigned                        last_tex_ps_draw_ratio; /* for query */
 585
 586         /* Render condition. */
 587         struct r600_atom                render_cond_atom;
 588         struct pipe_query               *render_cond;
 589         unsigned                        render_cond_mode;
 590         bool                            render_cond_invert;
 591         bool                            render_cond_force_off; /* for u_blitter */
 592
 593         /* MSAA sample locations.
 594          * The first index is the sample index.
 595          * The second index is the coordinate: X, Y. */
 596         float                           sample_locations_1x[1][2];
 597         float                           sample_locations_2x[2][2];
 598         float                           sample_locations_4x[4][2];
 599         float                           sample_locations_8x[8][2];
 600         float                           sample_locations_16x[16][2];
 601
 602         /* Statistics gathering for the DCC enablement heuristic. It can't be
 603          * in r600_texture because r600_texture can be shared by multiple
 604          * contexts. This is for back buffers only. We shouldn't get too many
 605          * of those.
 606          *
 607          * X11 DRI3 rotates among a finite set of back buffers. They should
 608          * all fit in this array. If they don't, separate DCC might never be
 609          * enabled by DCC stat gathering.
 610          */
 611         struct {
 612                 struct r600_texture             *tex;
 613                 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
 614                 struct pipe_query               *ps_stats[3];
 615                 /* If all slots are used and another slot is needed,
 616                  * the least recently used slot is evicted based on this. */
 617                 int64_t                         last_use_timestamp;
 618                 bool                            query_active;
 619         } dcc_stats[5];
 620
 621         struct pipe_debug_callback      debug;
 622
 623         void                            *query_result_shader;
 624
 625         /* Copy one resource to another using async DMA. */
 626         void (*dma_copy)(struct pipe_context *ctx,
 627                          struct pipe_resource *dst,
 628                          unsigned dst_level,
 629                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 630                          struct pipe_resource *src,
 631                          unsigned src_level,
 632                          const struct pipe_box *src_box);
 633
 634         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 635                              uint64_t offset, uint64_t size, unsigned value,
 636                              enum r600_coherency coher);
 637
 638         void (*blit_decompress_depth)(struct pipe_context *ctx,
 639                                       struct r600_texture *texture,
 640                                       struct r600_texture *staging,
 641                                       unsigned first_level, unsigned last_level,
 642                                       unsigned first_layer, unsigned last_layer,
 643                                       unsigned first_sample, unsigned last_sample);
 644
 645         void (*decompress_dcc)(struct pipe_context *ctx,
 646                                struct r600_texture *rtex);
 647
 648         /* Reallocate the buffer and update all resource bindings where
 649          * the buffer is bound, including all resource descriptors. */
 650         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 651
 652         /* Enable or disable occlusion queries. */
 653         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 654
 655         void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state *st);
 656
 657         /* This ensures there is enough space in the command stream. */
 658         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 659                                   bool include_draw_vbo);
 660
 661         void (*set_atom_dirty)(struct r600_common_context *ctx,
 662                                struct r600_atom *atom, bool dirty);
 663
 664         void (*check_vm_faults)(struct r600_common_context *ctx,
 665                                 struct radeon_saved_cs *saved,
 666                                 enum ring_type ring);
 667 };
 668
 669 /* r600_buffer.c */
 670 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 671                                      struct pb_buffer *buf,
 672                                      enum radeon_bo_usage usage);
 673 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 674                                       struct r600_resource *resource,
 675                                       unsigned usage);
 676 void r600_buffer_subdata(struct pipe_context *ctx,
 677                          struct pipe_resource *buffer,
 678                          unsigned usage, unsigned offset,
 679                          unsigned size, const void *data);
 680 void r600_init_resource_fields(struct r600_common_screen *rscreen,
 681                                struct r600_resource *res,
 682                                uint64_t size, unsigned alignment);
 683 bool r600_alloc_resource(struct r600_common_screen *rscreen,
 684                          struct r600_resource *res);
 685 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 686                                          const struct pipe_resource *templ,
 687                                          unsigned alignment);
 688 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
 689                                                   unsigned bind,
 690                                                   unsigned usage,
 691                                                   unsigned size,
 692                                                   unsigned alignment);
 693 struct pipe_resource *
 694 r600_buffer_from_user_memory(struct pipe_screen *screen,
 695                              const struct pipe_resource *templ,
 696                              void *user_memory);
 697 void
 698 r600_invalidate_resource(struct pipe_context *ctx,
 699                          struct pipe_resource *resource);
 700
 701 /* r600_common_pipe.c */
 702 void r600_gfx_write_fence(struct r600_common_context *ctx, struct r600_resource *buf,
 703                           uint64_t va, uint32_t old_value, uint32_t new_value);
 704 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen);
 705 void r600_gfx_wait_fence(struct r600_common_context *ctx,
 706                          uint64_t va, uint32_t ref, uint32_t mask);
 707 void r600_draw_rectangle(struct blitter_context *blitter,
 708                          int x1, int y1, int x2, int y2, float depth,
 709                          enum blitter_attrib_type type,
 710                          const union pipe_color_union *attrib);
 711 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 712                              struct radeon_winsys *ws);
 713 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 714 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 715 void r600_postflush_resume_features(struct r600_common_context *ctx);
 716 bool r600_common_context_init(struct r600_common_context *rctx,
 717                               struct r600_common_screen *rscreen,
 718                               unsigned context_flags);
 719 void r600_common_context_cleanup(struct r600_common_context *rctx);
 720 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 721                           unsigned processor);
 722 bool r600_extra_shader_checks(struct r600_common_screen *rscreen,
 723                               unsigned processor);
 724 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 725                               uint64_t offset, uint64_t size, unsigned value,
 726                               enum r600_coherency coher);
 727 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 728                                                   const struct pipe_resource *templ);
 729 const char *r600_get_llvm_processor_name(enum radeon_family family);
 730 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
 731                          struct r600_resource *dst, struct r600_resource *src);
 732 void r600_dma_emit_wait_idle(struct r600_common_context *rctx);
 733 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
 734                     struct radeon_saved_cs *saved);
 735 void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
 736
 737 /* r600_gpu_load.c */
 738 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 739 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 740 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 741
 742 /* r600_perfcounters.c */
 743 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
 744
 745 /* r600_query.c */
 746 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
 747 void r600_query_init(struct r600_common_context *rctx);
 748 void r600_suspend_queries(struct r600_common_context *ctx);
 749 void r600_resume_queries(struct r600_common_context *ctx);
 750 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 751
 752 /* r600_streamout.c */
 753 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 754 void r600_set_streamout_targets(struct pipe_context *ctx,
 755                                 unsigned num_targets,
 756                                 struct pipe_stream_output_target **targets,
 757                                 const unsigned *offset);
 758 void r600_emit_streamout_end(struct r600_common_context *rctx);
 759 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 760                                              unsigned type, int diff);
 761 void r600_streamout_init(struct r600_common_context *rctx);
 762
 763 /* r600_test_dma.c */
 764 void r600_test_dma(struct r600_common_screen *rscreen);
 765
 766 /* r600_texture.c */
 767 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
 768                                 struct r600_texture *rdst,
 769                                 unsigned dst_level, unsigned dstx,
 770                                 unsigned dsty, unsigned dstz,
 771                                 struct r600_texture *rsrc,
 772                                 unsigned src_level,
 773                                 const struct pipe_box *src_box);
 774 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 775                                  struct r600_texture *rtex,
 776                                  unsigned nr_samples,
 777                                  struct r600_fmask_info *out);
 778 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 779                                  struct r600_texture *rtex,
 780                                  struct r600_cmask_info *out);
 781 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 782                                      struct pipe_resource *texture,
 783                                      struct r600_texture **staging);
 784 void r600_print_texture_info(struct r600_texture *rtex, FILE *f);
 785 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 786                                         const struct pipe_resource *templ);
 787 bool vi_dcc_formats_compatible(enum pipe_format format1,
 788                                enum pipe_format format2);
 789 void vi_dcc_disable_if_incompatible_format(struct r600_common_context *rctx,
 790                                            struct pipe_resource *tex,
 791                                            unsigned level,
 792                                            enum pipe_format view_format);
 793 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 794                                                 struct pipe_resource *texture,
 795                                                 const struct pipe_surface *templ,
 796                                                 unsigned width, unsigned height);
 797 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
 798 void vi_separate_dcc_start_query(struct pipe_context *ctx,
 799                                  struct r600_texture *tex);
 800 void vi_separate_dcc_stop_query(struct pipe_context *ctx,
 801                                 struct r600_texture *tex);
 802 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
 803                                              struct r600_texture *tex);
 804 void vi_dcc_clear_level(struct r600_common_context *rctx,
 805                         struct r600_texture *rtex,
 806                         unsigned level, unsigned clear_value);
 807 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 808                                    struct pipe_framebuffer_state *fb,
 809                                    struct r600_atom *fb_state,
 810                                    unsigned *buffers, unsigned *dirty_cbufs,
 811                                    const union pipe_color_union *color);
 812 bool r600_texture_disable_dcc(struct r600_common_context *rctx,
 813                               struct r600_texture *rtex);
 814 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 815 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 816
 817 /* r600_viewport.c */
 818 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
 819                                             struct pipe_scissor_state *scissor);
 820 void r600_viewport_set_rast_deps(struct r600_common_context *rctx,
 821                                  bool scissor_enable, bool clip_halfz);
 822 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
 823                                           struct tgsi_shader_info *info);
 824 void r600_init_viewport_functions(struct r600_common_context *rctx);
 825
 826 /* cayman_msaa.c */
 827 extern const uint32_t eg_sample_locs_2x[4];
 828 extern const unsigned eg_max_dist_2x;
 829 extern const uint32_t eg_sample_locs_4x[4];
 830 extern const unsigned eg_max_dist_4x;
 831 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 832                                 unsigned sample_index, float *out_value);
 833 void cayman_init_msaa(struct pipe_context *ctx);
 834 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 835 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 836                              int ps_iter_samples, int overrast_samples,
 837                              unsigned sc_mode_cntl_1);
 838
 839
 840 /* Inline helpers. */
 841
 842 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 843 {
 844         return (struct r600_resource*)r;
 845 }
 846
 847 static inline void
 848 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 849 {
 850         pipe_resource_reference((struct pipe_resource **)ptr,
 851                                 (struct pipe_resource *)res);
 852 }
 853
 854 static inline void
 855 r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
 856 {
 857         pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
 858 }
 859
 860 static inline void
 861 r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 862 {
 863         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 864         struct r600_resource *res = (struct r600_resource *)r;
 865
 866         if (res) {
 867                 /* Add memory usage for need_gfx_cs_space */
 868                 rctx->vram += res->vram_usage;
 869                 rctx->gtt += res->gart_usage;
 870         }
 871 }
 872
 873 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
 874 {
 875         return rctx->streamout.streamout_enabled ||
 876                rctx->streamout.prims_gen_query_enabled;
 877 }
 878
 879 #define     SQ_TEX_XY_FILTER_POINT                         0x00
 880 #define     SQ_TEX_XY_FILTER_BILINEAR                      0x01
 881 #define     SQ_TEX_XY_FILTER_ANISO_POINT                   0x02
 882 #define     SQ_TEX_XY_FILTER_ANISO_BILINEAR                0x03
 883
 884 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
 885 {
 886         if (filter == PIPE_TEX_FILTER_LINEAR)
 887                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
 888                                      : SQ_TEX_XY_FILTER_BILINEAR;
 889         else
 890                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
 891                                      : SQ_TEX_XY_FILTER_POINT;
 892 }
 893
 894 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 895 {
 896         if (filter < 2)
 897                 return 0;
 898         if (filter < 4)
 899                 return 1;
 900         if (filter < 8)
 901                 return 2;
 902         if (filter < 16)
 903                 return 3;
 904         return 4;
 905 }
 906
 907 static inline unsigned r600_wavefront_size(enum radeon_family family)
 908 {
 909         switch (family) {
 910         case CHIP_RV610:
 911         case CHIP_RS780:
 912         case CHIP_RV620:
 913         case CHIP_RS880:
 914                 return 16;
 915         case CHIP_RV630:
 916         case CHIP_RV635:
 917         case CHIP_RV730:
 918         case CHIP_RV710:
 919         case CHIP_PALM:
 920         case CHIP_CEDAR:
 921                 return 32;
 922         default:
 923                 return 64;
 924         }
 925 }
 926
 927 static inline enum radeon_bo_priority
 928 r600_get_sampler_view_priority(struct r600_resource *res)
 929 {
 930         if (res->b.b.target == PIPE_BUFFER)
 931                 return RADEON_PRIO_SAMPLER_BUFFER;
 932
 933         if (res->b.b.nr_samples > 1)
 934                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 935
 936         return RADEON_PRIO_SAMPLER_TEXTURE;
 937 }
 938
 939 static inline bool
 940 r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
 941 {
 942         return (stencil_sampler && tex->can_sample_s) ||
 943                (!stencil_sampler && tex->can_sample_z);
 944 }
 945
 946 #define COMPUTE_DBG(rscreen, fmt, args...) \
 947         do { \
 948                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 949         } while (0);
 950
 951 #define R600_ERR(fmt, args...) \
 952         fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 953
 954 /* For MSAA sample positions. */
 955 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 956         (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) |                  \
 957         (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) |         \
 958         (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) |        \
 959          (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
 960
 961 #endif