src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include "../../winsys/radeon/drm/radeon_winsys.h"
  36
  37 #include "util/u_range.h"
  38 #include "util/u_suballoc.h"
  39 #include "util/u_transfer.h"
  40
  41 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  42 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  43 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  44
  45 /* read caches */
  46 #define R600_CONTEXT_INV_VERTEX_CACHE           (1 << 0)
  47 #define R600_CONTEXT_INV_TEX_CACHE              (1 << 1)
  48 #define R600_CONTEXT_INV_CONST_CACHE            (1 << 2)
  49 #define R600_CONTEXT_INV_SHADER_CACHE           (1 << 3)
  50 /* read-write caches */
  51 #define R600_CONTEXT_STREAMOUT_FLUSH            (1 << 8)
  52 #define R600_CONTEXT_FLUSH_AND_INV              (1 << 9)
  53 #define R600_CONTEXT_FLUSH_AND_INV_CB_META      (1 << 10)
  54 #define R600_CONTEXT_FLUSH_AND_INV_DB_META      (1 << 11)
  55 #define R600_CONTEXT_FLUSH_AND_INV_DB           (1 << 12)
  56 #define R600_CONTEXT_FLUSH_AND_INV_CB           (1 << 13)
  57 /* engine synchronization */
  58 #define R600_CONTEXT_PS_PARTIAL_FLUSH           (1 << 16)
  59 #define R600_CONTEXT_WAIT_3D_IDLE               (1 << 17)
  60 #define R600_CONTEXT_WAIT_CP_DMA_IDLE           (1 << 18)
  61
  62 /* Debug flags. */
  63 /* logging */
  64 #define DBG_TEX_DEPTH           (1 << 0)
  65 #define DBG_COMPUTE             (1 << 1)
  66 #define DBG_VM                  (1 << 2)
  67 #define DBG_TRACE_CS            (1 << 3)
  68 /* shaders */
  69 #define DBG_FS                  (1 << 8)
  70 #define DBG_VS                  (1 << 9)
  71 #define DBG_GS                  (1 << 10)
  72 #define DBG_PS                  (1 << 11)
  73 #define DBG_CS                  (1 << 12)
  74 /* The maximum allowed bit is 15. */
  75
  76 struct r600_common_context;
  77
  78 struct r600_resource {
  79         struct u_resource               b;
  80
  81         /* Winsys objects. */
  82         struct pb_buffer                *buf;
  83         struct radeon_winsys_cs_handle  *cs_buf;
  84
  85         /* Resource state. */
  86         enum radeon_bo_domain           domains;
  87
  88         /* The buffer range which is initialized (with a write transfer,
  89          * streamout, DMA, or as a random access target). The rest of
  90          * the buffer is considered invalid and can be mapped unsynchronized.
  91          *
  92          * This allows unsychronized mapping of a buffer range which hasn't
  93          * been used yet. It's for applications which forget to use
  94          * the unsynchronized map flag and expect the driver to figure it out.
  95          */
  96         struct util_range               valid_buffer_range;
  97 };
  98
  99 struct r600_transfer {
 100         struct pipe_transfer            transfer;
 101         struct r600_resource            *staging;
 102         unsigned                        offset;
 103 };
 104
 105 struct r600_fmask_info {
 106         unsigned offset;
 107         unsigned size;
 108         unsigned alignment;
 109         unsigned pitch;
 110         unsigned bank_height;
 111         unsigned slice_tile_max;
 112         unsigned tile_mode_index;
 113 };
 114
 115 struct r600_cmask_info {
 116         unsigned offset;
 117         unsigned size;
 118         unsigned alignment;
 119         unsigned slice_tile_max;
 120 };
 121
 122 struct r600_texture {
 123         struct r600_resource            resource;
 124
 125         unsigned                        size;
 126         unsigned                        pitch_override;
 127         bool                            is_depth;
 128         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 129         struct r600_texture             *flushed_depth_texture;
 130         boolean                         is_flushing_texture;
 131         struct radeon_surface           surface;
 132
 133         /* Colorbuffer compression and fast clear. */
 134         struct r600_fmask_info          fmask;
 135         struct r600_cmask_info          cmask;
 136
 137         struct r600_resource            *htile;
 138         float                           depth_clear; /* use htile only for first level */
 139
 140         struct r600_resource            *cmask_buffer;
 141         unsigned                        color_clear_value[2];
 142
 143         bool                            non_disp_tiling; /* R600-Cayman only */
 144         unsigned                        mipmap_shift;
 145 };
 146
 147 struct r600_tiling_info {
 148         unsigned num_channels;
 149         unsigned num_banks;
 150         unsigned group_bytes;
 151 };
 152
 153 struct r600_common_screen {
 154         struct pipe_screen              b;
 155         struct radeon_winsys            *ws;
 156         enum radeon_family              family;
 157         enum chip_class                 chip_class;
 158         struct radeon_info              info;
 159         struct r600_tiling_info         tiling_info;
 160         unsigned                        debug_flags;
 161
 162         /* Auxiliary context. Mainly used to initialize resources.
 163          * It must be locked prior to using and flushed before unlocking. */
 164         struct pipe_context             *aux_context;
 165         pipe_mutex                      aux_context_lock;
 166 };
 167
 168 /* This encapsulates a state or an operation which can emitted into the GPU
 169  * command stream. */
 170 struct r600_atom {
 171         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 172         unsigned                num_dw;
 173         bool                    dirty;
 174 };
 175
 176 struct r600_so_target {
 177         struct pipe_stream_output_target b;
 178
 179         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 180         struct r600_resource    *buf_filled_size;
 181         unsigned                buf_filled_size_offset;
 182
 183         unsigned                stride_in_dw;
 184 };
 185
 186 struct r600_streamout {
 187         struct r600_atom                begin_atom;
 188         bool                            begin_emitted;
 189         unsigned                        num_dw_for_end;
 190
 191         unsigned                        enabled_mask;
 192         unsigned                        num_targets;
 193         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 194
 195         unsigned                        append_bitmask;
 196         bool                            suspended;
 197
 198         /* External state which comes from the vertex shader,
 199          * it must be set explicitly when binding a shader. */
 200         unsigned                        *stride_in_dw;
 201 };
 202
 203 struct r600_ring {
 204         struct radeon_winsys_cs         *cs;
 205         bool                            flushing;
 206         void (*flush)(void *ctx, unsigned flags);
 207 };
 208
 209 struct r600_rings {
 210         struct r600_ring                gfx;
 211         struct r600_ring                dma;
 212 };
 213
 214 struct r600_common_context {
 215         struct pipe_context b; /* base class */
 216
 217         struct radeon_winsys            *ws;
 218         enum radeon_family              family;
 219         enum chip_class                 chip_class;
 220         struct r600_rings               rings;
 221
 222         struct u_suballocator           *allocator_so_filled_size;
 223
 224         /* Current unaccounted memory usage. */
 225         uint64_t                        vram;
 226         uint64_t                        gtt;
 227
 228         /* States. */
 229         struct r600_streamout           streamout;
 230
 231         /* Additional context states. */
 232         unsigned flags; /* flush flags */
 233
 234         /* Copy one resource to another using async DMA.
 235          * False is returned if the copy couldn't be done. */
 236         boolean (*dma_copy)(struct pipe_context *ctx,
 237                             struct pipe_resource *dst,
 238                             unsigned dst_level,
 239                             unsigned dst_x, unsigned dst_y, unsigned dst_z,
 240                             struct pipe_resource *src,
 241                             unsigned src_level,
 242                             const struct pipe_box *src_box);
 243
 244         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 245                              unsigned offset, unsigned size, unsigned value);
 246 };
 247
 248 /* r600_common_pipe.c */
 249 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 250                              struct radeon_winsys *ws);
 251 void r600_common_screen_cleanup(struct r600_common_screen *rscreen);
 252 bool r600_common_context_init(struct r600_common_context *rctx,
 253                               struct r600_common_screen *rscreen);
 254 void r600_common_context_cleanup(struct r600_common_context *rctx);
 255 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 256 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 257                           const struct tgsi_token *tokens);
 258 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 259                               unsigned offset, unsigned size, unsigned value);
 260 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 261                                         struct radeon_winsys_cs_handle *buf,
 262                                         enum radeon_bo_usage usage);
 263 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 264                                       struct r600_resource *resource,
 265                                       unsigned usage);
 266
 267 /* r600_streamout.c */
 268 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 269 void r600_set_streamout_targets(struct pipe_context *ctx,
 270                                 unsigned num_targets,
 271                                 struct pipe_stream_output_target **targets,
 272                                 unsigned append_bitmask);
 273 void r600_emit_streamout_end(struct r600_common_context *rctx);
 274 void r600_streamout_init(struct r600_common_context *rctx);
 275
 276 /* Inline helpers. */
 277
 278 static INLINE struct r600_resource *r600_resource(struct pipe_resource *r)
 279 {
 280         return (struct r600_resource*)r;
 281 }
 282
 283 static INLINE void
 284 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 285 {
 286         pipe_resource_reference((struct pipe_resource **)ptr,
 287                                 (struct pipe_resource *)res);
 288 }
 289
 290 #endif