src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "amd/common/ac_binary.h"
  38
  39 #include "radeon/radeon_winsys.h"
  40
  41 #include "util/disk_cache.h"
  42 #include "util/u_blitter.h"
  43 #include "util/list.h"
  44 #include "util/u_range.h"
  45 #include "util/slab.h"
  46 #include "util/u_suballoc.h"
  47 #include "util/u_transfer.h"
  48 #include "util/u_threaded_context.h"
  49
  50 struct u_log_context;
  51
  52 #define ATI_VENDOR_ID 0x1002
  53
  54 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  55 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  56 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  57 #define R600_RESOURCE_FLAG_DISABLE_DCC          (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
  58 #define R600_RESOURCE_FLAG_UNMAPPABLE           (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
  59
  60 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  61 /* Pipeline & streamout query controls. */
  62 #define R600_CONTEXT_START_PIPELINE_STATS       (1u << 1)
  63 #define R600_CONTEXT_STOP_PIPELINE_STATS        (1u << 2)
  64 #define R600_CONTEXT_FLUSH_FOR_RENDER_COND      (1u << 3)
  65 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 4)
  66
  67 /* special primitive types */
  68 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  69
  70 #define R600_NOT_QUERY          0xffffffff
  71
  72 /* Debug flags. */
  73 enum {
  74         /* Shader logging options: */
  75         DBG_VS = PIPE_SHADER_VERTEX,
  76         DBG_PS = PIPE_SHADER_FRAGMENT,
  77         DBG_GS = PIPE_SHADER_GEOMETRY,
  78         DBG_TCS = PIPE_SHADER_TESS_CTRL,
  79         DBG_TES = PIPE_SHADER_TESS_EVAL,
  80         DBG_CS = PIPE_SHADER_COMPUTE,
  81         DBG_NO_IR,
  82         DBG_NO_TGSI,
  83         DBG_NO_ASM,
  84         DBG_PREOPT_IR,
  85
  86         /* Shader compiler options the shader cache should be aware of: */
  87         DBG_FS_CORRECT_DERIVS_AFTER_KILL,
  88         DBG_UNSAFE_MATH,
  89         DBG_SI_SCHED,
  90
  91         /* Shader compiler options (with no effect on the shader cache): */
  92         DBG_CHECK_IR,
  93         DBG_PRECOMPILE,
  94         DBG_NIR,
  95         DBG_MONOLITHIC_SHADERS,
  96         DBG_NO_OPT_VARIANT,
  97
  98         /* Information logging options: */
  99         DBG_INFO,
 100         DBG_TEX,
 101         DBG_COMPUTE,
 102         DBG_VM,
 103
 104         /* Driver options: */
 105         DBG_FORCE_DMA,
 106         DBG_NO_ASYNC_DMA,
 107         DBG_NO_DISCARD_RANGE,
 108         DBG_NO_WC,
 109         DBG_CHECK_VM,
 110         DBG_RESERVE_VMID,
 111
 112         /* 3D engine options: */
 113         DBG_SWITCH_ON_EOP,
 114         DBG_NO_OUT_OF_ORDER,
 115         DBG_NO_DPBB,
 116         DBG_NO_DFSM,
 117         DBG_DPBB,
 118         DBG_DFSM,
 119         DBG_NO_HYPERZ,
 120         DBG_NO_RB_PLUS,
 121         DBG_NO_2D_TILING,
 122         DBG_NO_TILING,
 123         DBG_NO_DCC,
 124         DBG_NO_DCC_CLEAR,
 125         DBG_NO_DCC_FB,
 126
 127         /* Tests: */
 128         DBG_TEST_DMA,
 129         DBG_TEST_VMFAULT_CP,
 130         DBG_TEST_VMFAULT_SDMA,
 131         DBG_TEST_VMFAULT_SHADER,
 132 };
 133
 134 #define DBG_ALL_SHADERS         (((1 << (DBG_CS + 1)) - 1))
 135 #define DBG(name)               (1ull << DBG_##name)
 136
 137 #define R600_MAP_BUFFER_ALIGNMENT 64
 138
 139 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
 140
 141 enum r600_coherency {
 142         R600_COHERENCY_NONE, /* no cache flushes needed */
 143         R600_COHERENCY_SHADER,
 144         R600_COHERENCY_CB_META,
 145 };
 146
 147 #ifdef PIPE_ARCH_BIG_ENDIAN
 148 #define R600_BIG_ENDIAN 1
 149 #else
 150 #define R600_BIG_ENDIAN 0
 151 #endif
 152
 153 struct r600_common_context;
 154 struct r600_perfcounters;
 155 struct tgsi_shader_info;
 156 struct r600_qbo_state;
 157
 158 void si_radeon_shader_binary_init(struct ac_shader_binary *b);
 159 void si_radeon_shader_binary_clean(struct ac_shader_binary *b);
 160
 161 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
 162  * at the moment.
 163  */
 164 struct r600_resource {
 165         struct threaded_resource        b;
 166
 167         /* Winsys objects. */
 168         struct pb_buffer                *buf;
 169         uint64_t                        gpu_address;
 170         /* Memory usage if the buffer placement is optimal. */
 171         uint64_t                        vram_usage;
 172         uint64_t                        gart_usage;
 173
 174         /* Resource properties. */
 175         uint64_t                        bo_size;
 176         unsigned                        bo_alignment;
 177         enum radeon_bo_domain           domains;
 178         enum radeon_bo_flag             flags;
 179         unsigned                        bind_history;
 180
 181         /* The buffer range which is initialized (with a write transfer,
 182          * streamout, DMA, or as a random access target). The rest of
 183          * the buffer is considered invalid and can be mapped unsynchronized.
 184          *
 185          * This allows unsychronized mapping of a buffer range which hasn't
 186          * been used yet. It's for applications which forget to use
 187          * the unsynchronized map flag and expect the driver to figure it out.
 188          */
 189         struct util_range               valid_buffer_range;
 190
 191         /* For buffers only. This indicates that a write operation has been
 192          * performed by TC L2, but the cache hasn't been flushed.
 193          * Any hw block which doesn't use or bypasses TC L2 should check this
 194          * flag and flush the cache before using the buffer.
 195          *
 196          * For example, TC L2 must be flushed if a buffer which has been
 197          * modified by a shader store instruction is about to be used as
 198          * an index buffer. The reason is that VGT DMA index fetching doesn't
 199          * use TC L2.
 200          */
 201         bool                            TC_L2_dirty;
 202
 203         /* Whether the resource has been exported via resource_get_handle. */
 204         unsigned                        external_usage; /* PIPE_HANDLE_USAGE_* */
 205
 206         /* Whether this resource is referenced by bindless handles. */
 207         bool                            texture_handle_allocated;
 208         bool                            image_handle_allocated;
 209 };
 210
 211 struct r600_transfer {
 212         struct threaded_transfer        b;
 213         struct r600_resource            *staging;
 214         unsigned                        offset;
 215 };
 216
 217 struct r600_fmask_info {
 218         uint64_t offset;
 219         uint64_t size;
 220         unsigned alignment;
 221         unsigned pitch_in_pixels;
 222         unsigned bank_height;
 223         unsigned slice_tile_max;
 224         unsigned tile_mode_index;
 225         unsigned tile_swizzle;
 226 };
 227
 228 struct r600_cmask_info {
 229         uint64_t offset;
 230         uint64_t size;
 231         unsigned alignment;
 232         unsigned slice_tile_max;
 233         uint64_t base_address_reg;
 234 };
 235
 236 struct r600_texture {
 237         struct r600_resource            resource;
 238
 239         uint64_t                        size;
 240         unsigned                        num_level0_transfers;
 241         enum pipe_format                db_render_format;
 242         bool                            is_depth;
 243         bool                            db_compatible;
 244         bool                            can_sample_z;
 245         bool                            can_sample_s;
 246         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 247         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 248         struct r600_texture             *flushed_depth_texture;
 249         struct radeon_surf              surface;
 250
 251         /* Colorbuffer compression and fast clear. */
 252         struct r600_fmask_info          fmask;
 253         struct r600_cmask_info          cmask;
 254         struct r600_resource            *cmask_buffer;
 255         uint64_t                        dcc_offset; /* 0 = disabled */
 256         unsigned                        cb_color_info; /* fast clear enable bit */
 257         unsigned                        color_clear_value[2];
 258         unsigned                        last_msaa_resolve_target_micro_mode;
 259
 260         /* Depth buffer compression and fast clear. */
 261         uint64_t                        htile_offset;
 262         bool                            tc_compatible_htile;
 263         bool                            depth_cleared; /* if it was cleared at least once */
 264         float                           depth_clear_value;
 265         bool                            stencil_cleared; /* if it was cleared at least once */
 266         uint8_t                         stencil_clear_value;
 267         bool                            upgraded_depth; /* upgraded from unorm to Z32_FLOAT */
 268
 269         bool                            non_disp_tiling; /* R600-Cayman only */
 270
 271         /* Whether the texture is a displayable back buffer and needs DCC
 272          * decompression, which is expensive. Therefore, it's enabled only
 273          * if statistics suggest that it will pay off and it's allocated
 274          * separately. It can't be bound as a sampler by apps. Limited to
 275          * target == 2D and last_level == 0. If enabled, dcc_offset contains
 276          * the absolute GPUVM address, not the relative one.
 277          */
 278         struct r600_resource            *dcc_separate_buffer;
 279         /* When DCC is temporarily disabled, the separate buffer is here. */
 280         struct r600_resource            *last_dcc_separate_buffer;
 281         /* We need to track DCC dirtiness, because st/dri usually calls
 282          * flush_resource twice per frame (not a bug) and we don't wanna
 283          * decompress DCC twice. Also, the dirty tracking must be done even
 284          * if DCC isn't used, because it's required by the DCC usage analysis
 285          * for a possible future enablement.
 286          */
 287         bool                            separate_dcc_dirty;
 288         /* Statistics gathering for the DCC enablement heuristic. */
 289         bool                            dcc_gather_statistics;
 290         /* Estimate of how much this color buffer is written to in units of
 291          * full-screen draws: ps_invocations / (width * height)
 292          * Shader kills, late Z, and blending with trivial discards make it
 293          * inaccurate (we need to count CB updates, not PS invocations).
 294          */
 295         unsigned                        ps_draw_ratio;
 296         /* The number of clears since the last DCC usage analysis. */
 297         unsigned                        num_slow_clears;
 298
 299         /* Counter that should be non-zero if the texture is bound to a
 300          * framebuffer. Implemented in radeonsi only.
 301          */
 302         uint32_t                        framebuffers_bound;
 303 };
 304
 305 struct r600_surface {
 306         struct pipe_surface             base;
 307
 308         /* These can vary with block-compressed textures. */
 309         unsigned width0;
 310         unsigned height0;
 311
 312         bool color_initialized;
 313         bool depth_initialized;
 314
 315         /* Misc. color flags. */
 316         bool alphatest_bypass;
 317         bool export_16bpc;
 318         bool color_is_int8;
 319         bool color_is_int10;
 320         bool dcc_incompatible;
 321
 322         /* Color registers. */
 323         unsigned cb_color_info;
 324         unsigned cb_color_base;
 325         unsigned cb_color_view;
 326         unsigned cb_color_size;         /* R600 only */
 327         unsigned cb_color_dim;          /* EG only */
 328         unsigned cb_color_pitch;        /* EG and later */
 329         unsigned cb_color_slice;        /* EG and later */
 330         unsigned cb_color_attrib;       /* EG and later */
 331         unsigned cb_color_attrib2;      /* GFX9 and later */
 332         unsigned cb_dcc_control;        /* VI and later */
 333         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 334         unsigned cb_color_fmask_slice;  /* EG and later */
 335         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 336         unsigned cb_color_mask;         /* R600 only */
 337         unsigned spi_shader_col_format;         /* SI+, no blending, no alpha-to-coverage. */
 338         unsigned spi_shader_col_format_alpha;   /* SI+, alpha-to-coverage */
 339         unsigned spi_shader_col_format_blend;   /* SI+, blending without alpha. */
 340         unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
 341         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 342         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 343
 344         /* DB registers. */
 345         uint64_t db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 346         uint64_t db_stencil_base;       /* EG and later */
 347         uint64_t db_htile_data_base;
 348         unsigned db_depth_info;         /* R600 only, then SI and later */
 349         unsigned db_z_info;             /* EG and later */
 350         unsigned db_z_info2;            /* GFX9+ */
 351         unsigned db_depth_view;
 352         unsigned db_depth_size;
 353         unsigned db_depth_slice;        /* EG and later */
 354         unsigned db_stencil_info;       /* EG and later */
 355         unsigned db_stencil_info2;      /* GFX9+ */
 356         unsigned db_prefetch_limit;     /* R600 only */
 357         unsigned db_htile_surface;
 358         unsigned db_preload_control;    /* EG and later */
 359 };
 360
 361 struct r600_mmio_counter {
 362         unsigned busy;
 363         unsigned idle;
 364 };
 365
 366 union r600_mmio_counters {
 367         struct {
 368                 /* For global GPU load including SDMA. */
 369                 struct r600_mmio_counter gpu;
 370
 371                 /* GRBM_STATUS */
 372                 struct r600_mmio_counter spi;
 373                 struct r600_mmio_counter gui;
 374                 struct r600_mmio_counter ta;
 375                 struct r600_mmio_counter gds;
 376                 struct r600_mmio_counter vgt;
 377                 struct r600_mmio_counter ia;
 378                 struct r600_mmio_counter sx;
 379                 struct r600_mmio_counter wd;
 380                 struct r600_mmio_counter bci;
 381                 struct r600_mmio_counter sc;
 382                 struct r600_mmio_counter pa;
 383                 struct r600_mmio_counter db;
 384                 struct r600_mmio_counter cp;
 385                 struct r600_mmio_counter cb;
 386
 387                 /* SRBM_STATUS2 */
 388                 struct r600_mmio_counter sdma;
 389
 390                 /* CP_STAT */
 391                 struct r600_mmio_counter pfp;
 392                 struct r600_mmio_counter meq;
 393                 struct r600_mmio_counter me;
 394                 struct r600_mmio_counter surf_sync;
 395                 struct r600_mmio_counter cp_dma;
 396                 struct r600_mmio_counter scratch_ram;
 397         } named;
 398         unsigned array[0];
 399 };
 400
 401 struct r600_memory_object {
 402         struct pipe_memory_object       b;
 403         struct pb_buffer                *buf;
 404         uint32_t                        stride;
 405         uint32_t                        offset;
 406 };
 407
 408 struct r600_common_screen {
 409         struct pipe_screen              b;
 410         struct radeon_winsys            *ws;
 411         enum radeon_family              family;
 412         enum chip_class                 chip_class;
 413         struct radeon_info              info;
 414         uint64_t                        debug_flags;
 415         bool                            has_cp_dma;
 416         bool                            has_streamout;
 417         bool                            has_rbplus;     /* if RB+ registers exist */
 418         bool                            rbplus_allowed; /* if RB+ is allowed */
 419
 420         struct disk_cache               *disk_shader_cache;
 421
 422         struct slab_parent_pool         pool_transfers;
 423
 424         /* Texture filter settings. */
 425         int                             force_aniso; /* -1 = disabled */
 426
 427         /* Auxiliary context. Mainly used to initialize resources.
 428          * It must be locked prior to using and flushed before unlocking. */
 429         struct pipe_context             *aux_context;
 430         mtx_t                           aux_context_lock;
 431
 432         /* This must be in the screen, because UE4 uses one context for
 433          * compilation and another one for rendering.
 434          */
 435         unsigned                        num_compilations;
 436         /* Along with ST_DEBUG=precompile, this should show if applications
 437          * are loading shaders on demand. This is a monotonic counter.
 438          */
 439         unsigned                        num_shaders_created;
 440         unsigned                        num_shader_cache_hits;
 441
 442         /* GPU load thread. */
 443         mtx_t                           gpu_load_mutex;
 444         thrd_t                          gpu_load_thread;
 445         union r600_mmio_counters        mmio_counters;
 446         volatile unsigned               gpu_load_stop_thread; /* bool */
 447
 448         char                            renderer_string[100];
 449
 450         /* Performance counters. */
 451         struct r600_perfcounters        *perfcounters;
 452
 453         /* If pipe_screen wants to recompute and re-emit the framebuffer,
 454          * sampler, and image states of all contexts, it should atomically
 455          * increment this.
 456          *
 457          * Each context will compare this with its own last known value of
 458          * the counter before drawing and re-emit the states accordingly.
 459          */
 460         unsigned                        dirty_tex_counter;
 461
 462         /* Atomically increment this counter when an existing texture's
 463          * metadata is enabled or disabled in a way that requires changing
 464          * contexts' compressed texture binding masks.
 465          */
 466         unsigned                        compressed_colortex_counter;
 467
 468         struct {
 469                 /* Context flags to set so that all writes from earlier jobs
 470                  * in the CP are seen by L2 clients.
 471                  */
 472                 unsigned cp_to_L2;
 473
 474                 /* Context flags to set so that all writes from earlier jobs
 475                  * that end in L2 are seen by CP.
 476                  */
 477                 unsigned L2_to_cp;
 478
 479                 /* Context flags to set so that all writes from earlier
 480                  * compute jobs are seen by L2 clients.
 481                  */
 482                 unsigned compute_to_L2;
 483         } barrier_flags;
 484
 485         void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
 486                                       struct r600_texture *rtex,
 487                                       struct radeon_bo_metadata *md);
 488
 489         void (*apply_opaque_metadata)(struct r600_common_screen *rscreen,
 490                                     struct r600_texture *rtex,
 491                                     struct radeon_bo_metadata *md);
 492 };
 493
 494 /* This encapsulates a state or an operation which can emitted into the GPU
 495  * command stream. */
 496 struct r600_atom {
 497         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 498         unsigned short          id;
 499 };
 500
 501 struct r600_ring {
 502         struct radeon_winsys_cs         *cs;
 503         void (*flush)(void *ctx, unsigned flags,
 504                       struct pipe_fence_handle **fence);
 505 };
 506
 507 /* Saved CS data for debugging features. */
 508 struct radeon_saved_cs {
 509         uint32_t                        *ib;
 510         unsigned                        num_dw;
 511
 512         struct radeon_bo_list_item      *bo_list;
 513         unsigned                        bo_count;
 514 };
 515
 516 struct r600_common_context {
 517         struct pipe_context b; /* base class */
 518
 519         struct r600_common_screen       *screen;
 520         struct radeon_winsys            *ws;
 521         struct radeon_winsys_ctx        *ctx;
 522         enum radeon_family              family;
 523         enum chip_class                 chip_class;
 524         struct r600_ring                gfx;
 525         struct r600_ring                dma;
 526         struct pipe_fence_handle        *last_gfx_fence;
 527         struct pipe_fence_handle        *last_sdma_fence;
 528         struct r600_resource            *eop_bug_scratch;
 529         unsigned                        num_gfx_cs_flushes;
 530         unsigned                        initial_gfx_cs_size;
 531         unsigned                        gpu_reset_counter;
 532         unsigned                        last_dirty_tex_counter;
 533         unsigned                        last_compressed_colortex_counter;
 534         unsigned                        last_num_draw_calls;
 535
 536         struct threaded_context         *tc;
 537         struct u_suballocator           *allocator_zeroed_memory;
 538         struct slab_child_pool          pool_transfers;
 539         struct slab_child_pool          pool_transfers_unsync; /* for threaded_context */
 540
 541         /* Current unaccounted memory usage. */
 542         uint64_t                        vram;
 543         uint64_t                        gtt;
 544
 545         /* Additional context states. */
 546         unsigned flags; /* flush flags */
 547
 548         /* Queries. */
 549         /* Maintain the list of active queries for pausing between IBs. */
 550         int                             num_occlusion_queries;
 551         int                             num_perfect_occlusion_queries;
 552         struct list_head                active_queries;
 553         unsigned                        num_cs_dw_queries_suspend;
 554         /* Misc stats. */
 555         unsigned                        num_draw_calls;
 556         unsigned                        num_decompress_calls;
 557         unsigned                        num_mrt_draw_calls;
 558         unsigned                        num_prim_restart_calls;
 559         unsigned                        num_spill_draw_calls;
 560         unsigned                        num_compute_calls;
 561         unsigned                        num_spill_compute_calls;
 562         unsigned                        num_dma_calls;
 563         unsigned                        num_cp_dma_calls;
 564         unsigned                        num_vs_flushes;
 565         unsigned                        num_ps_flushes;
 566         unsigned                        num_cs_flushes;
 567         unsigned                        num_cb_cache_flushes;
 568         unsigned                        num_db_cache_flushes;
 569         unsigned                        num_L2_invalidates;
 570         unsigned                        num_L2_writebacks;
 571         unsigned                        num_resident_handles;
 572         uint64_t                        num_alloc_tex_transfer_bytes;
 573         unsigned                        last_tex_ps_draw_ratio; /* for query */
 574
 575         /* Render condition. */
 576         struct r600_atom                render_cond_atom;
 577         struct pipe_query               *render_cond;
 578         unsigned                        render_cond_mode;
 579         bool                            render_cond_invert;
 580         bool                            render_cond_force_off; /* for u_blitter */
 581
 582         /* Statistics gathering for the DCC enablement heuristic. It can't be
 583          * in r600_texture because r600_texture can be shared by multiple
 584          * contexts. This is for back buffers only. We shouldn't get too many
 585          * of those.
 586          *
 587          * X11 DRI3 rotates among a finite set of back buffers. They should
 588          * all fit in this array. If they don't, separate DCC might never be
 589          * enabled by DCC stat gathering.
 590          */
 591         struct {
 592                 struct r600_texture             *tex;
 593                 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
 594                 struct pipe_query               *ps_stats[3];
 595                 /* If all slots are used and another slot is needed,
 596                  * the least recently used slot is evicted based on this. */
 597                 int64_t                         last_use_timestamp;
 598                 bool                            query_active;
 599         } dcc_stats[5];
 600
 601         struct pipe_debug_callback      debug;
 602         struct pipe_device_reset_callback device_reset_callback;
 603         struct u_log_context            *log;
 604
 605         void                            *query_result_shader;
 606
 607         /* Copy one resource to another using async DMA. */
 608         void (*dma_copy)(struct pipe_context *ctx,
 609                          struct pipe_resource *dst,
 610                          unsigned dst_level,
 611                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 612                          struct pipe_resource *src,
 613                          unsigned src_level,
 614                          const struct pipe_box *src_box);
 615
 616         void (*dma_clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 617                                  uint64_t offset, uint64_t size, unsigned value);
 618
 619         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 620                              uint64_t offset, uint64_t size, unsigned value,
 621                              enum r600_coherency coher);
 622
 623         void (*blit_decompress_depth)(struct pipe_context *ctx,
 624                                       struct r600_texture *texture,
 625                                       struct r600_texture *staging,
 626                                       unsigned first_level, unsigned last_level,
 627                                       unsigned first_layer, unsigned last_layer,
 628                                       unsigned first_sample, unsigned last_sample);
 629
 630         void (*decompress_dcc)(struct pipe_context *ctx,
 631                                struct r600_texture *rtex);
 632
 633         /* Reallocate the buffer and update all resource bindings where
 634          * the buffer is bound, including all resource descriptors. */
 635         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 636
 637         /* Update all resource bindings where the buffer is bound, including
 638          * all resource descriptors. This is invalidate_buffer without
 639          * the invalidation. */
 640         void (*rebind_buffer)(struct pipe_context *ctx, struct pipe_resource *buf,
 641                               uint64_t old_gpu_address);
 642
 643         /* Enable or disable occlusion queries. */
 644         void (*set_occlusion_query_state)(struct pipe_context *ctx,
 645                                           bool old_enable,
 646                                           bool old_perfect_enable);
 647
 648         void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state *st);
 649
 650         /* This ensures there is enough space in the command stream. */
 651         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 652                                   bool include_draw_vbo);
 653
 654         void (*set_atom_dirty)(struct r600_common_context *ctx,
 655                                struct r600_atom *atom, bool dirty);
 656
 657         void (*check_vm_faults)(struct r600_common_context *ctx,
 658                                 struct radeon_saved_cs *saved,
 659                                 enum ring_type ring);
 660 };
 661
 662 /* r600_buffer_common.c */
 663 bool si_rings_is_buffer_referenced(struct r600_common_context *ctx,
 664                                    struct pb_buffer *buf,
 665                                    enum radeon_bo_usage usage);
 666 void *si_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 667                                     struct r600_resource *resource,
 668                                     unsigned usage);
 669 void si_buffer_subdata(struct pipe_context *ctx,
 670                        struct pipe_resource *buffer,
 671                        unsigned usage, unsigned offset,
 672                        unsigned size, const void *data);
 673 void si_init_resource_fields(struct r600_common_screen *rscreen,
 674                              struct r600_resource *res,
 675                              uint64_t size, unsigned alignment);
 676 bool si_alloc_resource(struct r600_common_screen *rscreen,
 677                        struct r600_resource *res);
 678 struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
 679                                        const struct pipe_resource *templ,
 680                                        unsigned alignment);
 681 struct pipe_resource *si_aligned_buffer_create(struct pipe_screen *screen,
 682                                                unsigned flags,
 683                                                unsigned usage,
 684                                                unsigned size,
 685                                                unsigned alignment);
 686 struct pipe_resource *
 687 si_buffer_from_user_memory(struct pipe_screen *screen,
 688                            const struct pipe_resource *templ,
 689                            void *user_memory);
 690 void si_invalidate_resource(struct pipe_context *ctx,
 691                             struct pipe_resource *resource);
 692 void si_replace_buffer_storage(struct pipe_context *ctx,
 693                                struct pipe_resource *dst,
 694                                struct pipe_resource *src);
 695
 696 /* r600_common_pipe.c */
 697 void si_gfx_write_event_eop(struct r600_common_context *ctx,
 698                             unsigned event, unsigned event_flags,
 699                             unsigned data_sel,
 700                             struct r600_resource *buf, uint64_t va,
 701                             uint32_t new_fence, unsigned query_type);
 702 unsigned si_gfx_write_fence_dwords(struct r600_common_screen *screen);
 703 void si_gfx_wait_fence(struct r600_common_context *ctx,
 704                        uint64_t va, uint32_t ref, uint32_t mask);
 705 bool si_common_screen_init(struct r600_common_screen *rscreen,
 706                            struct radeon_winsys *ws);
 707 void si_destroy_common_screen(struct r600_common_screen *rscreen);
 708 void si_preflush_suspend_features(struct r600_common_context *ctx);
 709 void si_postflush_resume_features(struct r600_common_context *ctx);
 710 bool si_common_context_init(struct r600_common_context *rctx,
 711                             struct r600_common_screen *rscreen,
 712                             unsigned context_flags);
 713 void si_common_context_cleanup(struct r600_common_context *rctx);
 714 bool si_can_dump_shader(struct r600_common_screen *rscreen,
 715                         unsigned processor);
 716 bool si_extra_shader_checks(struct r600_common_screen *rscreen,
 717                             unsigned processor);
 718 void si_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 719                             uint64_t offset, uint64_t size, unsigned value);
 720 struct pipe_resource *si_resource_create_common(struct pipe_screen *screen,
 721                                                 const struct pipe_resource *templ);
 722 const char *si_get_llvm_processor_name(enum radeon_family family);
 723 void si_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
 724                        struct r600_resource *dst, struct r600_resource *src);
 725 void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
 726                 struct radeon_saved_cs *saved, bool get_buffer_list);
 727 void si_clear_saved_cs(struct radeon_saved_cs *saved);
 728 bool si_check_device_reset(struct r600_common_context *rctx);
 729
 730 /* r600_gpu_load.c */
 731 void si_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 732 uint64_t si_begin_counter(struct r600_common_screen *rscreen, unsigned type);
 733 unsigned si_end_counter(struct r600_common_screen *rscreen, unsigned type,
 734                         uint64_t begin);
 735
 736 /* r600_perfcounters.c */
 737 void si_perfcounters_destroy(struct r600_common_screen *rscreen);
 738
 739 /* r600_query.c */
 740 void si_init_screen_query_functions(struct r600_common_screen *rscreen);
 741 void si_init_query_functions(struct r600_common_context *rctx);
 742 void si_suspend_queries(struct r600_common_context *ctx);
 743 void si_resume_queries(struct r600_common_context *ctx);
 744
 745 /* r600_test_dma.c */
 746 void si_test_dma(struct r600_common_screen *rscreen);
 747
 748 /* r600_texture.c */
 749 bool si_prepare_for_dma_blit(struct r600_common_context *rctx,
 750                              struct r600_texture *rdst,
 751                              unsigned dst_level, unsigned dstx,
 752                              unsigned dsty, unsigned dstz,
 753                              struct r600_texture *rsrc,
 754                              unsigned src_level,
 755                              const struct pipe_box *src_box);
 756 void si_texture_get_fmask_info(struct r600_common_screen *rscreen,
 757                                struct r600_texture *rtex,
 758                                unsigned nr_samples,
 759                                struct r600_fmask_info *out);
 760 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
 761                                    struct pipe_resource *texture,
 762                                    struct r600_texture **staging);
 763 void si_print_texture_info(struct r600_common_screen *rscreen,
 764                            struct r600_texture *rtex, struct u_log_context *log);
 765 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
 766                                         const struct pipe_resource *templ);
 767 bool vi_dcc_formats_compatible(enum pipe_format format1,
 768                                enum pipe_format format2);
 769 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
 770                                      unsigned level,
 771                                      enum pipe_format view_format);
 772 void vi_disable_dcc_if_incompatible_format(struct r600_common_context *rctx,
 773                                            struct pipe_resource *tex,
 774                                            unsigned level,
 775                                            enum pipe_format view_format);
 776 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
 777                                               struct pipe_resource *texture,
 778                                               const struct pipe_surface *templ,
 779                                               unsigned width0, unsigned height0,
 780                                               unsigned width, unsigned height);
 781 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
 782 void vi_separate_dcc_start_query(struct pipe_context *ctx,
 783                                  struct r600_texture *tex);
 784 void vi_separate_dcc_stop_query(struct pipe_context *ctx,
 785                                 struct r600_texture *tex);
 786 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
 787                                              struct r600_texture *tex);
 788 void vi_dcc_clear_level(struct r600_common_context *rctx,
 789                         struct r600_texture *rtex,
 790                         unsigned level, unsigned clear_value);
 791 void si_do_fast_color_clear(struct r600_common_context *rctx,
 792                             struct pipe_framebuffer_state *fb,
 793                             struct r600_atom *fb_state,
 794                             unsigned *buffers, ubyte *dirty_cbufs,
 795                             const union pipe_color_union *color);
 796 bool si_texture_disable_dcc(struct r600_common_context *rctx,
 797                             struct r600_texture *rtex);
 798 void si_init_screen_texture_functions(struct r600_common_screen *rscreen);
 799 void si_init_context_texture_functions(struct r600_common_context *rctx);
 800
 801
 802 /* Inline helpers. */
 803
 804 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 805 {
 806         return (struct r600_resource*)r;
 807 }
 808
 809 static inline void
 810 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 811 {
 812         pipe_resource_reference((struct pipe_resource **)ptr,
 813                                 (struct pipe_resource *)res);
 814 }
 815
 816 static inline void
 817 r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
 818 {
 819         pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
 820 }
 821
 822 static inline void
 823 r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
 824 {
 825         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 826         struct r600_resource *res = (struct r600_resource *)r;
 827
 828         if (res) {
 829                 /* Add memory usage for need_gfx_cs_space */
 830                 rctx->vram += res->vram_usage;
 831                 rctx->gtt += res->gart_usage;
 832         }
 833 }
 834
 835 #define     SQ_TEX_XY_FILTER_POINT                         0x00
 836 #define     SQ_TEX_XY_FILTER_BILINEAR                      0x01
 837 #define     SQ_TEX_XY_FILTER_ANISO_POINT                   0x02
 838 #define     SQ_TEX_XY_FILTER_ANISO_BILINEAR                0x03
 839
 840 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
 841 {
 842         if (filter == PIPE_TEX_FILTER_LINEAR)
 843                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
 844                                      : SQ_TEX_XY_FILTER_BILINEAR;
 845         else
 846                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
 847                                      : SQ_TEX_XY_FILTER_POINT;
 848 }
 849
 850 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 851 {
 852         if (filter < 2)
 853                 return 0;
 854         if (filter < 4)
 855                 return 1;
 856         if (filter < 8)
 857                 return 2;
 858         if (filter < 16)
 859                 return 3;
 860         return 4;
 861 }
 862
 863 static inline enum radeon_bo_priority
 864 r600_get_sampler_view_priority(struct r600_resource *res)
 865 {
 866         if (res->b.b.target == PIPE_BUFFER)
 867                 return RADEON_PRIO_SAMPLER_BUFFER;
 868
 869         if (res->b.b.nr_samples > 1)
 870                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 871
 872         return RADEON_PRIO_SAMPLER_TEXTURE;
 873 }
 874
 875 static inline bool
 876 r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
 877 {
 878         return (stencil_sampler && tex->can_sample_s) ||
 879                (!stencil_sampler && tex->can_sample_z);
 880 }
 881
 882 static inline bool
 883 vi_dcc_enabled(struct r600_texture *tex, unsigned level)
 884 {
 885         return tex->dcc_offset && level < tex->surface.num_dcc_levels;
 886 }
 887
 888 static inline bool
 889 r600_htile_enabled(struct r600_texture *tex, unsigned level)
 890 {
 891         return tex->htile_offset && level == 0;
 892 }
 893
 894 static inline bool
 895 vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
 896 {
 897         assert(!tex->tc_compatible_htile || tex->htile_offset);
 898         return tex->tc_compatible_htile && level == 0;
 899 }
 900
 901 #define COMPUTE_DBG(rscreen, fmt, args...) \
 902         do { \
 903                 if ((rscreen->b.debug_flags & DBG(COMPUTE))) fprintf(stderr, fmt, ##args); \
 904         } while (0);
 905
 906 #define R600_ERR(fmt, args...) \
 907         fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 908
 909 static inline int S_FIXED(float value, unsigned frac_bits)
 910 {
 911         return value * (1 << frac_bits);
 912 }
 913
 914 #endif