src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/u_slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define ATI_VENDOR_ID 0x1002
  47
  48 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  49 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  50 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  51
  52 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  53 /* Pipeline & streamout query controls. */
  54 #define R600_CONTEXT_START_PIPELINE_STATS       (1u << 1)
  55 #define R600_CONTEXT_STOP_PIPELINE_STATS        (1u << 2)
  56 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 3)
  57
  58 /* special primitive types */
  59 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  60
  61 /* Debug flags. */
  62 /* logging */
  63 #define DBG_TEX                 (1 << 0)
  64 /* gap - reuse */
  65 #define DBG_COMPUTE             (1 << 2)
  66 #define DBG_VM                  (1 << 3)
  67 /* gap - reuse */
  68 /* shader logging */
  69 #define DBG_FS                  (1 << 5)
  70 #define DBG_VS                  (1 << 6)
  71 #define DBG_GS                  (1 << 7)
  72 #define DBG_PS                  (1 << 8)
  73 #define DBG_CS                  (1 << 9)
  74 #define DBG_TCS                 (1 << 10)
  75 #define DBG_TES                 (1 << 11)
  76 #define DBG_NO_IR               (1 << 12)
  77 #define DBG_NO_TGSI             (1 << 13)
  78 #define DBG_NO_ASM              (1 << 14)
  79 #define DBG_PREOPT_IR           (1 << 15)
  80 /* Bits 21-31 are reserved for the r600g driver. */
  81 /* features */
  82 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  83 #define DBG_NO_HYPERZ           (1llu << 33)
  84 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  85 #define DBG_NO_2D_TILING        (1llu << 35)
  86 #define DBG_NO_TILING           (1llu << 36)
  87 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  88 #define DBG_FORCE_DMA           (1llu << 38)
  89 #define DBG_PRECOMPILE          (1llu << 39)
  90 #define DBG_INFO                (1llu << 40)
  91 #define DBG_NO_WC               (1llu << 41)
  92 #define DBG_CHECK_VM            (1llu << 42)
  93 #define DBG_NO_DCC              (1llu << 43)
  94 #define DBG_NO_DCC_CLEAR        (1llu << 44)
  95 #define DBG_NO_RB_PLUS          (1llu << 45)
  96 #define DBG_SI_SCHED            (1llu << 46)
  97 #define DBG_MONOLITHIC_SHADERS  (1llu << 47)
  98 #define DBG_NO_CE               (1llu << 48)
  99
 100 #define R600_MAP_BUFFER_ALIGNMENT 64
 101 #define R600_MAX_VIEWPORTS        16
 102
 103 enum r600_coherency {
 104         R600_COHERENCY_NONE, /* no cache flushes needed */
 105         R600_COHERENCY_SHADER,
 106         R600_COHERENCY_CB_META,
 107 };
 108
 109 #ifdef PIPE_ARCH_BIG_ENDIAN
 110 #define R600_BIG_ENDIAN 1
 111 #else
 112 #define R600_BIG_ENDIAN 0
 113 #endif
 114
 115 struct r600_common_context;
 116 struct r600_perfcounters;
 117 struct tgsi_shader_info;
 118
 119 struct radeon_shader_reloc {
 120         char name[32];
 121         uint64_t offset;
 122 };
 123
 124 struct radeon_shader_binary {
 125         /** Shader code */
 126         unsigned char *code;
 127         unsigned code_size;
 128
 129         /** Config/Context register state that accompanies this shader.
 130          * This is a stream of dword pairs.  First dword contains the
 131          * register address, the second dword contains the value.*/
 132         unsigned char *config;
 133         unsigned config_size;
 134
 135         /** The number of bytes of config information for each global symbol.
 136          */
 137         unsigned config_size_per_symbol;
 138
 139         /** Constant data accessed by the shader.  This will be uploaded
 140          * into a constant buffer. */
 141         unsigned char *rodata;
 142         unsigned rodata_size;
 143
 144         /** List of symbol offsets for the shader */
 145         uint64_t *global_symbol_offsets;
 146         unsigned global_symbol_count;
 147
 148         struct radeon_shader_reloc *relocs;
 149         unsigned reloc_count;
 150
 151         /** Disassembled shader in a string. */
 152         char *disasm_string;
 153 };
 154
 155 void radeon_shader_binary_init(struct radeon_shader_binary *b);
 156 void radeon_shader_binary_clean(struct radeon_shader_binary *b);
 157
 158 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
 159  * at the moment.
 160  */
 161 struct r600_resource {
 162         struct u_resource               b;
 163
 164         /* Winsys objects. */
 165         struct pb_buffer                *buf;
 166         uint64_t                        gpu_address;
 167
 168         /* Resource state. */
 169         enum radeon_bo_domain           domains;
 170
 171         /* The buffer range which is initialized (with a write transfer,
 172          * streamout, DMA, or as a random access target). The rest of
 173          * the buffer is considered invalid and can be mapped unsynchronized.
 174          *
 175          * This allows unsychronized mapping of a buffer range which hasn't
 176          * been used yet. It's for applications which forget to use
 177          * the unsynchronized map flag and expect the driver to figure it out.
 178          */
 179         struct util_range               valid_buffer_range;
 180
 181         /* For buffers only. This indicates that a write operation has been
 182          * performed by TC L2, but the cache hasn't been flushed.
 183          * Any hw block which doesn't use or bypasses TC L2 should check this
 184          * flag and flush the cache before using the buffer.
 185          *
 186          * For example, TC L2 must be flushed if a buffer which has been
 187          * modified by a shader store instruction is about to be used as
 188          * an index buffer. The reason is that VGT DMA index fetching doesn't
 189          * use TC L2.
 190          */
 191         bool                            TC_L2_dirty;
 192
 193         /* Whether the resource has been exported via resource_get_handle. */
 194         bool                            is_shared;
 195         unsigned                        external_usage; /* PIPE_HANDLE_USAGE_* */
 196 };
 197
 198 struct r600_transfer {
 199         struct pipe_transfer            transfer;
 200         struct r600_resource            *staging;
 201         unsigned                        offset;
 202 };
 203
 204 struct r600_fmask_info {
 205         uint64_t offset;
 206         uint64_t size;
 207         unsigned alignment;
 208         unsigned pitch_in_pixels;
 209         unsigned bank_height;
 210         unsigned slice_tile_max;
 211         unsigned tile_mode_index;
 212 };
 213
 214 struct r600_cmask_info {
 215         uint64_t offset;
 216         uint64_t size;
 217         unsigned alignment;
 218         unsigned pitch;
 219         unsigned height;
 220         unsigned xalign;
 221         unsigned yalign;
 222         unsigned slice_tile_max;
 223         unsigned base_address_reg;
 224 };
 225
 226 struct r600_htile_info {
 227         unsigned pitch;
 228         unsigned height;
 229         unsigned xalign;
 230         unsigned yalign;
 231 };
 232
 233 struct r600_texture {
 234         struct r600_resource            resource;
 235
 236         uint64_t                        size;
 237         bool                            is_depth;
 238         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 239         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 240         struct r600_texture             *flushed_depth_texture;
 241         boolean                         is_flushing_texture;
 242         struct radeon_surf              surface;
 243
 244         /* Colorbuffer compression and fast clear. */
 245         struct r600_fmask_info          fmask;
 246         struct r600_cmask_info          cmask;
 247         struct r600_resource            *cmask_buffer;
 248         uint64_t                        dcc_offset; /* 0 = disabled */
 249         unsigned                        cb_color_info; /* fast clear enable bit */
 250         unsigned                        color_clear_value[2];
 251
 252         /* Depth buffer compression and fast clear. */
 253         struct r600_htile_info          htile;
 254         struct r600_resource            *htile_buffer;
 255         bool                            depth_cleared; /* if it was cleared at least once */
 256         float                           depth_clear_value;
 257         bool                            stencil_cleared; /* if it was cleared at least once */
 258         uint8_t                         stencil_clear_value;
 259
 260         bool                            non_disp_tiling; /* R600-Cayman only */
 261 };
 262
 263 struct r600_surface {
 264         struct pipe_surface             base;
 265
 266         bool color_initialized;
 267         bool depth_initialized;
 268
 269         /* Misc. color flags. */
 270         bool alphatest_bypass;
 271         bool export_16bpc;
 272         bool color_is_int8;
 273
 274         /* Color registers. */
 275         unsigned cb_color_info;
 276         unsigned cb_color_base;
 277         unsigned cb_color_view;
 278         unsigned cb_color_size;         /* R600 only */
 279         unsigned cb_color_dim;          /* EG only */
 280         unsigned cb_color_pitch;        /* EG and later */
 281         unsigned cb_color_slice;        /* EG and later */
 282         unsigned cb_dcc_base;           /* VI and later */
 283         unsigned cb_color_attrib;       /* EG and later */
 284         unsigned cb_dcc_control;        /* VI and later */
 285         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 286         unsigned cb_color_fmask_slice;  /* EG and later */
 287         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 288         unsigned cb_color_mask;         /* R600 only */
 289         unsigned spi_shader_col_format;         /* SI+, no blending, no alpha-to-coverage. */
 290         unsigned spi_shader_col_format_alpha;   /* SI+, alpha-to-coverage */
 291         unsigned spi_shader_col_format_blend;   /* SI+, blending without alpha. */
 292         unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
 293         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 294         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 295
 296         /* DB registers. */
 297         unsigned db_depth_info;         /* R600 only, then SI and later */
 298         unsigned db_z_info;             /* EG and later */
 299         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 300         unsigned db_depth_view;
 301         unsigned db_depth_size;
 302         unsigned db_depth_slice;        /* EG and later */
 303         unsigned db_stencil_base;       /* EG and later */
 304         unsigned db_stencil_info;       /* EG and later */
 305         unsigned db_prefetch_limit;     /* R600 only */
 306         unsigned db_htile_surface;
 307         unsigned db_htile_data_base;
 308         unsigned db_preload_control;    /* EG and later */
 309         unsigned pa_su_poly_offset_db_fmt_cntl;
 310 };
 311
 312 struct r600_common_screen {
 313         struct pipe_screen              b;
 314         struct radeon_winsys            *ws;
 315         enum radeon_family              family;
 316         enum chip_class                 chip_class;
 317         struct radeon_info              info;
 318         uint64_t                        debug_flags;
 319         bool                            has_cp_dma;
 320         bool                            has_streamout;
 321
 322         /* Texture filter settings. */
 323         int                             force_aniso; /* -1 = disabled */
 324
 325         /* Auxiliary context. Mainly used to initialize resources.
 326          * It must be locked prior to using and flushed before unlocking. */
 327         struct pipe_context             *aux_context;
 328         pipe_mutex                      aux_context_lock;
 329
 330         /* This must be in the screen, because UE4 uses one context for
 331          * compilation and another one for rendering.
 332          */
 333         unsigned                        num_compilations;
 334         /* Along with ST_DEBUG=precompile, this should show if applications
 335          * are loading shaders on demand. This is a monotonic counter.
 336          */
 337         unsigned                        num_shaders_created;
 338
 339         /* GPU load thread. */
 340         pipe_mutex                      gpu_load_mutex;
 341         pipe_thread                     gpu_load_thread;
 342         unsigned                        gpu_load_counter_busy;
 343         unsigned                        gpu_load_counter_idle;
 344         volatile unsigned               gpu_load_stop_thread; /* bool */
 345
 346         char                            renderer_string[64];
 347
 348         /* Performance counters. */
 349         struct r600_perfcounters        *perfcounters;
 350
 351         /* If pipe_screen wants to re-emit the framebuffer state of all
 352          * contexts, it should atomically increment this. Each context will
 353          * compare this with its own last known value of the counter before
 354          * drawing and re-emit the framebuffer state accordingly.
 355          */
 356         unsigned                        dirty_fb_counter;
 357
 358         /* Atomically increment this counter when an existing texture's
 359          * metadata is enabled or disabled in a way that requires changing
 360          * contexts' compressed texture binding masks.
 361          */
 362         unsigned                        compressed_colortex_counter;
 363
 364         void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
 365                                       struct r600_texture *rtex,
 366                                       struct radeon_bo_metadata *md);
 367 };
 368
 369 /* This encapsulates a state or an operation which can emitted into the GPU
 370  * command stream. */
 371 struct r600_atom {
 372         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 373         unsigned                num_dw;
 374         unsigned short          id;
 375 };
 376
 377 struct r600_so_target {
 378         struct pipe_stream_output_target b;
 379
 380         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 381         struct r600_resource    *buf_filled_size;
 382         unsigned                buf_filled_size_offset;
 383         bool                    buf_filled_size_valid;
 384
 385         unsigned                stride_in_dw;
 386 };
 387
 388 struct r600_streamout {
 389         struct r600_atom                begin_atom;
 390         bool                            begin_emitted;
 391         unsigned                        num_dw_for_end;
 392
 393         unsigned                        enabled_mask;
 394         unsigned                        num_targets;
 395         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 396
 397         unsigned                        append_bitmask;
 398         bool                            suspended;
 399
 400         /* External state which comes from the vertex shader,
 401          * it must be set explicitly when binding a shader. */
 402         unsigned                        *stride_in_dw;
 403         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 404
 405         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 406         unsigned                        hw_enabled_mask;
 407
 408         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 409         struct r600_atom                enable_atom;
 410         bool                            streamout_enabled;
 411         bool                            prims_gen_query_enabled;
 412         int                             num_prims_gen_queries;
 413 };
 414
 415 struct r600_signed_scissor {
 416         int minx;
 417         int miny;
 418         int maxx;
 419         int maxy;
 420 };
 421
 422 struct r600_scissors {
 423         struct r600_atom                atom;
 424         unsigned                        dirty_mask;
 425         struct pipe_scissor_state       states[R600_MAX_VIEWPORTS];
 426 };
 427
 428 struct r600_viewports {
 429         struct r600_atom                atom;
 430         unsigned                        dirty_mask;
 431         struct pipe_viewport_state      states[R600_MAX_VIEWPORTS];
 432         struct r600_signed_scissor      as_scissor[R600_MAX_VIEWPORTS];
 433 };
 434
 435 struct r600_ring {
 436         struct radeon_winsys_cs         *cs;
 437         void (*flush)(void *ctx, unsigned flags,
 438                       struct pipe_fence_handle **fence);
 439 };
 440
 441 struct r600_common_context {
 442         struct pipe_context b; /* base class */
 443
 444         struct r600_common_screen       *screen;
 445         struct radeon_winsys            *ws;
 446         struct radeon_winsys_ctx        *ctx;
 447         enum radeon_family              family;
 448         enum chip_class                 chip_class;
 449         struct r600_ring                gfx;
 450         struct r600_ring                dma;
 451         struct pipe_fence_handle        *last_sdma_fence;
 452         unsigned                        initial_gfx_cs_size;
 453         unsigned                        gpu_reset_counter;
 454         unsigned                        last_dirty_fb_counter;
 455         unsigned                        last_compressed_colortex_counter;
 456
 457         struct u_upload_mgr             *uploader;
 458         struct u_suballocator           *allocator_so_filled_size;
 459         struct util_slab_mempool        pool_transfers;
 460
 461         /* Current unaccounted memory usage. */
 462         uint64_t                        vram;
 463         uint64_t                        gtt;
 464
 465         /* States. */
 466         struct r600_streamout           streamout;
 467         struct r600_scissors            scissors;
 468         struct r600_viewports           viewports;
 469         bool                            scissor_enabled;
 470         bool                            vs_writes_viewport_index;
 471         bool                            vs_disables_clipping_viewport;
 472
 473         /* Additional context states. */
 474         unsigned flags; /* flush flags */
 475
 476         /* Queries. */
 477         /* Maintain the list of active queries for pausing between IBs. */
 478         int                             num_occlusion_queries;
 479         int                             num_perfect_occlusion_queries;
 480         struct list_head                active_queries;
 481         unsigned                        num_cs_dw_queries_suspend;
 482         /* Additional hardware info. */
 483         unsigned                        backend_mask;
 484         unsigned                        max_db; /* for OQ */
 485         /* Misc stats. */
 486         unsigned                        num_draw_calls;
 487
 488         /* Render condition. */
 489         struct r600_atom                render_cond_atom;
 490         struct pipe_query               *render_cond;
 491         unsigned                        render_cond_mode;
 492         boolean                         render_cond_invert;
 493         bool                            render_cond_force_off; /* for u_blitter */
 494
 495         /* MSAA sample locations.
 496          * The first index is the sample index.
 497          * The second index is the coordinate: X, Y. */
 498         float                           sample_locations_1x[1][2];
 499         float                           sample_locations_2x[2][2];
 500         float                           sample_locations_4x[4][2];
 501         float                           sample_locations_8x[8][2];
 502         float                           sample_locations_16x[16][2];
 503
 504         /* The list of all texture buffer objects in this context.
 505          * This list is walked when a buffer is invalidated/reallocated and
 506          * the GPU addresses are updated. */
 507         struct list_head                texture_buffers;
 508
 509         struct pipe_debug_callback      debug;
 510
 511         /* Copy one resource to another using async DMA. */
 512         void (*dma_copy)(struct pipe_context *ctx,
 513                          struct pipe_resource *dst,
 514                          unsigned dst_level,
 515                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 516                          struct pipe_resource *src,
 517                          unsigned src_level,
 518                          const struct pipe_box *src_box);
 519
 520         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 521                              uint64_t offset, uint64_t size, unsigned value,
 522                              enum r600_coherency coher);
 523
 524         void (*blit_decompress_depth)(struct pipe_context *ctx,
 525                                       struct r600_texture *texture,
 526                                       struct r600_texture *staging,
 527                                       unsigned first_level, unsigned last_level,
 528                                       unsigned first_layer, unsigned last_layer,
 529                                       unsigned first_sample, unsigned last_sample);
 530
 531         void (*decompress_dcc)(struct pipe_context *ctx,
 532                                struct r600_texture *rtex);
 533
 534         /* Reallocate the buffer and update all resource bindings where
 535          * the buffer is bound, including all resource descriptors. */
 536         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 537
 538         /* Enable or disable occlusion queries. */
 539         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 540
 541         /* This ensures there is enough space in the command stream. */
 542         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 543                                   bool include_draw_vbo);
 544
 545         void (*set_atom_dirty)(struct r600_common_context *ctx,
 546                                struct r600_atom *atom, bool dirty);
 547 };
 548
 549 /* r600_buffer.c */
 550 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 551                                         struct pb_buffer *buf,
 552                                         enum radeon_bo_usage usage);
 553 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 554                                       struct r600_resource *resource,
 555                                       unsigned usage);
 556 bool r600_init_resource(struct r600_common_screen *rscreen,
 557                         struct r600_resource *res,
 558                         uint64_t size, unsigned alignment);
 559 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 560                                          const struct pipe_resource *templ,
 561                                          unsigned alignment);
 562 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
 563                                                   unsigned bind,
 564                                                   unsigned usage,
 565                                                   unsigned size,
 566                                                   unsigned alignment);
 567 struct pipe_resource *
 568 r600_buffer_from_user_memory(struct pipe_screen *screen,
 569                              const struct pipe_resource *templ,
 570                              void *user_memory);
 571 void
 572 r600_invalidate_resource(struct pipe_context *ctx,
 573                          struct pipe_resource *resource);
 574
 575 /* r600_common_pipe.c */
 576 void r600_draw_rectangle(struct blitter_context *blitter,
 577                          int x1, int y1, int x2, int y2, float depth,
 578                          enum blitter_attrib_type type,
 579                          const union pipe_color_union *attrib);
 580 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 581                              struct radeon_winsys *ws);
 582 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 583 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 584 void r600_postflush_resume_features(struct r600_common_context *ctx);
 585 bool r600_common_context_init(struct r600_common_context *rctx,
 586                               struct r600_common_screen *rscreen);
 587 void r600_common_context_cleanup(struct r600_common_context *rctx);
 588 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 589 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 590                           unsigned processor);
 591 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 592                               uint64_t offset, uint64_t size, unsigned value,
 593                               enum r600_coherency coher);
 594 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 595                                                   const struct pipe_resource *templ);
 596 const char *r600_get_llvm_processor_name(enum radeon_family family);
 597 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw);
 598
 599 /* r600_gpu_load.c */
 600 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 601 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 602 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 603
 604 /* r600_perfcounters.c */
 605 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
 606
 607 /* r600_query.c */
 608 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
 609 void r600_query_init(struct r600_common_context *rctx);
 610 void r600_suspend_queries(struct r600_common_context *ctx);
 611 void r600_resume_queries(struct r600_common_context *ctx);
 612 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 613
 614 /* r600_streamout.c */
 615 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 616 void r600_set_streamout_targets(struct pipe_context *ctx,
 617                                 unsigned num_targets,
 618                                 struct pipe_stream_output_target **targets,
 619                                 const unsigned *offset);
 620 void r600_emit_streamout_end(struct r600_common_context *rctx);
 621 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 622                                              unsigned type, int diff);
 623 void r600_streamout_init(struct r600_common_context *rctx);
 624
 625 /* r600_texture.c */
 626 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 627                                  struct r600_texture *rtex,
 628                                  unsigned nr_samples,
 629                                  struct r600_fmask_info *out);
 630 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 631                                  struct r600_texture *rtex,
 632                                  struct r600_cmask_info *out);
 633 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 634                                      struct pipe_resource *texture,
 635                                      struct r600_texture **staging);
 636 void r600_print_texture_info(struct r600_texture *rtex, FILE *f);
 637 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 638                                         const struct pipe_resource *templ);
 639 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 640                                                 struct pipe_resource *texture,
 641                                                 const struct pipe_surface *templ,
 642                                                 unsigned width, unsigned height);
 643 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
 644 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 645                                    struct pipe_framebuffer_state *fb,
 646                                    struct r600_atom *fb_state,
 647                                    unsigned *buffers, unsigned *dirty_cbufs,
 648                                    const union pipe_color_union *color);
 649 void r600_texture_disable_dcc(struct r600_common_screen *rscreen,
 650                               struct r600_texture *rtex);
 651 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 652 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 653
 654 /* r600_viewport.c */
 655 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
 656                                             struct pipe_scissor_state *scissor);
 657 void r600_set_scissor_enable(struct r600_common_context *rctx, bool enable);
 658 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
 659                                           struct tgsi_shader_info *info);
 660 void r600_init_viewport_functions(struct r600_common_context *rctx);
 661
 662 /* cayman_msaa.c */
 663 extern const uint32_t eg_sample_locs_2x[4];
 664 extern const unsigned eg_max_dist_2x;
 665 extern const uint32_t eg_sample_locs_4x[4];
 666 extern const unsigned eg_max_dist_4x;
 667 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 668                                 unsigned sample_index, float *out_value);
 669 void cayman_init_msaa(struct pipe_context *ctx);
 670 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 671 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 672                              int ps_iter_samples, int overrast_samples);
 673
 674
 675 /* Inline helpers. */
 676
 677 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 678 {
 679         return (struct r600_resource*)r;
 680 }
 681
 682 static inline void
 683 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 684 {
 685         pipe_resource_reference((struct pipe_resource **)ptr,
 686                                 (struct pipe_resource *)res);
 687 }
 688
 689 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
 690 {
 691         return rctx->streamout.streamout_enabled ||
 692                rctx->streamout.prims_gen_query_enabled;
 693 }
 694
 695 #define     SQ_TEX_XY_FILTER_POINT                         0x00
 696 #define     SQ_TEX_XY_FILTER_BILINEAR                      0x01
 697 #define     SQ_TEX_XY_FILTER_ANISO_POINT                   0x02
 698 #define     SQ_TEX_XY_FILTER_ANISO_BILINEAR                0x03
 699
 700 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
 701 {
 702         if (filter == PIPE_TEX_FILTER_LINEAR)
 703                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
 704                                      : SQ_TEX_XY_FILTER_BILINEAR;
 705         else
 706                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
 707                                      : SQ_TEX_XY_FILTER_POINT;
 708 }
 709
 710 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 711 {
 712         if (filter < 2)
 713                 return 0;
 714         if (filter < 4)
 715                 return 1;
 716         if (filter < 8)
 717                 return 2;
 718         if (filter < 16)
 719                 return 3;
 720         return 4;
 721 }
 722
 723 static inline unsigned r600_wavefront_size(enum radeon_family family)
 724 {
 725         switch (family) {
 726         case CHIP_RV610:
 727         case CHIP_RS780:
 728         case CHIP_RV620:
 729         case CHIP_RS880:
 730                 return 16;
 731         case CHIP_RV630:
 732         case CHIP_RV635:
 733         case CHIP_RV730:
 734         case CHIP_RV710:
 735         case CHIP_PALM:
 736         case CHIP_CEDAR:
 737                 return 32;
 738         default:
 739                 return 64;
 740         }
 741 }
 742
 743 static inline enum radeon_bo_priority
 744 r600_get_sampler_view_priority(struct r600_resource *res)
 745 {
 746         if (res->b.b.target == PIPE_BUFFER)
 747                 return RADEON_PRIO_SAMPLER_BUFFER;
 748
 749         if (res->b.b.nr_samples > 1)
 750                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 751
 752         return RADEON_PRIO_SAMPLER_TEXTURE;
 753 }
 754
 755 #define COMPUTE_DBG(rscreen, fmt, args...) \
 756         do { \
 757                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 758         } while (0);
 759
 760 #define R600_ERR(fmt, args...) \
 761         fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 762
 763 /* For MSAA sample positions. */
 764 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 765         (((s0x) & 0xf) | (((s0y) & 0xf) << 4) |            \
 766         (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |     \
 767         (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |    \
 768          (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
 769
 770 #endif