src/gallium/drivers/radeon/r600_pipe_common.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 /**
  28  * This file contains common screen and context structures and functions
  29  * for r600g and radeonsi.
  30  */
  31
  32 #ifndef R600_PIPE_COMMON_H
  33 #define R600_PIPE_COMMON_H
  34
  35 #include <stdio.h>
  36
  37 #include "radeon/radeon_winsys.h"
  38
  39 #include "util/u_blitter.h"
  40 #include "util/list.h"
  41 #include "util/u_range.h"
  42 #include "util/u_slab.h"
  43 #include "util/u_suballoc.h"
  44 #include "util/u_transfer.h"
  45
  46 #define ATI_VENDOR_ID 0x1002
  47
  48 #define R600_RESOURCE_FLAG_TRANSFER             (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  49 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  50 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  51
  52 #define R600_CONTEXT_STREAMOUT_FLUSH            (1u << 0)
  53 /* Pipeline & streamout query controls. */
  54 #define R600_CONTEXT_START_PIPELINE_STATS       (1u << 1)
  55 #define R600_CONTEXT_STOP_PIPELINE_STATS        (1u << 2)
  56 #define R600_CONTEXT_PRIVATE_FLAG               (1u << 3)
  57
  58 /* special primitive types */
  59 #define R600_PRIM_RECTANGLE_LIST        PIPE_PRIM_MAX
  60
  61 /* Debug flags. */
  62 /* logging */
  63 #define DBG_TEX                 (1 << 0)
  64 /* gap - reuse */
  65 #define DBG_COMPUTE             (1 << 2)
  66 #define DBG_VM                  (1 << 3)
  67 /* gap - reuse */
  68 /* shader logging */
  69 #define DBG_FS                  (1 << 5)
  70 #define DBG_VS                  (1 << 6)
  71 #define DBG_GS                  (1 << 7)
  72 #define DBG_PS                  (1 << 8)
  73 #define DBG_CS                  (1 << 9)
  74 #define DBG_TCS                 (1 << 10)
  75 #define DBG_TES                 (1 << 11)
  76 #define DBG_NO_IR               (1 << 12)
  77 #define DBG_NO_TGSI             (1 << 13)
  78 #define DBG_NO_ASM              (1 << 14)
  79 #define DBG_PREOPT_IR           (1 << 15)
  80 /* gaps */
  81 #define DBG_TEST_DMA            (1 << 20)
  82 /* Bits 21-31 are reserved for the r600g driver. */
  83 /* features */
  84 #define DBG_NO_ASYNC_DMA        (1llu << 32)
  85 #define DBG_NO_HYPERZ           (1llu << 33)
  86 #define DBG_NO_DISCARD_RANGE    (1llu << 34)
  87 #define DBG_NO_2D_TILING        (1llu << 35)
  88 #define DBG_NO_TILING           (1llu << 36)
  89 #define DBG_SWITCH_ON_EOP       (1llu << 37)
  90 #define DBG_FORCE_DMA           (1llu << 38)
  91 #define DBG_PRECOMPILE          (1llu << 39)
  92 #define DBG_INFO                (1llu << 40)
  93 #define DBG_NO_WC               (1llu << 41)
  94 #define DBG_CHECK_VM            (1llu << 42)
  95 #define DBG_NO_DCC              (1llu << 43)
  96 #define DBG_NO_DCC_CLEAR        (1llu << 44)
  97 #define DBG_NO_RB_PLUS          (1llu << 45)
  98 #define DBG_SI_SCHED            (1llu << 46)
  99 #define DBG_MONOLITHIC_SHADERS  (1llu << 47)
 100 #define DBG_NO_CE               (1llu << 48)
 101
 102 #define R600_MAP_BUFFER_ALIGNMENT 64
 103 #define R600_MAX_VIEWPORTS        16
 104
 105 enum r600_coherency {
 106         R600_COHERENCY_NONE, /* no cache flushes needed */
 107         R600_COHERENCY_SHADER,
 108         R600_COHERENCY_CB_META,
 109 };
 110
 111 #ifdef PIPE_ARCH_BIG_ENDIAN
 112 #define R600_BIG_ENDIAN 1
 113 #else
 114 #define R600_BIG_ENDIAN 0
 115 #endif
 116
 117 struct r600_common_context;
 118 struct r600_perfcounters;
 119 struct tgsi_shader_info;
 120
 121 struct radeon_shader_reloc {
 122         char name[32];
 123         uint64_t offset;
 124 };
 125
 126 struct radeon_shader_binary {
 127         /** Shader code */
 128         unsigned char *code;
 129         unsigned code_size;
 130
 131         /** Config/Context register state that accompanies this shader.
 132          * This is a stream of dword pairs.  First dword contains the
 133          * register address, the second dword contains the value.*/
 134         unsigned char *config;
 135         unsigned config_size;
 136
 137         /** The number of bytes of config information for each global symbol.
 138          */
 139         unsigned config_size_per_symbol;
 140
 141         /** Constant data accessed by the shader.  This will be uploaded
 142          * into a constant buffer. */
 143         unsigned char *rodata;
 144         unsigned rodata_size;
 145
 146         /** List of symbol offsets for the shader */
 147         uint64_t *global_symbol_offsets;
 148         unsigned global_symbol_count;
 149
 150         struct radeon_shader_reloc *relocs;
 151         unsigned reloc_count;
 152
 153         /** Disassembled shader in a string. */
 154         char *disasm_string;
 155 };
 156
 157 void radeon_shader_binary_init(struct radeon_shader_binary *b);
 158 void radeon_shader_binary_clean(struct radeon_shader_binary *b);
 159
 160 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
 161  * at the moment.
 162  */
 163 struct r600_resource {
 164         struct u_resource               b;
 165
 166         /* Winsys objects. */
 167         struct pb_buffer                *buf;
 168         uint64_t                        gpu_address;
 169
 170         /* Resource state. */
 171         enum radeon_bo_domain           domains;
 172
 173         /* The buffer range which is initialized (with a write transfer,
 174          * streamout, DMA, or as a random access target). The rest of
 175          * the buffer is considered invalid and can be mapped unsynchronized.
 176          *
 177          * This allows unsychronized mapping of a buffer range which hasn't
 178          * been used yet. It's for applications which forget to use
 179          * the unsynchronized map flag and expect the driver to figure it out.
 180          */
 181         struct util_range               valid_buffer_range;
 182
 183         /* For buffers only. This indicates that a write operation has been
 184          * performed by TC L2, but the cache hasn't been flushed.
 185          * Any hw block which doesn't use or bypasses TC L2 should check this
 186          * flag and flush the cache before using the buffer.
 187          *
 188          * For example, TC L2 must be flushed if a buffer which has been
 189          * modified by a shader store instruction is about to be used as
 190          * an index buffer. The reason is that VGT DMA index fetching doesn't
 191          * use TC L2.
 192          */
 193         bool                            TC_L2_dirty;
 194
 195         /* Whether the resource has been exported via resource_get_handle. */
 196         bool                            is_shared;
 197         unsigned                        external_usage; /* PIPE_HANDLE_USAGE_* */
 198 };
 199
 200 struct r600_transfer {
 201         struct pipe_transfer            transfer;
 202         struct r600_resource            *staging;
 203         unsigned                        offset;
 204 };
 205
 206 struct r600_fmask_info {
 207         uint64_t offset;
 208         uint64_t size;
 209         unsigned alignment;
 210         unsigned pitch_in_pixels;
 211         unsigned bank_height;
 212         unsigned slice_tile_max;
 213         unsigned tile_mode_index;
 214 };
 215
 216 struct r600_cmask_info {
 217         uint64_t offset;
 218         uint64_t size;
 219         unsigned alignment;
 220         unsigned pitch;
 221         unsigned height;
 222         unsigned xalign;
 223         unsigned yalign;
 224         unsigned slice_tile_max;
 225         unsigned base_address_reg;
 226 };
 227
 228 struct r600_htile_info {
 229         unsigned pitch;
 230         unsigned height;
 231         unsigned xalign;
 232         unsigned yalign;
 233 };
 234
 235 struct r600_texture {
 236         struct r600_resource            resource;
 237
 238         uint64_t                        size;
 239         unsigned                        num_level0_transfers;
 240         bool                            is_depth;
 241         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
 242         unsigned                        stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
 243         struct r600_texture             *flushed_depth_texture;
 244         boolean                         is_flushing_texture;
 245         struct radeon_surf              surface;
 246
 247         /* Colorbuffer compression and fast clear. */
 248         struct r600_fmask_info          fmask;
 249         struct r600_cmask_info          cmask;
 250         struct r600_resource            *cmask_buffer;
 251         uint64_t                        dcc_offset; /* 0 = disabled */
 252         unsigned                        cb_color_info; /* fast clear enable bit */
 253         unsigned                        color_clear_value[2];
 254
 255         /* Depth buffer compression and fast clear. */
 256         struct r600_htile_info          htile;
 257         struct r600_resource            *htile_buffer;
 258         bool                            depth_cleared; /* if it was cleared at least once */
 259         float                           depth_clear_value;
 260         bool                            stencil_cleared; /* if it was cleared at least once */
 261         uint8_t                         stencil_clear_value;
 262
 263         bool                            non_disp_tiling; /* R600-Cayman only */
 264
 265         /* Counter that should be non-zero if the texture is bound to a
 266          * framebuffer. Implemented in radeonsi only.
 267          */
 268         uint32_t                        framebuffers_bound;
 269 };
 270
 271 struct r600_surface {
 272         struct pipe_surface             base;
 273         const struct radeon_surf_level  *level_info;
 274
 275         bool color_initialized;
 276         bool depth_initialized;
 277
 278         /* Misc. color flags. */
 279         bool alphatest_bypass;
 280         bool export_16bpc;
 281         bool color_is_int8;
 282
 283         /* Color registers. */
 284         unsigned cb_color_info;
 285         unsigned cb_color_base;
 286         unsigned cb_color_view;
 287         unsigned cb_color_size;         /* R600 only */
 288         unsigned cb_color_dim;          /* EG only */
 289         unsigned cb_color_pitch;        /* EG and later */
 290         unsigned cb_color_slice;        /* EG and later */
 291         unsigned cb_dcc_base;           /* VI and later */
 292         unsigned cb_color_attrib;       /* EG and later */
 293         unsigned cb_dcc_control;        /* VI and later */
 294         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
 295         unsigned cb_color_fmask_slice;  /* EG and later */
 296         unsigned cb_color_cmask;        /* CB_COLORn_TILE (r600 only) */
 297         unsigned cb_color_mask;         /* R600 only */
 298         unsigned spi_shader_col_format;         /* SI+, no blending, no alpha-to-coverage. */
 299         unsigned spi_shader_col_format_alpha;   /* SI+, alpha-to-coverage */
 300         unsigned spi_shader_col_format_blend;   /* SI+, blending without alpha. */
 301         unsigned spi_shader_col_format_blend_alpha; /* SI+, blending with alpha. */
 302         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 303         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 304
 305         /* DB registers. */
 306         unsigned db_depth_info;         /* R600 only, then SI and later */
 307         unsigned db_z_info;             /* EG and later */
 308         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
 309         unsigned db_depth_view;
 310         unsigned db_depth_size;
 311         unsigned db_depth_slice;        /* EG and later */
 312         unsigned db_stencil_base;       /* EG and later */
 313         unsigned db_stencil_info;       /* EG and later */
 314         unsigned db_prefetch_limit;     /* R600 only */
 315         unsigned db_htile_surface;
 316         unsigned db_htile_data_base;
 317         unsigned db_preload_control;    /* EG and later */
 318         unsigned pa_su_poly_offset_db_fmt_cntl;
 319 };
 320
 321 struct r600_common_screen {
 322         struct pipe_screen              b;
 323         struct radeon_winsys            *ws;
 324         enum radeon_family              family;
 325         enum chip_class                 chip_class;
 326         struct radeon_info              info;
 327         uint64_t                        debug_flags;
 328         bool                            has_cp_dma;
 329         bool                            has_streamout;
 330
 331         /* Texture filter settings. */
 332         int                             force_aniso; /* -1 = disabled */
 333
 334         /* Auxiliary context. Mainly used to initialize resources.
 335          * It must be locked prior to using and flushed before unlocking. */
 336         struct pipe_context             *aux_context;
 337         pipe_mutex                      aux_context_lock;
 338
 339         /* This must be in the screen, because UE4 uses one context for
 340          * compilation and another one for rendering.
 341          */
 342         unsigned                        num_compilations;
 343         /* Along with ST_DEBUG=precompile, this should show if applications
 344          * are loading shaders on demand. This is a monotonic counter.
 345          */
 346         unsigned                        num_shaders_created;
 347
 348         /* GPU load thread. */
 349         pipe_mutex                      gpu_load_mutex;
 350         pipe_thread                     gpu_load_thread;
 351         unsigned                        gpu_load_counter_busy;
 352         unsigned                        gpu_load_counter_idle;
 353         volatile unsigned               gpu_load_stop_thread; /* bool */
 354
 355         char                            renderer_string[64];
 356
 357         /* Performance counters. */
 358         struct r600_perfcounters        *perfcounters;
 359
 360         /* If pipe_screen wants to re-emit the framebuffer state of all
 361          * contexts, it should atomically increment this. Each context will
 362          * compare this with its own last known value of the counter before
 363          * drawing and re-emit the framebuffer state accordingly.
 364          */
 365         unsigned                        dirty_fb_counter;
 366
 367         /* Atomically increment this counter when an existing texture's
 368          * metadata is enabled or disabled in a way that requires changing
 369          * contexts' compressed texture binding masks.
 370          */
 371         unsigned                        compressed_colortex_counter;
 372
 373         /* Atomically increment this counter when an existing texture's
 374          * backing buffer or tile mode parameters have changed that requires
 375          * recomputation of shader descriptors.
 376          */
 377         unsigned                        dirty_tex_descriptor_counter;
 378
 379         void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
 380                                       struct r600_texture *rtex,
 381                                       struct radeon_bo_metadata *md);
 382 };
 383
 384 /* This encapsulates a state or an operation which can emitted into the GPU
 385  * command stream. */
 386 struct r600_atom {
 387         void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
 388         unsigned                num_dw;
 389         unsigned short          id;
 390 };
 391
 392 struct r600_so_target {
 393         struct pipe_stream_output_target b;
 394
 395         /* The buffer where BUFFER_FILLED_SIZE is stored. */
 396         struct r600_resource    *buf_filled_size;
 397         unsigned                buf_filled_size_offset;
 398         bool                    buf_filled_size_valid;
 399
 400         unsigned                stride_in_dw;
 401 };
 402
 403 struct r600_streamout {
 404         struct r600_atom                begin_atom;
 405         bool                            begin_emitted;
 406         unsigned                        num_dw_for_end;
 407
 408         unsigned                        enabled_mask;
 409         unsigned                        num_targets;
 410         struct r600_so_target           *targets[PIPE_MAX_SO_BUFFERS];
 411
 412         unsigned                        append_bitmask;
 413         bool                            suspended;
 414
 415         /* External state which comes from the vertex shader,
 416          * it must be set explicitly when binding a shader. */
 417         unsigned                        *stride_in_dw;
 418         unsigned                        enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
 419
 420         /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
 421         unsigned                        hw_enabled_mask;
 422
 423         /* The state of VGT_STRMOUT_(CONFIG|EN). */
 424         struct r600_atom                enable_atom;
 425         bool                            streamout_enabled;
 426         bool                            prims_gen_query_enabled;
 427         int                             num_prims_gen_queries;
 428 };
 429
 430 struct r600_signed_scissor {
 431         int minx;
 432         int miny;
 433         int maxx;
 434         int maxy;
 435 };
 436
 437 struct r600_scissors {
 438         struct r600_atom                atom;
 439         unsigned                        dirty_mask;
 440         struct pipe_scissor_state       states[R600_MAX_VIEWPORTS];
 441 };
 442
 443 struct r600_viewports {
 444         struct r600_atom                atom;
 445         unsigned                        dirty_mask;
 446         struct pipe_viewport_state      states[R600_MAX_VIEWPORTS];
 447         struct r600_signed_scissor      as_scissor[R600_MAX_VIEWPORTS];
 448 };
 449
 450 struct r600_ring {
 451         struct radeon_winsys_cs         *cs;
 452         void (*flush)(void *ctx, unsigned flags,
 453                       struct pipe_fence_handle **fence);
 454 };
 455
 456 struct r600_common_context {
 457         struct pipe_context b; /* base class */
 458
 459         struct r600_common_screen       *screen;
 460         struct radeon_winsys            *ws;
 461         struct radeon_winsys_ctx        *ctx;
 462         enum radeon_family              family;
 463         enum chip_class                 chip_class;
 464         struct r600_ring                gfx;
 465         struct r600_ring                dma;
 466         struct pipe_fence_handle        *last_sdma_fence;
 467         unsigned                        initial_gfx_cs_size;
 468         unsigned                        gpu_reset_counter;
 469         unsigned                        last_dirty_fb_counter;
 470         unsigned                        last_compressed_colortex_counter;
 471         unsigned                        last_dirty_tex_descriptor_counter;
 472
 473         struct u_upload_mgr             *uploader;
 474         struct u_suballocator           *allocator_so_filled_size;
 475         struct util_slab_mempool        pool_transfers;
 476
 477         /* Current unaccounted memory usage. */
 478         uint64_t                        vram;
 479         uint64_t                        gtt;
 480
 481         /* States. */
 482         struct r600_streamout           streamout;
 483         struct r600_scissors            scissors;
 484         struct r600_viewports           viewports;
 485         bool                            scissor_enabled;
 486         bool                            vs_writes_viewport_index;
 487         bool                            vs_disables_clipping_viewport;
 488
 489         /* Additional context states. */
 490         unsigned flags; /* flush flags */
 491
 492         /* Queries. */
 493         /* Maintain the list of active queries for pausing between IBs. */
 494         int                             num_occlusion_queries;
 495         int                             num_perfect_occlusion_queries;
 496         struct list_head                active_queries;
 497         unsigned                        num_cs_dw_queries_suspend;
 498         /* Additional hardware info. */
 499         unsigned                        backend_mask;
 500         unsigned                        max_db; /* for OQ */
 501         /* Misc stats. */
 502         unsigned                        num_draw_calls;
 503         unsigned                        num_dma_calls;
 504
 505         /* Render condition. */
 506         struct r600_atom                render_cond_atom;
 507         struct pipe_query               *render_cond;
 508         unsigned                        render_cond_mode;
 509         boolean                         render_cond_invert;
 510         bool                            render_cond_force_off; /* for u_blitter */
 511
 512         /* MSAA sample locations.
 513          * The first index is the sample index.
 514          * The second index is the coordinate: X, Y. */
 515         float                           sample_locations_1x[1][2];
 516         float                           sample_locations_2x[2][2];
 517         float                           sample_locations_4x[4][2];
 518         float                           sample_locations_8x[8][2];
 519         float                           sample_locations_16x[16][2];
 520
 521         /* The list of all texture buffer objects in this context.
 522          * This list is walked when a buffer is invalidated/reallocated and
 523          * the GPU addresses are updated. */
 524         struct list_head                texture_buffers;
 525
 526         struct pipe_debug_callback      debug;
 527
 528         /* Copy one resource to another using async DMA. */
 529         void (*dma_copy)(struct pipe_context *ctx,
 530                          struct pipe_resource *dst,
 531                          unsigned dst_level,
 532                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
 533                          struct pipe_resource *src,
 534                          unsigned src_level,
 535                          const struct pipe_box *src_box);
 536
 537         void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
 538                              uint64_t offset, uint64_t size, unsigned value,
 539                              enum r600_coherency coher);
 540
 541         void (*blit_decompress_depth)(struct pipe_context *ctx,
 542                                       struct r600_texture *texture,
 543                                       struct r600_texture *staging,
 544                                       unsigned first_level, unsigned last_level,
 545                                       unsigned first_layer, unsigned last_layer,
 546                                       unsigned first_sample, unsigned last_sample);
 547
 548         void (*decompress_dcc)(struct pipe_context *ctx,
 549                                struct r600_texture *rtex);
 550
 551         /* Reallocate the buffer and update all resource bindings where
 552          * the buffer is bound, including all resource descriptors. */
 553         void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
 554
 555         /* Enable or disable occlusion queries. */
 556         void (*set_occlusion_query_state)(struct pipe_context *ctx, bool enable);
 557
 558         /* This ensures there is enough space in the command stream. */
 559         void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
 560                                   bool include_draw_vbo);
 561
 562         void (*set_atom_dirty)(struct r600_common_context *ctx,
 563                                struct r600_atom *atom, bool dirty);
 564 };
 565
 566 /* r600_buffer.c */
 567 boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
 568                                         struct pb_buffer *buf,
 569                                         enum radeon_bo_usage usage);
 570 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
 571                                       struct r600_resource *resource,
 572                                       unsigned usage);
 573 bool r600_init_resource(struct r600_common_screen *rscreen,
 574                         struct r600_resource *res,
 575                         uint64_t size, unsigned alignment);
 576 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 577                                          const struct pipe_resource *templ,
 578                                          unsigned alignment);
 579 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
 580                                                   unsigned bind,
 581                                                   unsigned usage,
 582                                                   unsigned size,
 583                                                   unsigned alignment);
 584 struct pipe_resource *
 585 r600_buffer_from_user_memory(struct pipe_screen *screen,
 586                              const struct pipe_resource *templ,
 587                              void *user_memory);
 588 void
 589 r600_invalidate_resource(struct pipe_context *ctx,
 590                          struct pipe_resource *resource);
 591
 592 /* r600_common_pipe.c */
 593 void r600_draw_rectangle(struct blitter_context *blitter,
 594                          int x1, int y1, int x2, int y2, float depth,
 595                          enum blitter_attrib_type type,
 596                          const union pipe_color_union *attrib);
 597 bool r600_common_screen_init(struct r600_common_screen *rscreen,
 598                              struct radeon_winsys *ws);
 599 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
 600 void r600_preflush_suspend_features(struct r600_common_context *ctx);
 601 void r600_postflush_resume_features(struct r600_common_context *ctx);
 602 bool r600_common_context_init(struct r600_common_context *rctx,
 603                               struct r600_common_screen *rscreen);
 604 void r600_common_context_cleanup(struct r600_common_context *rctx);
 605 void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
 606 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 607                           unsigned processor);
 608 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
 609                               uint64_t offset, uint64_t size, unsigned value,
 610                               enum r600_coherency coher);
 611 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
 612                                                   const struct pipe_resource *templ);
 613 const char *r600_get_llvm_processor_name(enum radeon_family family);
 614 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
 615                          struct r600_resource *dst, struct r600_resource *src);
 616 void r600_dma_emit_wait_idle(struct r600_common_context *rctx);
 617
 618 /* r600_gpu_load.c */
 619 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
 620 uint64_t r600_gpu_load_begin(struct r600_common_screen *rscreen);
 621 unsigned r600_gpu_load_end(struct r600_common_screen *rscreen, uint64_t begin);
 622
 623 /* r600_perfcounters.c */
 624 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
 625
 626 /* r600_query.c */
 627 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
 628 void r600_query_init(struct r600_common_context *rctx);
 629 void r600_suspend_queries(struct r600_common_context *ctx);
 630 void r600_resume_queries(struct r600_common_context *ctx);
 631 void r600_query_init_backend_mask(struct r600_common_context *ctx);
 632
 633 /* r600_streamout.c */
 634 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
 635 void r600_set_streamout_targets(struct pipe_context *ctx,
 636                                 unsigned num_targets,
 637                                 struct pipe_stream_output_target **targets,
 638                                 const unsigned *offset);
 639 void r600_emit_streamout_end(struct r600_common_context *rctx);
 640 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 641                                              unsigned type, int diff);
 642 void r600_streamout_init(struct r600_common_context *rctx);
 643
 644 /* r600_test_dma.c */
 645 void r600_test_dma(struct r600_common_screen *rscreen);
 646
 647 /* r600_texture.c */
 648 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
 649                                 struct r600_texture *rdst,
 650                                 unsigned dst_level, unsigned dstx,
 651                                 unsigned dsty, unsigned dstz,
 652                                 struct r600_texture *rsrc,
 653                                 unsigned src_level,
 654                                 const struct pipe_box *src_box);
 655 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 656                                  struct r600_texture *rtex,
 657                                  unsigned nr_samples,
 658                                  struct r600_fmask_info *out);
 659 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
 660                                  struct r600_texture *rtex,
 661                                  struct r600_cmask_info *out);
 662 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 663                                      struct pipe_resource *texture,
 664                                      struct r600_texture **staging);
 665 void r600_print_texture_info(struct r600_texture *rtex, FILE *f);
 666 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 667                                         const struct pipe_resource *templ);
 668 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
 669                                                 struct pipe_resource *texture,
 670                                                 const struct pipe_surface *templ,
 671                                                 unsigned width, unsigned height);
 672 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
 673 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
 674                                    struct pipe_framebuffer_state *fb,
 675                                    struct r600_atom *fb_state,
 676                                    unsigned *buffers, unsigned *dirty_cbufs,
 677                                    const union pipe_color_union *color);
 678 void r600_texture_disable_dcc(struct r600_common_screen *rscreen,
 679                               struct r600_texture *rtex);
 680 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
 681 void r600_init_context_texture_functions(struct r600_common_context *rctx);
 682
 683 /* r600_viewport.c */
 684 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
 685                                             struct pipe_scissor_state *scissor);
 686 void r600_set_scissor_enable(struct r600_common_context *rctx, bool enable);
 687 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
 688                                           struct tgsi_shader_info *info);
 689 void r600_init_viewport_functions(struct r600_common_context *rctx);
 690
 691 /* cayman_msaa.c */
 692 extern const uint32_t eg_sample_locs_2x[4];
 693 extern const unsigned eg_max_dist_2x;
 694 extern const uint32_t eg_sample_locs_4x[4];
 695 extern const unsigned eg_max_dist_4x;
 696 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
 697                                 unsigned sample_index, float *out_value);
 698 void cayman_init_msaa(struct pipe_context *ctx);
 699 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 700 void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
 701                              int ps_iter_samples, int overrast_samples);
 702
 703
 704 /* Inline helpers. */
 705
 706 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
 707 {
 708         return (struct r600_resource*)r;
 709 }
 710
 711 static inline void
 712 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
 713 {
 714         pipe_resource_reference((struct pipe_resource **)ptr,
 715                                 (struct pipe_resource *)res);
 716 }
 717
 718 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
 719 {
 720         return rctx->streamout.streamout_enabled ||
 721                rctx->streamout.prims_gen_query_enabled;
 722 }
 723
 724 #define     SQ_TEX_XY_FILTER_POINT                         0x00
 725 #define     SQ_TEX_XY_FILTER_BILINEAR                      0x01
 726 #define     SQ_TEX_XY_FILTER_ANISO_POINT                   0x02
 727 #define     SQ_TEX_XY_FILTER_ANISO_BILINEAR                0x03
 728
 729 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
 730 {
 731         if (filter == PIPE_TEX_FILTER_LINEAR)
 732                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
 733                                      : SQ_TEX_XY_FILTER_BILINEAR;
 734         else
 735                 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
 736                                      : SQ_TEX_XY_FILTER_POINT;
 737 }
 738
 739 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 740 {
 741         if (filter < 2)
 742                 return 0;
 743         if (filter < 4)
 744                 return 1;
 745         if (filter < 8)
 746                 return 2;
 747         if (filter < 16)
 748                 return 3;
 749         return 4;
 750 }
 751
 752 static inline unsigned r600_wavefront_size(enum radeon_family family)
 753 {
 754         switch (family) {
 755         case CHIP_RV610:
 756         case CHIP_RS780:
 757         case CHIP_RV620:
 758         case CHIP_RS880:
 759                 return 16;
 760         case CHIP_RV630:
 761         case CHIP_RV635:
 762         case CHIP_RV730:
 763         case CHIP_RV710:
 764         case CHIP_PALM:
 765         case CHIP_CEDAR:
 766                 return 32;
 767         default:
 768                 return 64;
 769         }
 770 }
 771
 772 static inline enum radeon_bo_priority
 773 r600_get_sampler_view_priority(struct r600_resource *res)
 774 {
 775         if (res->b.b.target == PIPE_BUFFER)
 776                 return RADEON_PRIO_SAMPLER_BUFFER;
 777
 778         if (res->b.b.nr_samples > 1)
 779                 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
 780
 781         return RADEON_PRIO_SAMPLER_TEXTURE;
 782 }
 783
 784 #define COMPUTE_DBG(rscreen, fmt, args...) \
 785         do { \
 786                 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
 787         } while (0);
 788
 789 #define R600_ERR(fmt, args...) \
 790         fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
 791
 792 /* For MSAA sample positions. */
 793 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
 794         (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) |                  \
 795         (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) |         \
 796         (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) |        \
 797          (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
 798
 799 #endif