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gallium/radeon: switch the buffer-wait-time query to microseconds
[mesa.git] / src / gallium / drivers / radeon / r600_query.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014 Marek Olšák <marek.olsak@amd.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "r600_cs.h"
26 #include "util/u_memory.h"
27
28
29 struct r600_query_buffer {
30 /* The buffer where query results are stored. */
31 struct r600_resource *buf;
32 /* Offset of the next free result after current query data */
33 unsigned results_end;
34 /* If a query buffer is full, a new buffer is created and the old one
35 * is put in here. When we calculate the result, we sum up the samples
36 * from all buffers. */
37 struct r600_query_buffer *previous;
38 };
39
40 struct r600_query {
41 /* The query buffer and how many results are in it. */
42 struct r600_query_buffer buffer;
43 /* The type of query */
44 unsigned type;
45 /* Size of the result in memory for both begin_query and end_query,
46 * this can be one or two numbers, or it could even be a size of a structure. */
47 unsigned result_size;
48 /* The number of dwords for begin_query or end_query. */
49 unsigned num_cs_dw;
50 /* linked list of queries */
51 struct list_head list;
52 /* for custom non-GPU queries */
53 uint64_t begin_result;
54 uint64_t end_result;
55 /* Fence for GPU_FINISHED. */
56 struct pipe_fence_handle *fence;
57 /* For transform feedback: which stream the query is for */
58 unsigned stream;
59 };
60
61
62 static bool r600_is_timer_query(unsigned type)
63 {
64 return type == PIPE_QUERY_TIME_ELAPSED ||
65 type == PIPE_QUERY_TIMESTAMP;
66 }
67
68 static bool r600_query_needs_begin(unsigned type)
69 {
70 return type != PIPE_QUERY_GPU_FINISHED &&
71 type != PIPE_QUERY_TIMESTAMP;
72 }
73
74 static struct r600_resource *r600_new_query_buffer(struct r600_common_context *ctx, unsigned type)
75 {
76 unsigned j, i, num_results, buf_size = 4096;
77 uint32_t *results;
78
79 /* Non-GPU queries. */
80 switch (type) {
81 case PIPE_QUERY_TIMESTAMP_DISJOINT:
82 case PIPE_QUERY_GPU_FINISHED:
83 case R600_QUERY_DRAW_CALLS:
84 case R600_QUERY_REQUESTED_VRAM:
85 case R600_QUERY_REQUESTED_GTT:
86 case R600_QUERY_BUFFER_WAIT_TIME:
87 case R600_QUERY_NUM_CS_FLUSHES:
88 case R600_QUERY_NUM_BYTES_MOVED:
89 case R600_QUERY_VRAM_USAGE:
90 case R600_QUERY_GTT_USAGE:
91 case R600_QUERY_GPU_TEMPERATURE:
92 case R600_QUERY_CURRENT_GPU_SCLK:
93 case R600_QUERY_CURRENT_GPU_MCLK:
94 case R600_QUERY_GPU_LOAD:
95 return NULL;
96 }
97
98 /* Queries are normally read by the CPU after
99 * being written by the gpu, hence staging is probably a good
100 * usage pattern.
101 */
102 struct r600_resource *buf = (struct r600_resource*)
103 pipe_buffer_create(ctx->b.screen, PIPE_BIND_CUSTOM,
104 PIPE_USAGE_STAGING, buf_size);
105
106 switch (type) {
107 case PIPE_QUERY_OCCLUSION_COUNTER:
108 case PIPE_QUERY_OCCLUSION_PREDICATE:
109 results = r600_buffer_map_sync_with_rings(ctx, buf, PIPE_TRANSFER_WRITE);
110 memset(results, 0, buf_size);
111
112 /* Set top bits for unused backends. */
113 num_results = buf_size / (16 * ctx->max_db);
114 for (j = 0; j < num_results; j++) {
115 for (i = 0; i < ctx->max_db; i++) {
116 if (!(ctx->backend_mask & (1<<i))) {
117 results[(i * 4)+1] = 0x80000000;
118 results[(i * 4)+3] = 0x80000000;
119 }
120 }
121 results += 4 * ctx->max_db;
122 }
123 break;
124 case PIPE_QUERY_TIME_ELAPSED:
125 case PIPE_QUERY_TIMESTAMP:
126 break;
127 case PIPE_QUERY_PRIMITIVES_EMITTED:
128 case PIPE_QUERY_PRIMITIVES_GENERATED:
129 case PIPE_QUERY_SO_STATISTICS:
130 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
131 case PIPE_QUERY_PIPELINE_STATISTICS:
132 results = r600_buffer_map_sync_with_rings(ctx, buf, PIPE_TRANSFER_WRITE);
133 memset(results, 0, buf_size);
134 break;
135 default:
136 assert(0);
137 }
138 return buf;
139 }
140
141 static void r600_update_occlusion_query_state(struct r600_common_context *rctx,
142 unsigned type, int diff)
143 {
144 if (type == PIPE_QUERY_OCCLUSION_COUNTER ||
145 type == PIPE_QUERY_OCCLUSION_PREDICATE) {
146 bool old_enable = rctx->num_occlusion_queries != 0;
147 bool enable;
148
149 rctx->num_occlusion_queries += diff;
150 assert(rctx->num_occlusion_queries >= 0);
151
152 enable = rctx->num_occlusion_queries != 0;
153
154 if (enable != old_enable) {
155 rctx->set_occlusion_query_state(&rctx->b, enable);
156 }
157 }
158 }
159
160 static unsigned event_type_for_stream(struct r600_query *query)
161 {
162 switch (query->stream) {
163 default:
164 case 0: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS;
165 case 1: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS1;
166 case 2: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS2;
167 case 3: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS3;
168 }
169 }
170
171 static void r600_emit_query_begin(struct r600_common_context *ctx, struct r600_query *query)
172 {
173 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
174 uint64_t va;
175
176 r600_update_occlusion_query_state(ctx, query->type, 1);
177 r600_update_prims_generated_query_state(ctx, query->type, 1);
178 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw * 2, TRUE);
179
180 /* Get a new query buffer if needed. */
181 if (query->buffer.results_end + query->result_size > query->buffer.buf->b.b.width0) {
182 struct r600_query_buffer *qbuf = MALLOC_STRUCT(r600_query_buffer);
183 *qbuf = query->buffer;
184 query->buffer.buf = r600_new_query_buffer(ctx, query->type);
185 query->buffer.results_end = 0;
186 query->buffer.previous = qbuf;
187 }
188
189 /* emit begin query */
190 va = query->buffer.buf->gpu_address + query->buffer.results_end;
191
192 switch (query->type) {
193 case PIPE_QUERY_OCCLUSION_COUNTER:
194 case PIPE_QUERY_OCCLUSION_PREDICATE:
195 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
196 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
197 radeon_emit(cs, va);
198 radeon_emit(cs, (va >> 32UL) & 0xFF);
199 break;
200 case PIPE_QUERY_PRIMITIVES_EMITTED:
201 case PIPE_QUERY_PRIMITIVES_GENERATED:
202 case PIPE_QUERY_SO_STATISTICS:
203 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
204 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
205 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | EVENT_INDEX(3));
206 radeon_emit(cs, va);
207 radeon_emit(cs, (va >> 32UL) & 0xFF);
208 break;
209 case PIPE_QUERY_TIME_ELAPSED:
210 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
211 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
212 radeon_emit(cs, va);
213 radeon_emit(cs, (3 << 29) | ((va >> 32UL) & 0xFF));
214 radeon_emit(cs, 0);
215 radeon_emit(cs, 0);
216 break;
217 case PIPE_QUERY_PIPELINE_STATISTICS:
218 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
219 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
220 radeon_emit(cs, va);
221 radeon_emit(cs, (va >> 32UL) & 0xFF);
222 break;
223 default:
224 assert(0);
225 }
226 r600_emit_reloc(ctx, &ctx->rings.gfx, query->buffer.buf, RADEON_USAGE_WRITE,
227 RADEON_PRIO_MIN);
228
229 if (r600_is_timer_query(query->type))
230 ctx->num_cs_dw_timer_queries_suspend += query->num_cs_dw;
231 else
232 ctx->num_cs_dw_nontimer_queries_suspend += query->num_cs_dw;
233 }
234
235 static void r600_emit_query_end(struct r600_common_context *ctx, struct r600_query *query)
236 {
237 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
238 uint64_t va;
239
240 /* The queries which need begin already called this in begin_query. */
241 if (!r600_query_needs_begin(query->type)) {
242 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw, FALSE);
243 }
244
245 va = query->buffer.buf->gpu_address;
246
247 /* emit end query */
248 switch (query->type) {
249 case PIPE_QUERY_OCCLUSION_COUNTER:
250 case PIPE_QUERY_OCCLUSION_PREDICATE:
251 va += query->buffer.results_end + 8;
252 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
253 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
254 radeon_emit(cs, va);
255 radeon_emit(cs, (va >> 32UL) & 0xFF);
256 break;
257 case PIPE_QUERY_PRIMITIVES_EMITTED:
258 case PIPE_QUERY_PRIMITIVES_GENERATED:
259 case PIPE_QUERY_SO_STATISTICS:
260 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
261 va += query->buffer.results_end + query->result_size/2;
262 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
263 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | EVENT_INDEX(3));
264 radeon_emit(cs, va);
265 radeon_emit(cs, (va >> 32UL) & 0xFF);
266 break;
267 case PIPE_QUERY_TIME_ELAPSED:
268 va += query->buffer.results_end + query->result_size/2;
269 /* fall through */
270 case PIPE_QUERY_TIMESTAMP:
271 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
272 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
273 radeon_emit(cs, va);
274 radeon_emit(cs, (3 << 29) | ((va >> 32UL) & 0xFF));
275 radeon_emit(cs, 0);
276 radeon_emit(cs, 0);
277 break;
278 case PIPE_QUERY_PIPELINE_STATISTICS:
279 va += query->buffer.results_end + query->result_size/2;
280 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
281 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
282 radeon_emit(cs, va);
283 radeon_emit(cs, (va >> 32UL) & 0xFF);
284 break;
285 default:
286 assert(0);
287 }
288 r600_emit_reloc(ctx, &ctx->rings.gfx, query->buffer.buf, RADEON_USAGE_WRITE,
289 RADEON_PRIO_MIN);
290
291 query->buffer.results_end += query->result_size;
292
293 if (r600_query_needs_begin(query->type)) {
294 if (r600_is_timer_query(query->type))
295 ctx->num_cs_dw_timer_queries_suspend -= query->num_cs_dw;
296 else
297 ctx->num_cs_dw_nontimer_queries_suspend -= query->num_cs_dw;
298 }
299
300 r600_update_occlusion_query_state(ctx, query->type, -1);
301 r600_update_prims_generated_query_state(ctx, query->type, -1);
302 }
303
304 static void r600_emit_query_predication(struct r600_common_context *ctx, struct r600_query *query,
305 int operation, bool flag_wait)
306 {
307 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
308 uint32_t op = PRED_OP(operation);
309
310 /* if true then invert, see GL_ARB_conditional_render_inverted */
311 if (ctx->current_render_cond_cond)
312 op |= PREDICATION_DRAW_NOT_VISIBLE; /* Draw if not visable/overflow */
313 else
314 op |= PREDICATION_DRAW_VISIBLE; /* Draw if visable/overflow */
315
316 if (operation == PREDICATION_OP_CLEAR) {
317 ctx->need_gfx_cs_space(&ctx->b, 3, FALSE);
318
319 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
320 radeon_emit(cs, 0);
321 radeon_emit(cs, PRED_OP(PREDICATION_OP_CLEAR));
322 } else {
323 struct r600_query_buffer *qbuf;
324 unsigned count;
325 /* Find how many results there are. */
326 count = 0;
327 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
328 count += qbuf->results_end / query->result_size;
329 }
330
331 ctx->need_gfx_cs_space(&ctx->b, 5 * count, TRUE);
332
333 op |= flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW;
334
335 /* emit predicate packets for all data blocks */
336 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
337 unsigned results_base = 0;
338 uint64_t va = qbuf->buf->gpu_address;
339
340 while (results_base < qbuf->results_end) {
341 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
342 radeon_emit(cs, (va + results_base) & 0xFFFFFFFFUL);
343 radeon_emit(cs, op | (((va + results_base) >> 32UL) & 0xFF));
344 r600_emit_reloc(ctx, &ctx->rings.gfx, qbuf->buf, RADEON_USAGE_READ,
345 RADEON_PRIO_MIN);
346 results_base += query->result_size;
347
348 /* set CONTINUE bit for all packets except the first */
349 op |= PREDICATION_CONTINUE;
350 }
351 }
352 }
353 }
354
355 static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type, unsigned index)
356 {
357 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
358 struct r600_query *query;
359 bool skip_allocation = false;
360
361 query = CALLOC_STRUCT(r600_query);
362 if (query == NULL)
363 return NULL;
364
365 query->type = query_type;
366
367 switch (query_type) {
368 case PIPE_QUERY_OCCLUSION_COUNTER:
369 case PIPE_QUERY_OCCLUSION_PREDICATE:
370 query->result_size = 16 * rctx->max_db;
371 query->num_cs_dw = 6;
372 break;
373 break;
374 case PIPE_QUERY_TIME_ELAPSED:
375 query->result_size = 16;
376 query->num_cs_dw = 8;
377 break;
378 case PIPE_QUERY_TIMESTAMP:
379 query->result_size = 8;
380 query->num_cs_dw = 8;
381 break;
382 case PIPE_QUERY_PRIMITIVES_EMITTED:
383 case PIPE_QUERY_PRIMITIVES_GENERATED:
384 case PIPE_QUERY_SO_STATISTICS:
385 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
386 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
387 query->result_size = 32;
388 query->num_cs_dw = 6;
389 query->stream = index;
390 break;
391 case PIPE_QUERY_PIPELINE_STATISTICS:
392 /* 11 values on EG, 8 on R600. */
393 query->result_size = (rctx->chip_class >= EVERGREEN ? 11 : 8) * 16;
394 query->num_cs_dw = 6;
395 break;
396 /* Non-GPU queries and queries not requiring a buffer. */
397 case PIPE_QUERY_TIMESTAMP_DISJOINT:
398 case PIPE_QUERY_GPU_FINISHED:
399 case R600_QUERY_DRAW_CALLS:
400 case R600_QUERY_REQUESTED_VRAM:
401 case R600_QUERY_REQUESTED_GTT:
402 case R600_QUERY_BUFFER_WAIT_TIME:
403 case R600_QUERY_NUM_CS_FLUSHES:
404 case R600_QUERY_NUM_BYTES_MOVED:
405 case R600_QUERY_VRAM_USAGE:
406 case R600_QUERY_GTT_USAGE:
407 case R600_QUERY_GPU_TEMPERATURE:
408 case R600_QUERY_CURRENT_GPU_SCLK:
409 case R600_QUERY_CURRENT_GPU_MCLK:
410 case R600_QUERY_GPU_LOAD:
411 skip_allocation = true;
412 break;
413 default:
414 assert(0);
415 FREE(query);
416 return NULL;
417 }
418
419 if (!skip_allocation) {
420 query->buffer.buf = r600_new_query_buffer(rctx, query_type);
421 if (!query->buffer.buf) {
422 FREE(query);
423 return NULL;
424 }
425 }
426 return (struct pipe_query*)query;
427 }
428
429 static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
430 {
431 struct r600_query *rquery = (struct r600_query*)query;
432 struct r600_query_buffer *prev = rquery->buffer.previous;
433
434 /* Release all query buffers. */
435 while (prev) {
436 struct r600_query_buffer *qbuf = prev;
437 prev = prev->previous;
438 pipe_resource_reference((struct pipe_resource**)&qbuf->buf, NULL);
439 FREE(qbuf);
440 }
441
442 pipe_resource_reference((struct pipe_resource**)&rquery->buffer.buf, NULL);
443 FREE(query);
444 }
445
446 static boolean r600_begin_query(struct pipe_context *ctx,
447 struct pipe_query *query)
448 {
449 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
450 struct r600_query *rquery = (struct r600_query *)query;
451 struct r600_query_buffer *prev = rquery->buffer.previous;
452
453 if (!r600_query_needs_begin(rquery->type)) {
454 assert(0);
455 return false;
456 }
457
458 /* Non-GPU queries. */
459 switch (rquery->type) {
460 case PIPE_QUERY_TIMESTAMP_DISJOINT:
461 return true;
462 case R600_QUERY_DRAW_CALLS:
463 rquery->begin_result = rctx->num_draw_calls;
464 return true;
465 case R600_QUERY_REQUESTED_VRAM:
466 case R600_QUERY_REQUESTED_GTT:
467 case R600_QUERY_VRAM_USAGE:
468 case R600_QUERY_GTT_USAGE:
469 case R600_QUERY_GPU_TEMPERATURE:
470 case R600_QUERY_CURRENT_GPU_SCLK:
471 case R600_QUERY_CURRENT_GPU_MCLK:
472 rquery->begin_result = 0;
473 return true;
474 case R600_QUERY_BUFFER_WAIT_TIME:
475 rquery->begin_result = rctx->ws->query_value(rctx->ws, RADEON_BUFFER_WAIT_TIME_NS) / 1000;
476 return true;
477 case R600_QUERY_NUM_CS_FLUSHES:
478 rquery->begin_result = rctx->ws->query_value(rctx->ws, RADEON_NUM_CS_FLUSHES);
479 return true;
480 case R600_QUERY_NUM_BYTES_MOVED:
481 rquery->begin_result = rctx->ws->query_value(rctx->ws, RADEON_NUM_BYTES_MOVED);
482 return true;
483 case R600_QUERY_GPU_LOAD:
484 rquery->begin_result = r600_gpu_load_begin(rctx->screen);
485 return true;
486 }
487
488 /* Discard the old query buffers. */
489 while (prev) {
490 struct r600_query_buffer *qbuf = prev;
491 prev = prev->previous;
492 pipe_resource_reference((struct pipe_resource**)&qbuf->buf, NULL);
493 FREE(qbuf);
494 }
495
496 /* Obtain a new buffer if the current one can't be mapped without a stall. */
497 if (r600_rings_is_buffer_referenced(rctx, rquery->buffer.buf->cs_buf, RADEON_USAGE_READWRITE) ||
498 rctx->ws->buffer_is_busy(rquery->buffer.buf->buf, RADEON_USAGE_READWRITE)) {
499 pipe_resource_reference((struct pipe_resource**)&rquery->buffer.buf, NULL);
500 rquery->buffer.buf = r600_new_query_buffer(rctx, rquery->type);
501 }
502
503 rquery->buffer.results_end = 0;
504 rquery->buffer.previous = NULL;
505
506 r600_emit_query_begin(rctx, rquery);
507
508 if (r600_is_timer_query(rquery->type))
509 LIST_ADDTAIL(&rquery->list, &rctx->active_timer_queries);
510 else
511 LIST_ADDTAIL(&rquery->list, &rctx->active_nontimer_queries);
512 return true;
513 }
514
515 static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
516 {
517 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
518 struct r600_query *rquery = (struct r600_query *)query;
519
520 /* Non-GPU queries. */
521 switch (rquery->type) {
522 case PIPE_QUERY_TIMESTAMP_DISJOINT:
523 return;
524 case PIPE_QUERY_GPU_FINISHED:
525 rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC, &rquery->fence);
526 return;
527 case R600_QUERY_DRAW_CALLS:
528 rquery->end_result = rctx->num_draw_calls;
529 return;
530 case R600_QUERY_REQUESTED_VRAM:
531 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_REQUESTED_VRAM_MEMORY);
532 return;
533 case R600_QUERY_REQUESTED_GTT:
534 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_REQUESTED_GTT_MEMORY);
535 return;
536 case R600_QUERY_BUFFER_WAIT_TIME:
537 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_BUFFER_WAIT_TIME_NS) / 1000;
538 return;
539 case R600_QUERY_NUM_CS_FLUSHES:
540 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_NUM_CS_FLUSHES);
541 return;
542 case R600_QUERY_NUM_BYTES_MOVED:
543 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_NUM_BYTES_MOVED);
544 return;
545 case R600_QUERY_VRAM_USAGE:
546 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_VRAM_USAGE);
547 return;
548 case R600_QUERY_GTT_USAGE:
549 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_GTT_USAGE);
550 return;
551 case R600_QUERY_GPU_TEMPERATURE:
552 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_GPU_TEMPERATURE) / 1000;
553 return;
554 case R600_QUERY_CURRENT_GPU_SCLK:
555 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_CURRENT_SCLK) * 1000000;
556 return;
557 case R600_QUERY_CURRENT_GPU_MCLK:
558 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_CURRENT_MCLK) * 1000000;
559 return;
560 case R600_QUERY_GPU_LOAD:
561 rquery->end_result = r600_gpu_load_end(rctx->screen, rquery->begin_result);
562 return;
563 }
564
565 r600_emit_query_end(rctx, rquery);
566
567 if (r600_query_needs_begin(rquery->type))
568 LIST_DELINIT(&rquery->list);
569 }
570
571 static unsigned r600_query_read_result(char *map, unsigned start_index, unsigned end_index,
572 bool test_status_bit)
573 {
574 uint32_t *current_result = (uint32_t*)map;
575 uint64_t start, end;
576
577 start = (uint64_t)current_result[start_index] |
578 (uint64_t)current_result[start_index+1] << 32;
579 end = (uint64_t)current_result[end_index] |
580 (uint64_t)current_result[end_index+1] << 32;
581
582 if (!test_status_bit ||
583 ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) {
584 return end - start;
585 }
586 return 0;
587 }
588
589 static boolean r600_get_query_buffer_result(struct r600_common_context *ctx,
590 struct r600_query *query,
591 struct r600_query_buffer *qbuf,
592 boolean wait,
593 union pipe_query_result *result)
594 {
595 struct pipe_screen *screen = ctx->b.screen;
596 unsigned results_base = 0;
597 char *map;
598
599 /* Non-GPU queries. */
600 switch (query->type) {
601 case PIPE_QUERY_TIMESTAMP_DISJOINT:
602 /* Convert from cycles per millisecond to cycles per second (Hz). */
603 result->timestamp_disjoint.frequency =
604 (uint64_t)ctx->screen->info.r600_clock_crystal_freq * 1000;
605 result->timestamp_disjoint.disjoint = FALSE;
606 return TRUE;
607 case PIPE_QUERY_GPU_FINISHED:
608 result->b = screen->fence_finish(screen, query->fence,
609 wait ? PIPE_TIMEOUT_INFINITE : 0);
610 return result->b;
611 case R600_QUERY_DRAW_CALLS:
612 case R600_QUERY_REQUESTED_VRAM:
613 case R600_QUERY_REQUESTED_GTT:
614 case R600_QUERY_BUFFER_WAIT_TIME:
615 case R600_QUERY_NUM_CS_FLUSHES:
616 case R600_QUERY_NUM_BYTES_MOVED:
617 case R600_QUERY_VRAM_USAGE:
618 case R600_QUERY_GTT_USAGE:
619 case R600_QUERY_GPU_TEMPERATURE:
620 case R600_QUERY_CURRENT_GPU_SCLK:
621 case R600_QUERY_CURRENT_GPU_MCLK:
622 result->u64 = query->end_result - query->begin_result;
623 return TRUE;
624 case R600_QUERY_GPU_LOAD:
625 result->u64 = query->end_result;
626 return TRUE;
627 }
628
629 map = r600_buffer_map_sync_with_rings(ctx, qbuf->buf,
630 PIPE_TRANSFER_READ |
631 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK));
632 if (!map)
633 return FALSE;
634
635 /* count all results across all data blocks */
636 switch (query->type) {
637 case PIPE_QUERY_OCCLUSION_COUNTER:
638 while (results_base != qbuf->results_end) {
639 result->u64 +=
640 r600_query_read_result(map + results_base, 0, 2, true);
641 results_base += 16;
642 }
643 break;
644 case PIPE_QUERY_OCCLUSION_PREDICATE:
645 while (results_base != qbuf->results_end) {
646 result->b = result->b ||
647 r600_query_read_result(map + results_base, 0, 2, true) != 0;
648 results_base += 16;
649 }
650 break;
651 case PIPE_QUERY_TIME_ELAPSED:
652 while (results_base != qbuf->results_end) {
653 result->u64 +=
654 r600_query_read_result(map + results_base, 0, 2, false);
655 results_base += query->result_size;
656 }
657 break;
658 case PIPE_QUERY_TIMESTAMP:
659 {
660 uint32_t *current_result = (uint32_t*)map;
661 result->u64 = (uint64_t)current_result[0] |
662 (uint64_t)current_result[1] << 32;
663 break;
664 }
665 case PIPE_QUERY_PRIMITIVES_EMITTED:
666 /* SAMPLE_STREAMOUTSTATS stores this structure:
667 * {
668 * u64 NumPrimitivesWritten;
669 * u64 PrimitiveStorageNeeded;
670 * }
671 * We only need NumPrimitivesWritten here. */
672 while (results_base != qbuf->results_end) {
673 result->u64 +=
674 r600_query_read_result(map + results_base, 2, 6, true);
675 results_base += query->result_size;
676 }
677 break;
678 case PIPE_QUERY_PRIMITIVES_GENERATED:
679 /* Here we read PrimitiveStorageNeeded. */
680 while (results_base != qbuf->results_end) {
681 result->u64 +=
682 r600_query_read_result(map + results_base, 0, 4, true);
683 results_base += query->result_size;
684 }
685 break;
686 case PIPE_QUERY_SO_STATISTICS:
687 while (results_base != qbuf->results_end) {
688 result->so_statistics.num_primitives_written +=
689 r600_query_read_result(map + results_base, 2, 6, true);
690 result->so_statistics.primitives_storage_needed +=
691 r600_query_read_result(map + results_base, 0, 4, true);
692 results_base += query->result_size;
693 }
694 break;
695 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
696 while (results_base != qbuf->results_end) {
697 result->b = result->b ||
698 r600_query_read_result(map + results_base, 2, 6, true) !=
699 r600_query_read_result(map + results_base, 0, 4, true);
700 results_base += query->result_size;
701 }
702 break;
703 case PIPE_QUERY_PIPELINE_STATISTICS:
704 if (ctx->chip_class >= EVERGREEN) {
705 while (results_base != qbuf->results_end) {
706 result->pipeline_statistics.ps_invocations +=
707 r600_query_read_result(map + results_base, 0, 22, false);
708 result->pipeline_statistics.c_primitives +=
709 r600_query_read_result(map + results_base, 2, 24, false);
710 result->pipeline_statistics.c_invocations +=
711 r600_query_read_result(map + results_base, 4, 26, false);
712 result->pipeline_statistics.vs_invocations +=
713 r600_query_read_result(map + results_base, 6, 28, false);
714 result->pipeline_statistics.gs_invocations +=
715 r600_query_read_result(map + results_base, 8, 30, false);
716 result->pipeline_statistics.gs_primitives +=
717 r600_query_read_result(map + results_base, 10, 32, false);
718 result->pipeline_statistics.ia_primitives +=
719 r600_query_read_result(map + results_base, 12, 34, false);
720 result->pipeline_statistics.ia_vertices +=
721 r600_query_read_result(map + results_base, 14, 36, false);
722 result->pipeline_statistics.hs_invocations +=
723 r600_query_read_result(map + results_base, 16, 38, false);
724 result->pipeline_statistics.ds_invocations +=
725 r600_query_read_result(map + results_base, 18, 40, false);
726 result->pipeline_statistics.cs_invocations +=
727 r600_query_read_result(map + results_base, 20, 42, false);
728 results_base += query->result_size;
729 }
730 } else {
731 while (results_base != qbuf->results_end) {
732 result->pipeline_statistics.ps_invocations +=
733 r600_query_read_result(map + results_base, 0, 16, false);
734 result->pipeline_statistics.c_primitives +=
735 r600_query_read_result(map + results_base, 2, 18, false);
736 result->pipeline_statistics.c_invocations +=
737 r600_query_read_result(map + results_base, 4, 20, false);
738 result->pipeline_statistics.vs_invocations +=
739 r600_query_read_result(map + results_base, 6, 22, false);
740 result->pipeline_statistics.gs_invocations +=
741 r600_query_read_result(map + results_base, 8, 24, false);
742 result->pipeline_statistics.gs_primitives +=
743 r600_query_read_result(map + results_base, 10, 26, false);
744 result->pipeline_statistics.ia_primitives +=
745 r600_query_read_result(map + results_base, 12, 28, false);
746 result->pipeline_statistics.ia_vertices +=
747 r600_query_read_result(map + results_base, 14, 30, false);
748 results_base += query->result_size;
749 }
750 }
751 #if 0 /* for testing */
752 printf("Pipeline stats: IA verts=%llu, IA prims=%llu, VS=%llu, HS=%llu, "
753 "DS=%llu, GS=%llu, GS prims=%llu, Clipper=%llu, "
754 "Clipper prims=%llu, PS=%llu, CS=%llu\n",
755 result->pipeline_statistics.ia_vertices,
756 result->pipeline_statistics.ia_primitives,
757 result->pipeline_statistics.vs_invocations,
758 result->pipeline_statistics.hs_invocations,
759 result->pipeline_statistics.ds_invocations,
760 result->pipeline_statistics.gs_invocations,
761 result->pipeline_statistics.gs_primitives,
762 result->pipeline_statistics.c_invocations,
763 result->pipeline_statistics.c_primitives,
764 result->pipeline_statistics.ps_invocations,
765 result->pipeline_statistics.cs_invocations);
766 #endif
767 break;
768 default:
769 assert(0);
770 }
771
772 return TRUE;
773 }
774
775 static boolean r600_get_query_result(struct pipe_context *ctx,
776 struct pipe_query *query,
777 boolean wait, union pipe_query_result *result)
778 {
779 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
780 struct r600_query *rquery = (struct r600_query *)query;
781 struct r600_query_buffer *qbuf;
782
783 util_query_clear_result(result, rquery->type);
784
785 for (qbuf = &rquery->buffer; qbuf; qbuf = qbuf->previous) {
786 if (!r600_get_query_buffer_result(rctx, rquery, qbuf, wait, result)) {
787 return FALSE;
788 }
789 }
790
791 /* Convert the time to expected units. */
792 if (rquery->type == PIPE_QUERY_TIME_ELAPSED ||
793 rquery->type == PIPE_QUERY_TIMESTAMP) {
794 result->u64 = (1000000 * result->u64) / rctx->screen->info.r600_clock_crystal_freq;
795 }
796 return TRUE;
797 }
798
799 static void r600_render_condition(struct pipe_context *ctx,
800 struct pipe_query *query,
801 boolean condition,
802 uint mode)
803 {
804 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
805 struct r600_query *rquery = (struct r600_query *)query;
806 bool wait_flag = false;
807
808 rctx->current_render_cond = query;
809 rctx->current_render_cond_cond = condition;
810 rctx->current_render_cond_mode = mode;
811
812 if (query == NULL) {
813 if (rctx->predicate_drawing) {
814 rctx->predicate_drawing = false;
815 r600_emit_query_predication(rctx, NULL, PREDICATION_OP_CLEAR, false);
816 }
817 return;
818 }
819
820 if (mode == PIPE_RENDER_COND_WAIT ||
821 mode == PIPE_RENDER_COND_BY_REGION_WAIT) {
822 wait_flag = true;
823 }
824
825 rctx->predicate_drawing = true;
826
827 switch (rquery->type) {
828 case PIPE_QUERY_OCCLUSION_COUNTER:
829 case PIPE_QUERY_OCCLUSION_PREDICATE:
830 r600_emit_query_predication(rctx, rquery, PREDICATION_OP_ZPASS, wait_flag);
831 break;
832 case PIPE_QUERY_PRIMITIVES_EMITTED:
833 case PIPE_QUERY_PRIMITIVES_GENERATED:
834 case PIPE_QUERY_SO_STATISTICS:
835 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
836 r600_emit_query_predication(rctx, rquery, PREDICATION_OP_PRIMCOUNT, wait_flag);
837 break;
838 default:
839 assert(0);
840 }
841 }
842
843 static void r600_suspend_queries(struct r600_common_context *ctx,
844 struct list_head *query_list,
845 unsigned *num_cs_dw_queries_suspend)
846 {
847 struct r600_query *query;
848
849 LIST_FOR_EACH_ENTRY(query, query_list, list) {
850 r600_emit_query_end(ctx, query);
851 }
852 assert(*num_cs_dw_queries_suspend == 0);
853 }
854
855 void r600_suspend_nontimer_queries(struct r600_common_context *ctx)
856 {
857 r600_suspend_queries(ctx, &ctx->active_nontimer_queries,
858 &ctx->num_cs_dw_nontimer_queries_suspend);
859 }
860
861 void r600_suspend_timer_queries(struct r600_common_context *ctx)
862 {
863 r600_suspend_queries(ctx, &ctx->active_timer_queries,
864 &ctx->num_cs_dw_timer_queries_suspend);
865 }
866
867 static unsigned r600_queries_num_cs_dw_for_resuming(struct r600_common_context *ctx,
868 struct list_head *query_list)
869 {
870 struct r600_query *query;
871 unsigned num_dw = 0;
872
873 LIST_FOR_EACH_ENTRY(query, query_list, list) {
874 /* begin + end */
875 num_dw += query->num_cs_dw * 2;
876
877 /* Workaround for the fact that
878 * num_cs_dw_nontimer_queries_suspend is incremented for every
879 * resumed query, which raises the bar in need_cs_space for
880 * queries about to be resumed.
881 */
882 num_dw += query->num_cs_dw;
883 }
884 /* primitives generated query */
885 num_dw += ctx->streamout.enable_atom.num_dw;
886 /* guess for ZPASS enable or PERFECT_ZPASS_COUNT enable updates */
887 num_dw += 13;
888
889 return num_dw;
890 }
891
892 static void r600_resume_queries(struct r600_common_context *ctx,
893 struct list_head *query_list,
894 unsigned *num_cs_dw_queries_suspend)
895 {
896 struct r600_query *query;
897 unsigned num_cs_dw = r600_queries_num_cs_dw_for_resuming(ctx, query_list);
898
899 assert(*num_cs_dw_queries_suspend == 0);
900
901 /* Check CS space here. Resuming must not be interrupted by flushes. */
902 ctx->need_gfx_cs_space(&ctx->b, num_cs_dw, TRUE);
903
904 LIST_FOR_EACH_ENTRY(query, query_list, list) {
905 r600_emit_query_begin(ctx, query);
906 }
907 }
908
909 void r600_resume_nontimer_queries(struct r600_common_context *ctx)
910 {
911 r600_resume_queries(ctx, &ctx->active_nontimer_queries,
912 &ctx->num_cs_dw_nontimer_queries_suspend);
913 }
914
915 void r600_resume_timer_queries(struct r600_common_context *ctx)
916 {
917 r600_resume_queries(ctx, &ctx->active_timer_queries,
918 &ctx->num_cs_dw_timer_queries_suspend);
919 }
920
921 /* Get backends mask */
922 void r600_query_init_backend_mask(struct r600_common_context *ctx)
923 {
924 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
925 struct r600_resource *buffer;
926 uint32_t *results;
927 unsigned num_backends = ctx->screen->info.r600_num_backends;
928 unsigned i, mask = 0;
929
930 /* if backend_map query is supported by the kernel */
931 if (ctx->screen->info.r600_backend_map_valid) {
932 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
933 unsigned backend_map = ctx->screen->info.r600_backend_map;
934 unsigned item_width, item_mask;
935
936 if (ctx->chip_class >= EVERGREEN) {
937 item_width = 4;
938 item_mask = 0x7;
939 } else {
940 item_width = 2;
941 item_mask = 0x3;
942 }
943
944 while(num_tile_pipes--) {
945 i = backend_map & item_mask;
946 mask |= (1<<i);
947 backend_map >>= item_width;
948 }
949 if (mask != 0) {
950 ctx->backend_mask = mask;
951 return;
952 }
953 }
954
955 /* otherwise backup path for older kernels */
956
957 /* create buffer for event data */
958 buffer = (struct r600_resource*)
959 pipe_buffer_create(ctx->b.screen, PIPE_BIND_CUSTOM,
960 PIPE_USAGE_STAGING, ctx->max_db*16);
961 if (!buffer)
962 goto err;
963
964 /* initialize buffer with zeroes */
965 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE);
966 if (results) {
967 memset(results, 0, ctx->max_db * 4 * 4);
968
969 /* emit EVENT_WRITE for ZPASS_DONE */
970 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
971 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
972 radeon_emit(cs, buffer->gpu_address);
973 radeon_emit(cs, buffer->gpu_address >> 32);
974
975 r600_emit_reloc(ctx, &ctx->rings.gfx, buffer, RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
976
977 /* analyze results */
978 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ);
979 if (results) {
980 for(i = 0; i < ctx->max_db; i++) {
981 /* at least highest bit will be set if backend is used */
982 if (results[i*4 + 1])
983 mask |= (1<<i);
984 }
985 }
986 }
987
988 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
989
990 if (mask != 0) {
991 ctx->backend_mask = mask;
992 return;
993 }
994
995 err:
996 /* fallback to old method - set num_backends lower bits to 1 */
997 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
998 return;
999 }
1000
1001 void r600_query_init(struct r600_common_context *rctx)
1002 {
1003 rctx->b.create_query = r600_create_query;
1004 rctx->b.destroy_query = r600_destroy_query;
1005 rctx->b.begin_query = r600_begin_query;
1006 rctx->b.end_query = r600_end_query;
1007 rctx->b.get_query_result = r600_get_query_result;
1008
1009 if (((struct r600_common_screen*)rctx->b.screen)->info.r600_num_backends > 0)
1010 rctx->b.render_condition = r600_render_condition;
1011
1012 LIST_INITHEAD(&rctx->active_nontimer_queries);
1013 LIST_INITHEAD(&rctx->active_timer_queries);
1014 }