projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
gallium/radeon: remove buffer_unmap calls that can potentially decrease perf
[mesa.git] / src / gallium / drivers / radeon / r600_query.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014 Marek Olšák <marek.olsak@amd.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "r600_cs.h"
26 #include "util/u_memory.h"
27
28
29 struct r600_query_buffer {
30 /* The buffer where query results are stored. */
31 struct r600_resource *buf;
32 /* Offset of the next free result after current query data */
33 unsigned results_end;
34 /* If a query buffer is full, a new buffer is created and the old one
35 * is put in here. When we calculate the result, we sum up the samples
36 * from all buffers. */
37 struct r600_query_buffer *previous;
38 };
39
40 struct r600_query {
41 /* The query buffer and how many results are in it. */
42 struct r600_query_buffer buffer;
43 /* The type of query */
44 unsigned type;
45 /* Size of the result in memory for both begin_query and end_query,
46 * this can be one or two numbers, or it could even be a size of a structure. */
47 unsigned result_size;
48 /* The number of dwords for begin_query or end_query. */
49 unsigned num_cs_dw;
50 /* linked list of queries */
51 struct list_head list;
52 /* for custom non-GPU queries */
53 uint64_t begin_result;
54 uint64_t end_result;
55 /* Fence for GPU_FINISHED. */
56 struct pipe_fence_handle *fence;
57 };
58
59
60 static bool r600_is_timer_query(unsigned type)
61 {
62 return type == PIPE_QUERY_TIME_ELAPSED ||
63 type == PIPE_QUERY_TIMESTAMP;
64 }
65
66 static bool r600_query_needs_begin(unsigned type)
67 {
68 return type != PIPE_QUERY_GPU_FINISHED &&
69 type != PIPE_QUERY_TIMESTAMP;
70 }
71
72 static struct r600_resource *r600_new_query_buffer(struct r600_common_context *ctx, unsigned type)
73 {
74 unsigned j, i, num_results, buf_size = 4096;
75 uint32_t *results;
76
77 /* Non-GPU queries. */
78 switch (type) {
79 case PIPE_QUERY_TIMESTAMP_DISJOINT:
80 case PIPE_QUERY_GPU_FINISHED:
81 case R600_QUERY_DRAW_CALLS:
82 case R600_QUERY_REQUESTED_VRAM:
83 case R600_QUERY_REQUESTED_GTT:
84 case R600_QUERY_BUFFER_WAIT_TIME:
85 case R600_QUERY_NUM_CS_FLUSHES:
86 case R600_QUERY_NUM_BYTES_MOVED:
87 case R600_QUERY_VRAM_USAGE:
88 case R600_QUERY_GTT_USAGE:
89 case R600_QUERY_GPU_TEMPERATURE:
90 case R600_QUERY_CURRENT_GPU_SCLK:
91 case R600_QUERY_CURRENT_GPU_MCLK:
92 case R600_QUERY_GPU_LOAD:
93 return NULL;
94 }
95
96 /* Queries are normally read by the CPU after
97 * being written by the gpu, hence staging is probably a good
98 * usage pattern.
99 */
100 struct r600_resource *buf = (struct r600_resource*)
101 pipe_buffer_create(ctx->b.screen, PIPE_BIND_CUSTOM,
102 PIPE_USAGE_STAGING, buf_size);
103
104 switch (type) {
105 case PIPE_QUERY_OCCLUSION_COUNTER:
106 case PIPE_QUERY_OCCLUSION_PREDICATE:
107 results = r600_buffer_map_sync_with_rings(ctx, buf, PIPE_TRANSFER_WRITE);
108 memset(results, 0, buf_size);
109
110 /* Set top bits for unused backends. */
111 num_results = buf_size / (16 * ctx->max_db);
112 for (j = 0; j < num_results; j++) {
113 for (i = 0; i < ctx->max_db; i++) {
114 if (!(ctx->backend_mask & (1<<i))) {
115 results[(i * 4)+1] = 0x80000000;
116 results[(i * 4)+3] = 0x80000000;
117 }
118 }
119 results += 4 * ctx->max_db;
120 }
121 break;
122 case PIPE_QUERY_TIME_ELAPSED:
123 case PIPE_QUERY_TIMESTAMP:
124 break;
125 case PIPE_QUERY_PRIMITIVES_EMITTED:
126 case PIPE_QUERY_PRIMITIVES_GENERATED:
127 case PIPE_QUERY_SO_STATISTICS:
128 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
129 case PIPE_QUERY_PIPELINE_STATISTICS:
130 results = r600_buffer_map_sync_with_rings(ctx, buf, PIPE_TRANSFER_WRITE);
131 memset(results, 0, buf_size);
132 break;
133 default:
134 assert(0);
135 }
136 return buf;
137 }
138
139 static void r600_update_occlusion_query_state(struct r600_common_context *rctx,
140 unsigned type, int diff)
141 {
142 if (type == PIPE_QUERY_OCCLUSION_COUNTER ||
143 type == PIPE_QUERY_OCCLUSION_PREDICATE) {
144 bool old_enable = rctx->num_occlusion_queries != 0;
145 bool enable;
146
147 rctx->num_occlusion_queries += diff;
148 assert(rctx->num_occlusion_queries >= 0);
149
150 enable = rctx->num_occlusion_queries != 0;
151
152 if (enable != old_enable) {
153 rctx->set_occlusion_query_state(&rctx->b, enable);
154 }
155 }
156 }
157
158 static void r600_emit_query_begin(struct r600_common_context *ctx, struct r600_query *query)
159 {
160 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
161 uint64_t va;
162
163 r600_update_occlusion_query_state(ctx, query->type, 1);
164 r600_update_prims_generated_query_state(ctx, query->type, 1);
165 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw * 2, TRUE);
166
167 /* Get a new query buffer if needed. */
168 if (query->buffer.results_end + query->result_size > query->buffer.buf->b.b.width0) {
169 struct r600_query_buffer *qbuf = MALLOC_STRUCT(r600_query_buffer);
170 *qbuf = query->buffer;
171 query->buffer.buf = r600_new_query_buffer(ctx, query->type);
172 query->buffer.results_end = 0;
173 query->buffer.previous = qbuf;
174 }
175
176 /* emit begin query */
177 va = query->buffer.buf->gpu_address + query->buffer.results_end;
178
179 switch (query->type) {
180 case PIPE_QUERY_OCCLUSION_COUNTER:
181 case PIPE_QUERY_OCCLUSION_PREDICATE:
182 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
183 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
184 radeon_emit(cs, va);
185 radeon_emit(cs, (va >> 32UL) & 0xFF);
186 break;
187 case PIPE_QUERY_PRIMITIVES_EMITTED:
188 case PIPE_QUERY_PRIMITIVES_GENERATED:
189 case PIPE_QUERY_SO_STATISTICS:
190 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
191 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
192 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3));
193 radeon_emit(cs, va);
194 radeon_emit(cs, (va >> 32UL) & 0xFF);
195 break;
196 case PIPE_QUERY_TIME_ELAPSED:
197 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
198 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
199 radeon_emit(cs, va);
200 radeon_emit(cs, (3 << 29) | ((va >> 32UL) & 0xFF));
201 radeon_emit(cs, 0);
202 radeon_emit(cs, 0);
203 break;
204 case PIPE_QUERY_PIPELINE_STATISTICS:
205 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
206 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
207 radeon_emit(cs, va);
208 radeon_emit(cs, (va >> 32UL) & 0xFF);
209 break;
210 default:
211 assert(0);
212 }
213 r600_emit_reloc(ctx, &ctx->rings.gfx, query->buffer.buf, RADEON_USAGE_WRITE,
214 RADEON_PRIO_MIN);
215
216 if (!r600_is_timer_query(query->type)) {
217 ctx->num_cs_dw_nontimer_queries_suspend += query->num_cs_dw;
218 }
219 }
220
221 static void r600_emit_query_end(struct r600_common_context *ctx, struct r600_query *query)
222 {
223 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
224 uint64_t va;
225
226 /* The queries which need begin already called this in begin_query. */
227 if (!r600_query_needs_begin(query->type)) {
228 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw, FALSE);
229 }
230
231 va = query->buffer.buf->gpu_address;
232
233 /* emit end query */
234 switch (query->type) {
235 case PIPE_QUERY_OCCLUSION_COUNTER:
236 case PIPE_QUERY_OCCLUSION_PREDICATE:
237 va += query->buffer.results_end + 8;
238 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
239 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
240 radeon_emit(cs, va);
241 radeon_emit(cs, (va >> 32UL) & 0xFF);
242 break;
243 case PIPE_QUERY_PRIMITIVES_EMITTED:
244 case PIPE_QUERY_PRIMITIVES_GENERATED:
245 case PIPE_QUERY_SO_STATISTICS:
246 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
247 va += query->buffer.results_end + query->result_size/2;
248 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
249 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3));
250 radeon_emit(cs, va);
251 radeon_emit(cs, (va >> 32UL) & 0xFF);
252 break;
253 case PIPE_QUERY_TIME_ELAPSED:
254 va += query->buffer.results_end + query->result_size/2;
255 /* fall through */
256 case PIPE_QUERY_TIMESTAMP:
257 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
258 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
259 radeon_emit(cs, va);
260 radeon_emit(cs, (3 << 29) | ((va >> 32UL) & 0xFF));
261 radeon_emit(cs, 0);
262 radeon_emit(cs, 0);
263 break;
264 case PIPE_QUERY_PIPELINE_STATISTICS:
265 va += query->buffer.results_end + query->result_size/2;
266 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
267 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
268 radeon_emit(cs, va);
269 radeon_emit(cs, (va >> 32UL) & 0xFF);
270 break;
271 default:
272 assert(0);
273 }
274 r600_emit_reloc(ctx, &ctx->rings.gfx, query->buffer.buf, RADEON_USAGE_WRITE,
275 RADEON_PRIO_MIN);
276
277 query->buffer.results_end += query->result_size;
278
279 if (r600_query_needs_begin(query->type)) {
280 if (!r600_is_timer_query(query->type)) {
281 ctx->num_cs_dw_nontimer_queries_suspend -= query->num_cs_dw;
282 }
283 }
284
285 r600_update_occlusion_query_state(ctx, query->type, -1);
286 r600_update_prims_generated_query_state(ctx, query->type, -1);
287 }
288
289 static void r600_emit_query_predication(struct r600_common_context *ctx, struct r600_query *query,
290 int operation, bool flag_wait)
291 {
292 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
293
294 if (operation == PREDICATION_OP_CLEAR) {
295 ctx->need_gfx_cs_space(&ctx->b, 3, FALSE);
296
297 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
298 radeon_emit(cs, 0);
299 radeon_emit(cs, PRED_OP(PREDICATION_OP_CLEAR));
300 } else {
301 struct r600_query_buffer *qbuf;
302 unsigned count;
303 uint32_t op;
304
305 /* Find how many results there are. */
306 count = 0;
307 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
308 count += qbuf->results_end / query->result_size;
309 }
310
311 ctx->need_gfx_cs_space(&ctx->b, 5 * count, TRUE);
312
313 op = PRED_OP(operation) | PREDICATION_DRAW_VISIBLE |
314 (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW);
315
316 /* emit predicate packets for all data blocks */
317 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
318 unsigned results_base = 0;
319 uint64_t va = qbuf->buf->gpu_address;
320
321 while (results_base < qbuf->results_end) {
322 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
323 radeon_emit(cs, (va + results_base) & 0xFFFFFFFFUL);
324 radeon_emit(cs, op | (((va + results_base) >> 32UL) & 0xFF));
325 r600_emit_reloc(ctx, &ctx->rings.gfx, qbuf->buf, RADEON_USAGE_READ,
326 RADEON_PRIO_MIN);
327 results_base += query->result_size;
328
329 /* set CONTINUE bit for all packets except the first */
330 op |= PREDICATION_CONTINUE;
331 }
332 }
333 }
334 }
335
336 static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type, unsigned index)
337 {
338 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
339 struct r600_query *query;
340 bool skip_allocation = false;
341
342 query = CALLOC_STRUCT(r600_query);
343 if (query == NULL)
344 return NULL;
345
346 query->type = query_type;
347
348 switch (query_type) {
349 case PIPE_QUERY_OCCLUSION_COUNTER:
350 case PIPE_QUERY_OCCLUSION_PREDICATE:
351 query->result_size = 16 * rctx->max_db;
352 query->num_cs_dw = 6;
353 break;
354 break;
355 case PIPE_QUERY_TIME_ELAPSED:
356 query->result_size = 16;
357 query->num_cs_dw = 8;
358 break;
359 case PIPE_QUERY_TIMESTAMP:
360 query->result_size = 8;
361 query->num_cs_dw = 8;
362 break;
363 case PIPE_QUERY_PRIMITIVES_EMITTED:
364 case PIPE_QUERY_PRIMITIVES_GENERATED:
365 case PIPE_QUERY_SO_STATISTICS:
366 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
367 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
368 query->result_size = 32;
369 query->num_cs_dw = 6;
370 break;
371 case PIPE_QUERY_PIPELINE_STATISTICS:
372 /* 11 values on EG, 8 on R600. */
373 query->result_size = (rctx->chip_class >= EVERGREEN ? 11 : 8) * 16;
374 query->num_cs_dw = 6;
375 break;
376 /* Non-GPU queries and queries not requiring a buffer. */
377 case PIPE_QUERY_TIMESTAMP_DISJOINT:
378 case PIPE_QUERY_GPU_FINISHED:
379 case R600_QUERY_DRAW_CALLS:
380 case R600_QUERY_REQUESTED_VRAM:
381 case R600_QUERY_REQUESTED_GTT:
382 case R600_QUERY_BUFFER_WAIT_TIME:
383 case R600_QUERY_NUM_CS_FLUSHES:
384 case R600_QUERY_NUM_BYTES_MOVED:
385 case R600_QUERY_VRAM_USAGE:
386 case R600_QUERY_GTT_USAGE:
387 case R600_QUERY_GPU_TEMPERATURE:
388 case R600_QUERY_CURRENT_GPU_SCLK:
389 case R600_QUERY_CURRENT_GPU_MCLK:
390 case R600_QUERY_GPU_LOAD:
391 skip_allocation = true;
392 break;
393 default:
394 assert(0);
395 FREE(query);
396 return NULL;
397 }
398
399 if (!skip_allocation) {
400 query->buffer.buf = r600_new_query_buffer(rctx, query_type);
401 if (!query->buffer.buf) {
402 FREE(query);
403 return NULL;
404 }
405 }
406 return (struct pipe_query*)query;
407 }
408
409 static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
410 {
411 struct r600_query *rquery = (struct r600_query*)query;
412 struct r600_query_buffer *prev = rquery->buffer.previous;
413
414 /* Release all query buffers. */
415 while (prev) {
416 struct r600_query_buffer *qbuf = prev;
417 prev = prev->previous;
418 pipe_resource_reference((struct pipe_resource**)&qbuf->buf, NULL);
419 FREE(qbuf);
420 }
421
422 pipe_resource_reference((struct pipe_resource**)&rquery->buffer.buf, NULL);
423 FREE(query);
424 }
425
426 static boolean r600_begin_query(struct pipe_context *ctx,
427 struct pipe_query *query)
428 {
429 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
430 struct r600_query *rquery = (struct r600_query *)query;
431 struct r600_query_buffer *prev = rquery->buffer.previous;
432
433 if (!r600_query_needs_begin(rquery->type)) {
434 assert(0);
435 return false;
436 }
437
438 /* Non-GPU queries. */
439 switch (rquery->type) {
440 case PIPE_QUERY_TIMESTAMP_DISJOINT:
441 return true;
442 case R600_QUERY_DRAW_CALLS:
443 rquery->begin_result = rctx->num_draw_calls;
444 return true;
445 case R600_QUERY_REQUESTED_VRAM:
446 case R600_QUERY_REQUESTED_GTT:
447 case R600_QUERY_VRAM_USAGE:
448 case R600_QUERY_GTT_USAGE:
449 case R600_QUERY_GPU_TEMPERATURE:
450 case R600_QUERY_CURRENT_GPU_SCLK:
451 case R600_QUERY_CURRENT_GPU_MCLK:
452 rquery->begin_result = 0;
453 return true;
454 case R600_QUERY_BUFFER_WAIT_TIME:
455 rquery->begin_result = rctx->ws->query_value(rctx->ws, RADEON_BUFFER_WAIT_TIME_NS);
456 return true;
457 case R600_QUERY_NUM_CS_FLUSHES:
458 rquery->begin_result = rctx->ws->query_value(rctx->ws, RADEON_NUM_CS_FLUSHES);
459 return true;
460 case R600_QUERY_NUM_BYTES_MOVED:
461 rquery->begin_result = rctx->ws->query_value(rctx->ws, RADEON_NUM_BYTES_MOVED);
462 return true;
463 case R600_QUERY_GPU_LOAD:
464 rquery->begin_result = r600_gpu_load_begin(rctx->screen);
465 return true;
466 }
467
468 /* Discard the old query buffers. */
469 while (prev) {
470 struct r600_query_buffer *qbuf = prev;
471 prev = prev->previous;
472 pipe_resource_reference((struct pipe_resource**)&qbuf->buf, NULL);
473 FREE(qbuf);
474 }
475
476 /* Obtain a new buffer if the current one can't be mapped without a stall. */
477 if (r600_rings_is_buffer_referenced(rctx, rquery->buffer.buf->cs_buf, RADEON_USAGE_READWRITE) ||
478 rctx->ws->buffer_is_busy(rquery->buffer.buf->buf, RADEON_USAGE_READWRITE)) {
479 pipe_resource_reference((struct pipe_resource**)&rquery->buffer.buf, NULL);
480 rquery->buffer.buf = r600_new_query_buffer(rctx, rquery->type);
481 }
482
483 rquery->buffer.results_end = 0;
484 rquery->buffer.previous = NULL;
485
486 r600_emit_query_begin(rctx, rquery);
487
488 if (!r600_is_timer_query(rquery->type)) {
489 LIST_ADDTAIL(&rquery->list, &rctx->active_nontimer_queries);
490 }
491 return true;
492 }
493
494 static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
495 {
496 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
497 struct r600_query *rquery = (struct r600_query *)query;
498
499 /* Non-GPU queries. */
500 switch (rquery->type) {
501 case PIPE_QUERY_TIMESTAMP_DISJOINT:
502 return;
503 case PIPE_QUERY_GPU_FINISHED:
504 rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC, &rquery->fence);
505 return;
506 case R600_QUERY_DRAW_CALLS:
507 rquery->end_result = rctx->num_draw_calls;
508 return;
509 case R600_QUERY_REQUESTED_VRAM:
510 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_REQUESTED_VRAM_MEMORY);
511 return;
512 case R600_QUERY_REQUESTED_GTT:
513 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_REQUESTED_GTT_MEMORY);
514 return;
515 case R600_QUERY_BUFFER_WAIT_TIME:
516 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_BUFFER_WAIT_TIME_NS);
517 return;
518 case R600_QUERY_NUM_CS_FLUSHES:
519 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_NUM_CS_FLUSHES);
520 return;
521 case R600_QUERY_NUM_BYTES_MOVED:
522 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_NUM_BYTES_MOVED);
523 return;
524 case R600_QUERY_VRAM_USAGE:
525 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_VRAM_USAGE);
526 return;
527 case R600_QUERY_GTT_USAGE:
528 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_GTT_USAGE);
529 return;
530 case R600_QUERY_GPU_TEMPERATURE:
531 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_GPU_TEMPERATURE) / 1000;
532 return;
533 case R600_QUERY_CURRENT_GPU_SCLK:
534 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_CURRENT_SCLK) * 1000000;
535 return;
536 case R600_QUERY_CURRENT_GPU_MCLK:
537 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_CURRENT_MCLK) * 1000000;
538 return;
539 case R600_QUERY_GPU_LOAD:
540 rquery->end_result = r600_gpu_load_end(rctx->screen, rquery->begin_result);
541 return;
542 }
543
544 r600_emit_query_end(rctx, rquery);
545
546 if (r600_query_needs_begin(rquery->type) && !r600_is_timer_query(rquery->type)) {
547 LIST_DELINIT(&rquery->list);
548 }
549 }
550
551 static unsigned r600_query_read_result(char *map, unsigned start_index, unsigned end_index,
552 bool test_status_bit)
553 {
554 uint32_t *current_result = (uint32_t*)map;
555 uint64_t start, end;
556
557 start = (uint64_t)current_result[start_index] |
558 (uint64_t)current_result[start_index+1] << 32;
559 end = (uint64_t)current_result[end_index] |
560 (uint64_t)current_result[end_index+1] << 32;
561
562 if (!test_status_bit ||
563 ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) {
564 return end - start;
565 }
566 return 0;
567 }
568
569 static boolean r600_get_query_buffer_result(struct r600_common_context *ctx,
570 struct r600_query *query,
571 struct r600_query_buffer *qbuf,
572 boolean wait,
573 union pipe_query_result *result)
574 {
575 struct pipe_screen *screen = ctx->b.screen;
576 unsigned results_base = 0;
577 char *map;
578
579 /* Non-GPU queries. */
580 switch (query->type) {
581 case PIPE_QUERY_TIMESTAMP_DISJOINT:
582 /* Convert from cycles per millisecond to cycles per second (Hz). */
583 result->timestamp_disjoint.frequency =
584 (uint64_t)ctx->screen->info.r600_clock_crystal_freq * 1000;
585 result->timestamp_disjoint.disjoint = FALSE;
586 return TRUE;
587 case PIPE_QUERY_GPU_FINISHED:
588 result->b = screen->fence_finish(screen, query->fence,
589 wait ? PIPE_TIMEOUT_INFINITE : 0);
590 return result->b;
591 case R600_QUERY_DRAW_CALLS:
592 case R600_QUERY_REQUESTED_VRAM:
593 case R600_QUERY_REQUESTED_GTT:
594 case R600_QUERY_BUFFER_WAIT_TIME:
595 case R600_QUERY_NUM_CS_FLUSHES:
596 case R600_QUERY_NUM_BYTES_MOVED:
597 case R600_QUERY_VRAM_USAGE:
598 case R600_QUERY_GTT_USAGE:
599 case R600_QUERY_GPU_TEMPERATURE:
600 case R600_QUERY_CURRENT_GPU_SCLK:
601 case R600_QUERY_CURRENT_GPU_MCLK:
602 result->u64 = query->end_result - query->begin_result;
603 return TRUE;
604 case R600_QUERY_GPU_LOAD:
605 result->u64 = query->end_result;
606 return TRUE;
607 }
608
609 map = r600_buffer_map_sync_with_rings(ctx, qbuf->buf,
610 PIPE_TRANSFER_READ |
611 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK));
612 if (!map)
613 return FALSE;
614
615 /* count all results across all data blocks */
616 switch (query->type) {
617 case PIPE_QUERY_OCCLUSION_COUNTER:
618 while (results_base != qbuf->results_end) {
619 result->u64 +=
620 r600_query_read_result(map + results_base, 0, 2, true);
621 results_base += 16;
622 }
623 break;
624 case PIPE_QUERY_OCCLUSION_PREDICATE:
625 while (results_base != qbuf->results_end) {
626 result->b = result->b ||
627 r600_query_read_result(map + results_base, 0, 2, true) != 0;
628 results_base += 16;
629 }
630 break;
631 case PIPE_QUERY_TIME_ELAPSED:
632 while (results_base != qbuf->results_end) {
633 result->u64 +=
634 r600_query_read_result(map + results_base, 0, 2, false);
635 results_base += query->result_size;
636 }
637 break;
638 case PIPE_QUERY_TIMESTAMP:
639 {
640 uint32_t *current_result = (uint32_t*)map;
641 result->u64 = (uint64_t)current_result[0] |
642 (uint64_t)current_result[1] << 32;
643 break;
644 }
645 case PIPE_QUERY_PRIMITIVES_EMITTED:
646 /* SAMPLE_STREAMOUTSTATS stores this structure:
647 * {
648 * u64 NumPrimitivesWritten;
649 * u64 PrimitiveStorageNeeded;
650 * }
651 * We only need NumPrimitivesWritten here. */
652 while (results_base != qbuf->results_end) {
653 result->u64 +=
654 r600_query_read_result(map + results_base, 2, 6, true);
655 results_base += query->result_size;
656 }
657 break;
658 case PIPE_QUERY_PRIMITIVES_GENERATED:
659 /* Here we read PrimitiveStorageNeeded. */
660 while (results_base != qbuf->results_end) {
661 result->u64 +=
662 r600_query_read_result(map + results_base, 0, 4, true);
663 results_base += query->result_size;
664 }
665 break;
666 case PIPE_QUERY_SO_STATISTICS:
667 while (results_base != qbuf->results_end) {
668 result->so_statistics.num_primitives_written +=
669 r600_query_read_result(map + results_base, 2, 6, true);
670 result->so_statistics.primitives_storage_needed +=
671 r600_query_read_result(map + results_base, 0, 4, true);
672 results_base += query->result_size;
673 }
674 break;
675 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
676 while (results_base != qbuf->results_end) {
677 result->b = result->b ||
678 r600_query_read_result(map + results_base, 2, 6, true) !=
679 r600_query_read_result(map + results_base, 0, 4, true);
680 results_base += query->result_size;
681 }
682 break;
683 case PIPE_QUERY_PIPELINE_STATISTICS:
684 if (ctx->chip_class >= EVERGREEN) {
685 while (results_base != qbuf->results_end) {
686 result->pipeline_statistics.ps_invocations +=
687 r600_query_read_result(map + results_base, 0, 22, false);
688 result->pipeline_statistics.c_primitives +=
689 r600_query_read_result(map + results_base, 2, 24, false);
690 result->pipeline_statistics.c_invocations +=
691 r600_query_read_result(map + results_base, 4, 26, false);
692 result->pipeline_statistics.vs_invocations +=
693 r600_query_read_result(map + results_base, 6, 28, false);
694 result->pipeline_statistics.gs_invocations +=
695 r600_query_read_result(map + results_base, 8, 30, false);
696 result->pipeline_statistics.gs_primitives +=
697 r600_query_read_result(map + results_base, 10, 32, false);
698 result->pipeline_statistics.ia_primitives +=
699 r600_query_read_result(map + results_base, 12, 34, false);
700 result->pipeline_statistics.ia_vertices +=
701 r600_query_read_result(map + results_base, 14, 36, false);
702 result->pipeline_statistics.hs_invocations +=
703 r600_query_read_result(map + results_base, 16, 38, false);
704 result->pipeline_statistics.ds_invocations +=
705 r600_query_read_result(map + results_base, 18, 40, false);
706 result->pipeline_statistics.cs_invocations +=
707 r600_query_read_result(map + results_base, 20, 42, false);
708 results_base += query->result_size;
709 }
710 } else {
711 while (results_base != qbuf->results_end) {
712 result->pipeline_statistics.ps_invocations +=
713 r600_query_read_result(map + results_base, 0, 16, false);
714 result->pipeline_statistics.c_primitives +=
715 r600_query_read_result(map + results_base, 2, 18, false);
716 result->pipeline_statistics.c_invocations +=
717 r600_query_read_result(map + results_base, 4, 20, false);
718 result->pipeline_statistics.vs_invocations +=
719 r600_query_read_result(map + results_base, 6, 22, false);
720 result->pipeline_statistics.gs_invocations +=
721 r600_query_read_result(map + results_base, 8, 24, false);
722 result->pipeline_statistics.gs_primitives +=
723 r600_query_read_result(map + results_base, 10, 26, false);
724 result->pipeline_statistics.ia_primitives +=
725 r600_query_read_result(map + results_base, 12, 28, false);
726 result->pipeline_statistics.ia_vertices +=
727 r600_query_read_result(map + results_base, 14, 30, false);
728 results_base += query->result_size;
729 }
730 }
731 #if 0 /* for testing */
732 printf("Pipeline stats: IA verts=%llu, IA prims=%llu, VS=%llu, HS=%llu, "
733 "DS=%llu, GS=%llu, GS prims=%llu, Clipper=%llu, "
734 "Clipper prims=%llu, PS=%llu, CS=%llu\n",
735 result->pipeline_statistics.ia_vertices,
736 result->pipeline_statistics.ia_primitives,
737 result->pipeline_statistics.vs_invocations,
738 result->pipeline_statistics.hs_invocations,
739 result->pipeline_statistics.ds_invocations,
740 result->pipeline_statistics.gs_invocations,
741 result->pipeline_statistics.gs_primitives,
742 result->pipeline_statistics.c_invocations,
743 result->pipeline_statistics.c_primitives,
744 result->pipeline_statistics.ps_invocations,
745 result->pipeline_statistics.cs_invocations);
746 #endif
747 break;
748 default:
749 assert(0);
750 }
751
752 return TRUE;
753 }
754
755 static boolean r600_get_query_result(struct pipe_context *ctx,
756 struct pipe_query *query,
757 boolean wait, union pipe_query_result *result)
758 {
759 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
760 struct r600_query *rquery = (struct r600_query *)query;
761 struct r600_query_buffer *qbuf;
762
763 util_query_clear_result(result, rquery->type);
764
765 for (qbuf = &rquery->buffer; qbuf; qbuf = qbuf->previous) {
766 if (!r600_get_query_buffer_result(rctx, rquery, qbuf, wait, result)) {
767 return FALSE;
768 }
769 }
770
771 /* Convert the time to expected units. */
772 if (rquery->type == PIPE_QUERY_TIME_ELAPSED ||
773 rquery->type == PIPE_QUERY_TIMESTAMP) {
774 result->u64 = (1000000 * result->u64) / rctx->screen->info.r600_clock_crystal_freq;
775 }
776 return TRUE;
777 }
778
779 static void r600_render_condition(struct pipe_context *ctx,
780 struct pipe_query *query,
781 boolean condition,
782 uint mode)
783 {
784 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
785 struct r600_query *rquery = (struct r600_query *)query;
786 bool wait_flag = false;
787
788 rctx->current_render_cond = query;
789 rctx->current_render_cond_cond = condition;
790 rctx->current_render_cond_mode = mode;
791
792 if (query == NULL) {
793 if (rctx->predicate_drawing) {
794 rctx->predicate_drawing = false;
795 r600_emit_query_predication(rctx, NULL, PREDICATION_OP_CLEAR, false);
796 }
797 return;
798 }
799
800 if (mode == PIPE_RENDER_COND_WAIT ||
801 mode == PIPE_RENDER_COND_BY_REGION_WAIT) {
802 wait_flag = true;
803 }
804
805 rctx->predicate_drawing = true;
806
807 switch (rquery->type) {
808 case PIPE_QUERY_OCCLUSION_COUNTER:
809 case PIPE_QUERY_OCCLUSION_PREDICATE:
810 r600_emit_query_predication(rctx, rquery, PREDICATION_OP_ZPASS, wait_flag);
811 break;
812 case PIPE_QUERY_PRIMITIVES_EMITTED:
813 case PIPE_QUERY_PRIMITIVES_GENERATED:
814 case PIPE_QUERY_SO_STATISTICS:
815 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
816 r600_emit_query_predication(rctx, rquery, PREDICATION_OP_PRIMCOUNT, wait_flag);
817 break;
818 default:
819 assert(0);
820 }
821 }
822
823 void r600_suspend_nontimer_queries(struct r600_common_context *ctx)
824 {
825 struct r600_query *query;
826
827 LIST_FOR_EACH_ENTRY(query, &ctx->active_nontimer_queries, list) {
828 r600_emit_query_end(ctx, query);
829 }
830 assert(ctx->num_cs_dw_nontimer_queries_suspend == 0);
831 }
832
833 static unsigned r600_queries_num_cs_dw_for_resuming(struct r600_common_context *ctx)
834 {
835 struct r600_query *query;
836 unsigned num_dw = 0;
837
838 LIST_FOR_EACH_ENTRY(query, &ctx->active_nontimer_queries, list) {
839 /* begin + end */
840 num_dw += query->num_cs_dw * 2;
841
842 /* Workaround for the fact that
843 * num_cs_dw_nontimer_queries_suspend is incremented for every
844 * resumed query, which raises the bar in need_cs_space for
845 * queries about to be resumed.
846 */
847 num_dw += query->num_cs_dw;
848 }
849 /* primitives generated query */
850 num_dw += ctx->streamout.enable_atom.num_dw;
851 /* guess for ZPASS enable or PERFECT_ZPASS_COUNT enable updates */
852 num_dw += 13;
853
854 return num_dw;
855 }
856
857 void r600_resume_nontimer_queries(struct r600_common_context *ctx)
858 {
859 struct r600_query *query;
860
861 assert(ctx->num_cs_dw_nontimer_queries_suspend == 0);
862
863 /* Check CS space here. Resuming must not be interrupted by flushes. */
864 ctx->need_gfx_cs_space(&ctx->b,
865 r600_queries_num_cs_dw_for_resuming(ctx), TRUE);
866
867 LIST_FOR_EACH_ENTRY(query, &ctx->active_nontimer_queries, list) {
868 r600_emit_query_begin(ctx, query);
869 }
870 }
871
872 /* Get backends mask */
873 void r600_query_init_backend_mask(struct r600_common_context *ctx)
874 {
875 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
876 struct r600_resource *buffer;
877 uint32_t *results;
878 unsigned num_backends = ctx->screen->info.r600_num_backends;
879 unsigned i, mask = 0;
880
881 /* if backend_map query is supported by the kernel */
882 if (ctx->screen->info.r600_backend_map_valid) {
883 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
884 unsigned backend_map = ctx->screen->info.r600_backend_map;
885 unsigned item_width, item_mask;
886
887 if (ctx->chip_class >= EVERGREEN) {
888 item_width = 4;
889 item_mask = 0x7;
890 } else {
891 item_width = 2;
892 item_mask = 0x3;
893 }
894
895 while(num_tile_pipes--) {
896 i = backend_map & item_mask;
897 mask |= (1<<i);
898 backend_map >>= item_width;
899 }
900 if (mask != 0) {
901 ctx->backend_mask = mask;
902 return;
903 }
904 }
905
906 /* otherwise backup path for older kernels */
907
908 /* create buffer for event data */
909 buffer = (struct r600_resource*)
910 pipe_buffer_create(ctx->b.screen, PIPE_BIND_CUSTOM,
911 PIPE_USAGE_STAGING, ctx->max_db*16);
912 if (!buffer)
913 goto err;
914
915 /* initialize buffer with zeroes */
916 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE);
917 if (results) {
918 memset(results, 0, ctx->max_db * 4 * 4);
919
920 /* emit EVENT_WRITE for ZPASS_DONE */
921 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
922 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
923 radeon_emit(cs, buffer->gpu_address);
924 radeon_emit(cs, buffer->gpu_address >> 32);
925
926 r600_emit_reloc(ctx, &ctx->rings.gfx, buffer, RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
927
928 /* analyze results */
929 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ);
930 if (results) {
931 for(i = 0; i < ctx->max_db; i++) {
932 /* at least highest bit will be set if backend is used */
933 if (results[i*4 + 1])
934 mask |= (1<<i);
935 }
936 }
937 }
938
939 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
940
941 if (mask != 0) {
942 ctx->backend_mask = mask;
943 return;
944 }
945
946 err:
947 /* fallback to old method - set num_backends lower bits to 1 */
948 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
949 return;
950 }
951
952 void r600_query_init(struct r600_common_context *rctx)
953 {
954 rctx->b.create_query = r600_create_query;
955 rctx->b.destroy_query = r600_destroy_query;
956 rctx->b.begin_query = r600_begin_query;
957 rctx->b.end_query = r600_end_query;
958 rctx->b.get_query_result = r600_get_query_result;
959
960 if (((struct r600_common_screen*)rctx->b.screen)->info.r600_num_backends > 0)
961 rctx->b.render_condition = r600_render_condition;
962
963 LIST_INITHEAD(&rctx->active_nontimer_queries);
964 }