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r600: Fix use after free in compute_memory_promote_item.
[mesa.git] / src / gallium / drivers / radeon / r600_query.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014 Marek Olšák <marek.olsak@amd.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "r600_cs.h"
26 #include "util/u_memory.h"
27
28
29 struct r600_query_buffer {
30 /* The buffer where query results are stored. */
31 struct r600_resource *buf;
32 /* Offset of the next free result after current query data */
33 unsigned results_end;
34 /* If a query buffer is full, a new buffer is created and the old one
35 * is put in here. When we calculate the result, we sum up the samples
36 * from all buffers. */
37 struct r600_query_buffer *previous;
38 };
39
40 struct r600_query {
41 /* The query buffer and how many results are in it. */
42 struct r600_query_buffer buffer;
43 /* The type of query */
44 unsigned type;
45 /* Size of the result in memory for both begin_query and end_query,
46 * this can be one or two numbers, or it could even be a size of a structure. */
47 unsigned result_size;
48 /* The number of dwords for begin_query or end_query. */
49 unsigned num_cs_dw;
50 /* linked list of queries */
51 struct list_head list;
52 /* for custom non-GPU queries */
53 uint64_t begin_result;
54 uint64_t end_result;
55 };
56
57
58 static bool r600_is_timer_query(unsigned type)
59 {
60 return type == PIPE_QUERY_TIME_ELAPSED ||
61 type == PIPE_QUERY_TIMESTAMP ||
62 type == PIPE_QUERY_TIMESTAMP_DISJOINT;
63 }
64
65 static bool r600_query_needs_begin(unsigned type)
66 {
67 return type != PIPE_QUERY_GPU_FINISHED &&
68 type != PIPE_QUERY_TIMESTAMP;
69 }
70
71 static struct r600_resource *r600_new_query_buffer(struct r600_common_context *ctx, unsigned type)
72 {
73 unsigned j, i, num_results, buf_size = 4096;
74 uint32_t *results;
75
76 /* Non-GPU queries. */
77 switch (type) {
78 case R600_QUERY_DRAW_CALLS:
79 case R600_QUERY_REQUESTED_VRAM:
80 case R600_QUERY_REQUESTED_GTT:
81 case R600_QUERY_BUFFER_WAIT_TIME:
82 case R600_QUERY_NUM_CS_FLUSHES:
83 case R600_QUERY_NUM_BYTES_MOVED:
84 case R600_QUERY_VRAM_USAGE:
85 case R600_QUERY_GTT_USAGE:
86 return NULL;
87 }
88
89 /* Queries are normally read by the CPU after
90 * being written by the gpu, hence staging is probably a good
91 * usage pattern.
92 */
93 struct r600_resource *buf = (struct r600_resource*)
94 pipe_buffer_create(ctx->b.screen, PIPE_BIND_CUSTOM,
95 PIPE_USAGE_STAGING, buf_size);
96
97 switch (type) {
98 case PIPE_QUERY_OCCLUSION_COUNTER:
99 case PIPE_QUERY_OCCLUSION_PREDICATE:
100 results = r600_buffer_map_sync_with_rings(ctx, buf, PIPE_TRANSFER_WRITE);
101 memset(results, 0, buf_size);
102
103 /* Set top bits for unused backends. */
104 num_results = buf_size / (16 * ctx->max_db);
105 for (j = 0; j < num_results; j++) {
106 for (i = 0; i < ctx->max_db; i++) {
107 if (!(ctx->backend_mask & (1<<i))) {
108 results[(i * 4)+1] = 0x80000000;
109 results[(i * 4)+3] = 0x80000000;
110 }
111 }
112 results += 4 * ctx->max_db;
113 }
114 ctx->ws->buffer_unmap(buf->cs_buf);
115 break;
116 case PIPE_QUERY_GPU_FINISHED:
117 case PIPE_QUERY_TIME_ELAPSED:
118 case PIPE_QUERY_TIMESTAMP:
119 case PIPE_QUERY_TIMESTAMP_DISJOINT:
120 break;
121 case PIPE_QUERY_PRIMITIVES_EMITTED:
122 case PIPE_QUERY_PRIMITIVES_GENERATED:
123 case PIPE_QUERY_SO_STATISTICS:
124 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
125 case PIPE_QUERY_PIPELINE_STATISTICS:
126 results = r600_buffer_map_sync_with_rings(ctx, buf, PIPE_TRANSFER_WRITE);
127 memset(results, 0, buf_size);
128 ctx->ws->buffer_unmap(buf->cs_buf);
129 break;
130 default:
131 assert(0);
132 }
133 return buf;
134 }
135
136 static void r600_update_occlusion_query_state(struct r600_common_context *rctx,
137 unsigned type, int diff)
138 {
139 if (type == PIPE_QUERY_OCCLUSION_COUNTER ||
140 type == PIPE_QUERY_OCCLUSION_PREDICATE) {
141 bool old_enable = rctx->num_occlusion_queries != 0;
142 bool enable;
143
144 rctx->num_occlusion_queries += diff;
145 assert(rctx->num_occlusion_queries >= 0);
146
147 enable = rctx->num_occlusion_queries != 0;
148
149 if (enable != old_enable) {
150 rctx->set_occlusion_query_state(&rctx->b, enable);
151 }
152 }
153 }
154
155 static void r600_emit_query_begin(struct r600_common_context *ctx, struct r600_query *query)
156 {
157 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
158 uint64_t va;
159
160 r600_update_occlusion_query_state(ctx, query->type, 1);
161 r600_update_prims_generated_query_state(ctx, query->type, 1);
162 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw * 2, TRUE);
163
164 /* Get a new query buffer if needed. */
165 if (query->buffer.results_end + query->result_size > query->buffer.buf->b.b.width0) {
166 struct r600_query_buffer *qbuf = MALLOC_STRUCT(r600_query_buffer);
167 *qbuf = query->buffer;
168 query->buffer.buf = r600_new_query_buffer(ctx, query->type);
169 query->buffer.results_end = 0;
170 query->buffer.previous = qbuf;
171 }
172
173 /* emit begin query */
174 va = r600_resource_va(ctx->b.screen, (void*)query->buffer.buf);
175 va += query->buffer.results_end;
176
177 switch (query->type) {
178 case PIPE_QUERY_OCCLUSION_COUNTER:
179 case PIPE_QUERY_OCCLUSION_PREDICATE:
180 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
181 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
182 radeon_emit(cs, va);
183 radeon_emit(cs, (va >> 32UL) & 0xFF);
184 break;
185 case PIPE_QUERY_PRIMITIVES_EMITTED:
186 case PIPE_QUERY_PRIMITIVES_GENERATED:
187 case PIPE_QUERY_SO_STATISTICS:
188 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
189 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
190 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3));
191 radeon_emit(cs, va);
192 radeon_emit(cs, (va >> 32UL) & 0xFF);
193 break;
194 case PIPE_QUERY_TIME_ELAPSED:
195 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
196 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
197 radeon_emit(cs, va);
198 radeon_emit(cs, (3 << 29) | ((va >> 32UL) & 0xFF));
199 radeon_emit(cs, 0);
200 radeon_emit(cs, 0);
201 break;
202 case PIPE_QUERY_PIPELINE_STATISTICS:
203 if (!ctx->num_pipelinestat_queries) {
204 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
205 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
206 }
207 ctx->num_pipelinestat_queries++;
208 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
209 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
210 radeon_emit(cs, va);
211 radeon_emit(cs, (va >> 32UL) & 0xFF);
212 break;
213 case PIPE_QUERY_TIMESTAMP_DISJOINT:
214 break;
215 default:
216 assert(0);
217 }
218 r600_emit_reloc(ctx, &ctx->rings.gfx, query->buffer.buf, RADEON_USAGE_WRITE,
219 RADEON_PRIO_MIN);
220
221 if (!r600_is_timer_query(query->type)) {
222 ctx->num_cs_dw_nontimer_queries_suspend += query->num_cs_dw;
223 }
224 }
225
226 static void r600_emit_query_end(struct r600_common_context *ctx, struct r600_query *query)
227 {
228 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
229 uint64_t va;
230
231 /* The queries which need begin already called this in begin_query. */
232 if (!r600_query_needs_begin(query->type)) {
233 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw, FALSE);
234 }
235
236 va = r600_resource_va(ctx->b.screen, (void*)query->buffer.buf);
237 /* emit end query */
238 switch (query->type) {
239 case PIPE_QUERY_OCCLUSION_COUNTER:
240 case PIPE_QUERY_OCCLUSION_PREDICATE:
241 va += query->buffer.results_end + 8;
242 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
243 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
244 radeon_emit(cs, va);
245 radeon_emit(cs, (va >> 32UL) & 0xFF);
246 break;
247 case PIPE_QUERY_PRIMITIVES_EMITTED:
248 case PIPE_QUERY_PRIMITIVES_GENERATED:
249 case PIPE_QUERY_SO_STATISTICS:
250 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
251 va += query->buffer.results_end + query->result_size/2;
252 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
253 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3));
254 radeon_emit(cs, va);
255 radeon_emit(cs, (va >> 32UL) & 0xFF);
256 break;
257 case PIPE_QUERY_TIME_ELAPSED:
258 va += query->buffer.results_end + query->result_size/2;
259 /* fall through */
260 case PIPE_QUERY_TIMESTAMP:
261 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
262 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
263 radeon_emit(cs, va);
264 radeon_emit(cs, (3 << 29) | ((va >> 32UL) & 0xFF));
265 radeon_emit(cs, 0);
266 radeon_emit(cs, 0);
267 break;
268 case PIPE_QUERY_PIPELINE_STATISTICS:
269 assert(ctx->num_pipelinestat_queries > 0);
270 ctx->num_pipelinestat_queries--;
271 if (!ctx->num_pipelinestat_queries) {
272 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
273 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_STOP) | EVENT_INDEX(0));
274 }
275 va += query->buffer.results_end + query->result_size/2;
276 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
277 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
278 radeon_emit(cs, va);
279 radeon_emit(cs, (va >> 32UL) & 0xFF);
280 break;
281 case PIPE_QUERY_GPU_FINISHED:
282 case PIPE_QUERY_TIMESTAMP_DISJOINT:
283 break;
284 default:
285 assert(0);
286 }
287 r600_emit_reloc(ctx, &ctx->rings.gfx, query->buffer.buf, RADEON_USAGE_WRITE,
288 RADEON_PRIO_MIN);
289
290 query->buffer.results_end += query->result_size;
291
292 if (r600_query_needs_begin(query->type)) {
293 if (!r600_is_timer_query(query->type)) {
294 ctx->num_cs_dw_nontimer_queries_suspend -= query->num_cs_dw;
295 }
296 }
297
298 r600_update_occlusion_query_state(ctx, query->type, -1);
299 r600_update_prims_generated_query_state(ctx, query->type, -1);
300 }
301
302 static void r600_emit_query_predication(struct r600_common_context *ctx, struct r600_query *query,
303 int operation, bool flag_wait)
304 {
305 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
306
307 if (operation == PREDICATION_OP_CLEAR) {
308 ctx->need_gfx_cs_space(&ctx->b, 3, FALSE);
309
310 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
311 radeon_emit(cs, 0);
312 radeon_emit(cs, PRED_OP(PREDICATION_OP_CLEAR));
313 } else {
314 struct r600_query_buffer *qbuf;
315 unsigned count;
316 uint32_t op;
317
318 /* Find how many results there are. */
319 count = 0;
320 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
321 count += qbuf->results_end / query->result_size;
322 }
323
324 ctx->need_gfx_cs_space(&ctx->b, 5 * count, TRUE);
325
326 op = PRED_OP(operation) | PREDICATION_DRAW_VISIBLE |
327 (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW);
328
329 /* emit predicate packets for all data blocks */
330 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
331 unsigned results_base = 0;
332 uint64_t va = r600_resource_va(ctx->b.screen, &qbuf->buf->b.b);
333
334 while (results_base < qbuf->results_end) {
335 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
336 radeon_emit(cs, (va + results_base) & 0xFFFFFFFFUL);
337 radeon_emit(cs, op | (((va + results_base) >> 32UL) & 0xFF));
338 r600_emit_reloc(ctx, &ctx->rings.gfx, qbuf->buf, RADEON_USAGE_READ,
339 RADEON_PRIO_MIN);
340 results_base += query->result_size;
341
342 /* set CONTINUE bit for all packets except the first */
343 op |= PREDICATION_CONTINUE;
344 }
345 }
346 }
347 }
348
349 static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type)
350 {
351 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
352 struct r600_query *query;
353 bool skip_allocation = false;
354
355 query = CALLOC_STRUCT(r600_query);
356 if (query == NULL)
357 return NULL;
358
359 query->type = query_type;
360
361 switch (query_type) {
362 case PIPE_QUERY_OCCLUSION_COUNTER:
363 case PIPE_QUERY_OCCLUSION_PREDICATE:
364 query->result_size = 16 * rctx->max_db;
365 query->num_cs_dw = 6;
366 break;
367 case PIPE_QUERY_GPU_FINISHED:
368 query->num_cs_dw = 2;
369 break;
370 case PIPE_QUERY_TIME_ELAPSED:
371 query->result_size = 16;
372 query->num_cs_dw = 8;
373 break;
374 case PIPE_QUERY_TIMESTAMP:
375 query->result_size = 8;
376 query->num_cs_dw = 8;
377 break;
378 case PIPE_QUERY_TIMESTAMP_DISJOINT:
379 break;
380 case PIPE_QUERY_PRIMITIVES_EMITTED:
381 case PIPE_QUERY_PRIMITIVES_GENERATED:
382 case PIPE_QUERY_SO_STATISTICS:
383 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
384 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
385 query->result_size = 32;
386 query->num_cs_dw = 6;
387 break;
388 case PIPE_QUERY_PIPELINE_STATISTICS:
389 /* 11 values on EG, 8 on R600. */
390 query->result_size = (rctx->chip_class >= EVERGREEN ? 11 : 8) * 16;
391 query->num_cs_dw = 8;
392 break;
393 /* Non-GPU queries. */
394 case R600_QUERY_DRAW_CALLS:
395 case R600_QUERY_REQUESTED_VRAM:
396 case R600_QUERY_REQUESTED_GTT:
397 case R600_QUERY_BUFFER_WAIT_TIME:
398 case R600_QUERY_NUM_CS_FLUSHES:
399 case R600_QUERY_NUM_BYTES_MOVED:
400 case R600_QUERY_VRAM_USAGE:
401 case R600_QUERY_GTT_USAGE:
402 skip_allocation = true;
403 break;
404 default:
405 assert(0);
406 FREE(query);
407 return NULL;
408 }
409
410 if (!skip_allocation) {
411 query->buffer.buf = r600_new_query_buffer(rctx, query_type);
412 if (!query->buffer.buf) {
413 FREE(query);
414 return NULL;
415 }
416 }
417 return (struct pipe_query*)query;
418 }
419
420 static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
421 {
422 struct r600_query *rquery = (struct r600_query*)query;
423 struct r600_query_buffer *prev = rquery->buffer.previous;
424
425 /* Release all query buffers. */
426 while (prev) {
427 struct r600_query_buffer *qbuf = prev;
428 prev = prev->previous;
429 pipe_resource_reference((struct pipe_resource**)&qbuf->buf, NULL);
430 FREE(qbuf);
431 }
432
433 pipe_resource_reference((struct pipe_resource**)&rquery->buffer.buf, NULL);
434 FREE(query);
435 }
436
437 static void r600_begin_query(struct pipe_context *ctx, struct pipe_query *query)
438 {
439 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
440 struct r600_query *rquery = (struct r600_query *)query;
441 struct r600_query_buffer *prev = rquery->buffer.previous;
442
443 if (!r600_query_needs_begin(rquery->type)) {
444 assert(0);
445 return;
446 }
447
448 /* Non-GPU queries. */
449 switch (rquery->type) {
450 case R600_QUERY_DRAW_CALLS:
451 rquery->begin_result = rctx->num_draw_calls;
452 return;
453 case R600_QUERY_REQUESTED_VRAM:
454 case R600_QUERY_REQUESTED_GTT:
455 case R600_QUERY_VRAM_USAGE:
456 case R600_QUERY_GTT_USAGE:
457 rquery->begin_result = 0;
458 return;
459 case R600_QUERY_BUFFER_WAIT_TIME:
460 rquery->begin_result = rctx->ws->query_value(rctx->ws, RADEON_BUFFER_WAIT_TIME_NS);
461 return;
462 case R600_QUERY_NUM_CS_FLUSHES:
463 rquery->begin_result = rctx->ws->query_value(rctx->ws, RADEON_NUM_CS_FLUSHES);
464 return;
465 case R600_QUERY_NUM_BYTES_MOVED:
466 rquery->begin_result = rctx->ws->query_value(rctx->ws, RADEON_NUM_BYTES_MOVED);
467 return;
468 }
469
470 /* Discard the old query buffers. */
471 while (prev) {
472 struct r600_query_buffer *qbuf = prev;
473 prev = prev->previous;
474 pipe_resource_reference((struct pipe_resource**)&qbuf->buf, NULL);
475 FREE(qbuf);
476 }
477
478 /* Obtain a new buffer if the current one can't be mapped without a stall. */
479 if (r600_rings_is_buffer_referenced(rctx, rquery->buffer.buf->cs_buf, RADEON_USAGE_READWRITE) ||
480 rctx->ws->buffer_is_busy(rquery->buffer.buf->buf, RADEON_USAGE_READWRITE)) {
481 pipe_resource_reference((struct pipe_resource**)&rquery->buffer.buf, NULL);
482 rquery->buffer.buf = r600_new_query_buffer(rctx, rquery->type);
483 }
484
485 rquery->buffer.results_end = 0;
486 rquery->buffer.previous = NULL;
487
488 r600_emit_query_begin(rctx, rquery);
489
490 if (!r600_is_timer_query(rquery->type)) {
491 LIST_ADDTAIL(&rquery->list, &rctx->active_nontimer_queries);
492 }
493 }
494
495 static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
496 {
497 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
498 struct r600_query *rquery = (struct r600_query *)query;
499
500 /* Non-GPU queries. */
501 switch (rquery->type) {
502 case R600_QUERY_DRAW_CALLS:
503 rquery->end_result = rctx->num_draw_calls;
504 return;
505 case R600_QUERY_REQUESTED_VRAM:
506 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_REQUESTED_VRAM_MEMORY);
507 return;
508 case R600_QUERY_REQUESTED_GTT:
509 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_REQUESTED_GTT_MEMORY);
510 return;
511 case R600_QUERY_BUFFER_WAIT_TIME:
512 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_BUFFER_WAIT_TIME_NS);
513 return;
514 case R600_QUERY_NUM_CS_FLUSHES:
515 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_NUM_CS_FLUSHES);
516 return;
517 case R600_QUERY_NUM_BYTES_MOVED:
518 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_NUM_BYTES_MOVED);
519 return;
520 case R600_QUERY_VRAM_USAGE:
521 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_VRAM_USAGE);
522 return;
523 case R600_QUERY_GTT_USAGE:
524 rquery->end_result = rctx->ws->query_value(rctx->ws, RADEON_GTT_USAGE);
525 return;
526 }
527
528 r600_emit_query_end(rctx, rquery);
529
530 if (r600_query_needs_begin(rquery->type) && !r600_is_timer_query(rquery->type)) {
531 LIST_DELINIT(&rquery->list);
532 }
533 }
534
535 static unsigned r600_query_read_result(char *map, unsigned start_index, unsigned end_index,
536 bool test_status_bit)
537 {
538 uint32_t *current_result = (uint32_t*)map;
539 uint64_t start, end;
540
541 start = (uint64_t)current_result[start_index] |
542 (uint64_t)current_result[start_index+1] << 32;
543 end = (uint64_t)current_result[end_index] |
544 (uint64_t)current_result[end_index+1] << 32;
545
546 if (!test_status_bit ||
547 ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) {
548 return end - start;
549 }
550 return 0;
551 }
552
553 static boolean r600_get_query_buffer_result(struct r600_common_context *ctx,
554 struct r600_query *query,
555 struct r600_query_buffer *qbuf,
556 boolean wait,
557 union pipe_query_result *result)
558 {
559 unsigned results_base = 0;
560 char *map;
561
562 /* Non-GPU queries. */
563 switch (query->type) {
564 case R600_QUERY_DRAW_CALLS:
565 case R600_QUERY_REQUESTED_VRAM:
566 case R600_QUERY_REQUESTED_GTT:
567 case R600_QUERY_BUFFER_WAIT_TIME:
568 case R600_QUERY_NUM_CS_FLUSHES:
569 case R600_QUERY_NUM_BYTES_MOVED:
570 case R600_QUERY_VRAM_USAGE:
571 case R600_QUERY_GTT_USAGE:
572 result->u64 = query->end_result - query->begin_result;
573 return TRUE;
574 }
575
576 map = r600_buffer_map_sync_with_rings(ctx, qbuf->buf,
577 PIPE_TRANSFER_READ |
578 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK));
579 if (!map)
580 return FALSE;
581
582 /* count all results across all data blocks */
583 switch (query->type) {
584 case PIPE_QUERY_OCCLUSION_COUNTER:
585 while (results_base != qbuf->results_end) {
586 result->u64 +=
587 r600_query_read_result(map + results_base, 0, 2, true);
588 results_base += 16;
589 }
590 break;
591 case PIPE_QUERY_OCCLUSION_PREDICATE:
592 while (results_base != qbuf->results_end) {
593 result->b = result->b ||
594 r600_query_read_result(map + results_base, 0, 2, true) != 0;
595 results_base += 16;
596 }
597 break;
598 case PIPE_QUERY_GPU_FINISHED:
599 result->b = TRUE;
600 break;
601 case PIPE_QUERY_TIME_ELAPSED:
602 while (results_base != qbuf->results_end) {
603 result->u64 +=
604 r600_query_read_result(map + results_base, 0, 2, false);
605 results_base += query->result_size;
606 }
607 break;
608 case PIPE_QUERY_TIMESTAMP:
609 {
610 uint32_t *current_result = (uint32_t*)map;
611 result->u64 = (uint64_t)current_result[0] |
612 (uint64_t)current_result[1] << 32;
613 break;
614 }
615 case PIPE_QUERY_TIMESTAMP_DISJOINT:
616 /* Convert from cycles per millisecond to cycles per second (Hz). */
617 result->timestamp_disjoint.frequency =
618 (uint64_t)ctx->screen->info.r600_clock_crystal_freq * 1000;
619 result->timestamp_disjoint.disjoint = FALSE;
620 break;
621 case PIPE_QUERY_PRIMITIVES_EMITTED:
622 /* SAMPLE_STREAMOUTSTATS stores this structure:
623 * {
624 * u64 NumPrimitivesWritten;
625 * u64 PrimitiveStorageNeeded;
626 * }
627 * We only need NumPrimitivesWritten here. */
628 while (results_base != qbuf->results_end) {
629 result->u64 +=
630 r600_query_read_result(map + results_base, 2, 6, true);
631 results_base += query->result_size;
632 }
633 break;
634 case PIPE_QUERY_PRIMITIVES_GENERATED:
635 /* Here we read PrimitiveStorageNeeded. */
636 while (results_base != qbuf->results_end) {
637 result->u64 +=
638 r600_query_read_result(map + results_base, 0, 4, true);
639 results_base += query->result_size;
640 }
641 break;
642 case PIPE_QUERY_SO_STATISTICS:
643 while (results_base != qbuf->results_end) {
644 result->so_statistics.num_primitives_written +=
645 r600_query_read_result(map + results_base, 2, 6, true);
646 result->so_statistics.primitives_storage_needed +=
647 r600_query_read_result(map + results_base, 0, 4, true);
648 results_base += query->result_size;
649 }
650 break;
651 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
652 while (results_base != qbuf->results_end) {
653 result->b = result->b ||
654 r600_query_read_result(map + results_base, 2, 6, true) !=
655 r600_query_read_result(map + results_base, 0, 4, true);
656 results_base += query->result_size;
657 }
658 break;
659 case PIPE_QUERY_PIPELINE_STATISTICS:
660 if (ctx->chip_class >= EVERGREEN) {
661 while (results_base != qbuf->results_end) {
662 result->pipeline_statistics.ps_invocations +=
663 r600_query_read_result(map + results_base, 0, 22, false);
664 result->pipeline_statistics.c_primitives +=
665 r600_query_read_result(map + results_base, 2, 24, false);
666 result->pipeline_statistics.c_invocations +=
667 r600_query_read_result(map + results_base, 4, 26, false);
668 result->pipeline_statistics.vs_invocations +=
669 r600_query_read_result(map + results_base, 6, 28, false);
670 result->pipeline_statistics.gs_invocations +=
671 r600_query_read_result(map + results_base, 8, 30, false);
672 result->pipeline_statistics.gs_primitives +=
673 r600_query_read_result(map + results_base, 10, 32, false);
674 result->pipeline_statistics.ia_primitives +=
675 r600_query_read_result(map + results_base, 12, 34, false);
676 result->pipeline_statistics.ia_vertices +=
677 r600_query_read_result(map + results_base, 14, 36, false);
678 result->pipeline_statistics.hs_invocations +=
679 r600_query_read_result(map + results_base, 16, 38, false);
680 result->pipeline_statistics.ds_invocations +=
681 r600_query_read_result(map + results_base, 18, 40, false);
682 result->pipeline_statistics.cs_invocations +=
683 r600_query_read_result(map + results_base, 20, 42, false);
684 results_base += query->result_size;
685 }
686 } else {
687 while (results_base != qbuf->results_end) {
688 result->pipeline_statistics.ps_invocations +=
689 r600_query_read_result(map + results_base, 0, 16, false);
690 result->pipeline_statistics.c_primitives +=
691 r600_query_read_result(map + results_base, 2, 18, false);
692 result->pipeline_statistics.c_invocations +=
693 r600_query_read_result(map + results_base, 4, 20, false);
694 result->pipeline_statistics.vs_invocations +=
695 r600_query_read_result(map + results_base, 6, 22, false);
696 result->pipeline_statistics.gs_invocations +=
697 r600_query_read_result(map + results_base, 8, 24, false);
698 result->pipeline_statistics.gs_primitives +=
699 r600_query_read_result(map + results_base, 10, 26, false);
700 result->pipeline_statistics.ia_primitives +=
701 r600_query_read_result(map + results_base, 12, 28, false);
702 result->pipeline_statistics.ia_vertices +=
703 r600_query_read_result(map + results_base, 14, 30, false);
704 results_base += query->result_size;
705 }
706 }
707 #if 0 /* for testing */
708 printf("Pipeline stats: IA verts=%llu, IA prims=%llu, VS=%llu, HS=%llu, "
709 "DS=%llu, GS=%llu, GS prims=%llu, Clipper=%llu, "
710 "Clipper prims=%llu, PS=%llu, CS=%llu\n",
711 result->pipeline_statistics.ia_vertices,
712 result->pipeline_statistics.ia_primitives,
713 result->pipeline_statistics.vs_invocations,
714 result->pipeline_statistics.hs_invocations,
715 result->pipeline_statistics.ds_invocations,
716 result->pipeline_statistics.gs_invocations,
717 result->pipeline_statistics.gs_primitives,
718 result->pipeline_statistics.c_invocations,
719 result->pipeline_statistics.c_primitives,
720 result->pipeline_statistics.ps_invocations,
721 result->pipeline_statistics.cs_invocations);
722 #endif
723 break;
724 default:
725 assert(0);
726 }
727
728 ctx->ws->buffer_unmap(qbuf->buf->cs_buf);
729 return TRUE;
730 }
731
732 static boolean r600_get_query_result(struct pipe_context *ctx,
733 struct pipe_query *query,
734 boolean wait, union pipe_query_result *result)
735 {
736 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
737 struct r600_query *rquery = (struct r600_query *)query;
738 struct r600_query_buffer *qbuf;
739
740 util_query_clear_result(result, rquery->type);
741
742 for (qbuf = &rquery->buffer; qbuf; qbuf = qbuf->previous) {
743 if (!r600_get_query_buffer_result(rctx, rquery, qbuf, wait, result)) {
744 return FALSE;
745 }
746 }
747
748 /* Convert the time to expected units. */
749 if (rquery->type == PIPE_QUERY_TIME_ELAPSED ||
750 rquery->type == PIPE_QUERY_TIMESTAMP) {
751 result->u64 = (1000000 * result->u64) / rctx->screen->info.r600_clock_crystal_freq;
752 }
753 return TRUE;
754 }
755
756 static void r600_render_condition(struct pipe_context *ctx,
757 struct pipe_query *query,
758 boolean condition,
759 uint mode)
760 {
761 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
762 struct r600_query *rquery = (struct r600_query *)query;
763 bool wait_flag = false;
764
765 rctx->current_render_cond = query;
766 rctx->current_render_cond_cond = condition;
767 rctx->current_render_cond_mode = mode;
768
769 if (query == NULL) {
770 if (rctx->predicate_drawing) {
771 rctx->predicate_drawing = false;
772 r600_emit_query_predication(rctx, NULL, PREDICATION_OP_CLEAR, false);
773 }
774 return;
775 }
776
777 if (mode == PIPE_RENDER_COND_WAIT ||
778 mode == PIPE_RENDER_COND_BY_REGION_WAIT) {
779 wait_flag = true;
780 }
781
782 rctx->predicate_drawing = true;
783
784 switch (rquery->type) {
785 case PIPE_QUERY_OCCLUSION_COUNTER:
786 case PIPE_QUERY_OCCLUSION_PREDICATE:
787 r600_emit_query_predication(rctx, rquery, PREDICATION_OP_ZPASS, wait_flag);
788 break;
789 case PIPE_QUERY_PRIMITIVES_EMITTED:
790 case PIPE_QUERY_PRIMITIVES_GENERATED:
791 case PIPE_QUERY_SO_STATISTICS:
792 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
793 r600_emit_query_predication(rctx, rquery, PREDICATION_OP_PRIMCOUNT, wait_flag);
794 break;
795 default:
796 assert(0);
797 }
798 }
799
800 void r600_suspend_nontimer_queries(struct r600_common_context *ctx)
801 {
802 struct r600_query *query;
803
804 LIST_FOR_EACH_ENTRY(query, &ctx->active_nontimer_queries, list) {
805 r600_emit_query_end(ctx, query);
806 }
807 assert(ctx->num_cs_dw_nontimer_queries_suspend == 0);
808 }
809
810 void r600_resume_nontimer_queries(struct r600_common_context *ctx)
811 {
812 struct r600_query *query;
813
814 assert(ctx->num_cs_dw_nontimer_queries_suspend == 0);
815
816 LIST_FOR_EACH_ENTRY(query, &ctx->active_nontimer_queries, list) {
817 r600_emit_query_begin(ctx, query);
818 }
819 }
820
821 /* Get backends mask */
822 void r600_query_init_backend_mask(struct r600_common_context *ctx)
823 {
824 struct radeon_winsys_cs *cs = ctx->rings.gfx.cs;
825 struct r600_resource *buffer;
826 uint32_t *results;
827 unsigned num_backends = ctx->screen->info.r600_num_backends;
828 unsigned i, mask = 0;
829 uint64_t va;
830
831 /* if backend_map query is supported by the kernel */
832 if (ctx->screen->info.r600_backend_map_valid) {
833 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
834 unsigned backend_map = ctx->screen->info.r600_backend_map;
835 unsigned item_width, item_mask;
836
837 if (ctx->chip_class >= EVERGREEN) {
838 item_width = 4;
839 item_mask = 0x7;
840 } else {
841 item_width = 2;
842 item_mask = 0x3;
843 }
844
845 while(num_tile_pipes--) {
846 i = backend_map & item_mask;
847 mask |= (1<<i);
848 backend_map >>= item_width;
849 }
850 if (mask != 0) {
851 ctx->backend_mask = mask;
852 return;
853 }
854 }
855
856 /* otherwise backup path for older kernels */
857
858 /* create buffer for event data */
859 buffer = (struct r600_resource*)
860 pipe_buffer_create(ctx->b.screen, PIPE_BIND_CUSTOM,
861 PIPE_USAGE_STAGING, ctx->max_db*16);
862 if (!buffer)
863 goto err;
864 va = r600_resource_va(ctx->b.screen, (void*)buffer);
865
866 /* initialize buffer with zeroes */
867 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE);
868 if (results) {
869 memset(results, 0, ctx->max_db * 4 * 4);
870 ctx->ws->buffer_unmap(buffer->cs_buf);
871
872 /* emit EVENT_WRITE for ZPASS_DONE */
873 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
874 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
875 radeon_emit(cs, va);
876 radeon_emit(cs, va >> 32);
877
878 r600_emit_reloc(ctx, &ctx->rings.gfx, buffer, RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
879
880 /* analyze results */
881 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ);
882 if (results) {
883 for(i = 0; i < ctx->max_db; i++) {
884 /* at least highest bit will be set if backend is used */
885 if (results[i*4 + 1])
886 mask |= (1<<i);
887 }
888 ctx->ws->buffer_unmap(buffer->cs_buf);
889 }
890 }
891
892 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
893
894 if (mask != 0) {
895 ctx->backend_mask = mask;
896 return;
897 }
898
899 err:
900 /* fallback to old method - set num_backends lower bits to 1 */
901 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
902 return;
903 }
904
905 void r600_query_init(struct r600_common_context *rctx)
906 {
907 rctx->b.create_query = r600_create_query;
908 rctx->b.destroy_query = r600_destroy_query;
909 rctx->b.begin_query = r600_begin_query;
910 rctx->b.end_query = r600_end_query;
911 rctx->b.get_query_result = r600_get_query_result;
912
913 if (((struct r600_common_screen*)rctx->b.screen)->info.r600_num_backends > 0)
914 rctx->b.render_condition = r600_render_condition;
915
916 LIST_INITHEAD(&rctx->active_nontimer_queries);
917 }