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[mesa.git] / src / gallium / drivers / radeon / r600_query.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014 Marek Olšák <marek.olsak@amd.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "radeonsi/si_pipe.h"
26 #include "r600_query.h"
27 #include "r600_cs.h"
28 #include "util/u_memory.h"
29 #include "util/u_upload_mgr.h"
30 #include "util/os_time.h"
31 #include "tgsi/tgsi_text.h"
32 #include "amd/common/sid.h"
33
34 #define R600_MAX_STREAMS 4
35
36 struct r600_hw_query_params {
37 unsigned start_offset;
38 unsigned end_offset;
39 unsigned fence_offset;
40 unsigned pair_stride;
41 unsigned pair_count;
42 };
43
44 /* Queries without buffer handling or suspend/resume. */
45 struct r600_query_sw {
46 struct r600_query b;
47
48 uint64_t begin_result;
49 uint64_t end_result;
50
51 uint64_t begin_time;
52 uint64_t end_time;
53
54 /* Fence for GPU_FINISHED. */
55 struct pipe_fence_handle *fence;
56 };
57
58 static void r600_query_sw_destroy(struct si_screen *sscreen,
59 struct r600_query *rquery)
60 {
61 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
62
63 sscreen->b.fence_reference(&sscreen->b, &query->fence, NULL);
64 FREE(query);
65 }
66
67 static enum radeon_value_id winsys_id_from_type(unsigned type)
68 {
69 switch (type) {
70 case R600_QUERY_REQUESTED_VRAM: return RADEON_REQUESTED_VRAM_MEMORY;
71 case R600_QUERY_REQUESTED_GTT: return RADEON_REQUESTED_GTT_MEMORY;
72 case R600_QUERY_MAPPED_VRAM: return RADEON_MAPPED_VRAM;
73 case R600_QUERY_MAPPED_GTT: return RADEON_MAPPED_GTT;
74 case R600_QUERY_BUFFER_WAIT_TIME: return RADEON_BUFFER_WAIT_TIME_NS;
75 case R600_QUERY_NUM_MAPPED_BUFFERS: return RADEON_NUM_MAPPED_BUFFERS;
76 case R600_QUERY_NUM_GFX_IBS: return RADEON_NUM_GFX_IBS;
77 case R600_QUERY_NUM_SDMA_IBS: return RADEON_NUM_SDMA_IBS;
78 case R600_QUERY_GFX_BO_LIST_SIZE: return RADEON_GFX_BO_LIST_COUNTER;
79 case R600_QUERY_GFX_IB_SIZE: return RADEON_GFX_IB_SIZE_COUNTER;
80 case R600_QUERY_NUM_BYTES_MOVED: return RADEON_NUM_BYTES_MOVED;
81 case R600_QUERY_NUM_EVICTIONS: return RADEON_NUM_EVICTIONS;
82 case R600_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: return RADEON_NUM_VRAM_CPU_PAGE_FAULTS;
83 case R600_QUERY_VRAM_USAGE: return RADEON_VRAM_USAGE;
84 case R600_QUERY_VRAM_VIS_USAGE: return RADEON_VRAM_VIS_USAGE;
85 case R600_QUERY_GTT_USAGE: return RADEON_GTT_USAGE;
86 case R600_QUERY_GPU_TEMPERATURE: return RADEON_GPU_TEMPERATURE;
87 case R600_QUERY_CURRENT_GPU_SCLK: return RADEON_CURRENT_SCLK;
88 case R600_QUERY_CURRENT_GPU_MCLK: return RADEON_CURRENT_MCLK;
89 case R600_QUERY_CS_THREAD_BUSY: return RADEON_CS_THREAD_TIME;
90 default: unreachable("query type does not correspond to winsys id");
91 }
92 }
93
94 static bool r600_query_sw_begin(struct r600_common_context *rctx,
95 struct r600_query *rquery)
96 {
97 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
98 enum radeon_value_id ws_id;
99
100 switch(query->b.type) {
101 case PIPE_QUERY_TIMESTAMP_DISJOINT:
102 case PIPE_QUERY_GPU_FINISHED:
103 break;
104 case R600_QUERY_DRAW_CALLS:
105 query->begin_result = rctx->num_draw_calls;
106 break;
107 case R600_QUERY_DECOMPRESS_CALLS:
108 query->begin_result = rctx->num_decompress_calls;
109 break;
110 case R600_QUERY_MRT_DRAW_CALLS:
111 query->begin_result = rctx->num_mrt_draw_calls;
112 break;
113 case R600_QUERY_PRIM_RESTART_CALLS:
114 query->begin_result = rctx->num_prim_restart_calls;
115 break;
116 case R600_QUERY_SPILL_DRAW_CALLS:
117 query->begin_result = rctx->num_spill_draw_calls;
118 break;
119 case R600_QUERY_COMPUTE_CALLS:
120 query->begin_result = rctx->num_compute_calls;
121 break;
122 case R600_QUERY_SPILL_COMPUTE_CALLS:
123 query->begin_result = rctx->num_spill_compute_calls;
124 break;
125 case R600_QUERY_DMA_CALLS:
126 query->begin_result = rctx->num_dma_calls;
127 break;
128 case R600_QUERY_CP_DMA_CALLS:
129 query->begin_result = rctx->num_cp_dma_calls;
130 break;
131 case R600_QUERY_NUM_VS_FLUSHES:
132 query->begin_result = rctx->num_vs_flushes;
133 break;
134 case R600_QUERY_NUM_PS_FLUSHES:
135 query->begin_result = rctx->num_ps_flushes;
136 break;
137 case R600_QUERY_NUM_CS_FLUSHES:
138 query->begin_result = rctx->num_cs_flushes;
139 break;
140 case R600_QUERY_NUM_CB_CACHE_FLUSHES:
141 query->begin_result = rctx->num_cb_cache_flushes;
142 break;
143 case R600_QUERY_NUM_DB_CACHE_FLUSHES:
144 query->begin_result = rctx->num_db_cache_flushes;
145 break;
146 case R600_QUERY_NUM_L2_INVALIDATES:
147 query->begin_result = rctx->num_L2_invalidates;
148 break;
149 case R600_QUERY_NUM_L2_WRITEBACKS:
150 query->begin_result = rctx->num_L2_writebacks;
151 break;
152 case R600_QUERY_NUM_RESIDENT_HANDLES:
153 query->begin_result = rctx->num_resident_handles;
154 break;
155 case R600_QUERY_TC_OFFLOADED_SLOTS:
156 query->begin_result = rctx->tc ? rctx->tc->num_offloaded_slots : 0;
157 break;
158 case R600_QUERY_TC_DIRECT_SLOTS:
159 query->begin_result = rctx->tc ? rctx->tc->num_direct_slots : 0;
160 break;
161 case R600_QUERY_TC_NUM_SYNCS:
162 query->begin_result = rctx->tc ? rctx->tc->num_syncs : 0;
163 break;
164 case R600_QUERY_REQUESTED_VRAM:
165 case R600_QUERY_REQUESTED_GTT:
166 case R600_QUERY_MAPPED_VRAM:
167 case R600_QUERY_MAPPED_GTT:
168 case R600_QUERY_VRAM_USAGE:
169 case R600_QUERY_VRAM_VIS_USAGE:
170 case R600_QUERY_GTT_USAGE:
171 case R600_QUERY_GPU_TEMPERATURE:
172 case R600_QUERY_CURRENT_GPU_SCLK:
173 case R600_QUERY_CURRENT_GPU_MCLK:
174 case R600_QUERY_BACK_BUFFER_PS_DRAW_RATIO:
175 case R600_QUERY_NUM_MAPPED_BUFFERS:
176 query->begin_result = 0;
177 break;
178 case R600_QUERY_BUFFER_WAIT_TIME:
179 case R600_QUERY_GFX_IB_SIZE:
180 case R600_QUERY_NUM_GFX_IBS:
181 case R600_QUERY_NUM_SDMA_IBS:
182 case R600_QUERY_NUM_BYTES_MOVED:
183 case R600_QUERY_NUM_EVICTIONS:
184 case R600_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: {
185 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
186 query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
187 break;
188 }
189 case R600_QUERY_GFX_BO_LIST_SIZE:
190 ws_id = winsys_id_from_type(query->b.type);
191 query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
192 query->begin_time = rctx->ws->query_value(rctx->ws,
193 RADEON_NUM_GFX_IBS);
194 break;
195 case R600_QUERY_CS_THREAD_BUSY:
196 ws_id = winsys_id_from_type(query->b.type);
197 query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
198 query->begin_time = os_time_get_nano();
199 break;
200 case R600_QUERY_GALLIUM_THREAD_BUSY:
201 query->begin_result =
202 rctx->tc ? util_queue_get_thread_time_nano(&rctx->tc->queue, 0) : 0;
203 query->begin_time = os_time_get_nano();
204 break;
205 case R600_QUERY_GPU_LOAD:
206 case R600_QUERY_GPU_SHADERS_BUSY:
207 case R600_QUERY_GPU_TA_BUSY:
208 case R600_QUERY_GPU_GDS_BUSY:
209 case R600_QUERY_GPU_VGT_BUSY:
210 case R600_QUERY_GPU_IA_BUSY:
211 case R600_QUERY_GPU_SX_BUSY:
212 case R600_QUERY_GPU_WD_BUSY:
213 case R600_QUERY_GPU_BCI_BUSY:
214 case R600_QUERY_GPU_SC_BUSY:
215 case R600_QUERY_GPU_PA_BUSY:
216 case R600_QUERY_GPU_DB_BUSY:
217 case R600_QUERY_GPU_CP_BUSY:
218 case R600_QUERY_GPU_CB_BUSY:
219 case R600_QUERY_GPU_SDMA_BUSY:
220 case R600_QUERY_GPU_PFP_BUSY:
221 case R600_QUERY_GPU_MEQ_BUSY:
222 case R600_QUERY_GPU_ME_BUSY:
223 case R600_QUERY_GPU_SURF_SYNC_BUSY:
224 case R600_QUERY_GPU_CP_DMA_BUSY:
225 case R600_QUERY_GPU_SCRATCH_RAM_BUSY:
226 query->begin_result = si_begin_counter(rctx->screen,
227 query->b.type);
228 break;
229 case R600_QUERY_NUM_COMPILATIONS:
230 query->begin_result = p_atomic_read(&rctx->screen->num_compilations);
231 break;
232 case R600_QUERY_NUM_SHADERS_CREATED:
233 query->begin_result = p_atomic_read(&rctx->screen->num_shaders_created);
234 break;
235 case R600_QUERY_NUM_SHADER_CACHE_HITS:
236 query->begin_result =
237 p_atomic_read(&rctx->screen->num_shader_cache_hits);
238 break;
239 case R600_QUERY_GPIN_ASIC_ID:
240 case R600_QUERY_GPIN_NUM_SIMD:
241 case R600_QUERY_GPIN_NUM_RB:
242 case R600_QUERY_GPIN_NUM_SPI:
243 case R600_QUERY_GPIN_NUM_SE:
244 break;
245 default:
246 unreachable("r600_query_sw_begin: bad query type");
247 }
248
249 return true;
250 }
251
252 static bool r600_query_sw_end(struct r600_common_context *rctx,
253 struct r600_query *rquery)
254 {
255 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
256 enum radeon_value_id ws_id;
257
258 switch(query->b.type) {
259 case PIPE_QUERY_TIMESTAMP_DISJOINT:
260 break;
261 case PIPE_QUERY_GPU_FINISHED:
262 rctx->b.flush(&rctx->b, &query->fence, PIPE_FLUSH_DEFERRED);
263 break;
264 case R600_QUERY_DRAW_CALLS:
265 query->end_result = rctx->num_draw_calls;
266 break;
267 case R600_QUERY_DECOMPRESS_CALLS:
268 query->end_result = rctx->num_decompress_calls;
269 break;
270 case R600_QUERY_MRT_DRAW_CALLS:
271 query->end_result = rctx->num_mrt_draw_calls;
272 break;
273 case R600_QUERY_PRIM_RESTART_CALLS:
274 query->end_result = rctx->num_prim_restart_calls;
275 break;
276 case R600_QUERY_SPILL_DRAW_CALLS:
277 query->end_result = rctx->num_spill_draw_calls;
278 break;
279 case R600_QUERY_COMPUTE_CALLS:
280 query->end_result = rctx->num_compute_calls;
281 break;
282 case R600_QUERY_SPILL_COMPUTE_CALLS:
283 query->end_result = rctx->num_spill_compute_calls;
284 break;
285 case R600_QUERY_DMA_CALLS:
286 query->end_result = rctx->num_dma_calls;
287 break;
288 case R600_QUERY_CP_DMA_CALLS:
289 query->end_result = rctx->num_cp_dma_calls;
290 break;
291 case R600_QUERY_NUM_VS_FLUSHES:
292 query->end_result = rctx->num_vs_flushes;
293 break;
294 case R600_QUERY_NUM_PS_FLUSHES:
295 query->end_result = rctx->num_ps_flushes;
296 break;
297 case R600_QUERY_NUM_CS_FLUSHES:
298 query->end_result = rctx->num_cs_flushes;
299 break;
300 case R600_QUERY_NUM_CB_CACHE_FLUSHES:
301 query->end_result = rctx->num_cb_cache_flushes;
302 break;
303 case R600_QUERY_NUM_DB_CACHE_FLUSHES:
304 query->end_result = rctx->num_db_cache_flushes;
305 break;
306 case R600_QUERY_NUM_L2_INVALIDATES:
307 query->end_result = rctx->num_L2_invalidates;
308 break;
309 case R600_QUERY_NUM_L2_WRITEBACKS:
310 query->end_result = rctx->num_L2_writebacks;
311 break;
312 case R600_QUERY_NUM_RESIDENT_HANDLES:
313 query->end_result = rctx->num_resident_handles;
314 break;
315 case R600_QUERY_TC_OFFLOADED_SLOTS:
316 query->end_result = rctx->tc ? rctx->tc->num_offloaded_slots : 0;
317 break;
318 case R600_QUERY_TC_DIRECT_SLOTS:
319 query->end_result = rctx->tc ? rctx->tc->num_direct_slots : 0;
320 break;
321 case R600_QUERY_TC_NUM_SYNCS:
322 query->end_result = rctx->tc ? rctx->tc->num_syncs : 0;
323 break;
324 case R600_QUERY_REQUESTED_VRAM:
325 case R600_QUERY_REQUESTED_GTT:
326 case R600_QUERY_MAPPED_VRAM:
327 case R600_QUERY_MAPPED_GTT:
328 case R600_QUERY_VRAM_USAGE:
329 case R600_QUERY_VRAM_VIS_USAGE:
330 case R600_QUERY_GTT_USAGE:
331 case R600_QUERY_GPU_TEMPERATURE:
332 case R600_QUERY_CURRENT_GPU_SCLK:
333 case R600_QUERY_CURRENT_GPU_MCLK:
334 case R600_QUERY_BUFFER_WAIT_TIME:
335 case R600_QUERY_GFX_IB_SIZE:
336 case R600_QUERY_NUM_MAPPED_BUFFERS:
337 case R600_QUERY_NUM_GFX_IBS:
338 case R600_QUERY_NUM_SDMA_IBS:
339 case R600_QUERY_NUM_BYTES_MOVED:
340 case R600_QUERY_NUM_EVICTIONS:
341 case R600_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: {
342 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
343 query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
344 break;
345 }
346 case R600_QUERY_GFX_BO_LIST_SIZE:
347 ws_id = winsys_id_from_type(query->b.type);
348 query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
349 query->end_time = rctx->ws->query_value(rctx->ws,
350 RADEON_NUM_GFX_IBS);
351 break;
352 case R600_QUERY_CS_THREAD_BUSY:
353 ws_id = winsys_id_from_type(query->b.type);
354 query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
355 query->end_time = os_time_get_nano();
356 break;
357 case R600_QUERY_GALLIUM_THREAD_BUSY:
358 query->end_result =
359 rctx->tc ? util_queue_get_thread_time_nano(&rctx->tc->queue, 0) : 0;
360 query->end_time = os_time_get_nano();
361 break;
362 case R600_QUERY_GPU_LOAD:
363 case R600_QUERY_GPU_SHADERS_BUSY:
364 case R600_QUERY_GPU_TA_BUSY:
365 case R600_QUERY_GPU_GDS_BUSY:
366 case R600_QUERY_GPU_VGT_BUSY:
367 case R600_QUERY_GPU_IA_BUSY:
368 case R600_QUERY_GPU_SX_BUSY:
369 case R600_QUERY_GPU_WD_BUSY:
370 case R600_QUERY_GPU_BCI_BUSY:
371 case R600_QUERY_GPU_SC_BUSY:
372 case R600_QUERY_GPU_PA_BUSY:
373 case R600_QUERY_GPU_DB_BUSY:
374 case R600_QUERY_GPU_CP_BUSY:
375 case R600_QUERY_GPU_CB_BUSY:
376 case R600_QUERY_GPU_SDMA_BUSY:
377 case R600_QUERY_GPU_PFP_BUSY:
378 case R600_QUERY_GPU_MEQ_BUSY:
379 case R600_QUERY_GPU_ME_BUSY:
380 case R600_QUERY_GPU_SURF_SYNC_BUSY:
381 case R600_QUERY_GPU_CP_DMA_BUSY:
382 case R600_QUERY_GPU_SCRATCH_RAM_BUSY:
383 query->end_result = si_end_counter(rctx->screen,
384 query->b.type,
385 query->begin_result);
386 query->begin_result = 0;
387 break;
388 case R600_QUERY_NUM_COMPILATIONS:
389 query->end_result = p_atomic_read(&rctx->screen->num_compilations);
390 break;
391 case R600_QUERY_NUM_SHADERS_CREATED:
392 query->end_result = p_atomic_read(&rctx->screen->num_shaders_created);
393 break;
394 case R600_QUERY_BACK_BUFFER_PS_DRAW_RATIO:
395 query->end_result = rctx->last_tex_ps_draw_ratio;
396 break;
397 case R600_QUERY_NUM_SHADER_CACHE_HITS:
398 query->end_result =
399 p_atomic_read(&rctx->screen->num_shader_cache_hits);
400 break;
401 case R600_QUERY_GPIN_ASIC_ID:
402 case R600_QUERY_GPIN_NUM_SIMD:
403 case R600_QUERY_GPIN_NUM_RB:
404 case R600_QUERY_GPIN_NUM_SPI:
405 case R600_QUERY_GPIN_NUM_SE:
406 break;
407 default:
408 unreachable("r600_query_sw_end: bad query type");
409 }
410
411 return true;
412 }
413
414 static bool r600_query_sw_get_result(struct r600_common_context *rctx,
415 struct r600_query *rquery,
416 bool wait,
417 union pipe_query_result *result)
418 {
419 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
420
421 switch (query->b.type) {
422 case PIPE_QUERY_TIMESTAMP_DISJOINT:
423 /* Convert from cycles per millisecond to cycles per second (Hz). */
424 result->timestamp_disjoint.frequency =
425 (uint64_t)rctx->screen->info.clock_crystal_freq * 1000;
426 result->timestamp_disjoint.disjoint = false;
427 return true;
428 case PIPE_QUERY_GPU_FINISHED: {
429 struct pipe_screen *screen = rctx->b.screen;
430 struct pipe_context *ctx = rquery->b.flushed ? NULL : &rctx->b;
431
432 result->b = screen->fence_finish(screen, ctx, query->fence,
433 wait ? PIPE_TIMEOUT_INFINITE : 0);
434 return result->b;
435 }
436
437 case R600_QUERY_GFX_BO_LIST_SIZE:
438 result->u64 = (query->end_result - query->begin_result) /
439 (query->end_time - query->begin_time);
440 return true;
441 case R600_QUERY_CS_THREAD_BUSY:
442 case R600_QUERY_GALLIUM_THREAD_BUSY:
443 result->u64 = (query->end_result - query->begin_result) * 100 /
444 (query->end_time - query->begin_time);
445 return true;
446 case R600_QUERY_GPIN_ASIC_ID:
447 result->u32 = 0;
448 return true;
449 case R600_QUERY_GPIN_NUM_SIMD:
450 result->u32 = rctx->screen->info.num_good_compute_units;
451 return true;
452 case R600_QUERY_GPIN_NUM_RB:
453 result->u32 = rctx->screen->info.num_render_backends;
454 return true;
455 case R600_QUERY_GPIN_NUM_SPI:
456 result->u32 = 1; /* all supported chips have one SPI per SE */
457 return true;
458 case R600_QUERY_GPIN_NUM_SE:
459 result->u32 = rctx->screen->info.max_se;
460 return true;
461 }
462
463 result->u64 = query->end_result - query->begin_result;
464
465 switch (query->b.type) {
466 case R600_QUERY_BUFFER_WAIT_TIME:
467 case R600_QUERY_GPU_TEMPERATURE:
468 result->u64 /= 1000;
469 break;
470 case R600_QUERY_CURRENT_GPU_SCLK:
471 case R600_QUERY_CURRENT_GPU_MCLK:
472 result->u64 *= 1000000;
473 break;
474 }
475
476 return true;
477 }
478
479
480 static struct r600_query_ops sw_query_ops = {
481 .destroy = r600_query_sw_destroy,
482 .begin = r600_query_sw_begin,
483 .end = r600_query_sw_end,
484 .get_result = r600_query_sw_get_result,
485 .get_result_resource = NULL
486 };
487
488 static struct pipe_query *r600_query_sw_create(unsigned query_type)
489 {
490 struct r600_query_sw *query;
491
492 query = CALLOC_STRUCT(r600_query_sw);
493 if (!query)
494 return NULL;
495
496 query->b.type = query_type;
497 query->b.ops = &sw_query_ops;
498
499 return (struct pipe_query *)query;
500 }
501
502 void si_query_hw_destroy(struct si_screen *sscreen,
503 struct r600_query *rquery)
504 {
505 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
506 struct r600_query_buffer *prev = query->buffer.previous;
507
508 /* Release all query buffers. */
509 while (prev) {
510 struct r600_query_buffer *qbuf = prev;
511 prev = prev->previous;
512 r600_resource_reference(&qbuf->buf, NULL);
513 FREE(qbuf);
514 }
515
516 r600_resource_reference(&query->buffer.buf, NULL);
517 r600_resource_reference(&query->workaround_buf, NULL);
518 FREE(rquery);
519 }
520
521 static struct r600_resource *r600_new_query_buffer(struct si_screen *sscreen,
522 struct r600_query_hw *query)
523 {
524 unsigned buf_size = MAX2(query->result_size,
525 sscreen->info.min_alloc_size);
526
527 /* Queries are normally read by the CPU after
528 * being written by the gpu, hence staging is probably a good
529 * usage pattern.
530 */
531 struct r600_resource *buf = (struct r600_resource*)
532 pipe_buffer_create(&sscreen->b, 0,
533 PIPE_USAGE_STAGING, buf_size);
534 if (!buf)
535 return NULL;
536
537 if (!query->ops->prepare_buffer(sscreen, query, buf)) {
538 r600_resource_reference(&buf, NULL);
539 return NULL;
540 }
541
542 return buf;
543 }
544
545 static bool r600_query_hw_prepare_buffer(struct si_screen *sscreen,
546 struct r600_query_hw *query,
547 struct r600_resource *buffer)
548 {
549 /* Callers ensure that the buffer is currently unused by the GPU. */
550 uint32_t *results = sscreen->ws->buffer_map(buffer->buf, NULL,
551 PIPE_TRANSFER_WRITE |
552 PIPE_TRANSFER_UNSYNCHRONIZED);
553 if (!results)
554 return false;
555
556 memset(results, 0, buffer->b.b.width0);
557
558 if (query->b.type == PIPE_QUERY_OCCLUSION_COUNTER ||
559 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE ||
560 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
561 unsigned max_rbs = sscreen->info.num_render_backends;
562 unsigned enabled_rb_mask = sscreen->info.enabled_rb_mask;
563 unsigned num_results;
564 unsigned i, j;
565
566 /* Set top bits for unused backends. */
567 num_results = buffer->b.b.width0 / query->result_size;
568 for (j = 0; j < num_results; j++) {
569 for (i = 0; i < max_rbs; i++) {
570 if (!(enabled_rb_mask & (1<<i))) {
571 results[(i * 4)+1] = 0x80000000;
572 results[(i * 4)+3] = 0x80000000;
573 }
574 }
575 results += 4 * max_rbs;
576 }
577 }
578
579 return true;
580 }
581
582 static void r600_query_hw_get_result_resource(struct r600_common_context *rctx,
583 struct r600_query *rquery,
584 bool wait,
585 enum pipe_query_value_type result_type,
586 int index,
587 struct pipe_resource *resource,
588 unsigned offset);
589
590 static struct r600_query_ops query_hw_ops = {
591 .destroy = si_query_hw_destroy,
592 .begin = si_query_hw_begin,
593 .end = si_query_hw_end,
594 .get_result = si_query_hw_get_result,
595 .get_result_resource = r600_query_hw_get_result_resource,
596 };
597
598 static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
599 struct r600_query_hw *query,
600 struct r600_resource *buffer,
601 uint64_t va);
602 static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
603 struct r600_query_hw *query,
604 struct r600_resource *buffer,
605 uint64_t va);
606 static void r600_query_hw_add_result(struct si_screen *sscreen,
607 struct r600_query_hw *, void *buffer,
608 union pipe_query_result *result);
609 static void r600_query_hw_clear_result(struct r600_query_hw *,
610 union pipe_query_result *);
611
612 static struct r600_query_hw_ops query_hw_default_hw_ops = {
613 .prepare_buffer = r600_query_hw_prepare_buffer,
614 .emit_start = r600_query_hw_do_emit_start,
615 .emit_stop = r600_query_hw_do_emit_stop,
616 .clear_result = r600_query_hw_clear_result,
617 .add_result = r600_query_hw_add_result,
618 };
619
620 bool si_query_hw_init(struct si_screen *sscreen,
621 struct r600_query_hw *query)
622 {
623 query->buffer.buf = r600_new_query_buffer(sscreen, query);
624 if (!query->buffer.buf)
625 return false;
626
627 return true;
628 }
629
630 static struct pipe_query *r600_query_hw_create(struct si_screen *sscreen,
631 unsigned query_type,
632 unsigned index)
633 {
634 struct r600_query_hw *query = CALLOC_STRUCT(r600_query_hw);
635 if (!query)
636 return NULL;
637
638 query->b.type = query_type;
639 query->b.ops = &query_hw_ops;
640 query->ops = &query_hw_default_hw_ops;
641
642 switch (query_type) {
643 case PIPE_QUERY_OCCLUSION_COUNTER:
644 case PIPE_QUERY_OCCLUSION_PREDICATE:
645 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
646 query->result_size = 16 * sscreen->info.num_render_backends;
647 query->result_size += 16; /* for the fence + alignment */
648 query->num_cs_dw_end = 6 + si_gfx_write_fence_dwords(sscreen);
649 break;
650 case PIPE_QUERY_TIME_ELAPSED:
651 query->result_size = 24;
652 query->num_cs_dw_end = 8 + si_gfx_write_fence_dwords(sscreen);
653 break;
654 case PIPE_QUERY_TIMESTAMP:
655 query->result_size = 16;
656 query->num_cs_dw_end = 8 + si_gfx_write_fence_dwords(sscreen);
657 query->flags = R600_QUERY_HW_FLAG_NO_START;
658 break;
659 case PIPE_QUERY_PRIMITIVES_EMITTED:
660 case PIPE_QUERY_PRIMITIVES_GENERATED:
661 case PIPE_QUERY_SO_STATISTICS:
662 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
663 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
664 query->result_size = 32;
665 query->num_cs_dw_end = 6;
666 query->stream = index;
667 break;
668 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
669 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
670 query->result_size = 32 * R600_MAX_STREAMS;
671 query->num_cs_dw_end = 6 * R600_MAX_STREAMS;
672 break;
673 case PIPE_QUERY_PIPELINE_STATISTICS:
674 /* 11 values on GCN. */
675 query->result_size = 11 * 16;
676 query->result_size += 8; /* for the fence + alignment */
677 query->num_cs_dw_end = 6 + si_gfx_write_fence_dwords(sscreen);
678 break;
679 default:
680 assert(0);
681 FREE(query);
682 return NULL;
683 }
684
685 if (!si_query_hw_init(sscreen, query)) {
686 FREE(query);
687 return NULL;
688 }
689
690 return (struct pipe_query *)query;
691 }
692
693 static void r600_update_occlusion_query_state(struct r600_common_context *rctx,
694 unsigned type, int diff)
695 {
696 if (type == PIPE_QUERY_OCCLUSION_COUNTER ||
697 type == PIPE_QUERY_OCCLUSION_PREDICATE ||
698 type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
699 bool old_enable = rctx->num_occlusion_queries != 0;
700 bool old_perfect_enable =
701 rctx->num_perfect_occlusion_queries != 0;
702 bool enable, perfect_enable;
703
704 rctx->num_occlusion_queries += diff;
705 assert(rctx->num_occlusion_queries >= 0);
706
707 if (type != PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
708 rctx->num_perfect_occlusion_queries += diff;
709 assert(rctx->num_perfect_occlusion_queries >= 0);
710 }
711
712 enable = rctx->num_occlusion_queries != 0;
713 perfect_enable = rctx->num_perfect_occlusion_queries != 0;
714
715 if (enable != old_enable || perfect_enable != old_perfect_enable) {
716 si_set_occlusion_query_state(&rctx->b, old_perfect_enable);
717 }
718 }
719 }
720
721 static unsigned event_type_for_stream(unsigned stream)
722 {
723 switch (stream) {
724 default:
725 case 0: return V_028A90_SAMPLE_STREAMOUTSTATS;
726 case 1: return V_028A90_SAMPLE_STREAMOUTSTATS1;
727 case 2: return V_028A90_SAMPLE_STREAMOUTSTATS2;
728 case 3: return V_028A90_SAMPLE_STREAMOUTSTATS3;
729 }
730 }
731
732 static void emit_sample_streamout(struct radeon_winsys_cs *cs, uint64_t va,
733 unsigned stream)
734 {
735 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
736 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(stream)) | EVENT_INDEX(3));
737 radeon_emit(cs, va);
738 radeon_emit(cs, va >> 32);
739 }
740
741 static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
742 struct r600_query_hw *query,
743 struct r600_resource *buffer,
744 uint64_t va)
745 {
746 struct radeon_winsys_cs *cs = ctx->gfx_cs;
747
748 switch (query->b.type) {
749 case PIPE_QUERY_OCCLUSION_COUNTER:
750 case PIPE_QUERY_OCCLUSION_PREDICATE:
751 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
752 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
753 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
754 radeon_emit(cs, va);
755 radeon_emit(cs, va >> 32);
756 break;
757 case PIPE_QUERY_PRIMITIVES_EMITTED:
758 case PIPE_QUERY_PRIMITIVES_GENERATED:
759 case PIPE_QUERY_SO_STATISTICS:
760 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
761 emit_sample_streamout(cs, va, query->stream);
762 break;
763 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
764 for (unsigned stream = 0; stream < R600_MAX_STREAMS; ++stream)
765 emit_sample_streamout(cs, va + 32 * stream, stream);
766 break;
767 case PIPE_QUERY_TIME_ELAPSED:
768 /* Write the timestamp from the CP not waiting for
769 * outstanding draws (top-of-pipe).
770 */
771 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
772 radeon_emit(cs, COPY_DATA_COUNT_SEL |
773 COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
774 COPY_DATA_DST_SEL(COPY_DATA_MEM_ASYNC));
775 radeon_emit(cs, 0);
776 radeon_emit(cs, 0);
777 radeon_emit(cs, va);
778 radeon_emit(cs, va >> 32);
779 break;
780 case PIPE_QUERY_PIPELINE_STATISTICS:
781 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
782 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
783 radeon_emit(cs, va);
784 radeon_emit(cs, va >> 32);
785 break;
786 default:
787 assert(0);
788 }
789 radeon_add_to_buffer_list(ctx, ctx->gfx_cs, query->buffer.buf, RADEON_USAGE_WRITE,
790 RADEON_PRIO_QUERY);
791 }
792
793 static void r600_query_hw_emit_start(struct r600_common_context *ctx,
794 struct r600_query_hw *query)
795 {
796 uint64_t va;
797
798 if (!query->buffer.buf)
799 return; // previous buffer allocation failure
800
801 r600_update_occlusion_query_state(ctx, query->b.type, 1);
802 si_update_prims_generated_query_state((void*)ctx, query->b.type, 1);
803
804 si_need_gfx_cs_space((struct si_context*)ctx);
805
806 /* Get a new query buffer if needed. */
807 if (query->buffer.results_end + query->result_size > query->buffer.buf->b.b.width0) {
808 struct r600_query_buffer *qbuf = MALLOC_STRUCT(r600_query_buffer);
809 *qbuf = query->buffer;
810 query->buffer.results_end = 0;
811 query->buffer.previous = qbuf;
812 query->buffer.buf = r600_new_query_buffer(ctx->screen, query);
813 if (!query->buffer.buf)
814 return;
815 }
816
817 /* emit begin query */
818 va = query->buffer.buf->gpu_address + query->buffer.results_end;
819
820 query->ops->emit_start(ctx, query, query->buffer.buf, va);
821
822 ctx->num_cs_dw_queries_suspend += query->num_cs_dw_end;
823 }
824
825 static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
826 struct r600_query_hw *query,
827 struct r600_resource *buffer,
828 uint64_t va)
829 {
830 struct si_context *sctx = (struct si_context*)ctx;
831 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
832 uint64_t fence_va = 0;
833
834 switch (query->b.type) {
835 case PIPE_QUERY_OCCLUSION_COUNTER:
836 case PIPE_QUERY_OCCLUSION_PREDICATE:
837 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
838 va += 8;
839 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
840 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
841 radeon_emit(cs, va);
842 radeon_emit(cs, va >> 32);
843
844 fence_va = va + ctx->screen->info.num_render_backends * 16 - 8;
845 break;
846 case PIPE_QUERY_PRIMITIVES_EMITTED:
847 case PIPE_QUERY_PRIMITIVES_GENERATED:
848 case PIPE_QUERY_SO_STATISTICS:
849 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
850 va += 16;
851 emit_sample_streamout(cs, va, query->stream);
852 break;
853 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
854 va += 16;
855 for (unsigned stream = 0; stream < R600_MAX_STREAMS; ++stream)
856 emit_sample_streamout(cs, va + 32 * stream, stream);
857 break;
858 case PIPE_QUERY_TIME_ELAPSED:
859 va += 8;
860 /* fall through */
861 case PIPE_QUERY_TIMESTAMP:
862 si_gfx_write_event_eop(sctx, V_028A90_BOTTOM_OF_PIPE_TS,
863 0, EOP_DATA_SEL_TIMESTAMP, NULL, va,
864 0, query->b.type);
865 fence_va = va + 8;
866 break;
867 case PIPE_QUERY_PIPELINE_STATISTICS: {
868 unsigned sample_size = (query->result_size - 8) / 2;
869
870 va += sample_size;
871 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
872 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
873 radeon_emit(cs, va);
874 radeon_emit(cs, va >> 32);
875
876 fence_va = va + sample_size;
877 break;
878 }
879 default:
880 assert(0);
881 }
882 radeon_add_to_buffer_list(ctx, ctx->gfx_cs, query->buffer.buf, RADEON_USAGE_WRITE,
883 RADEON_PRIO_QUERY);
884
885 if (fence_va)
886 si_gfx_write_event_eop(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
887 EOP_DATA_SEL_VALUE_32BIT,
888 query->buffer.buf, fence_va, 0x80000000,
889 query->b.type);
890 }
891
892 static void r600_query_hw_emit_stop(struct r600_common_context *ctx,
893 struct r600_query_hw *query)
894 {
895 uint64_t va;
896
897 if (!query->buffer.buf)
898 return; // previous buffer allocation failure
899
900 /* The queries which need begin already called this in begin_query. */
901 if (query->flags & R600_QUERY_HW_FLAG_NO_START)
902 si_need_gfx_cs_space((struct si_context*)ctx);
903
904 /* emit end query */
905 va = query->buffer.buf->gpu_address + query->buffer.results_end;
906
907 query->ops->emit_stop(ctx, query, query->buffer.buf, va);
908
909 query->buffer.results_end += query->result_size;
910
911 if (!(query->flags & R600_QUERY_HW_FLAG_NO_START))
912 ctx->num_cs_dw_queries_suspend -= query->num_cs_dw_end;
913
914 r600_update_occlusion_query_state(ctx, query->b.type, -1);
915 si_update_prims_generated_query_state((void*)ctx, query->b.type, -1);
916 }
917
918 static void emit_set_predicate(struct si_context *ctx,
919 struct r600_resource *buf, uint64_t va,
920 uint32_t op)
921 {
922 struct radeon_winsys_cs *cs = ctx->b.gfx_cs;
923
924 if (ctx->b.chip_class >= GFX9) {
925 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
926 radeon_emit(cs, op);
927 radeon_emit(cs, va);
928 radeon_emit(cs, va >> 32);
929 } else {
930 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
931 radeon_emit(cs, va);
932 radeon_emit(cs, op | ((va >> 32) & 0xFF));
933 }
934 radeon_add_to_buffer_list(&ctx->b, ctx->b.gfx_cs, buf, RADEON_USAGE_READ,
935 RADEON_PRIO_QUERY);
936 }
937
938 static void r600_emit_query_predication(struct si_context *ctx,
939 struct r600_atom *atom)
940 {
941 struct r600_query_hw *query = (struct r600_query_hw *)ctx->b.render_cond;
942 struct r600_query_buffer *qbuf;
943 uint32_t op;
944 bool flag_wait, invert;
945
946 if (!query)
947 return;
948
949 invert = ctx->b.render_cond_invert;
950 flag_wait = ctx->b.render_cond_mode == PIPE_RENDER_COND_WAIT ||
951 ctx->b.render_cond_mode == PIPE_RENDER_COND_BY_REGION_WAIT;
952
953 if (query->workaround_buf) {
954 op = PRED_OP(PREDICATION_OP_BOOL64);
955 } else {
956 switch (query->b.type) {
957 case PIPE_QUERY_OCCLUSION_COUNTER:
958 case PIPE_QUERY_OCCLUSION_PREDICATE:
959 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
960 op = PRED_OP(PREDICATION_OP_ZPASS);
961 break;
962 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
963 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
964 op = PRED_OP(PREDICATION_OP_PRIMCOUNT);
965 invert = !invert;
966 break;
967 default:
968 assert(0);
969 return;
970 }
971 }
972
973 /* if true then invert, see GL_ARB_conditional_render_inverted */
974 if (invert)
975 op |= PREDICATION_DRAW_NOT_VISIBLE; /* Draw if not visible or overflow */
976 else
977 op |= PREDICATION_DRAW_VISIBLE; /* Draw if visible or no overflow */
978
979 /* Use the value written by compute shader as a workaround. Note that
980 * the wait flag does not apply in this predication mode.
981 *
982 * The shader outputs the result value to L2. Workarounds only affect VI
983 * and later, where the CP reads data from L2, so we don't need an
984 * additional flush.
985 */
986 if (query->workaround_buf) {
987 uint64_t va = query->workaround_buf->gpu_address + query->workaround_offset;
988 emit_set_predicate(ctx, query->workaround_buf, va, op);
989 return;
990 }
991
992 op |= flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW;
993
994 /* emit predicate packets for all data blocks */
995 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
996 unsigned results_base = 0;
997 uint64_t va_base = qbuf->buf->gpu_address;
998
999 while (results_base < qbuf->results_end) {
1000 uint64_t va = va_base + results_base;
1001
1002 if (query->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE) {
1003 for (unsigned stream = 0; stream < R600_MAX_STREAMS; ++stream) {
1004 emit_set_predicate(ctx, qbuf->buf, va + 32 * stream, op);
1005
1006 /* set CONTINUE bit for all packets except the first */
1007 op |= PREDICATION_CONTINUE;
1008 }
1009 } else {
1010 emit_set_predicate(ctx, qbuf->buf, va, op);
1011 op |= PREDICATION_CONTINUE;
1012 }
1013
1014 results_base += query->result_size;
1015 }
1016 }
1017 }
1018
1019 static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type, unsigned index)
1020 {
1021 struct si_screen *sscreen =
1022 (struct si_screen *)ctx->screen;
1023
1024 if (query_type == PIPE_QUERY_TIMESTAMP_DISJOINT ||
1025 query_type == PIPE_QUERY_GPU_FINISHED ||
1026 query_type >= PIPE_QUERY_DRIVER_SPECIFIC)
1027 return r600_query_sw_create(query_type);
1028
1029 return r600_query_hw_create(sscreen, query_type, index);
1030 }
1031
1032 static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
1033 {
1034 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1035 struct r600_query *rquery = (struct r600_query *)query;
1036
1037 rquery->ops->destroy(rctx->screen, rquery);
1038 }
1039
1040 static boolean r600_begin_query(struct pipe_context *ctx,
1041 struct pipe_query *query)
1042 {
1043 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1044 struct r600_query *rquery = (struct r600_query *)query;
1045
1046 return rquery->ops->begin(rctx, rquery);
1047 }
1048
1049 void si_query_hw_reset_buffers(struct r600_common_context *rctx,
1050 struct r600_query_hw *query)
1051 {
1052 struct si_context *sctx = (struct si_context*)rctx;
1053 struct r600_query_buffer *prev = query->buffer.previous;
1054
1055 /* Discard the old query buffers. */
1056 while (prev) {
1057 struct r600_query_buffer *qbuf = prev;
1058 prev = prev->previous;
1059 r600_resource_reference(&qbuf->buf, NULL);
1060 FREE(qbuf);
1061 }
1062
1063 query->buffer.results_end = 0;
1064 query->buffer.previous = NULL;
1065
1066 /* Obtain a new buffer if the current one can't be mapped without a stall. */
1067 if (si_rings_is_buffer_referenced(sctx, query->buffer.buf->buf, RADEON_USAGE_READWRITE) ||
1068 !rctx->ws->buffer_wait(query->buffer.buf->buf, 0, RADEON_USAGE_READWRITE)) {
1069 r600_resource_reference(&query->buffer.buf, NULL);
1070 query->buffer.buf = r600_new_query_buffer(rctx->screen, query);
1071 } else {
1072 if (!query->ops->prepare_buffer(rctx->screen, query, query->buffer.buf))
1073 r600_resource_reference(&query->buffer.buf, NULL);
1074 }
1075 }
1076
1077 bool si_query_hw_begin(struct r600_common_context *rctx,
1078 struct r600_query *rquery)
1079 {
1080 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
1081
1082 if (query->flags & R600_QUERY_HW_FLAG_NO_START) {
1083 assert(0);
1084 return false;
1085 }
1086
1087 if (!(query->flags & R600_QUERY_HW_FLAG_BEGIN_RESUMES))
1088 si_query_hw_reset_buffers(rctx, query);
1089
1090 r600_resource_reference(&query->workaround_buf, NULL);
1091
1092 r600_query_hw_emit_start(rctx, query);
1093 if (!query->buffer.buf)
1094 return false;
1095
1096 LIST_ADDTAIL(&query->list, &rctx->active_queries);
1097 return true;
1098 }
1099
1100 static bool r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
1101 {
1102 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1103 struct r600_query *rquery = (struct r600_query *)query;
1104
1105 return rquery->ops->end(rctx, rquery);
1106 }
1107
1108 bool si_query_hw_end(struct r600_common_context *rctx,
1109 struct r600_query *rquery)
1110 {
1111 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
1112
1113 if (query->flags & R600_QUERY_HW_FLAG_NO_START)
1114 si_query_hw_reset_buffers(rctx, query);
1115
1116 r600_query_hw_emit_stop(rctx, query);
1117
1118 if (!(query->flags & R600_QUERY_HW_FLAG_NO_START))
1119 LIST_DELINIT(&query->list);
1120
1121 if (!query->buffer.buf)
1122 return false;
1123
1124 return true;
1125 }
1126
1127 static void r600_get_hw_query_params(struct r600_common_context *rctx,
1128 struct r600_query_hw *rquery, int index,
1129 struct r600_hw_query_params *params)
1130 {
1131 unsigned max_rbs = rctx->screen->info.num_render_backends;
1132
1133 params->pair_stride = 0;
1134 params->pair_count = 1;
1135
1136 switch (rquery->b.type) {
1137 case PIPE_QUERY_OCCLUSION_COUNTER:
1138 case PIPE_QUERY_OCCLUSION_PREDICATE:
1139 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1140 params->start_offset = 0;
1141 params->end_offset = 8;
1142 params->fence_offset = max_rbs * 16;
1143 params->pair_stride = 16;
1144 params->pair_count = max_rbs;
1145 break;
1146 case PIPE_QUERY_TIME_ELAPSED:
1147 params->start_offset = 0;
1148 params->end_offset = 8;
1149 params->fence_offset = 16;
1150 break;
1151 case PIPE_QUERY_TIMESTAMP:
1152 params->start_offset = 0;
1153 params->end_offset = 0;
1154 params->fence_offset = 8;
1155 break;
1156 case PIPE_QUERY_PRIMITIVES_EMITTED:
1157 params->start_offset = 8;
1158 params->end_offset = 24;
1159 params->fence_offset = params->end_offset + 4;
1160 break;
1161 case PIPE_QUERY_PRIMITIVES_GENERATED:
1162 params->start_offset = 0;
1163 params->end_offset = 16;
1164 params->fence_offset = params->end_offset + 4;
1165 break;
1166 case PIPE_QUERY_SO_STATISTICS:
1167 params->start_offset = 8 - index * 8;
1168 params->end_offset = 24 - index * 8;
1169 params->fence_offset = params->end_offset + 4;
1170 break;
1171 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
1172 params->pair_count = R600_MAX_STREAMS;
1173 params->pair_stride = 32;
1174 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1175 params->start_offset = 0;
1176 params->end_offset = 16;
1177
1178 /* We can re-use the high dword of the last 64-bit value as a
1179 * fence: it is initialized as 0, and the high bit is set by
1180 * the write of the streamout stats event.
1181 */
1182 params->fence_offset = rquery->result_size - 4;
1183 break;
1184 case PIPE_QUERY_PIPELINE_STATISTICS:
1185 {
1186 /* Offsets apply to EG+ */
1187 static const unsigned offsets[] = {56, 48, 24, 32, 40, 16, 8, 0, 64, 72, 80};
1188 params->start_offset = offsets[index];
1189 params->end_offset = 88 + offsets[index];
1190 params->fence_offset = 2 * 88;
1191 break;
1192 }
1193 default:
1194 unreachable("r600_get_hw_query_params unsupported");
1195 }
1196 }
1197
1198 static unsigned r600_query_read_result(void *map, unsigned start_index, unsigned end_index,
1199 bool test_status_bit)
1200 {
1201 uint32_t *current_result = (uint32_t*)map;
1202 uint64_t start, end;
1203
1204 start = (uint64_t)current_result[start_index] |
1205 (uint64_t)current_result[start_index+1] << 32;
1206 end = (uint64_t)current_result[end_index] |
1207 (uint64_t)current_result[end_index+1] << 32;
1208
1209 if (!test_status_bit ||
1210 ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) {
1211 return end - start;
1212 }
1213 return 0;
1214 }
1215
1216 static void r600_query_hw_add_result(struct si_screen *sscreen,
1217 struct r600_query_hw *query,
1218 void *buffer,
1219 union pipe_query_result *result)
1220 {
1221 unsigned max_rbs = sscreen->info.num_render_backends;
1222
1223 switch (query->b.type) {
1224 case PIPE_QUERY_OCCLUSION_COUNTER: {
1225 for (unsigned i = 0; i < max_rbs; ++i) {
1226 unsigned results_base = i * 16;
1227 result->u64 +=
1228 r600_query_read_result(buffer + results_base, 0, 2, true);
1229 }
1230 break;
1231 }
1232 case PIPE_QUERY_OCCLUSION_PREDICATE:
1233 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: {
1234 for (unsigned i = 0; i < max_rbs; ++i) {
1235 unsigned results_base = i * 16;
1236 result->b = result->b ||
1237 r600_query_read_result(buffer + results_base, 0, 2, true) != 0;
1238 }
1239 break;
1240 }
1241 case PIPE_QUERY_TIME_ELAPSED:
1242 result->u64 += r600_query_read_result(buffer, 0, 2, false);
1243 break;
1244 case PIPE_QUERY_TIMESTAMP:
1245 result->u64 = *(uint64_t*)buffer;
1246 break;
1247 case PIPE_QUERY_PRIMITIVES_EMITTED:
1248 /* SAMPLE_STREAMOUTSTATS stores this structure:
1249 * {
1250 * u64 NumPrimitivesWritten;
1251 * u64 PrimitiveStorageNeeded;
1252 * }
1253 * We only need NumPrimitivesWritten here. */
1254 result->u64 += r600_query_read_result(buffer, 2, 6, true);
1255 break;
1256 case PIPE_QUERY_PRIMITIVES_GENERATED:
1257 /* Here we read PrimitiveStorageNeeded. */
1258 result->u64 += r600_query_read_result(buffer, 0, 4, true);
1259 break;
1260 case PIPE_QUERY_SO_STATISTICS:
1261 result->so_statistics.num_primitives_written +=
1262 r600_query_read_result(buffer, 2, 6, true);
1263 result->so_statistics.primitives_storage_needed +=
1264 r600_query_read_result(buffer, 0, 4, true);
1265 break;
1266 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1267 result->b = result->b ||
1268 r600_query_read_result(buffer, 2, 6, true) !=
1269 r600_query_read_result(buffer, 0, 4, true);
1270 break;
1271 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
1272 for (unsigned stream = 0; stream < R600_MAX_STREAMS; ++stream) {
1273 result->b = result->b ||
1274 r600_query_read_result(buffer, 2, 6, true) !=
1275 r600_query_read_result(buffer, 0, 4, true);
1276 buffer = (char *)buffer + 32;
1277 }
1278 break;
1279 case PIPE_QUERY_PIPELINE_STATISTICS:
1280 result->pipeline_statistics.ps_invocations +=
1281 r600_query_read_result(buffer, 0, 22, false);
1282 result->pipeline_statistics.c_primitives +=
1283 r600_query_read_result(buffer, 2, 24, false);
1284 result->pipeline_statistics.c_invocations +=
1285 r600_query_read_result(buffer, 4, 26, false);
1286 result->pipeline_statistics.vs_invocations +=
1287 r600_query_read_result(buffer, 6, 28, false);
1288 result->pipeline_statistics.gs_invocations +=
1289 r600_query_read_result(buffer, 8, 30, false);
1290 result->pipeline_statistics.gs_primitives +=
1291 r600_query_read_result(buffer, 10, 32, false);
1292 result->pipeline_statistics.ia_primitives +=
1293 r600_query_read_result(buffer, 12, 34, false);
1294 result->pipeline_statistics.ia_vertices +=
1295 r600_query_read_result(buffer, 14, 36, false);
1296 result->pipeline_statistics.hs_invocations +=
1297 r600_query_read_result(buffer, 16, 38, false);
1298 result->pipeline_statistics.ds_invocations +=
1299 r600_query_read_result(buffer, 18, 40, false);
1300 result->pipeline_statistics.cs_invocations +=
1301 r600_query_read_result(buffer, 20, 42, false);
1302 #if 0 /* for testing */
1303 printf("Pipeline stats: IA verts=%llu, IA prims=%llu, VS=%llu, HS=%llu, "
1304 "DS=%llu, GS=%llu, GS prims=%llu, Clipper=%llu, "
1305 "Clipper prims=%llu, PS=%llu, CS=%llu\n",
1306 result->pipeline_statistics.ia_vertices,
1307 result->pipeline_statistics.ia_primitives,
1308 result->pipeline_statistics.vs_invocations,
1309 result->pipeline_statistics.hs_invocations,
1310 result->pipeline_statistics.ds_invocations,
1311 result->pipeline_statistics.gs_invocations,
1312 result->pipeline_statistics.gs_primitives,
1313 result->pipeline_statistics.c_invocations,
1314 result->pipeline_statistics.c_primitives,
1315 result->pipeline_statistics.ps_invocations,
1316 result->pipeline_statistics.cs_invocations);
1317 #endif
1318 break;
1319 default:
1320 assert(0);
1321 }
1322 }
1323
1324 static boolean r600_get_query_result(struct pipe_context *ctx,
1325 struct pipe_query *query, boolean wait,
1326 union pipe_query_result *result)
1327 {
1328 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1329 struct r600_query *rquery = (struct r600_query *)query;
1330
1331 return rquery->ops->get_result(rctx, rquery, wait, result);
1332 }
1333
1334 static void r600_get_query_result_resource(struct pipe_context *ctx,
1335 struct pipe_query *query,
1336 boolean wait,
1337 enum pipe_query_value_type result_type,
1338 int index,
1339 struct pipe_resource *resource,
1340 unsigned offset)
1341 {
1342 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1343 struct r600_query *rquery = (struct r600_query *)query;
1344
1345 rquery->ops->get_result_resource(rctx, rquery, wait, result_type, index,
1346 resource, offset);
1347 }
1348
1349 static void r600_query_hw_clear_result(struct r600_query_hw *query,
1350 union pipe_query_result *result)
1351 {
1352 util_query_clear_result(result, query->b.type);
1353 }
1354
1355 bool si_query_hw_get_result(struct r600_common_context *rctx,
1356 struct r600_query *rquery,
1357 bool wait, union pipe_query_result *result)
1358 {
1359 struct si_context *sctx = (struct si_context*)rctx;
1360 struct si_screen *sscreen = rctx->screen;
1361 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
1362 struct r600_query_buffer *qbuf;
1363
1364 query->ops->clear_result(query, result);
1365
1366 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
1367 unsigned usage = PIPE_TRANSFER_READ |
1368 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK);
1369 unsigned results_base = 0;
1370 void *map;
1371
1372 if (rquery->b.flushed)
1373 map = rctx->ws->buffer_map(qbuf->buf->buf, NULL, usage);
1374 else
1375 map = si_buffer_map_sync_with_rings(sctx, qbuf->buf, usage);
1376
1377 if (!map)
1378 return false;
1379
1380 while (results_base != qbuf->results_end) {
1381 query->ops->add_result(sscreen, query, map + results_base,
1382 result);
1383 results_base += query->result_size;
1384 }
1385 }
1386
1387 /* Convert the time to expected units. */
1388 if (rquery->type == PIPE_QUERY_TIME_ELAPSED ||
1389 rquery->type == PIPE_QUERY_TIMESTAMP) {
1390 result->u64 = (1000000 * result->u64) / sscreen->info.clock_crystal_freq;
1391 }
1392 return true;
1393 }
1394
1395 /* Create the compute shader that is used to collect the results.
1396 *
1397 * One compute grid with a single thread is launched for every query result
1398 * buffer. The thread (optionally) reads a previous summary buffer, then
1399 * accumulates data from the query result buffer, and writes the result either
1400 * to a summary buffer to be consumed by the next grid invocation or to the
1401 * user-supplied buffer.
1402 *
1403 * Data layout:
1404 *
1405 * CONST
1406 * 0.x = end_offset
1407 * 0.y = result_stride
1408 * 0.z = result_count
1409 * 0.w = bit field:
1410 * 1: read previously accumulated values
1411 * 2: write accumulated values for chaining
1412 * 4: write result available
1413 * 8: convert result to boolean (0/1)
1414 * 16: only read one dword and use that as result
1415 * 32: apply timestamp conversion
1416 * 64: store full 64 bits result
1417 * 128: store signed 32 bits result
1418 * 256: SO_OVERFLOW mode: take the difference of two successive half-pairs
1419 * 1.x = fence_offset
1420 * 1.y = pair_stride
1421 * 1.z = pair_count
1422 *
1423 * BUFFER[0] = query result buffer
1424 * BUFFER[1] = previous summary buffer
1425 * BUFFER[2] = next summary buffer or user-supplied buffer
1426 */
1427 static void r600_create_query_result_shader(struct r600_common_context *rctx)
1428 {
1429 /* TEMP[0].xy = accumulated result so far
1430 * TEMP[0].z = result not available
1431 *
1432 * TEMP[1].x = current result index
1433 * TEMP[1].y = current pair index
1434 */
1435 static const char text_tmpl[] =
1436 "COMP\n"
1437 "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
1438 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
1439 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
1440 "DCL BUFFER[0]\n"
1441 "DCL BUFFER[1]\n"
1442 "DCL BUFFER[2]\n"
1443 "DCL CONST[0][0..1]\n"
1444 "DCL TEMP[0..5]\n"
1445 "IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n"
1446 "IMM[1] UINT32 {1, 2, 4, 8}\n"
1447 "IMM[2] UINT32 {16, 32, 64, 128}\n"
1448 "IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */
1449 "IMM[4] UINT32 {256, 0, 0, 0}\n"
1450
1451 "AND TEMP[5], CONST[0][0].wwww, IMM[2].xxxx\n"
1452 "UIF TEMP[5]\n"
1453 /* Check result availability. */
1454 "LOAD TEMP[1].x, BUFFER[0], CONST[0][1].xxxx\n"
1455 "ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n"
1456 "MOV TEMP[1], TEMP[0].zzzz\n"
1457 "NOT TEMP[0].z, TEMP[0].zzzz\n"
1458
1459 /* Load result if available. */
1460 "UIF TEMP[1]\n"
1461 "LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n"
1462 "ENDIF\n"
1463 "ELSE\n"
1464 /* Load previously accumulated result if requested. */
1465 "MOV TEMP[0], IMM[0].xxxx\n"
1466 "AND TEMP[4], CONST[0][0].wwww, IMM[1].xxxx\n"
1467 "UIF TEMP[4]\n"
1468 "LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n"
1469 "ENDIF\n"
1470
1471 "MOV TEMP[1].x, IMM[0].xxxx\n"
1472 "BGNLOOP\n"
1473 /* Break if accumulated result so far is not available. */
1474 "UIF TEMP[0].zzzz\n"
1475 "BRK\n"
1476 "ENDIF\n"
1477
1478 /* Break if result_index >= result_count. */
1479 "USGE TEMP[5], TEMP[1].xxxx, CONST[0][0].zzzz\n"
1480 "UIF TEMP[5]\n"
1481 "BRK\n"
1482 "ENDIF\n"
1483
1484 /* Load fence and check result availability */
1485 "UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy, CONST[0][1].xxxx\n"
1486 "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
1487 "ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n"
1488 "NOT TEMP[0].z, TEMP[0].zzzz\n"
1489 "UIF TEMP[0].zzzz\n"
1490 "BRK\n"
1491 "ENDIF\n"
1492
1493 "MOV TEMP[1].y, IMM[0].xxxx\n"
1494 "BGNLOOP\n"
1495 /* Load start and end. */
1496 "UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy\n"
1497 "UMAD TEMP[5].x, TEMP[1].yyyy, CONST[0][1].yyyy, TEMP[5].xxxx\n"
1498 "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
1499
1500 "UADD TEMP[5].y, TEMP[5].xxxx, CONST[0][0].xxxx\n"
1501 "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
1502
1503 "U64ADD TEMP[4].xy, TEMP[3], -TEMP[2]\n"
1504
1505 "AND TEMP[5].z, CONST[0][0].wwww, IMM[4].xxxx\n"
1506 "UIF TEMP[5].zzzz\n"
1507 /* Load second start/end half-pair and
1508 * take the difference
1509 */
1510 "UADD TEMP[5].xy, TEMP[5], IMM[1].wwww\n"
1511 "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
1512 "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
1513
1514 "U64ADD TEMP[3].xy, TEMP[3], -TEMP[2]\n"
1515 "U64ADD TEMP[4].xy, TEMP[4], -TEMP[3]\n"
1516 "ENDIF\n"
1517
1518 "U64ADD TEMP[0].xy, TEMP[0], TEMP[4]\n"
1519
1520 /* Increment pair index */
1521 "UADD TEMP[1].y, TEMP[1].yyyy, IMM[1].xxxx\n"
1522 "USGE TEMP[5], TEMP[1].yyyy, CONST[0][1].zzzz\n"
1523 "UIF TEMP[5]\n"
1524 "BRK\n"
1525 "ENDIF\n"
1526 "ENDLOOP\n"
1527
1528 /* Increment result index */
1529 "UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n"
1530 "ENDLOOP\n"
1531 "ENDIF\n"
1532
1533 "AND TEMP[4], CONST[0][0].wwww, IMM[1].yyyy\n"
1534 "UIF TEMP[4]\n"
1535 /* Store accumulated data for chaining. */
1536 "STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n"
1537 "ELSE\n"
1538 "AND TEMP[4], CONST[0][0].wwww, IMM[1].zzzz\n"
1539 "UIF TEMP[4]\n"
1540 /* Store result availability. */
1541 "NOT TEMP[0].z, TEMP[0]\n"
1542 "AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n"
1543 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n"
1544
1545 "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
1546 "UIF TEMP[4]\n"
1547 "STORE BUFFER[2].y, IMM[0].xxxx, IMM[0].xxxx\n"
1548 "ENDIF\n"
1549 "ELSE\n"
1550 /* Store result if it is available. */
1551 "NOT TEMP[4], TEMP[0].zzzz\n"
1552 "UIF TEMP[4]\n"
1553 /* Apply timestamp conversion */
1554 "AND TEMP[4], CONST[0][0].wwww, IMM[2].yyyy\n"
1555 "UIF TEMP[4]\n"
1556 "U64MUL TEMP[0].xy, TEMP[0], IMM[3].xyxy\n"
1557 "U64DIV TEMP[0].xy, TEMP[0], IMM[3].zwzw\n"
1558 "ENDIF\n"
1559
1560 /* Convert to boolean */
1561 "AND TEMP[4], CONST[0][0].wwww, IMM[1].wwww\n"
1562 "UIF TEMP[4]\n"
1563 "U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[4].zwzw\n"
1564 "AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n"
1565 "MOV TEMP[0].y, IMM[0].xxxx\n"
1566 "ENDIF\n"
1567
1568 "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
1569 "UIF TEMP[4]\n"
1570 "STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0].xyxy\n"
1571 "ELSE\n"
1572 /* Clamping */
1573 "UIF TEMP[0].yyyy\n"
1574 "MOV TEMP[0].x, IMM[0].wwww\n"
1575 "ENDIF\n"
1576
1577 "AND TEMP[4], CONST[0][0].wwww, IMM[2].wwww\n"
1578 "UIF TEMP[4]\n"
1579 "UMIN TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz\n"
1580 "ENDIF\n"
1581
1582 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n"
1583 "ENDIF\n"
1584 "ENDIF\n"
1585 "ENDIF\n"
1586 "ENDIF\n"
1587
1588 "END\n";
1589
1590 char text[sizeof(text_tmpl) + 32];
1591 struct tgsi_token tokens[1024];
1592 struct pipe_compute_state state = {};
1593
1594 /* Hard code the frequency into the shader so that the backend can
1595 * use the full range of optimizations for divide-by-constant.
1596 */
1597 snprintf(text, sizeof(text), text_tmpl,
1598 rctx->screen->info.clock_crystal_freq);
1599
1600 if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
1601 assert(false);
1602 return;
1603 }
1604
1605 state.ir_type = PIPE_SHADER_IR_TGSI;
1606 state.prog = tokens;
1607
1608 rctx->query_result_shader = rctx->b.create_compute_state(&rctx->b, &state);
1609 }
1610
1611 static void r600_restore_qbo_state(struct r600_common_context *rctx,
1612 struct r600_qbo_state *st)
1613 {
1614 rctx->b.bind_compute_state(&rctx->b, st->saved_compute);
1615
1616 rctx->b.set_constant_buffer(&rctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1617 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1618
1619 rctx->b.set_shader_buffers(&rctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1620 for (unsigned i = 0; i < 3; ++i)
1621 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1622 }
1623
1624 static void r600_query_hw_get_result_resource(struct r600_common_context *rctx,
1625 struct r600_query *rquery,
1626 bool wait,
1627 enum pipe_query_value_type result_type,
1628 int index,
1629 struct pipe_resource *resource,
1630 unsigned offset)
1631 {
1632 struct si_context *sctx = (struct si_context*)rctx;
1633 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
1634 struct r600_query_buffer *qbuf;
1635 struct r600_query_buffer *qbuf_prev;
1636 struct pipe_resource *tmp_buffer = NULL;
1637 unsigned tmp_buffer_offset = 0;
1638 struct r600_qbo_state saved_state = {};
1639 struct pipe_grid_info grid = {};
1640 struct pipe_constant_buffer constant_buffer = {};
1641 struct pipe_shader_buffer ssbo[3];
1642 struct r600_hw_query_params params;
1643 struct {
1644 uint32_t end_offset;
1645 uint32_t result_stride;
1646 uint32_t result_count;
1647 uint32_t config;
1648 uint32_t fence_offset;
1649 uint32_t pair_stride;
1650 uint32_t pair_count;
1651 } consts;
1652
1653 if (!rctx->query_result_shader) {
1654 r600_create_query_result_shader(rctx);
1655 if (!rctx->query_result_shader)
1656 return;
1657 }
1658
1659 if (query->buffer.previous) {
1660 u_suballocator_alloc(rctx->allocator_zeroed_memory, 16, 16,
1661 &tmp_buffer_offset, &tmp_buffer);
1662 if (!tmp_buffer)
1663 return;
1664 }
1665
1666 si_save_qbo_state(&rctx->b, &saved_state);
1667
1668 r600_get_hw_query_params(rctx, query, index >= 0 ? index : 0, &params);
1669 consts.end_offset = params.end_offset - params.start_offset;
1670 consts.fence_offset = params.fence_offset - params.start_offset;
1671 consts.result_stride = query->result_size;
1672 consts.pair_stride = params.pair_stride;
1673 consts.pair_count = params.pair_count;
1674
1675 constant_buffer.buffer_size = sizeof(consts);
1676 constant_buffer.user_buffer = &consts;
1677
1678 ssbo[1].buffer = tmp_buffer;
1679 ssbo[1].buffer_offset = tmp_buffer_offset;
1680 ssbo[1].buffer_size = 16;
1681
1682 ssbo[2] = ssbo[1];
1683
1684 rctx->b.bind_compute_state(&rctx->b, rctx->query_result_shader);
1685
1686 grid.block[0] = 1;
1687 grid.block[1] = 1;
1688 grid.block[2] = 1;
1689 grid.grid[0] = 1;
1690 grid.grid[1] = 1;
1691 grid.grid[2] = 1;
1692
1693 consts.config = 0;
1694 if (index < 0)
1695 consts.config |= 4;
1696 if (query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE ||
1697 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE)
1698 consts.config |= 8;
1699 else if (query->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE ||
1700 query->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE)
1701 consts.config |= 8 | 256;
1702 else if (query->b.type == PIPE_QUERY_TIMESTAMP ||
1703 query->b.type == PIPE_QUERY_TIME_ELAPSED)
1704 consts.config |= 32;
1705
1706 switch (result_type) {
1707 case PIPE_QUERY_TYPE_U64:
1708 case PIPE_QUERY_TYPE_I64:
1709 consts.config |= 64;
1710 break;
1711 case PIPE_QUERY_TYPE_I32:
1712 consts.config |= 128;
1713 break;
1714 case PIPE_QUERY_TYPE_U32:
1715 break;
1716 }
1717
1718 rctx->flags |= rctx->screen->barrier_flags.cp_to_L2;
1719
1720 for (qbuf = &query->buffer; qbuf; qbuf = qbuf_prev) {
1721 if (query->b.type != PIPE_QUERY_TIMESTAMP) {
1722 qbuf_prev = qbuf->previous;
1723 consts.result_count = qbuf->results_end / query->result_size;
1724 consts.config &= ~3;
1725 if (qbuf != &query->buffer)
1726 consts.config |= 1;
1727 if (qbuf->previous)
1728 consts.config |= 2;
1729 } else {
1730 /* Only read the last timestamp. */
1731 qbuf_prev = NULL;
1732 consts.result_count = 0;
1733 consts.config |= 16;
1734 params.start_offset += qbuf->results_end - query->result_size;
1735 }
1736
1737 rctx->b.set_constant_buffer(&rctx->b, PIPE_SHADER_COMPUTE, 0, &constant_buffer);
1738
1739 ssbo[0].buffer = &qbuf->buf->b.b;
1740 ssbo[0].buffer_offset = params.start_offset;
1741 ssbo[0].buffer_size = qbuf->results_end - params.start_offset;
1742
1743 if (!qbuf->previous) {
1744 ssbo[2].buffer = resource;
1745 ssbo[2].buffer_offset = offset;
1746 ssbo[2].buffer_size = 8;
1747
1748 ((struct r600_resource *)resource)->TC_L2_dirty = true;
1749 }
1750
1751 rctx->b.set_shader_buffers(&rctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo);
1752
1753 if (wait && qbuf == &query->buffer) {
1754 uint64_t va;
1755
1756 /* Wait for result availability. Wait only for readiness
1757 * of the last entry, since the fence writes should be
1758 * serialized in the CP.
1759 */
1760 va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size;
1761 va += params.fence_offset;
1762
1763 si_gfx_wait_fence(sctx, va, 0x80000000, 0x80000000);
1764 }
1765
1766 rctx->b.launch_grid(&rctx->b, &grid);
1767 rctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
1768 }
1769
1770 r600_restore_qbo_state(rctx, &saved_state);
1771 pipe_resource_reference(&tmp_buffer, NULL);
1772 }
1773
1774 static void r600_render_condition(struct pipe_context *ctx,
1775 struct pipe_query *query,
1776 boolean condition,
1777 enum pipe_render_cond_flag mode)
1778 {
1779 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1780 struct r600_query_hw *rquery = (struct r600_query_hw *)query;
1781 struct r600_atom *atom = &rctx->render_cond_atom;
1782
1783 if (query) {
1784 bool needs_workaround = false;
1785
1786 /* There was a firmware regression in VI which causes successive
1787 * SET_PREDICATION packets to give the wrong answer for
1788 * non-inverted stream overflow predication.
1789 */
1790 if (((rctx->chip_class == VI && rctx->screen->info.pfp_fw_feature < 49) ||
1791 (rctx->chip_class == GFX9 && rctx->screen->info.pfp_fw_feature < 38)) &&
1792 !condition &&
1793 (rquery->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE ||
1794 (rquery->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE &&
1795 (rquery->buffer.previous ||
1796 rquery->buffer.results_end > rquery->result_size)))) {
1797 needs_workaround = true;
1798 }
1799
1800 if (needs_workaround && !rquery->workaround_buf) {
1801 bool old_force_off = rctx->render_cond_force_off;
1802 rctx->render_cond_force_off = true;
1803
1804 u_suballocator_alloc(
1805 rctx->allocator_zeroed_memory, 8, 8,
1806 &rquery->workaround_offset,
1807 (struct pipe_resource **)&rquery->workaround_buf);
1808
1809 /* Reset to NULL to avoid a redundant SET_PREDICATION
1810 * from launching the compute grid.
1811 */
1812 rctx->render_cond = NULL;
1813
1814 ctx->get_query_result_resource(
1815 ctx, query, true, PIPE_QUERY_TYPE_U64, 0,
1816 &rquery->workaround_buf->b.b, rquery->workaround_offset);
1817
1818 /* Settings this in the render cond atom is too late,
1819 * so set it here. */
1820 rctx->flags |= rctx->screen->barrier_flags.L2_to_cp |
1821 SI_CONTEXT_FLUSH_FOR_RENDER_COND;
1822
1823 rctx->render_cond_force_off = old_force_off;
1824 }
1825 }
1826
1827 rctx->render_cond = query;
1828 rctx->render_cond_invert = condition;
1829 rctx->render_cond_mode = mode;
1830
1831 si_set_atom_dirty((struct si_context*)rctx, atom, query != NULL);
1832 }
1833
1834 void si_suspend_queries(struct r600_common_context *ctx)
1835 {
1836 struct r600_query_hw *query;
1837
1838 LIST_FOR_EACH_ENTRY(query, &ctx->active_queries, list) {
1839 r600_query_hw_emit_stop(ctx, query);
1840 }
1841 assert(ctx->num_cs_dw_queries_suspend == 0);
1842 }
1843
1844 void si_resume_queries(struct r600_common_context *ctx)
1845 {
1846 struct r600_query_hw *query;
1847
1848 assert(ctx->num_cs_dw_queries_suspend == 0);
1849
1850 /* Check CS space here. Resuming must not be interrupted by flushes. */
1851 si_need_gfx_cs_space((struct si_context*)ctx);
1852
1853 LIST_FOR_EACH_ENTRY(query, &ctx->active_queries, list) {
1854 r600_query_hw_emit_start(ctx, query);
1855 }
1856 }
1857
1858 #define XFULL(name_, query_type_, type_, result_type_, group_id_) \
1859 { \
1860 .name = name_, \
1861 .query_type = R600_QUERY_##query_type_, \
1862 .type = PIPE_DRIVER_QUERY_TYPE_##type_, \
1863 .result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_##result_type_, \
1864 .group_id = group_id_ \
1865 }
1866
1867 #define X(name_, query_type_, type_, result_type_) \
1868 XFULL(name_, query_type_, type_, result_type_, ~(unsigned)0)
1869
1870 #define XG(group_, name_, query_type_, type_, result_type_) \
1871 XFULL(name_, query_type_, type_, result_type_, R600_QUERY_GROUP_##group_)
1872
1873 static struct pipe_driver_query_info r600_driver_query_list[] = {
1874 X("num-compilations", NUM_COMPILATIONS, UINT64, CUMULATIVE),
1875 X("num-shaders-created", NUM_SHADERS_CREATED, UINT64, CUMULATIVE),
1876 X("num-shader-cache-hits", NUM_SHADER_CACHE_HITS, UINT64, CUMULATIVE),
1877 X("draw-calls", DRAW_CALLS, UINT64, AVERAGE),
1878 X("decompress-calls", DECOMPRESS_CALLS, UINT64, AVERAGE),
1879 X("MRT-draw-calls", MRT_DRAW_CALLS, UINT64, AVERAGE),
1880 X("prim-restart-calls", PRIM_RESTART_CALLS, UINT64, AVERAGE),
1881 X("spill-draw-calls", SPILL_DRAW_CALLS, UINT64, AVERAGE),
1882 X("compute-calls", COMPUTE_CALLS, UINT64, AVERAGE),
1883 X("spill-compute-calls", SPILL_COMPUTE_CALLS, UINT64, AVERAGE),
1884 X("dma-calls", DMA_CALLS, UINT64, AVERAGE),
1885 X("cp-dma-calls", CP_DMA_CALLS, UINT64, AVERAGE),
1886 X("num-vs-flushes", NUM_VS_FLUSHES, UINT64, AVERAGE),
1887 X("num-ps-flushes", NUM_PS_FLUSHES, UINT64, AVERAGE),
1888 X("num-cs-flushes", NUM_CS_FLUSHES, UINT64, AVERAGE),
1889 X("num-CB-cache-flushes", NUM_CB_CACHE_FLUSHES, UINT64, AVERAGE),
1890 X("num-DB-cache-flushes", NUM_DB_CACHE_FLUSHES, UINT64, AVERAGE),
1891 X("num-L2-invalidates", NUM_L2_INVALIDATES, UINT64, AVERAGE),
1892 X("num-L2-writebacks", NUM_L2_WRITEBACKS, UINT64, AVERAGE),
1893 X("num-resident-handles", NUM_RESIDENT_HANDLES, UINT64, AVERAGE),
1894 X("tc-offloaded-slots", TC_OFFLOADED_SLOTS, UINT64, AVERAGE),
1895 X("tc-direct-slots", TC_DIRECT_SLOTS, UINT64, AVERAGE),
1896 X("tc-num-syncs", TC_NUM_SYNCS, UINT64, AVERAGE),
1897 X("CS-thread-busy", CS_THREAD_BUSY, UINT64, AVERAGE),
1898 X("gallium-thread-busy", GALLIUM_THREAD_BUSY, UINT64, AVERAGE),
1899 X("requested-VRAM", REQUESTED_VRAM, BYTES, AVERAGE),
1900 X("requested-GTT", REQUESTED_GTT, BYTES, AVERAGE),
1901 X("mapped-VRAM", MAPPED_VRAM, BYTES, AVERAGE),
1902 X("mapped-GTT", MAPPED_GTT, BYTES, AVERAGE),
1903 X("buffer-wait-time", BUFFER_WAIT_TIME, MICROSECONDS, CUMULATIVE),
1904 X("num-mapped-buffers", NUM_MAPPED_BUFFERS, UINT64, AVERAGE),
1905 X("num-GFX-IBs", NUM_GFX_IBS, UINT64, AVERAGE),
1906 X("num-SDMA-IBs", NUM_SDMA_IBS, UINT64, AVERAGE),
1907 X("GFX-BO-list-size", GFX_BO_LIST_SIZE, UINT64, AVERAGE),
1908 X("GFX-IB-size", GFX_IB_SIZE, UINT64, AVERAGE),
1909 X("num-bytes-moved", NUM_BYTES_MOVED, BYTES, CUMULATIVE),
1910 X("num-evictions", NUM_EVICTIONS, UINT64, CUMULATIVE),
1911 X("VRAM-CPU-page-faults", NUM_VRAM_CPU_PAGE_FAULTS, UINT64, CUMULATIVE),
1912 X("VRAM-usage", VRAM_USAGE, BYTES, AVERAGE),
1913 X("VRAM-vis-usage", VRAM_VIS_USAGE, BYTES, AVERAGE),
1914 X("GTT-usage", GTT_USAGE, BYTES, AVERAGE),
1915 X("back-buffer-ps-draw-ratio", BACK_BUFFER_PS_DRAW_RATIO, UINT64, AVERAGE),
1916
1917 /* GPIN queries are for the benefit of old versions of GPUPerfStudio,
1918 * which use it as a fallback path to detect the GPU type.
1919 *
1920 * Note: The names of these queries are significant for GPUPerfStudio
1921 * (and possibly their order as well). */
1922 XG(GPIN, "GPIN_000", GPIN_ASIC_ID, UINT, AVERAGE),
1923 XG(GPIN, "GPIN_001", GPIN_NUM_SIMD, UINT, AVERAGE),
1924 XG(GPIN, "GPIN_002", GPIN_NUM_RB, UINT, AVERAGE),
1925 XG(GPIN, "GPIN_003", GPIN_NUM_SPI, UINT, AVERAGE),
1926 XG(GPIN, "GPIN_004", GPIN_NUM_SE, UINT, AVERAGE),
1927
1928 X("temperature", GPU_TEMPERATURE, UINT64, AVERAGE),
1929 X("shader-clock", CURRENT_GPU_SCLK, HZ, AVERAGE),
1930 X("memory-clock", CURRENT_GPU_MCLK, HZ, AVERAGE),
1931
1932 /* The following queries must be at the end of the list because their
1933 * availability is adjusted dynamically based on the DRM version. */
1934 X("GPU-load", GPU_LOAD, UINT64, AVERAGE),
1935 X("GPU-shaders-busy", GPU_SHADERS_BUSY, UINT64, AVERAGE),
1936 X("GPU-ta-busy", GPU_TA_BUSY, UINT64, AVERAGE),
1937 X("GPU-gds-busy", GPU_GDS_BUSY, UINT64, AVERAGE),
1938 X("GPU-vgt-busy", GPU_VGT_BUSY, UINT64, AVERAGE),
1939 X("GPU-ia-busy", GPU_IA_BUSY, UINT64, AVERAGE),
1940 X("GPU-sx-busy", GPU_SX_BUSY, UINT64, AVERAGE),
1941 X("GPU-wd-busy", GPU_WD_BUSY, UINT64, AVERAGE),
1942 X("GPU-bci-busy", GPU_BCI_BUSY, UINT64, AVERAGE),
1943 X("GPU-sc-busy", GPU_SC_BUSY, UINT64, AVERAGE),
1944 X("GPU-pa-busy", GPU_PA_BUSY, UINT64, AVERAGE),
1945 X("GPU-db-busy", GPU_DB_BUSY, UINT64, AVERAGE),
1946 X("GPU-cp-busy", GPU_CP_BUSY, UINT64, AVERAGE),
1947 X("GPU-cb-busy", GPU_CB_BUSY, UINT64, AVERAGE),
1948 X("GPU-sdma-busy", GPU_SDMA_BUSY, UINT64, AVERAGE),
1949 X("GPU-pfp-busy", GPU_PFP_BUSY, UINT64, AVERAGE),
1950 X("GPU-meq-busy", GPU_MEQ_BUSY, UINT64, AVERAGE),
1951 X("GPU-me-busy", GPU_ME_BUSY, UINT64, AVERAGE),
1952 X("GPU-surf-sync-busy", GPU_SURF_SYNC_BUSY, UINT64, AVERAGE),
1953 X("GPU-cp-dma-busy", GPU_CP_DMA_BUSY, UINT64, AVERAGE),
1954 X("GPU-scratch-ram-busy", GPU_SCRATCH_RAM_BUSY, UINT64, AVERAGE),
1955 };
1956
1957 #undef X
1958 #undef XG
1959 #undef XFULL
1960
1961 static unsigned r600_get_num_queries(struct si_screen *sscreen)
1962 {
1963 if (sscreen->info.drm_major == 2 && sscreen->info.drm_minor >= 42)
1964 return ARRAY_SIZE(r600_driver_query_list);
1965 else if (sscreen->info.drm_major == 3) {
1966 if (sscreen->info.chip_class >= VI)
1967 return ARRAY_SIZE(r600_driver_query_list);
1968 else
1969 return ARRAY_SIZE(r600_driver_query_list) - 7;
1970 }
1971 else
1972 return ARRAY_SIZE(r600_driver_query_list) - 25;
1973 }
1974
1975 static int r600_get_driver_query_info(struct pipe_screen *screen,
1976 unsigned index,
1977 struct pipe_driver_query_info *info)
1978 {
1979 struct si_screen *sscreen = (struct si_screen*)screen;
1980 unsigned num_queries = r600_get_num_queries(sscreen);
1981
1982 if (!info) {
1983 unsigned num_perfcounters =
1984 si_get_perfcounter_info(sscreen, 0, NULL);
1985
1986 return num_queries + num_perfcounters;
1987 }
1988
1989 if (index >= num_queries)
1990 return si_get_perfcounter_info(sscreen, index - num_queries, info);
1991
1992 *info = r600_driver_query_list[index];
1993
1994 switch (info->query_type) {
1995 case R600_QUERY_REQUESTED_VRAM:
1996 case R600_QUERY_VRAM_USAGE:
1997 case R600_QUERY_MAPPED_VRAM:
1998 info->max_value.u64 = sscreen->info.vram_size;
1999 break;
2000 case R600_QUERY_REQUESTED_GTT:
2001 case R600_QUERY_GTT_USAGE:
2002 case R600_QUERY_MAPPED_GTT:
2003 info->max_value.u64 = sscreen->info.gart_size;
2004 break;
2005 case R600_QUERY_GPU_TEMPERATURE:
2006 info->max_value.u64 = 125;
2007 break;
2008 case R600_QUERY_VRAM_VIS_USAGE:
2009 info->max_value.u64 = sscreen->info.vram_vis_size;
2010 break;
2011 }
2012
2013 if (info->group_id != ~(unsigned)0 && sscreen->perfcounters)
2014 info->group_id += sscreen->perfcounters->num_groups;
2015
2016 return 1;
2017 }
2018
2019 /* Note: Unfortunately, GPUPerfStudio hardcodes the order of hardware
2020 * performance counter groups, so be careful when changing this and related
2021 * functions.
2022 */
2023 static int r600_get_driver_query_group_info(struct pipe_screen *screen,
2024 unsigned index,
2025 struct pipe_driver_query_group_info *info)
2026 {
2027 struct si_screen *sscreen = (struct si_screen *)screen;
2028 unsigned num_pc_groups = 0;
2029
2030 if (sscreen->perfcounters)
2031 num_pc_groups = sscreen->perfcounters->num_groups;
2032
2033 if (!info)
2034 return num_pc_groups + R600_NUM_SW_QUERY_GROUPS;
2035
2036 if (index < num_pc_groups)
2037 return si_get_perfcounter_group_info(sscreen, index, info);
2038
2039 index -= num_pc_groups;
2040 if (index >= R600_NUM_SW_QUERY_GROUPS)
2041 return 0;
2042
2043 info->name = "GPIN";
2044 info->max_active_queries = 5;
2045 info->num_queries = 5;
2046 return 1;
2047 }
2048
2049 void si_init_query_functions(struct r600_common_context *rctx)
2050 {
2051 rctx->b.create_query = r600_create_query;
2052 rctx->b.create_batch_query = si_create_batch_query;
2053 rctx->b.destroy_query = r600_destroy_query;
2054 rctx->b.begin_query = r600_begin_query;
2055 rctx->b.end_query = r600_end_query;
2056 rctx->b.get_query_result = r600_get_query_result;
2057 rctx->b.get_query_result_resource = r600_get_query_result_resource;
2058 rctx->render_cond_atom.emit = r600_emit_query_predication;
2059
2060 if (((struct si_screen*)rctx->b.screen)->info.num_render_backends > 0)
2061 rctx->b.render_condition = r600_render_condition;
2062
2063 LIST_INITHEAD(&rctx->active_queries);
2064 }
2065
2066 void si_init_screen_query_functions(struct si_screen *sscreen)
2067 {
2068 sscreen->b.get_driver_query_info = r600_get_driver_query_info;
2069 sscreen->b.get_driver_query_group_info = r600_get_driver_query_group_info;
2070 }