2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014 Marek Olšák <marek.olsak@amd.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "r600_query.h"
27 #include "util/u_memory.h"
28 #include "util/u_upload_mgr.h"
29 #include "os/os_time.h"
30 #include "tgsi/tgsi_text.h"
32 struct r600_hw_query_params
{
33 unsigned start_offset
;
35 unsigned fence_offset
;
40 /* Queries without buffer handling or suspend/resume. */
41 struct r600_query_sw
{
44 uint64_t begin_result
;
50 /* Fence for GPU_FINISHED. */
51 struct pipe_fence_handle
*fence
;
54 static void r600_query_sw_destroy(struct r600_common_screen
*rscreen
,
55 struct r600_query
*rquery
)
57 struct r600_query_sw
*query
= (struct r600_query_sw
*)rquery
;
59 rscreen
->b
.fence_reference(&rscreen
->b
, &query
->fence
, NULL
);
63 static enum radeon_value_id
winsys_id_from_type(unsigned type
)
66 case R600_QUERY_REQUESTED_VRAM
: return RADEON_REQUESTED_VRAM_MEMORY
;
67 case R600_QUERY_REQUESTED_GTT
: return RADEON_REQUESTED_GTT_MEMORY
;
68 case R600_QUERY_MAPPED_VRAM
: return RADEON_MAPPED_VRAM
;
69 case R600_QUERY_MAPPED_GTT
: return RADEON_MAPPED_GTT
;
70 case R600_QUERY_BUFFER_WAIT_TIME
: return RADEON_BUFFER_WAIT_TIME_NS
;
71 case R600_QUERY_NUM_MAPPED_BUFFERS
: return RADEON_NUM_MAPPED_BUFFERS
;
72 case R600_QUERY_NUM_GFX_IBS
: return RADEON_NUM_GFX_IBS
;
73 case R600_QUERY_NUM_SDMA_IBS
: return RADEON_NUM_SDMA_IBS
;
74 case R600_QUERY_GFX_BO_LIST_SIZE
: return RADEON_GFX_BO_LIST_COUNTER
;
75 case R600_QUERY_NUM_BYTES_MOVED
: return RADEON_NUM_BYTES_MOVED
;
76 case R600_QUERY_NUM_EVICTIONS
: return RADEON_NUM_EVICTIONS
;
77 case R600_QUERY_NUM_VRAM_CPU_PAGE_FAULTS
: return RADEON_NUM_VRAM_CPU_PAGE_FAULTS
;
78 case R600_QUERY_VRAM_USAGE
: return RADEON_VRAM_USAGE
;
79 case R600_QUERY_VRAM_VIS_USAGE
: return RADEON_VRAM_VIS_USAGE
;
80 case R600_QUERY_GTT_USAGE
: return RADEON_GTT_USAGE
;
81 case R600_QUERY_GPU_TEMPERATURE
: return RADEON_GPU_TEMPERATURE
;
82 case R600_QUERY_CURRENT_GPU_SCLK
: return RADEON_CURRENT_SCLK
;
83 case R600_QUERY_CURRENT_GPU_MCLK
: return RADEON_CURRENT_MCLK
;
84 case R600_QUERY_CS_THREAD_BUSY
: return RADEON_CS_THREAD_TIME
;
85 default: unreachable("query type does not correspond to winsys id");
89 static bool r600_query_sw_begin(struct r600_common_context
*rctx
,
90 struct r600_query
*rquery
)
92 struct r600_query_sw
*query
= (struct r600_query_sw
*)rquery
;
93 enum radeon_value_id ws_id
;
95 switch(query
->b
.type
) {
96 case PIPE_QUERY_TIMESTAMP_DISJOINT
:
97 case PIPE_QUERY_GPU_FINISHED
:
99 case R600_QUERY_DRAW_CALLS
:
100 query
->begin_result
= rctx
->num_draw_calls
;
102 case R600_QUERY_MRT_DRAW_CALLS
:
103 query
->begin_result
= rctx
->num_mrt_draw_calls
;
105 case R600_QUERY_PRIM_RESTART_CALLS
:
106 query
->begin_result
= rctx
->num_prim_restart_calls
;
108 case R600_QUERY_SPILL_DRAW_CALLS
:
109 query
->begin_result
= rctx
->num_spill_draw_calls
;
111 case R600_QUERY_COMPUTE_CALLS
:
112 query
->begin_result
= rctx
->num_compute_calls
;
114 case R600_QUERY_SPILL_COMPUTE_CALLS
:
115 query
->begin_result
= rctx
->num_spill_compute_calls
;
117 case R600_QUERY_DMA_CALLS
:
118 query
->begin_result
= rctx
->num_dma_calls
;
120 case R600_QUERY_CP_DMA_CALLS
:
121 query
->begin_result
= rctx
->num_cp_dma_calls
;
123 case R600_QUERY_NUM_VS_FLUSHES
:
124 query
->begin_result
= rctx
->num_vs_flushes
;
126 case R600_QUERY_NUM_PS_FLUSHES
:
127 query
->begin_result
= rctx
->num_ps_flushes
;
129 case R600_QUERY_NUM_CS_FLUSHES
:
130 query
->begin_result
= rctx
->num_cs_flushes
;
132 case R600_QUERY_NUM_CB_CACHE_FLUSHES
:
133 query
->begin_result
= rctx
->num_cb_cache_flushes
;
135 case R600_QUERY_NUM_DB_CACHE_FLUSHES
:
136 query
->begin_result
= rctx
->num_db_cache_flushes
;
138 case R600_QUERY_NUM_L2_INVALIDATES
:
139 query
->begin_result
= rctx
->num_L2_invalidates
;
141 case R600_QUERY_NUM_L2_WRITEBACKS
:
142 query
->begin_result
= rctx
->num_L2_writebacks
;
144 case R600_QUERY_NUM_RESIDENT_HANDLES
:
145 query
->begin_result
= rctx
->num_resident_handles
;
147 case R600_QUERY_TC_OFFLOADED_SLOTS
:
148 query
->begin_result
= rctx
->tc
? rctx
->tc
->num_offloaded_slots
: 0;
150 case R600_QUERY_TC_DIRECT_SLOTS
:
151 query
->begin_result
= rctx
->tc
? rctx
->tc
->num_direct_slots
: 0;
153 case R600_QUERY_TC_NUM_SYNCS
:
154 query
->begin_result
= rctx
->tc
? rctx
->tc
->num_syncs
: 0;
156 case R600_QUERY_REQUESTED_VRAM
:
157 case R600_QUERY_REQUESTED_GTT
:
158 case R600_QUERY_MAPPED_VRAM
:
159 case R600_QUERY_MAPPED_GTT
:
160 case R600_QUERY_VRAM_USAGE
:
161 case R600_QUERY_VRAM_VIS_USAGE
:
162 case R600_QUERY_GTT_USAGE
:
163 case R600_QUERY_GPU_TEMPERATURE
:
164 case R600_QUERY_CURRENT_GPU_SCLK
:
165 case R600_QUERY_CURRENT_GPU_MCLK
:
166 case R600_QUERY_BACK_BUFFER_PS_DRAW_RATIO
:
167 case R600_QUERY_NUM_MAPPED_BUFFERS
:
168 query
->begin_result
= 0;
170 case R600_QUERY_BUFFER_WAIT_TIME
:
171 case R600_QUERY_NUM_GFX_IBS
:
172 case R600_QUERY_NUM_SDMA_IBS
:
173 case R600_QUERY_NUM_BYTES_MOVED
:
174 case R600_QUERY_NUM_EVICTIONS
:
175 case R600_QUERY_NUM_VRAM_CPU_PAGE_FAULTS
: {
176 enum radeon_value_id ws_id
= winsys_id_from_type(query
->b
.type
);
177 query
->begin_result
= rctx
->ws
->query_value(rctx
->ws
, ws_id
);
180 case R600_QUERY_GFX_BO_LIST_SIZE
:
181 ws_id
= winsys_id_from_type(query
->b
.type
);
182 query
->begin_result
= rctx
->ws
->query_value(rctx
->ws
, ws_id
);
183 query
->begin_time
= rctx
->ws
->query_value(rctx
->ws
,
186 case R600_QUERY_CS_THREAD_BUSY
:
187 ws_id
= winsys_id_from_type(query
->b
.type
);
188 query
->begin_result
= rctx
->ws
->query_value(rctx
->ws
, ws_id
);
189 query
->begin_time
= os_time_get_nano();
191 case R600_QUERY_GALLIUM_THREAD_BUSY
:
192 query
->begin_result
=
193 rctx
->tc
? util_queue_get_thread_time_nano(&rctx
->tc
->queue
, 0) : 0;
194 query
->begin_time
= os_time_get_nano();
196 case R600_QUERY_GPU_LOAD
:
197 case R600_QUERY_GPU_SHADERS_BUSY
:
198 case R600_QUERY_GPU_TA_BUSY
:
199 case R600_QUERY_GPU_GDS_BUSY
:
200 case R600_QUERY_GPU_VGT_BUSY
:
201 case R600_QUERY_GPU_IA_BUSY
:
202 case R600_QUERY_GPU_SX_BUSY
:
203 case R600_QUERY_GPU_WD_BUSY
:
204 case R600_QUERY_GPU_BCI_BUSY
:
205 case R600_QUERY_GPU_SC_BUSY
:
206 case R600_QUERY_GPU_PA_BUSY
:
207 case R600_QUERY_GPU_DB_BUSY
:
208 case R600_QUERY_GPU_CP_BUSY
:
209 case R600_QUERY_GPU_CB_BUSY
:
210 case R600_QUERY_GPU_SDMA_BUSY
:
211 case R600_QUERY_GPU_PFP_BUSY
:
212 case R600_QUERY_GPU_MEQ_BUSY
:
213 case R600_QUERY_GPU_ME_BUSY
:
214 case R600_QUERY_GPU_SURF_SYNC_BUSY
:
215 case R600_QUERY_GPU_DMA_BUSY
:
216 case R600_QUERY_GPU_SCRATCH_RAM_BUSY
:
217 case R600_QUERY_GPU_CE_BUSY
:
218 query
->begin_result
= r600_begin_counter(rctx
->screen
,
221 case R600_QUERY_NUM_COMPILATIONS
:
222 query
->begin_result
= p_atomic_read(&rctx
->screen
->num_compilations
);
224 case R600_QUERY_NUM_SHADERS_CREATED
:
225 query
->begin_result
= p_atomic_read(&rctx
->screen
->num_shaders_created
);
227 case R600_QUERY_NUM_SHADER_CACHE_HITS
:
228 query
->begin_result
=
229 p_atomic_read(&rctx
->screen
->num_shader_cache_hits
);
231 case R600_QUERY_GPIN_ASIC_ID
:
232 case R600_QUERY_GPIN_NUM_SIMD
:
233 case R600_QUERY_GPIN_NUM_RB
:
234 case R600_QUERY_GPIN_NUM_SPI
:
235 case R600_QUERY_GPIN_NUM_SE
:
238 unreachable("r600_query_sw_begin: bad query type");
244 static bool r600_query_sw_end(struct r600_common_context
*rctx
,
245 struct r600_query
*rquery
)
247 struct r600_query_sw
*query
= (struct r600_query_sw
*)rquery
;
248 enum radeon_value_id ws_id
;
250 switch(query
->b
.type
) {
251 case PIPE_QUERY_TIMESTAMP_DISJOINT
:
253 case PIPE_QUERY_GPU_FINISHED
:
254 rctx
->b
.flush(&rctx
->b
, &query
->fence
, PIPE_FLUSH_DEFERRED
);
256 case R600_QUERY_DRAW_CALLS
:
257 query
->end_result
= rctx
->num_draw_calls
;
259 case R600_QUERY_MRT_DRAW_CALLS
:
260 query
->end_result
= rctx
->num_mrt_draw_calls
;
262 case R600_QUERY_PRIM_RESTART_CALLS
:
263 query
->end_result
= rctx
->num_prim_restart_calls
;
265 case R600_QUERY_SPILL_DRAW_CALLS
:
266 query
->end_result
= rctx
->num_spill_draw_calls
;
268 case R600_QUERY_COMPUTE_CALLS
:
269 query
->end_result
= rctx
->num_compute_calls
;
271 case R600_QUERY_SPILL_COMPUTE_CALLS
:
272 query
->end_result
= rctx
->num_spill_compute_calls
;
274 case R600_QUERY_DMA_CALLS
:
275 query
->end_result
= rctx
->num_dma_calls
;
277 case R600_QUERY_CP_DMA_CALLS
:
278 query
->end_result
= rctx
->num_cp_dma_calls
;
280 case R600_QUERY_NUM_VS_FLUSHES
:
281 query
->end_result
= rctx
->num_vs_flushes
;
283 case R600_QUERY_NUM_PS_FLUSHES
:
284 query
->end_result
= rctx
->num_ps_flushes
;
286 case R600_QUERY_NUM_CS_FLUSHES
:
287 query
->end_result
= rctx
->num_cs_flushes
;
289 case R600_QUERY_NUM_CB_CACHE_FLUSHES
:
290 query
->end_result
= rctx
->num_cb_cache_flushes
;
292 case R600_QUERY_NUM_DB_CACHE_FLUSHES
:
293 query
->end_result
= rctx
->num_db_cache_flushes
;
295 case R600_QUERY_NUM_L2_INVALIDATES
:
296 query
->end_result
= rctx
->num_L2_invalidates
;
298 case R600_QUERY_NUM_L2_WRITEBACKS
:
299 query
->end_result
= rctx
->num_L2_writebacks
;
301 case R600_QUERY_NUM_RESIDENT_HANDLES
:
302 query
->end_result
= rctx
->num_resident_handles
;
304 case R600_QUERY_TC_OFFLOADED_SLOTS
:
305 query
->end_result
= rctx
->tc
? rctx
->tc
->num_offloaded_slots
: 0;
307 case R600_QUERY_TC_DIRECT_SLOTS
:
308 query
->end_result
= rctx
->tc
? rctx
->tc
->num_direct_slots
: 0;
310 case R600_QUERY_TC_NUM_SYNCS
:
311 query
->end_result
= rctx
->tc
? rctx
->tc
->num_syncs
: 0;
313 case R600_QUERY_REQUESTED_VRAM
:
314 case R600_QUERY_REQUESTED_GTT
:
315 case R600_QUERY_MAPPED_VRAM
:
316 case R600_QUERY_MAPPED_GTT
:
317 case R600_QUERY_VRAM_USAGE
:
318 case R600_QUERY_VRAM_VIS_USAGE
:
319 case R600_QUERY_GTT_USAGE
:
320 case R600_QUERY_GPU_TEMPERATURE
:
321 case R600_QUERY_CURRENT_GPU_SCLK
:
322 case R600_QUERY_CURRENT_GPU_MCLK
:
323 case R600_QUERY_BUFFER_WAIT_TIME
:
324 case R600_QUERY_NUM_MAPPED_BUFFERS
:
325 case R600_QUERY_NUM_GFX_IBS
:
326 case R600_QUERY_NUM_SDMA_IBS
:
327 case R600_QUERY_NUM_BYTES_MOVED
:
328 case R600_QUERY_NUM_EVICTIONS
:
329 case R600_QUERY_NUM_VRAM_CPU_PAGE_FAULTS
: {
330 enum radeon_value_id ws_id
= winsys_id_from_type(query
->b
.type
);
331 query
->end_result
= rctx
->ws
->query_value(rctx
->ws
, ws_id
);
334 case R600_QUERY_GFX_BO_LIST_SIZE
:
335 ws_id
= winsys_id_from_type(query
->b
.type
);
336 query
->end_result
= rctx
->ws
->query_value(rctx
->ws
, ws_id
);
337 query
->end_time
= rctx
->ws
->query_value(rctx
->ws
,
340 case R600_QUERY_CS_THREAD_BUSY
:
341 ws_id
= winsys_id_from_type(query
->b
.type
);
342 query
->end_result
= rctx
->ws
->query_value(rctx
->ws
, ws_id
);
343 query
->end_time
= os_time_get_nano();
345 case R600_QUERY_GALLIUM_THREAD_BUSY
:
347 rctx
->tc
? util_queue_get_thread_time_nano(&rctx
->tc
->queue
, 0) : 0;
348 query
->end_time
= os_time_get_nano();
350 case R600_QUERY_GPU_LOAD
:
351 case R600_QUERY_GPU_SHADERS_BUSY
:
352 case R600_QUERY_GPU_TA_BUSY
:
353 case R600_QUERY_GPU_GDS_BUSY
:
354 case R600_QUERY_GPU_VGT_BUSY
:
355 case R600_QUERY_GPU_IA_BUSY
:
356 case R600_QUERY_GPU_SX_BUSY
:
357 case R600_QUERY_GPU_WD_BUSY
:
358 case R600_QUERY_GPU_BCI_BUSY
:
359 case R600_QUERY_GPU_SC_BUSY
:
360 case R600_QUERY_GPU_PA_BUSY
:
361 case R600_QUERY_GPU_DB_BUSY
:
362 case R600_QUERY_GPU_CP_BUSY
:
363 case R600_QUERY_GPU_CB_BUSY
:
364 case R600_QUERY_GPU_SDMA_BUSY
:
365 case R600_QUERY_GPU_PFP_BUSY
:
366 case R600_QUERY_GPU_MEQ_BUSY
:
367 case R600_QUERY_GPU_ME_BUSY
:
368 case R600_QUERY_GPU_SURF_SYNC_BUSY
:
369 case R600_QUERY_GPU_DMA_BUSY
:
370 case R600_QUERY_GPU_SCRATCH_RAM_BUSY
:
371 case R600_QUERY_GPU_CE_BUSY
:
372 query
->end_result
= r600_end_counter(rctx
->screen
,
374 query
->begin_result
);
375 query
->begin_result
= 0;
377 case R600_QUERY_NUM_COMPILATIONS
:
378 query
->end_result
= p_atomic_read(&rctx
->screen
->num_compilations
);
380 case R600_QUERY_NUM_SHADERS_CREATED
:
381 query
->end_result
= p_atomic_read(&rctx
->screen
->num_shaders_created
);
383 case R600_QUERY_BACK_BUFFER_PS_DRAW_RATIO
:
384 query
->end_result
= rctx
->last_tex_ps_draw_ratio
;
386 case R600_QUERY_NUM_SHADER_CACHE_HITS
:
388 p_atomic_read(&rctx
->screen
->num_shader_cache_hits
);
390 case R600_QUERY_GPIN_ASIC_ID
:
391 case R600_QUERY_GPIN_NUM_SIMD
:
392 case R600_QUERY_GPIN_NUM_RB
:
393 case R600_QUERY_GPIN_NUM_SPI
:
394 case R600_QUERY_GPIN_NUM_SE
:
397 unreachable("r600_query_sw_end: bad query type");
403 static bool r600_query_sw_get_result(struct r600_common_context
*rctx
,
404 struct r600_query
*rquery
,
406 union pipe_query_result
*result
)
408 struct r600_query_sw
*query
= (struct r600_query_sw
*)rquery
;
410 switch (query
->b
.type
) {
411 case PIPE_QUERY_TIMESTAMP_DISJOINT
:
412 /* Convert from cycles per millisecond to cycles per second (Hz). */
413 result
->timestamp_disjoint
.frequency
=
414 (uint64_t)rctx
->screen
->info
.clock_crystal_freq
* 1000;
415 result
->timestamp_disjoint
.disjoint
= false;
417 case PIPE_QUERY_GPU_FINISHED
: {
418 struct pipe_screen
*screen
= rctx
->b
.screen
;
419 struct pipe_context
*ctx
= rquery
->b
.flushed
? NULL
: &rctx
->b
;
421 result
->b
= screen
->fence_finish(screen
, ctx
, query
->fence
,
422 wait
? PIPE_TIMEOUT_INFINITE
: 0);
426 case R600_QUERY_GFX_BO_LIST_SIZE
:
427 result
->u64
= (query
->end_result
- query
->begin_result
) /
428 (query
->end_time
- query
->begin_time
);
430 case R600_QUERY_CS_THREAD_BUSY
:
431 case R600_QUERY_GALLIUM_THREAD_BUSY
:
432 result
->u64
= (query
->end_result
- query
->begin_result
) * 100 /
433 (query
->end_time
- query
->begin_time
);
435 case R600_QUERY_GPIN_ASIC_ID
:
438 case R600_QUERY_GPIN_NUM_SIMD
:
439 result
->u32
= rctx
->screen
->info
.num_good_compute_units
;
441 case R600_QUERY_GPIN_NUM_RB
:
442 result
->u32
= rctx
->screen
->info
.num_render_backends
;
444 case R600_QUERY_GPIN_NUM_SPI
:
445 result
->u32
= 1; /* all supported chips have one SPI per SE */
447 case R600_QUERY_GPIN_NUM_SE
:
448 result
->u32
= rctx
->screen
->info
.max_se
;
452 result
->u64
= query
->end_result
- query
->begin_result
;
454 switch (query
->b
.type
) {
455 case R600_QUERY_BUFFER_WAIT_TIME
:
456 case R600_QUERY_GPU_TEMPERATURE
:
459 case R600_QUERY_CURRENT_GPU_SCLK
:
460 case R600_QUERY_CURRENT_GPU_MCLK
:
461 result
->u64
*= 1000000;
469 static struct r600_query_ops sw_query_ops
= {
470 .destroy
= r600_query_sw_destroy
,
471 .begin
= r600_query_sw_begin
,
472 .end
= r600_query_sw_end
,
473 .get_result
= r600_query_sw_get_result
,
474 .get_result_resource
= NULL
477 static struct pipe_query
*r600_query_sw_create(unsigned query_type
)
479 struct r600_query_sw
*query
;
481 query
= CALLOC_STRUCT(r600_query_sw
);
485 query
->b
.type
= query_type
;
486 query
->b
.ops
= &sw_query_ops
;
488 return (struct pipe_query
*)query
;
491 void r600_query_hw_destroy(struct r600_common_screen
*rscreen
,
492 struct r600_query
*rquery
)
494 struct r600_query_hw
*query
= (struct r600_query_hw
*)rquery
;
495 struct r600_query_buffer
*prev
= query
->buffer
.previous
;
497 /* Release all query buffers. */
499 struct r600_query_buffer
*qbuf
= prev
;
500 prev
= prev
->previous
;
501 r600_resource_reference(&qbuf
->buf
, NULL
);
505 r600_resource_reference(&query
->buffer
.buf
, NULL
);
509 static struct r600_resource
*r600_new_query_buffer(struct r600_common_screen
*rscreen
,
510 struct r600_query_hw
*query
)
512 unsigned buf_size
= MAX2(query
->result_size
,
513 rscreen
->info
.min_alloc_size
);
515 /* Queries are normally read by the CPU after
516 * being written by the gpu, hence staging is probably a good
519 struct r600_resource
*buf
= (struct r600_resource
*)
520 pipe_buffer_create(&rscreen
->b
, 0,
521 PIPE_USAGE_STAGING
, buf_size
);
525 if (!query
->ops
->prepare_buffer(rscreen
, query
, buf
)) {
526 r600_resource_reference(&buf
, NULL
);
533 static bool r600_query_hw_prepare_buffer(struct r600_common_screen
*rscreen
,
534 struct r600_query_hw
*query
,
535 struct r600_resource
*buffer
)
537 /* Callers ensure that the buffer is currently unused by the GPU. */
538 uint32_t *results
= rscreen
->ws
->buffer_map(buffer
->buf
, NULL
,
539 PIPE_TRANSFER_WRITE
|
540 PIPE_TRANSFER_UNSYNCHRONIZED
);
544 memset(results
, 0, buffer
->b
.b
.width0
);
546 if (query
->b
.type
== PIPE_QUERY_OCCLUSION_COUNTER
||
547 query
->b
.type
== PIPE_QUERY_OCCLUSION_PREDICATE
) {
548 unsigned max_rbs
= rscreen
->info
.num_render_backends
;
549 unsigned enabled_rb_mask
= rscreen
->info
.enabled_rb_mask
;
550 unsigned num_results
;
553 /* Set top bits for unused backends. */
554 num_results
= buffer
->b
.b
.width0
/ query
->result_size
;
555 for (j
= 0; j
< num_results
; j
++) {
556 for (i
= 0; i
< max_rbs
; i
++) {
557 if (!(enabled_rb_mask
& (1<<i
))) {
558 results
[(i
* 4)+1] = 0x80000000;
559 results
[(i
* 4)+3] = 0x80000000;
562 results
+= 4 * max_rbs
;
569 static void r600_query_hw_get_result_resource(struct r600_common_context
*rctx
,
570 struct r600_query
*rquery
,
572 enum pipe_query_value_type result_type
,
574 struct pipe_resource
*resource
,
577 static struct r600_query_ops query_hw_ops
= {
578 .destroy
= r600_query_hw_destroy
,
579 .begin
= r600_query_hw_begin
,
580 .end
= r600_query_hw_end
,
581 .get_result
= r600_query_hw_get_result
,
582 .get_result_resource
= r600_query_hw_get_result_resource
,
585 static void r600_query_hw_do_emit_start(struct r600_common_context
*ctx
,
586 struct r600_query_hw
*query
,
587 struct r600_resource
*buffer
,
589 static void r600_query_hw_do_emit_stop(struct r600_common_context
*ctx
,
590 struct r600_query_hw
*query
,
591 struct r600_resource
*buffer
,
593 static void r600_query_hw_add_result(struct r600_common_screen
*rscreen
,
594 struct r600_query_hw
*, void *buffer
,
595 union pipe_query_result
*result
);
596 static void r600_query_hw_clear_result(struct r600_query_hw
*,
597 union pipe_query_result
*);
599 static struct r600_query_hw_ops query_hw_default_hw_ops
= {
600 .prepare_buffer
= r600_query_hw_prepare_buffer
,
601 .emit_start
= r600_query_hw_do_emit_start
,
602 .emit_stop
= r600_query_hw_do_emit_stop
,
603 .clear_result
= r600_query_hw_clear_result
,
604 .add_result
= r600_query_hw_add_result
,
607 bool r600_query_hw_init(struct r600_common_screen
*rscreen
,
608 struct r600_query_hw
*query
)
610 query
->buffer
.buf
= r600_new_query_buffer(rscreen
, query
);
611 if (!query
->buffer
.buf
)
617 static struct pipe_query
*r600_query_hw_create(struct r600_common_screen
*rscreen
,
621 struct r600_query_hw
*query
= CALLOC_STRUCT(r600_query_hw
);
625 query
->b
.type
= query_type
;
626 query
->b
.ops
= &query_hw_ops
;
627 query
->ops
= &query_hw_default_hw_ops
;
629 switch (query_type
) {
630 case PIPE_QUERY_OCCLUSION_COUNTER
:
631 case PIPE_QUERY_OCCLUSION_PREDICATE
:
632 query
->result_size
= 16 * rscreen
->info
.num_render_backends
;
633 query
->result_size
+= 16; /* for the fence + alignment */
634 query
->num_cs_dw_begin
= 6;
635 query
->num_cs_dw_end
= 6 + r600_gfx_write_fence_dwords(rscreen
);
637 case PIPE_QUERY_TIME_ELAPSED
:
638 query
->result_size
= 24;
639 query
->num_cs_dw_begin
= 8;
640 query
->num_cs_dw_end
= 8 + r600_gfx_write_fence_dwords(rscreen
);
642 case PIPE_QUERY_TIMESTAMP
:
643 query
->result_size
= 16;
644 query
->num_cs_dw_end
= 8 + r600_gfx_write_fence_dwords(rscreen
);
645 query
->flags
= R600_QUERY_HW_FLAG_NO_START
;
647 case PIPE_QUERY_PRIMITIVES_EMITTED
:
648 case PIPE_QUERY_PRIMITIVES_GENERATED
:
649 case PIPE_QUERY_SO_STATISTICS
:
650 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
651 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
652 query
->result_size
= 32;
653 query
->num_cs_dw_begin
= 6;
654 query
->num_cs_dw_end
= 6;
655 query
->stream
= index
;
657 case PIPE_QUERY_PIPELINE_STATISTICS
:
658 /* 11 values on EG, 8 on R600. */
659 query
->result_size
= (rscreen
->chip_class
>= EVERGREEN
? 11 : 8) * 16;
660 query
->result_size
+= 8; /* for the fence + alignment */
661 query
->num_cs_dw_begin
= 6;
662 query
->num_cs_dw_end
= 6 + r600_gfx_write_fence_dwords(rscreen
);
670 if (!r600_query_hw_init(rscreen
, query
)) {
675 return (struct pipe_query
*)query
;
678 static void r600_update_occlusion_query_state(struct r600_common_context
*rctx
,
679 unsigned type
, int diff
)
681 if (type
== PIPE_QUERY_OCCLUSION_COUNTER
||
682 type
== PIPE_QUERY_OCCLUSION_PREDICATE
) {
683 bool old_enable
= rctx
->num_occlusion_queries
!= 0;
684 bool old_perfect_enable
=
685 rctx
->num_perfect_occlusion_queries
!= 0;
686 bool enable
, perfect_enable
;
688 rctx
->num_occlusion_queries
+= diff
;
689 assert(rctx
->num_occlusion_queries
>= 0);
691 if (type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
692 rctx
->num_perfect_occlusion_queries
+= diff
;
693 assert(rctx
->num_perfect_occlusion_queries
>= 0);
696 enable
= rctx
->num_occlusion_queries
!= 0;
697 perfect_enable
= rctx
->num_perfect_occlusion_queries
!= 0;
699 if (enable
!= old_enable
|| perfect_enable
!= old_perfect_enable
) {
700 rctx
->set_occlusion_query_state(&rctx
->b
, enable
);
705 static unsigned event_type_for_stream(struct r600_query_hw
*query
)
707 switch (query
->stream
) {
709 case 0: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS
;
710 case 1: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS1
;
711 case 2: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS2
;
712 case 3: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS3
;
716 static void r600_query_hw_do_emit_start(struct r600_common_context
*ctx
,
717 struct r600_query_hw
*query
,
718 struct r600_resource
*buffer
,
721 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
723 switch (query
->b
.type
) {
724 case PIPE_QUERY_OCCLUSION_COUNTER
:
725 case PIPE_QUERY_OCCLUSION_PREDICATE
:
726 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
727 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE
) | EVENT_INDEX(1));
729 radeon_emit(cs
, va
>> 32);
731 case PIPE_QUERY_PRIMITIVES_EMITTED
:
732 case PIPE_QUERY_PRIMITIVES_GENERATED
:
733 case PIPE_QUERY_SO_STATISTICS
:
734 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
735 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
736 radeon_emit(cs
, EVENT_TYPE(event_type_for_stream(query
)) | EVENT_INDEX(3));
738 radeon_emit(cs
, va
>> 32);
740 case PIPE_QUERY_TIME_ELAPSED
:
741 if (ctx
->chip_class
>= SI
) {
742 /* Write the timestamp from the CP not waiting for
743 * outstanding draws (top-of-pipe).
745 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
746 radeon_emit(cs
, COPY_DATA_COUNT_SEL
|
747 COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP
) |
748 COPY_DATA_DST_SEL(COPY_DATA_MEM_ASYNC
));
752 radeon_emit(cs
, va
>> 32);
754 /* Write the timestamp after the last draw is done.
757 r600_gfx_write_event_eop(ctx
, EVENT_TYPE_BOTTOM_OF_PIPE_TS
,
758 0, 3, NULL
, va
, 0, 0);
761 case PIPE_QUERY_PIPELINE_STATISTICS
:
762 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
763 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT
) | EVENT_INDEX(2));
765 radeon_emit(cs
, va
>> 32);
770 r600_emit_reloc(ctx
, &ctx
->gfx
, query
->buffer
.buf
, RADEON_USAGE_WRITE
,
774 static void r600_query_hw_emit_start(struct r600_common_context
*ctx
,
775 struct r600_query_hw
*query
)
779 if (!query
->buffer
.buf
)
780 return; // previous buffer allocation failure
782 r600_update_occlusion_query_state(ctx
, query
->b
.type
, 1);
783 r600_update_prims_generated_query_state(ctx
, query
->b
.type
, 1);
785 ctx
->need_gfx_cs_space(&ctx
->b
, query
->num_cs_dw_begin
+ query
->num_cs_dw_end
,
788 /* Get a new query buffer if needed. */
789 if (query
->buffer
.results_end
+ query
->result_size
> query
->buffer
.buf
->b
.b
.width0
) {
790 struct r600_query_buffer
*qbuf
= MALLOC_STRUCT(r600_query_buffer
);
791 *qbuf
= query
->buffer
;
792 query
->buffer
.results_end
= 0;
793 query
->buffer
.previous
= qbuf
;
794 query
->buffer
.buf
= r600_new_query_buffer(ctx
->screen
, query
);
795 if (!query
->buffer
.buf
)
799 /* emit begin query */
800 va
= query
->buffer
.buf
->gpu_address
+ query
->buffer
.results_end
;
802 query
->ops
->emit_start(ctx
, query
, query
->buffer
.buf
, va
);
804 ctx
->num_cs_dw_queries_suspend
+= query
->num_cs_dw_end
;
807 static void r600_query_hw_do_emit_stop(struct r600_common_context
*ctx
,
808 struct r600_query_hw
*query
,
809 struct r600_resource
*buffer
,
812 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
813 uint64_t fence_va
= 0;
815 switch (query
->b
.type
) {
816 case PIPE_QUERY_OCCLUSION_COUNTER
:
817 case PIPE_QUERY_OCCLUSION_PREDICATE
:
819 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
820 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE
) | EVENT_INDEX(1));
822 radeon_emit(cs
, va
>> 32);
824 fence_va
= va
+ ctx
->screen
->info
.num_render_backends
* 16 - 8;
826 case PIPE_QUERY_PRIMITIVES_EMITTED
:
827 case PIPE_QUERY_PRIMITIVES_GENERATED
:
828 case PIPE_QUERY_SO_STATISTICS
:
829 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
830 va
+= query
->result_size
/2;
831 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
832 radeon_emit(cs
, EVENT_TYPE(event_type_for_stream(query
)) | EVENT_INDEX(3));
834 radeon_emit(cs
, va
>> 32);
836 case PIPE_QUERY_TIME_ELAPSED
:
839 case PIPE_QUERY_TIMESTAMP
:
840 r600_gfx_write_event_eop(ctx
, EVENT_TYPE_BOTTOM_OF_PIPE_TS
,
841 0, 3, NULL
, va
, 0, 0);
844 case PIPE_QUERY_PIPELINE_STATISTICS
: {
845 unsigned sample_size
= (query
->result_size
- 8) / 2;
848 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
849 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT
) | EVENT_INDEX(2));
851 radeon_emit(cs
, va
>> 32);
853 fence_va
= va
+ sample_size
;
859 r600_emit_reloc(ctx
, &ctx
->gfx
, query
->buffer
.buf
, RADEON_USAGE_WRITE
,
863 r600_gfx_write_event_eop(ctx
, EVENT_TYPE_BOTTOM_OF_PIPE_TS
, 0, 1,
864 query
->buffer
.buf
, fence_va
, 0, 0x80000000);
867 static void r600_query_hw_emit_stop(struct r600_common_context
*ctx
,
868 struct r600_query_hw
*query
)
872 if (!query
->buffer
.buf
)
873 return; // previous buffer allocation failure
875 /* The queries which need begin already called this in begin_query. */
876 if (query
->flags
& R600_QUERY_HW_FLAG_NO_START
) {
877 ctx
->need_gfx_cs_space(&ctx
->b
, query
->num_cs_dw_end
, false);
881 va
= query
->buffer
.buf
->gpu_address
+ query
->buffer
.results_end
;
883 query
->ops
->emit_stop(ctx
, query
, query
->buffer
.buf
, va
);
885 query
->buffer
.results_end
+= query
->result_size
;
887 if (!(query
->flags
& R600_QUERY_HW_FLAG_NO_START
))
888 ctx
->num_cs_dw_queries_suspend
-= query
->num_cs_dw_end
;
890 r600_update_occlusion_query_state(ctx
, query
->b
.type
, -1);
891 r600_update_prims_generated_query_state(ctx
, query
->b
.type
, -1);
894 static void r600_emit_query_predication(struct r600_common_context
*ctx
,
895 struct r600_atom
*atom
)
897 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
898 struct r600_query_hw
*query
= (struct r600_query_hw
*)ctx
->render_cond
;
899 struct r600_query_buffer
*qbuf
;
906 flag_wait
= ctx
->render_cond_mode
== PIPE_RENDER_COND_WAIT
||
907 ctx
->render_cond_mode
== PIPE_RENDER_COND_BY_REGION_WAIT
;
909 switch (query
->b
.type
) {
910 case PIPE_QUERY_OCCLUSION_COUNTER
:
911 case PIPE_QUERY_OCCLUSION_PREDICATE
:
912 op
= PRED_OP(PREDICATION_OP_ZPASS
);
914 case PIPE_QUERY_PRIMITIVES_EMITTED
:
915 case PIPE_QUERY_PRIMITIVES_GENERATED
:
916 case PIPE_QUERY_SO_STATISTICS
:
917 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
918 op
= PRED_OP(PREDICATION_OP_PRIMCOUNT
);
925 /* if true then invert, see GL_ARB_conditional_render_inverted */
926 if (ctx
->render_cond_invert
)
927 op
|= PREDICATION_DRAW_NOT_VISIBLE
; /* Draw if not visable/overflow */
929 op
|= PREDICATION_DRAW_VISIBLE
; /* Draw if visable/overflow */
931 op
|= flag_wait
? PREDICATION_HINT_WAIT
: PREDICATION_HINT_NOWAIT_DRAW
;
933 /* emit predicate packets for all data blocks */
934 for (qbuf
= &query
->buffer
; qbuf
; qbuf
= qbuf
->previous
) {
935 unsigned results_base
= 0;
936 uint64_t va_base
= qbuf
->buf
->gpu_address
;
938 while (results_base
< qbuf
->results_end
) {
939 uint64_t va
= va_base
+ results_base
;
941 if (ctx
->chip_class
>= GFX9
) {
942 radeon_emit(cs
, PKT3(PKT3_SET_PREDICATION
, 2, 0));
945 radeon_emit(cs
, va
>> 32);
947 radeon_emit(cs
, PKT3(PKT3_SET_PREDICATION
, 1, 0));
949 radeon_emit(cs
, op
| ((va
>> 32) & 0xFF));
951 r600_emit_reloc(ctx
, &ctx
->gfx
, qbuf
->buf
, RADEON_USAGE_READ
,
953 results_base
+= query
->result_size
;
955 /* set CONTINUE bit for all packets except the first */
956 op
|= PREDICATION_CONTINUE
;
961 static struct pipe_query
*r600_create_query(struct pipe_context
*ctx
, unsigned query_type
, unsigned index
)
963 struct r600_common_screen
*rscreen
=
964 (struct r600_common_screen
*)ctx
->screen
;
966 if (query_type
== PIPE_QUERY_TIMESTAMP_DISJOINT
||
967 query_type
== PIPE_QUERY_GPU_FINISHED
||
968 query_type
>= PIPE_QUERY_DRIVER_SPECIFIC
)
969 return r600_query_sw_create(query_type
);
971 return r600_query_hw_create(rscreen
, query_type
, index
);
974 static void r600_destroy_query(struct pipe_context
*ctx
, struct pipe_query
*query
)
976 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
977 struct r600_query
*rquery
= (struct r600_query
*)query
;
979 rquery
->ops
->destroy(rctx
->screen
, rquery
);
982 static boolean
r600_begin_query(struct pipe_context
*ctx
,
983 struct pipe_query
*query
)
985 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
986 struct r600_query
*rquery
= (struct r600_query
*)query
;
988 return rquery
->ops
->begin(rctx
, rquery
);
991 void r600_query_hw_reset_buffers(struct r600_common_context
*rctx
,
992 struct r600_query_hw
*query
)
994 struct r600_query_buffer
*prev
= query
->buffer
.previous
;
996 /* Discard the old query buffers. */
998 struct r600_query_buffer
*qbuf
= prev
;
999 prev
= prev
->previous
;
1000 r600_resource_reference(&qbuf
->buf
, NULL
);
1004 query
->buffer
.results_end
= 0;
1005 query
->buffer
.previous
= NULL
;
1007 /* Obtain a new buffer if the current one can't be mapped without a stall. */
1008 if (r600_rings_is_buffer_referenced(rctx
, query
->buffer
.buf
->buf
, RADEON_USAGE_READWRITE
) ||
1009 !rctx
->ws
->buffer_wait(query
->buffer
.buf
->buf
, 0, RADEON_USAGE_READWRITE
)) {
1010 r600_resource_reference(&query
->buffer
.buf
, NULL
);
1011 query
->buffer
.buf
= r600_new_query_buffer(rctx
->screen
, query
);
1013 if (!query
->ops
->prepare_buffer(rctx
->screen
, query
, query
->buffer
.buf
))
1014 r600_resource_reference(&query
->buffer
.buf
, NULL
);
1018 bool r600_query_hw_begin(struct r600_common_context
*rctx
,
1019 struct r600_query
*rquery
)
1021 struct r600_query_hw
*query
= (struct r600_query_hw
*)rquery
;
1023 if (query
->flags
& R600_QUERY_HW_FLAG_NO_START
) {
1028 if (!(query
->flags
& R600_QUERY_HW_FLAG_BEGIN_RESUMES
))
1029 r600_query_hw_reset_buffers(rctx
, query
);
1031 r600_query_hw_emit_start(rctx
, query
);
1032 if (!query
->buffer
.buf
)
1035 LIST_ADDTAIL(&query
->list
, &rctx
->active_queries
);
1039 static bool r600_end_query(struct pipe_context
*ctx
, struct pipe_query
*query
)
1041 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1042 struct r600_query
*rquery
= (struct r600_query
*)query
;
1044 return rquery
->ops
->end(rctx
, rquery
);
1047 bool r600_query_hw_end(struct r600_common_context
*rctx
,
1048 struct r600_query
*rquery
)
1050 struct r600_query_hw
*query
= (struct r600_query_hw
*)rquery
;
1052 if (query
->flags
& R600_QUERY_HW_FLAG_NO_START
)
1053 r600_query_hw_reset_buffers(rctx
, query
);
1055 r600_query_hw_emit_stop(rctx
, query
);
1057 if (!(query
->flags
& R600_QUERY_HW_FLAG_NO_START
))
1058 LIST_DELINIT(&query
->list
);
1060 if (!query
->buffer
.buf
)
1066 static void r600_get_hw_query_params(struct r600_common_context
*rctx
,
1067 struct r600_query_hw
*rquery
, int index
,
1068 struct r600_hw_query_params
*params
)
1070 unsigned max_rbs
= rctx
->screen
->info
.num_render_backends
;
1072 params
->pair_stride
= 0;
1073 params
->pair_count
= 1;
1075 switch (rquery
->b
.type
) {
1076 case PIPE_QUERY_OCCLUSION_COUNTER
:
1077 case PIPE_QUERY_OCCLUSION_PREDICATE
:
1078 params
->start_offset
= 0;
1079 params
->end_offset
= 8;
1080 params
->fence_offset
= max_rbs
* 16;
1081 params
->pair_stride
= 16;
1082 params
->pair_count
= max_rbs
;
1084 case PIPE_QUERY_TIME_ELAPSED
:
1085 params
->start_offset
= 0;
1086 params
->end_offset
= 8;
1087 params
->fence_offset
= 16;
1089 case PIPE_QUERY_TIMESTAMP
:
1090 params
->start_offset
= 0;
1091 params
->end_offset
= 0;
1092 params
->fence_offset
= 8;
1094 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1095 params
->start_offset
= 8;
1096 params
->end_offset
= 24;
1097 params
->fence_offset
= params
->end_offset
+ 4;
1099 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1100 params
->start_offset
= 0;
1101 params
->end_offset
= 16;
1102 params
->fence_offset
= params
->end_offset
+ 4;
1104 case PIPE_QUERY_SO_STATISTICS
:
1105 params
->start_offset
= 8 - index
* 8;
1106 params
->end_offset
= 24 - index
* 8;
1107 params
->fence_offset
= params
->end_offset
+ 4;
1109 case PIPE_QUERY_PIPELINE_STATISTICS
:
1111 /* Offsets apply to EG+ */
1112 static const unsigned offsets
[] = {56, 48, 24, 32, 40, 16, 8, 0, 64, 72, 80};
1113 params
->start_offset
= offsets
[index
];
1114 params
->end_offset
= 88 + offsets
[index
];
1115 params
->fence_offset
= 2 * 88;
1119 unreachable("r600_get_hw_query_params unsupported");
1123 static unsigned r600_query_read_result(void *map
, unsigned start_index
, unsigned end_index
,
1124 bool test_status_bit
)
1126 uint32_t *current_result
= (uint32_t*)map
;
1127 uint64_t start
, end
;
1129 start
= (uint64_t)current_result
[start_index
] |
1130 (uint64_t)current_result
[start_index
+1] << 32;
1131 end
= (uint64_t)current_result
[end_index
] |
1132 (uint64_t)current_result
[end_index
+1] << 32;
1134 if (!test_status_bit
||
1135 ((start
& 0x8000000000000000UL
) && (end
& 0x8000000000000000UL
))) {
1141 static void r600_query_hw_add_result(struct r600_common_screen
*rscreen
,
1142 struct r600_query_hw
*query
,
1144 union pipe_query_result
*result
)
1146 unsigned max_rbs
= rscreen
->info
.num_render_backends
;
1148 switch (query
->b
.type
) {
1149 case PIPE_QUERY_OCCLUSION_COUNTER
: {
1150 for (unsigned i
= 0; i
< max_rbs
; ++i
) {
1151 unsigned results_base
= i
* 16;
1153 r600_query_read_result(buffer
+ results_base
, 0, 2, true);
1157 case PIPE_QUERY_OCCLUSION_PREDICATE
: {
1158 for (unsigned i
= 0; i
< max_rbs
; ++i
) {
1159 unsigned results_base
= i
* 16;
1160 result
->b
= result
->b
||
1161 r600_query_read_result(buffer
+ results_base
, 0, 2, true) != 0;
1165 case PIPE_QUERY_TIME_ELAPSED
:
1166 result
->u64
+= r600_query_read_result(buffer
, 0, 2, false);
1168 case PIPE_QUERY_TIMESTAMP
:
1169 result
->u64
= *(uint64_t*)buffer
;
1171 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1172 /* SAMPLE_STREAMOUTSTATS stores this structure:
1174 * u64 NumPrimitivesWritten;
1175 * u64 PrimitiveStorageNeeded;
1177 * We only need NumPrimitivesWritten here. */
1178 result
->u64
+= r600_query_read_result(buffer
, 2, 6, true);
1180 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1181 /* Here we read PrimitiveStorageNeeded. */
1182 result
->u64
+= r600_query_read_result(buffer
, 0, 4, true);
1184 case PIPE_QUERY_SO_STATISTICS
:
1185 result
->so_statistics
.num_primitives_written
+=
1186 r600_query_read_result(buffer
, 2, 6, true);
1187 result
->so_statistics
.primitives_storage_needed
+=
1188 r600_query_read_result(buffer
, 0, 4, true);
1190 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
1191 result
->b
= result
->b
||
1192 r600_query_read_result(buffer
, 2, 6, true) !=
1193 r600_query_read_result(buffer
, 0, 4, true);
1195 case PIPE_QUERY_PIPELINE_STATISTICS
:
1196 if (rscreen
->chip_class
>= EVERGREEN
) {
1197 result
->pipeline_statistics
.ps_invocations
+=
1198 r600_query_read_result(buffer
, 0, 22, false);
1199 result
->pipeline_statistics
.c_primitives
+=
1200 r600_query_read_result(buffer
, 2, 24, false);
1201 result
->pipeline_statistics
.c_invocations
+=
1202 r600_query_read_result(buffer
, 4, 26, false);
1203 result
->pipeline_statistics
.vs_invocations
+=
1204 r600_query_read_result(buffer
, 6, 28, false);
1205 result
->pipeline_statistics
.gs_invocations
+=
1206 r600_query_read_result(buffer
, 8, 30, false);
1207 result
->pipeline_statistics
.gs_primitives
+=
1208 r600_query_read_result(buffer
, 10, 32, false);
1209 result
->pipeline_statistics
.ia_primitives
+=
1210 r600_query_read_result(buffer
, 12, 34, false);
1211 result
->pipeline_statistics
.ia_vertices
+=
1212 r600_query_read_result(buffer
, 14, 36, false);
1213 result
->pipeline_statistics
.hs_invocations
+=
1214 r600_query_read_result(buffer
, 16, 38, false);
1215 result
->pipeline_statistics
.ds_invocations
+=
1216 r600_query_read_result(buffer
, 18, 40, false);
1217 result
->pipeline_statistics
.cs_invocations
+=
1218 r600_query_read_result(buffer
, 20, 42, false);
1220 result
->pipeline_statistics
.ps_invocations
+=
1221 r600_query_read_result(buffer
, 0, 16, false);
1222 result
->pipeline_statistics
.c_primitives
+=
1223 r600_query_read_result(buffer
, 2, 18, false);
1224 result
->pipeline_statistics
.c_invocations
+=
1225 r600_query_read_result(buffer
, 4, 20, false);
1226 result
->pipeline_statistics
.vs_invocations
+=
1227 r600_query_read_result(buffer
, 6, 22, false);
1228 result
->pipeline_statistics
.gs_invocations
+=
1229 r600_query_read_result(buffer
, 8, 24, false);
1230 result
->pipeline_statistics
.gs_primitives
+=
1231 r600_query_read_result(buffer
, 10, 26, false);
1232 result
->pipeline_statistics
.ia_primitives
+=
1233 r600_query_read_result(buffer
, 12, 28, false);
1234 result
->pipeline_statistics
.ia_vertices
+=
1235 r600_query_read_result(buffer
, 14, 30, false);
1237 #if 0 /* for testing */
1238 printf("Pipeline stats: IA verts=%llu, IA prims=%llu, VS=%llu, HS=%llu, "
1239 "DS=%llu, GS=%llu, GS prims=%llu, Clipper=%llu, "
1240 "Clipper prims=%llu, PS=%llu, CS=%llu\n",
1241 result
->pipeline_statistics
.ia_vertices
,
1242 result
->pipeline_statistics
.ia_primitives
,
1243 result
->pipeline_statistics
.vs_invocations
,
1244 result
->pipeline_statistics
.hs_invocations
,
1245 result
->pipeline_statistics
.ds_invocations
,
1246 result
->pipeline_statistics
.gs_invocations
,
1247 result
->pipeline_statistics
.gs_primitives
,
1248 result
->pipeline_statistics
.c_invocations
,
1249 result
->pipeline_statistics
.c_primitives
,
1250 result
->pipeline_statistics
.ps_invocations
,
1251 result
->pipeline_statistics
.cs_invocations
);
1259 static boolean
r600_get_query_result(struct pipe_context
*ctx
,
1260 struct pipe_query
*query
, boolean wait
,
1261 union pipe_query_result
*result
)
1263 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1264 struct r600_query
*rquery
= (struct r600_query
*)query
;
1266 return rquery
->ops
->get_result(rctx
, rquery
, wait
, result
);
1269 static void r600_get_query_result_resource(struct pipe_context
*ctx
,
1270 struct pipe_query
*query
,
1272 enum pipe_query_value_type result_type
,
1274 struct pipe_resource
*resource
,
1277 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1278 struct r600_query
*rquery
= (struct r600_query
*)query
;
1280 rquery
->ops
->get_result_resource(rctx
, rquery
, wait
, result_type
, index
,
1284 static void r600_query_hw_clear_result(struct r600_query_hw
*query
,
1285 union pipe_query_result
*result
)
1287 util_query_clear_result(result
, query
->b
.type
);
1290 bool r600_query_hw_get_result(struct r600_common_context
*rctx
,
1291 struct r600_query
*rquery
,
1292 bool wait
, union pipe_query_result
*result
)
1294 struct r600_common_screen
*rscreen
= rctx
->screen
;
1295 struct r600_query_hw
*query
= (struct r600_query_hw
*)rquery
;
1296 struct r600_query_buffer
*qbuf
;
1298 query
->ops
->clear_result(query
, result
);
1300 for (qbuf
= &query
->buffer
; qbuf
; qbuf
= qbuf
->previous
) {
1301 unsigned usage
= PIPE_TRANSFER_READ
|
1302 (wait
? 0 : PIPE_TRANSFER_DONTBLOCK
);
1303 unsigned results_base
= 0;
1306 if (rquery
->b
.flushed
)
1307 map
= rctx
->ws
->buffer_map(qbuf
->buf
->buf
, NULL
, usage
);
1309 map
= r600_buffer_map_sync_with_rings(rctx
, qbuf
->buf
, usage
);
1314 while (results_base
!= qbuf
->results_end
) {
1315 query
->ops
->add_result(rscreen
, query
, map
+ results_base
,
1317 results_base
+= query
->result_size
;
1321 /* Convert the time to expected units. */
1322 if (rquery
->type
== PIPE_QUERY_TIME_ELAPSED
||
1323 rquery
->type
== PIPE_QUERY_TIMESTAMP
) {
1324 result
->u64
= (1000000 * result
->u64
) / rscreen
->info
.clock_crystal_freq
;
1329 /* Create the compute shader that is used to collect the results.
1331 * One compute grid with a single thread is launched for every query result
1332 * buffer. The thread (optionally) reads a previous summary buffer, then
1333 * accumulates data from the query result buffer, and writes the result either
1334 * to a summary buffer to be consumed by the next grid invocation or to the
1335 * user-supplied buffer.
1341 * 0.y = result_stride
1342 * 0.z = result_count
1344 * 1: read previously accumulated values
1345 * 2: write accumulated values for chaining
1346 * 4: write result available
1347 * 8: convert result to boolean (0/1)
1348 * 16: only read one dword and use that as result
1349 * 32: apply timestamp conversion
1350 * 64: store full 64 bits result
1351 * 128: store signed 32 bits result
1352 * 1.x = fence_offset
1356 * BUFFER[0] = query result buffer
1357 * BUFFER[1] = previous summary buffer
1358 * BUFFER[2] = next summary buffer or user-supplied buffer
1360 static void r600_create_query_result_shader(struct r600_common_context
*rctx
)
1362 /* TEMP[0].xy = accumulated result so far
1363 * TEMP[0].z = result not available
1365 * TEMP[1].x = current result index
1366 * TEMP[1].y = current pair index
1368 static const char text_tmpl
[] =
1370 "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
1371 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
1372 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
1378 "IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n"
1379 "IMM[1] UINT32 {1, 2, 4, 8}\n"
1380 "IMM[2] UINT32 {16, 32, 64, 128}\n"
1381 "IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */
1383 "AND TEMP[5], CONST[0].wwww, IMM[2].xxxx\n"
1385 /* Check result availability. */
1386 "LOAD TEMP[1].x, BUFFER[0], CONST[1].xxxx\n"
1387 "ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n"
1388 "MOV TEMP[1], TEMP[0].zzzz\n"
1389 "NOT TEMP[0].z, TEMP[0].zzzz\n"
1391 /* Load result if available. */
1393 "LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n"
1396 /* Load previously accumulated result if requested. */
1397 "MOV TEMP[0], IMM[0].xxxx\n"
1398 "AND TEMP[4], CONST[0].wwww, IMM[1].xxxx\n"
1400 "LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n"
1403 "MOV TEMP[1].x, IMM[0].xxxx\n"
1405 /* Break if accumulated result so far is not available. */
1406 "UIF TEMP[0].zzzz\n"
1410 /* Break if result_index >= result_count. */
1411 "USGE TEMP[5], TEMP[1].xxxx, CONST[0].zzzz\n"
1416 /* Load fence and check result availability */
1417 "UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0].yyyy, CONST[1].xxxx\n"
1418 "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
1419 "ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n"
1420 "NOT TEMP[0].z, TEMP[0].zzzz\n"
1421 "UIF TEMP[0].zzzz\n"
1425 "MOV TEMP[1].y, IMM[0].xxxx\n"
1427 /* Load start and end. */
1428 "UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0].yyyy\n"
1429 "UMAD TEMP[5].x, TEMP[1].yyyy, CONST[1].yyyy, TEMP[5].xxxx\n"
1430 "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
1432 "UADD TEMP[5].x, TEMP[5].xxxx, CONST[0].xxxx\n"
1433 "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].xxxx\n"
1435 "U64ADD TEMP[3].xy, TEMP[3], -TEMP[2]\n"
1436 "U64ADD TEMP[0].xy, TEMP[0], TEMP[3]\n"
1438 /* Increment pair index */
1439 "UADD TEMP[1].y, TEMP[1].yyyy, IMM[1].xxxx\n"
1440 "USGE TEMP[5], TEMP[1].yyyy, CONST[1].zzzz\n"
1446 /* Increment result index */
1447 "UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n"
1451 "AND TEMP[4], CONST[0].wwww, IMM[1].yyyy\n"
1453 /* Store accumulated data for chaining. */
1454 "STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n"
1456 "AND TEMP[4], CONST[0].wwww, IMM[1].zzzz\n"
1458 /* Store result availability. */
1459 "NOT TEMP[0].z, TEMP[0]\n"
1460 "AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n"
1461 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n"
1463 "AND TEMP[4], CONST[0].wwww, IMM[2].zzzz\n"
1465 "STORE BUFFER[2].y, IMM[0].xxxx, IMM[0].xxxx\n"
1468 /* Store result if it is available. */
1469 "NOT TEMP[4], TEMP[0].zzzz\n"
1471 /* Apply timestamp conversion */
1472 "AND TEMP[4], CONST[0].wwww, IMM[2].yyyy\n"
1474 "U64MUL TEMP[0].xy, TEMP[0], IMM[3].xyxy\n"
1475 "U64DIV TEMP[0].xy, TEMP[0], IMM[3].zwzw\n"
1478 /* Convert to boolean */
1479 "AND TEMP[4], CONST[0].wwww, IMM[1].wwww\n"
1481 "U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[0].xxxx\n"
1482 "AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n"
1483 "MOV TEMP[0].y, IMM[0].xxxx\n"
1486 "AND TEMP[4], CONST[0].wwww, IMM[2].zzzz\n"
1488 "STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0].xyxy\n"
1491 "UIF TEMP[0].yyyy\n"
1492 "MOV TEMP[0].x, IMM[0].wwww\n"
1495 "AND TEMP[4], CONST[0].wwww, IMM[2].wwww\n"
1497 "UMIN TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz\n"
1500 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n"
1508 char text
[sizeof(text_tmpl
) + 32];
1509 struct tgsi_token tokens
[1024];
1510 struct pipe_compute_state state
= {};
1512 /* Hard code the frequency into the shader so that the backend can
1513 * use the full range of optimizations for divide-by-constant.
1515 snprintf(text
, sizeof(text
), text_tmpl
,
1516 rctx
->screen
->info
.clock_crystal_freq
);
1518 if (!tgsi_text_translate(text
, tokens
, ARRAY_SIZE(tokens
))) {
1523 state
.ir_type
= PIPE_SHADER_IR_TGSI
;
1524 state
.prog
= tokens
;
1526 rctx
->query_result_shader
= rctx
->b
.create_compute_state(&rctx
->b
, &state
);
1529 static void r600_restore_qbo_state(struct r600_common_context
*rctx
,
1530 struct r600_qbo_state
*st
)
1532 rctx
->b
.bind_compute_state(&rctx
->b
, st
->saved_compute
);
1534 rctx
->b
.set_constant_buffer(&rctx
->b
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1535 pipe_resource_reference(&st
->saved_const0
.buffer
, NULL
);
1537 rctx
->b
.set_shader_buffers(&rctx
->b
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1538 for (unsigned i
= 0; i
< 3; ++i
)
1539 pipe_resource_reference(&st
->saved_ssbo
[i
].buffer
, NULL
);
1542 static void r600_query_hw_get_result_resource(struct r600_common_context
*rctx
,
1543 struct r600_query
*rquery
,
1545 enum pipe_query_value_type result_type
,
1547 struct pipe_resource
*resource
,
1550 struct r600_query_hw
*query
= (struct r600_query_hw
*)rquery
;
1551 struct r600_query_buffer
*qbuf
;
1552 struct r600_query_buffer
*qbuf_prev
;
1553 struct pipe_resource
*tmp_buffer
= NULL
;
1554 unsigned tmp_buffer_offset
= 0;
1555 struct r600_qbo_state saved_state
= {};
1556 struct pipe_grid_info grid
= {};
1557 struct pipe_constant_buffer constant_buffer
= {};
1558 struct pipe_shader_buffer ssbo
[3];
1559 struct r600_hw_query_params params
;
1561 uint32_t end_offset
;
1562 uint32_t result_stride
;
1563 uint32_t result_count
;
1565 uint32_t fence_offset
;
1566 uint32_t pair_stride
;
1567 uint32_t pair_count
;
1570 if (!rctx
->query_result_shader
) {
1571 r600_create_query_result_shader(rctx
);
1572 if (!rctx
->query_result_shader
)
1576 if (query
->buffer
.previous
) {
1577 u_suballocator_alloc(rctx
->allocator_zeroed_memory
, 16, 16,
1578 &tmp_buffer_offset
, &tmp_buffer
);
1583 rctx
->save_qbo_state(&rctx
->b
, &saved_state
);
1585 r600_get_hw_query_params(rctx
, query
, index
>= 0 ? index
: 0, ¶ms
);
1586 consts
.end_offset
= params
.end_offset
- params
.start_offset
;
1587 consts
.fence_offset
= params
.fence_offset
- params
.start_offset
;
1588 consts
.result_stride
= query
->result_size
;
1589 consts
.pair_stride
= params
.pair_stride
;
1590 consts
.pair_count
= params
.pair_count
;
1592 constant_buffer
.buffer_size
= sizeof(consts
);
1593 constant_buffer
.user_buffer
= &consts
;
1595 ssbo
[1].buffer
= tmp_buffer
;
1596 ssbo
[1].buffer_offset
= tmp_buffer_offset
;
1597 ssbo
[1].buffer_size
= 16;
1601 rctx
->b
.bind_compute_state(&rctx
->b
, rctx
->query_result_shader
);
1613 if (query
->b
.type
== PIPE_QUERY_OCCLUSION_PREDICATE
||
1614 query
->b
.type
== PIPE_QUERY_SO_OVERFLOW_PREDICATE
)
1616 else if (query
->b
.type
== PIPE_QUERY_TIMESTAMP
||
1617 query
->b
.type
== PIPE_QUERY_TIME_ELAPSED
)
1618 consts
.config
|= 32;
1620 switch (result_type
) {
1621 case PIPE_QUERY_TYPE_U64
:
1622 case PIPE_QUERY_TYPE_I64
:
1623 consts
.config
|= 64;
1625 case PIPE_QUERY_TYPE_I32
:
1626 consts
.config
|= 128;
1628 case PIPE_QUERY_TYPE_U32
:
1632 rctx
->flags
|= rctx
->screen
->barrier_flags
.cp_to_L2
;
1634 for (qbuf
= &query
->buffer
; qbuf
; qbuf
= qbuf_prev
) {
1635 if (query
->b
.type
!= PIPE_QUERY_TIMESTAMP
) {
1636 qbuf_prev
= qbuf
->previous
;
1637 consts
.result_count
= qbuf
->results_end
/ query
->result_size
;
1638 consts
.config
&= ~3;
1639 if (qbuf
!= &query
->buffer
)
1644 /* Only read the last timestamp. */
1646 consts
.result_count
= 0;
1647 consts
.config
|= 16;
1648 params
.start_offset
+= qbuf
->results_end
- query
->result_size
;
1651 rctx
->b
.set_constant_buffer(&rctx
->b
, PIPE_SHADER_COMPUTE
, 0, &constant_buffer
);
1653 ssbo
[0].buffer
= &qbuf
->buf
->b
.b
;
1654 ssbo
[0].buffer_offset
= params
.start_offset
;
1655 ssbo
[0].buffer_size
= qbuf
->results_end
- params
.start_offset
;
1657 if (!qbuf
->previous
) {
1658 ssbo
[2].buffer
= resource
;
1659 ssbo
[2].buffer_offset
= offset
;
1660 ssbo
[2].buffer_size
= 8;
1662 ((struct r600_resource
*)resource
)->TC_L2_dirty
= true;
1665 rctx
->b
.set_shader_buffers(&rctx
->b
, PIPE_SHADER_COMPUTE
, 0, 3, ssbo
);
1667 if (wait
&& qbuf
== &query
->buffer
) {
1670 /* Wait for result availability. Wait only for readiness
1671 * of the last entry, since the fence writes should be
1672 * serialized in the CP.
1674 va
= qbuf
->buf
->gpu_address
+ qbuf
->results_end
- query
->result_size
;
1675 va
+= params
.fence_offset
;
1677 r600_gfx_wait_fence(rctx
, va
, 0x80000000, 0x80000000);
1680 rctx
->b
.launch_grid(&rctx
->b
, &grid
);
1681 rctx
->flags
|= rctx
->screen
->barrier_flags
.compute_to_L2
;
1684 r600_restore_qbo_state(rctx
, &saved_state
);
1685 pipe_resource_reference(&tmp_buffer
, NULL
);
1688 static void r600_render_condition(struct pipe_context
*ctx
,
1689 struct pipe_query
*query
,
1691 enum pipe_render_cond_flag mode
)
1693 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1694 struct r600_query_hw
*rquery
= (struct r600_query_hw
*)query
;
1695 struct r600_query_buffer
*qbuf
;
1696 struct r600_atom
*atom
= &rctx
->render_cond_atom
;
1698 rctx
->render_cond
= query
;
1699 rctx
->render_cond_invert
= condition
;
1700 rctx
->render_cond_mode
= mode
;
1702 /* Compute the size of SET_PREDICATION packets. */
1705 for (qbuf
= &rquery
->buffer
; qbuf
; qbuf
= qbuf
->previous
)
1706 atom
->num_dw
+= (qbuf
->results_end
/ rquery
->result_size
) * 5;
1709 rctx
->set_atom_dirty(rctx
, atom
, query
!= NULL
);
1712 void r600_suspend_queries(struct r600_common_context
*ctx
)
1714 struct r600_query_hw
*query
;
1716 LIST_FOR_EACH_ENTRY(query
, &ctx
->active_queries
, list
) {
1717 r600_query_hw_emit_stop(ctx
, query
);
1719 assert(ctx
->num_cs_dw_queries_suspend
== 0);
1722 static unsigned r600_queries_num_cs_dw_for_resuming(struct r600_common_context
*ctx
,
1723 struct list_head
*query_list
)
1725 struct r600_query_hw
*query
;
1726 unsigned num_dw
= 0;
1728 LIST_FOR_EACH_ENTRY(query
, query_list
, list
) {
1730 num_dw
+= query
->num_cs_dw_begin
+ query
->num_cs_dw_end
;
1732 /* Workaround for the fact that
1733 * num_cs_dw_nontimer_queries_suspend is incremented for every
1734 * resumed query, which raises the bar in need_cs_space for
1735 * queries about to be resumed.
1737 num_dw
+= query
->num_cs_dw_end
;
1739 /* primitives generated query */
1740 num_dw
+= ctx
->streamout
.enable_atom
.num_dw
;
1741 /* guess for ZPASS enable or PERFECT_ZPASS_COUNT enable updates */
1747 void r600_resume_queries(struct r600_common_context
*ctx
)
1749 struct r600_query_hw
*query
;
1750 unsigned num_cs_dw
= r600_queries_num_cs_dw_for_resuming(ctx
, &ctx
->active_queries
);
1752 assert(ctx
->num_cs_dw_queries_suspend
== 0);
1754 /* Check CS space here. Resuming must not be interrupted by flushes. */
1755 ctx
->need_gfx_cs_space(&ctx
->b
, num_cs_dw
, true);
1757 LIST_FOR_EACH_ENTRY(query
, &ctx
->active_queries
, list
) {
1758 r600_query_hw_emit_start(ctx
, query
);
1762 /* Fix radeon_info::enabled_rb_mask for R600, R700, EVERGREEN, NI. */
1763 void r600_query_fix_enabled_rb_mask(struct r600_common_screen
*rscreen
)
1765 struct r600_common_context
*ctx
=
1766 (struct r600_common_context
*)rscreen
->aux_context
;
1767 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
1768 struct r600_resource
*buffer
;
1770 unsigned i
, mask
= 0;
1771 unsigned max_rbs
= ctx
->screen
->info
.num_render_backends
;
1773 assert(rscreen
->chip_class
<= CAYMAN
);
1775 /* if backend_map query is supported by the kernel */
1776 if (rscreen
->info
.r600_gb_backend_map_valid
) {
1777 unsigned num_tile_pipes
= rscreen
->info
.num_tile_pipes
;
1778 unsigned backend_map
= rscreen
->info
.r600_gb_backend_map
;
1779 unsigned item_width
, item_mask
;
1781 if (ctx
->chip_class
>= EVERGREEN
) {
1789 while (num_tile_pipes
--) {
1790 i
= backend_map
& item_mask
;
1792 backend_map
>>= item_width
;
1795 rscreen
->info
.enabled_rb_mask
= mask
;
1800 /* otherwise backup path for older kernels */
1802 /* create buffer for event data */
1803 buffer
= (struct r600_resource
*)
1804 pipe_buffer_create(ctx
->b
.screen
, 0,
1805 PIPE_USAGE_STAGING
, max_rbs
* 16);
1809 /* initialize buffer with zeroes */
1810 results
= r600_buffer_map_sync_with_rings(ctx
, buffer
, PIPE_TRANSFER_WRITE
);
1812 memset(results
, 0, max_rbs
* 4 * 4);
1814 /* emit EVENT_WRITE for ZPASS_DONE */
1815 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
1816 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE
) | EVENT_INDEX(1));
1817 radeon_emit(cs
, buffer
->gpu_address
);
1818 radeon_emit(cs
, buffer
->gpu_address
>> 32);
1820 r600_emit_reloc(ctx
, &ctx
->gfx
, buffer
,
1821 RADEON_USAGE_WRITE
, RADEON_PRIO_QUERY
);
1823 /* analyze results */
1824 results
= r600_buffer_map_sync_with_rings(ctx
, buffer
, PIPE_TRANSFER_READ
);
1826 for(i
= 0; i
< max_rbs
; i
++) {
1827 /* at least highest bit will be set if backend is used */
1828 if (results
[i
*4 + 1])
1834 r600_resource_reference(&buffer
, NULL
);
1837 rscreen
->info
.enabled_rb_mask
= mask
;
1840 #define XFULL(name_, query_type_, type_, result_type_, group_id_) \
1843 .query_type = R600_QUERY_##query_type_, \
1844 .type = PIPE_DRIVER_QUERY_TYPE_##type_, \
1845 .result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_##result_type_, \
1846 .group_id = group_id_ \
1849 #define X(name_, query_type_, type_, result_type_) \
1850 XFULL(name_, query_type_, type_, result_type_, ~(unsigned)0)
1852 #define XG(group_, name_, query_type_, type_, result_type_) \
1853 XFULL(name_, query_type_, type_, result_type_, R600_QUERY_GROUP_##group_)
1855 static struct pipe_driver_query_info r600_driver_query_list
[] = {
1856 X("num-compilations", NUM_COMPILATIONS
, UINT64
, CUMULATIVE
),
1857 X("num-shaders-created", NUM_SHADERS_CREATED
, UINT64
, CUMULATIVE
),
1858 X("num-shader-cache-hits", NUM_SHADER_CACHE_HITS
, UINT64
, CUMULATIVE
),
1859 X("draw-calls", DRAW_CALLS
, UINT64
, AVERAGE
),
1860 X("MRT-draw-calls", MRT_DRAW_CALLS
, UINT64
, AVERAGE
),
1861 X("prim-restart-calls", PRIM_RESTART_CALLS
, UINT64
, AVERAGE
),
1862 X("spill-draw-calls", SPILL_DRAW_CALLS
, UINT64
, AVERAGE
),
1863 X("compute-calls", COMPUTE_CALLS
, UINT64
, AVERAGE
),
1864 X("spill-compute-calls", SPILL_COMPUTE_CALLS
, UINT64
, AVERAGE
),
1865 X("dma-calls", DMA_CALLS
, UINT64
, AVERAGE
),
1866 X("cp-dma-calls", CP_DMA_CALLS
, UINT64
, AVERAGE
),
1867 X("num-vs-flushes", NUM_VS_FLUSHES
, UINT64
, AVERAGE
),
1868 X("num-ps-flushes", NUM_PS_FLUSHES
, UINT64
, AVERAGE
),
1869 X("num-cs-flushes", NUM_CS_FLUSHES
, UINT64
, AVERAGE
),
1870 X("num-CB-cache-flushes", NUM_CB_CACHE_FLUSHES
, UINT64
, AVERAGE
),
1871 X("num-DB-cache-flushes", NUM_DB_CACHE_FLUSHES
, UINT64
, AVERAGE
),
1872 X("num-L2-invalidates", NUM_L2_INVALIDATES
, UINT64
, AVERAGE
),
1873 X("num-L2-writebacks", NUM_L2_WRITEBACKS
, UINT64
, AVERAGE
),
1874 X("num-resident-handles", NUM_RESIDENT_HANDLES
, UINT64
, AVERAGE
),
1875 X("tc-offloaded-slots", TC_OFFLOADED_SLOTS
, UINT64
, AVERAGE
),
1876 X("tc-direct-slots", TC_DIRECT_SLOTS
, UINT64
, AVERAGE
),
1877 X("tc-num-syncs", TC_NUM_SYNCS
, UINT64
, AVERAGE
),
1878 X("CS-thread-busy", CS_THREAD_BUSY
, UINT64
, AVERAGE
),
1879 X("gallium-thread-busy", GALLIUM_THREAD_BUSY
, UINT64
, AVERAGE
),
1880 X("requested-VRAM", REQUESTED_VRAM
, BYTES
, AVERAGE
),
1881 X("requested-GTT", REQUESTED_GTT
, BYTES
, AVERAGE
),
1882 X("mapped-VRAM", MAPPED_VRAM
, BYTES
, AVERAGE
),
1883 X("mapped-GTT", MAPPED_GTT
, BYTES
, AVERAGE
),
1884 X("buffer-wait-time", BUFFER_WAIT_TIME
, MICROSECONDS
, CUMULATIVE
),
1885 X("num-mapped-buffers", NUM_MAPPED_BUFFERS
, UINT64
, AVERAGE
),
1886 X("num-GFX-IBs", NUM_GFX_IBS
, UINT64
, AVERAGE
),
1887 X("num-SDMA-IBs", NUM_SDMA_IBS
, UINT64
, AVERAGE
),
1888 X("GFX-BO-list-size", GFX_BO_LIST_SIZE
, UINT64
, AVERAGE
),
1889 X("num-bytes-moved", NUM_BYTES_MOVED
, BYTES
, CUMULATIVE
),
1890 X("num-evictions", NUM_EVICTIONS
, UINT64
, CUMULATIVE
),
1891 X("VRAM-CPU-page-faults", NUM_VRAM_CPU_PAGE_FAULTS
, UINT64
, CUMULATIVE
),
1892 X("VRAM-usage", VRAM_USAGE
, BYTES
, AVERAGE
),
1893 X("VRAM-vis-usage", VRAM_VIS_USAGE
, BYTES
, AVERAGE
),
1894 X("GTT-usage", GTT_USAGE
, BYTES
, AVERAGE
),
1895 X("back-buffer-ps-draw-ratio", BACK_BUFFER_PS_DRAW_RATIO
, UINT64
, AVERAGE
),
1897 /* GPIN queries are for the benefit of old versions of GPUPerfStudio,
1898 * which use it as a fallback path to detect the GPU type.
1900 * Note: The names of these queries are significant for GPUPerfStudio
1901 * (and possibly their order as well). */
1902 XG(GPIN
, "GPIN_000", GPIN_ASIC_ID
, UINT
, AVERAGE
),
1903 XG(GPIN
, "GPIN_001", GPIN_NUM_SIMD
, UINT
, AVERAGE
),
1904 XG(GPIN
, "GPIN_002", GPIN_NUM_RB
, UINT
, AVERAGE
),
1905 XG(GPIN
, "GPIN_003", GPIN_NUM_SPI
, UINT
, AVERAGE
),
1906 XG(GPIN
, "GPIN_004", GPIN_NUM_SE
, UINT
, AVERAGE
),
1908 X("temperature", GPU_TEMPERATURE
, UINT64
, AVERAGE
),
1909 X("shader-clock", CURRENT_GPU_SCLK
, HZ
, AVERAGE
),
1910 X("memory-clock", CURRENT_GPU_MCLK
, HZ
, AVERAGE
),
1912 /* The following queries must be at the end of the list because their
1913 * availability is adjusted dynamically based on the DRM version. */
1914 X("GPU-load", GPU_LOAD
, UINT64
, AVERAGE
),
1915 X("GPU-shaders-busy", GPU_SHADERS_BUSY
, UINT64
, AVERAGE
),
1916 X("GPU-ta-busy", GPU_TA_BUSY
, UINT64
, AVERAGE
),
1917 X("GPU-gds-busy", GPU_GDS_BUSY
, UINT64
, AVERAGE
),
1918 X("GPU-vgt-busy", GPU_VGT_BUSY
, UINT64
, AVERAGE
),
1919 X("GPU-ia-busy", GPU_IA_BUSY
, UINT64
, AVERAGE
),
1920 X("GPU-sx-busy", GPU_SX_BUSY
, UINT64
, AVERAGE
),
1921 X("GPU-wd-busy", GPU_WD_BUSY
, UINT64
, AVERAGE
),
1922 X("GPU-bci-busy", GPU_BCI_BUSY
, UINT64
, AVERAGE
),
1923 X("GPU-sc-busy", GPU_SC_BUSY
, UINT64
, AVERAGE
),
1924 X("GPU-pa-busy", GPU_PA_BUSY
, UINT64
, AVERAGE
),
1925 X("GPU-db-busy", GPU_DB_BUSY
, UINT64
, AVERAGE
),
1926 X("GPU-cp-busy", GPU_CP_BUSY
, UINT64
, AVERAGE
),
1927 X("GPU-cb-busy", GPU_CB_BUSY
, UINT64
, AVERAGE
),
1928 X("GPU-sdma-busy", GPU_SDMA_BUSY
, UINT64
, AVERAGE
),
1929 X("GPU-pfp-busy", GPU_PFP_BUSY
, UINT64
, AVERAGE
),
1930 X("GPU-meq-busy", GPU_MEQ_BUSY
, UINT64
, AVERAGE
),
1931 X("GPU-me-busy", GPU_ME_BUSY
, UINT64
, AVERAGE
),
1932 X("GPU-surf-sync-busy", GPU_SURF_SYNC_BUSY
, UINT64
, AVERAGE
),
1933 X("GPU-dma-busy", GPU_DMA_BUSY
, UINT64
, AVERAGE
),
1934 X("GPU-scratch-ram-busy", GPU_SCRATCH_RAM_BUSY
, UINT64
, AVERAGE
),
1935 X("GPU-ce-busy", GPU_CE_BUSY
, UINT64
, AVERAGE
),
1942 static unsigned r600_get_num_queries(struct r600_common_screen
*rscreen
)
1944 if (rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
>= 42)
1945 return ARRAY_SIZE(r600_driver_query_list
);
1946 else if (rscreen
->info
.drm_major
== 3) {
1947 if (rscreen
->chip_class
>= VI
)
1948 return ARRAY_SIZE(r600_driver_query_list
);
1950 return ARRAY_SIZE(r600_driver_query_list
) - 7;
1953 return ARRAY_SIZE(r600_driver_query_list
) - 25;
1956 static int r600_get_driver_query_info(struct pipe_screen
*screen
,
1958 struct pipe_driver_query_info
*info
)
1960 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1961 unsigned num_queries
= r600_get_num_queries(rscreen
);
1964 unsigned num_perfcounters
=
1965 r600_get_perfcounter_info(rscreen
, 0, NULL
);
1967 return num_queries
+ num_perfcounters
;
1970 if (index
>= num_queries
)
1971 return r600_get_perfcounter_info(rscreen
, index
- num_queries
, info
);
1973 *info
= r600_driver_query_list
[index
];
1975 switch (info
->query_type
) {
1976 case R600_QUERY_REQUESTED_VRAM
:
1977 case R600_QUERY_VRAM_USAGE
:
1978 case R600_QUERY_MAPPED_VRAM
:
1979 info
->max_value
.u64
= rscreen
->info
.vram_size
;
1981 case R600_QUERY_REQUESTED_GTT
:
1982 case R600_QUERY_GTT_USAGE
:
1983 case R600_QUERY_MAPPED_GTT
:
1984 info
->max_value
.u64
= rscreen
->info
.gart_size
;
1986 case R600_QUERY_GPU_TEMPERATURE
:
1987 info
->max_value
.u64
= 125;
1989 case R600_QUERY_VRAM_VIS_USAGE
:
1990 info
->max_value
.u64
= rscreen
->info
.vram_vis_size
;
1994 if (info
->group_id
!= ~(unsigned)0 && rscreen
->perfcounters
)
1995 info
->group_id
+= rscreen
->perfcounters
->num_groups
;
2000 /* Note: Unfortunately, GPUPerfStudio hardcodes the order of hardware
2001 * performance counter groups, so be careful when changing this and related
2004 static int r600_get_driver_query_group_info(struct pipe_screen
*screen
,
2006 struct pipe_driver_query_group_info
*info
)
2008 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
2009 unsigned num_pc_groups
= 0;
2011 if (rscreen
->perfcounters
)
2012 num_pc_groups
= rscreen
->perfcounters
->num_groups
;
2015 return num_pc_groups
+ R600_NUM_SW_QUERY_GROUPS
;
2017 if (index
< num_pc_groups
)
2018 return r600_get_perfcounter_group_info(rscreen
, index
, info
);
2020 index
-= num_pc_groups
;
2021 if (index
>= R600_NUM_SW_QUERY_GROUPS
)
2024 info
->name
= "GPIN";
2025 info
->max_active_queries
= 5;
2026 info
->num_queries
= 5;
2030 void r600_query_init(struct r600_common_context
*rctx
)
2032 rctx
->b
.create_query
= r600_create_query
;
2033 rctx
->b
.create_batch_query
= r600_create_batch_query
;
2034 rctx
->b
.destroy_query
= r600_destroy_query
;
2035 rctx
->b
.begin_query
= r600_begin_query
;
2036 rctx
->b
.end_query
= r600_end_query
;
2037 rctx
->b
.get_query_result
= r600_get_query_result
;
2038 rctx
->b
.get_query_result_resource
= r600_get_query_result_resource
;
2039 rctx
->render_cond_atom
.emit
= r600_emit_query_predication
;
2041 if (((struct r600_common_screen
*)rctx
->b
.screen
)->info
.num_render_backends
> 0)
2042 rctx
->b
.render_condition
= r600_render_condition
;
2044 LIST_INITHEAD(&rctx
->active_queries
);
2047 void r600_init_screen_query_functions(struct r600_common_screen
*rscreen
)
2049 rscreen
->b
.get_driver_query_info
= r600_get_driver_query_info
;
2050 rscreen
->b
.get_driver_query_group_info
= r600_get_driver_query_group_info
;