projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
gallium/radeon: add GPIN driver query group
[mesa.git] / src / gallium / drivers / radeon / r600_query.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014 Marek Olšák <marek.olsak@amd.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "r600_query.h"
26 #include "r600_cs.h"
27 #include "util/u_memory.h"
28
29 /* Queries without buffer handling or suspend/resume. */
30 struct r600_query_sw {
31 struct r600_query b;
32
33 uint64_t begin_result;
34 uint64_t end_result;
35 /* Fence for GPU_FINISHED. */
36 struct pipe_fence_handle *fence;
37 };
38
39 static void r600_query_sw_destroy(struct r600_common_context *rctx,
40 struct r600_query *rquery)
41 {
42 struct pipe_screen *screen = rctx->b.screen;
43 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
44
45 screen->fence_reference(screen, &query->fence, NULL);
46 FREE(query);
47 }
48
49 static enum radeon_value_id winsys_id_from_type(unsigned type)
50 {
51 switch (type) {
52 case R600_QUERY_REQUESTED_VRAM: return RADEON_REQUESTED_VRAM_MEMORY;
53 case R600_QUERY_REQUESTED_GTT: return RADEON_REQUESTED_GTT_MEMORY;
54 case R600_QUERY_BUFFER_WAIT_TIME: return RADEON_BUFFER_WAIT_TIME_NS;
55 case R600_QUERY_NUM_CS_FLUSHES: return RADEON_NUM_CS_FLUSHES;
56 case R600_QUERY_NUM_BYTES_MOVED: return RADEON_NUM_BYTES_MOVED;
57 case R600_QUERY_VRAM_USAGE: return RADEON_VRAM_USAGE;
58 case R600_QUERY_GTT_USAGE: return RADEON_GTT_USAGE;
59 case R600_QUERY_GPU_TEMPERATURE: return RADEON_GPU_TEMPERATURE;
60 case R600_QUERY_CURRENT_GPU_SCLK: return RADEON_CURRENT_SCLK;
61 case R600_QUERY_CURRENT_GPU_MCLK: return RADEON_CURRENT_MCLK;
62 default: unreachable("query type does not correspond to winsys id");
63 }
64 }
65
66 static boolean r600_query_sw_begin(struct r600_common_context *rctx,
67 struct r600_query *rquery)
68 {
69 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
70
71 switch(query->b.type) {
72 case PIPE_QUERY_TIMESTAMP_DISJOINT:
73 case PIPE_QUERY_GPU_FINISHED:
74 break;
75 case R600_QUERY_DRAW_CALLS:
76 query->begin_result = rctx->num_draw_calls;
77 break;
78 case R600_QUERY_REQUESTED_VRAM:
79 case R600_QUERY_REQUESTED_GTT:
80 case R600_QUERY_VRAM_USAGE:
81 case R600_QUERY_GTT_USAGE:
82 case R600_QUERY_GPU_TEMPERATURE:
83 case R600_QUERY_CURRENT_GPU_SCLK:
84 case R600_QUERY_CURRENT_GPU_MCLK:
85 query->begin_result = 0;
86 break;
87 case R600_QUERY_BUFFER_WAIT_TIME:
88 case R600_QUERY_NUM_CS_FLUSHES:
89 case R600_QUERY_NUM_BYTES_MOVED: {
90 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
91 query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
92 break;
93 }
94 case R600_QUERY_GPU_LOAD:
95 query->begin_result = r600_gpu_load_begin(rctx->screen);
96 break;
97 case R600_QUERY_NUM_COMPILATIONS:
98 query->begin_result = p_atomic_read(&rctx->screen->num_compilations);
99 break;
100 case R600_QUERY_NUM_SHADERS_CREATED:
101 query->begin_result = p_atomic_read(&rctx->screen->num_shaders_created);
102 break;
103 case R600_QUERY_GPIN_ASIC_ID:
104 case R600_QUERY_GPIN_NUM_SIMD:
105 case R600_QUERY_GPIN_NUM_RB:
106 case R600_QUERY_GPIN_NUM_SPI:
107 case R600_QUERY_GPIN_NUM_SE:
108 break;
109 default:
110 unreachable("r600_query_sw_begin: bad query type");
111 }
112
113 return TRUE;
114 }
115
116 static void r600_query_sw_end(struct r600_common_context *rctx,
117 struct r600_query *rquery)
118 {
119 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
120
121 switch(query->b.type) {
122 case PIPE_QUERY_TIMESTAMP_DISJOINT:
123 break;
124 case PIPE_QUERY_GPU_FINISHED:
125 rctx->b.flush(&rctx->b, &query->fence, 0);
126 break;
127 case R600_QUERY_DRAW_CALLS:
128 query->end_result = rctx->num_draw_calls;
129 break;
130 case R600_QUERY_REQUESTED_VRAM:
131 case R600_QUERY_REQUESTED_GTT:
132 case R600_QUERY_VRAM_USAGE:
133 case R600_QUERY_GTT_USAGE:
134 case R600_QUERY_GPU_TEMPERATURE:
135 case R600_QUERY_CURRENT_GPU_SCLK:
136 case R600_QUERY_CURRENT_GPU_MCLK:
137 case R600_QUERY_BUFFER_WAIT_TIME:
138 case R600_QUERY_NUM_CS_FLUSHES:
139 case R600_QUERY_NUM_BYTES_MOVED: {
140 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
141 query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
142 break;
143 }
144 case R600_QUERY_GPU_LOAD:
145 query->end_result = r600_gpu_load_end(rctx->screen,
146 query->begin_result);
147 query->begin_result = 0;
148 break;
149 case R600_QUERY_NUM_COMPILATIONS:
150 query->end_result = p_atomic_read(&rctx->screen->num_compilations);
151 break;
152 case R600_QUERY_NUM_SHADERS_CREATED:
153 query->end_result = p_atomic_read(&rctx->screen->num_shaders_created);
154 break;
155 case R600_QUERY_GPIN_ASIC_ID:
156 case R600_QUERY_GPIN_NUM_SIMD:
157 case R600_QUERY_GPIN_NUM_RB:
158 case R600_QUERY_GPIN_NUM_SPI:
159 case R600_QUERY_GPIN_NUM_SE:
160 break;
161 default:
162 unreachable("r600_query_sw_end: bad query type");
163 }
164 }
165
166 static boolean r600_query_sw_get_result(struct r600_common_context *rctx,
167 struct r600_query *rquery,
168 boolean wait,
169 union pipe_query_result *result)
170 {
171 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
172
173 switch (query->b.type) {
174 case PIPE_QUERY_TIMESTAMP_DISJOINT:
175 /* Convert from cycles per millisecond to cycles per second (Hz). */
176 result->timestamp_disjoint.frequency =
177 (uint64_t)rctx->screen->info.r600_clock_crystal_freq * 1000;
178 result->timestamp_disjoint.disjoint = FALSE;
179 return TRUE;
180 case PIPE_QUERY_GPU_FINISHED: {
181 struct pipe_screen *screen = rctx->b.screen;
182 result->b = screen->fence_finish(screen, query->fence,
183 wait ? PIPE_TIMEOUT_INFINITE : 0);
184 return result->b;
185 }
186
187 case R600_QUERY_GPIN_ASIC_ID:
188 result->u32 = 0;
189 return TRUE;
190 case R600_QUERY_GPIN_NUM_SIMD:
191 result->u32 = rctx->screen->info.num_good_compute_units;
192 return TRUE;
193 case R600_QUERY_GPIN_NUM_RB:
194 result->u32 = rctx->screen->info.r600_num_backends;
195 return TRUE;
196 case R600_QUERY_GPIN_NUM_SPI:
197 result->u32 = 1; /* all supported chips have one SPI per SE */
198 return TRUE;
199 case R600_QUERY_GPIN_NUM_SE:
200 result->u32 = rctx->screen->info.max_se;
201 return TRUE;
202 }
203
204 result->u64 = query->end_result - query->begin_result;
205
206 switch (query->b.type) {
207 case R600_QUERY_BUFFER_WAIT_TIME:
208 case R600_QUERY_GPU_TEMPERATURE:
209 result->u64 /= 1000;
210 break;
211 case R600_QUERY_CURRENT_GPU_SCLK:
212 case R600_QUERY_CURRENT_GPU_MCLK:
213 result->u64 *= 1000000;
214 break;
215 }
216
217 return TRUE;
218 }
219
220 static struct r600_query_ops sw_query_ops = {
221 .destroy = r600_query_sw_destroy,
222 .begin = r600_query_sw_begin,
223 .end = r600_query_sw_end,
224 .get_result = r600_query_sw_get_result
225 };
226
227 static struct pipe_query *r600_query_sw_create(struct pipe_context *ctx,
228 unsigned query_type)
229 {
230 struct r600_query_sw *query;
231
232 query = CALLOC_STRUCT(r600_query_sw);
233 if (!query)
234 return NULL;
235
236 query->b.type = query_type;
237 query->b.ops = &sw_query_ops;
238
239 return (struct pipe_query *)query;
240 }
241
242 void r600_query_hw_destroy(struct r600_common_context *rctx,
243 struct r600_query *rquery)
244 {
245 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
246 struct r600_query_buffer *prev = query->buffer.previous;
247
248 /* Release all query buffers. */
249 while (prev) {
250 struct r600_query_buffer *qbuf = prev;
251 prev = prev->previous;
252 pipe_resource_reference((struct pipe_resource**)&qbuf->buf, NULL);
253 FREE(qbuf);
254 }
255
256 pipe_resource_reference((struct pipe_resource**)&query->buffer.buf, NULL);
257 FREE(rquery);
258 }
259
260 static struct r600_resource *r600_new_query_buffer(struct r600_common_context *ctx,
261 struct r600_query_hw *query)
262 {
263 unsigned buf_size = MAX2(query->result_size, 4096);
264
265 /* Queries are normally read by the CPU after
266 * being written by the gpu, hence staging is probably a good
267 * usage pattern.
268 */
269 struct r600_resource *buf = (struct r600_resource*)
270 pipe_buffer_create(ctx->b.screen, PIPE_BIND_CUSTOM,
271 PIPE_USAGE_STAGING, buf_size);
272
273 if (query->flags & R600_QUERY_HW_FLAG_PREDICATE)
274 query->ops->prepare_buffer(ctx, query, buf);
275
276 return buf;
277 }
278
279 static void r600_query_hw_prepare_buffer(struct r600_common_context *ctx,
280 struct r600_query_hw *query,
281 struct r600_resource *buffer)
282 {
283 /* Callers ensure that the buffer is currently unused by the GPU. */
284 uint32_t *results = ctx->ws->buffer_map(buffer->buf, NULL,
285 PIPE_TRANSFER_WRITE |
286 PIPE_TRANSFER_UNSYNCHRONIZED);
287
288 memset(results, 0, buffer->b.b.width0);
289
290 if (query->b.type == PIPE_QUERY_OCCLUSION_COUNTER ||
291 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE) {
292 unsigned num_results;
293 unsigned i, j;
294
295 /* Set top bits for unused backends. */
296 num_results = buffer->b.b.width0 / (16 * ctx->max_db);
297 for (j = 0; j < num_results; j++) {
298 for (i = 0; i < ctx->max_db; i++) {
299 if (!(ctx->backend_mask & (1<<i))) {
300 results[(i * 4)+1] = 0x80000000;
301 results[(i * 4)+3] = 0x80000000;
302 }
303 }
304 results += 4 * ctx->max_db;
305 }
306 }
307 }
308
309 static struct r600_query_ops query_hw_ops = {
310 .destroy = r600_query_hw_destroy,
311 .begin = r600_query_hw_begin,
312 .end = r600_query_hw_end,
313 .get_result = r600_query_hw_get_result,
314 };
315
316 static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
317 struct r600_query_hw *query,
318 struct r600_resource *buffer,
319 uint64_t va);
320 static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
321 struct r600_query_hw *query,
322 struct r600_resource *buffer,
323 uint64_t va);
324 static void r600_query_hw_add_result(struct r600_common_context *ctx,
325 struct r600_query_hw *, void *buffer,
326 union pipe_query_result *result);
327 static void r600_query_hw_clear_result(struct r600_query_hw *,
328 union pipe_query_result *);
329
330 static struct r600_query_hw_ops query_hw_default_hw_ops = {
331 .prepare_buffer = r600_query_hw_prepare_buffer,
332 .emit_start = r600_query_hw_do_emit_start,
333 .emit_stop = r600_query_hw_do_emit_stop,
334 .clear_result = r600_query_hw_clear_result,
335 .add_result = r600_query_hw_add_result,
336 };
337
338 boolean r600_query_hw_init(struct r600_common_context *rctx,
339 struct r600_query_hw *query)
340 {
341 query->buffer.buf = r600_new_query_buffer(rctx, query);
342 if (!query->buffer.buf)
343 return FALSE;
344
345 return TRUE;
346 }
347
348 static struct pipe_query *r600_query_hw_create(struct r600_common_context *rctx,
349 unsigned query_type,
350 unsigned index)
351 {
352 struct r600_query_hw *query = CALLOC_STRUCT(r600_query_hw);
353 if (!query)
354 return NULL;
355
356 query->b.type = query_type;
357 query->b.ops = &query_hw_ops;
358 query->ops = &query_hw_default_hw_ops;
359
360 switch (query_type) {
361 case PIPE_QUERY_OCCLUSION_COUNTER:
362 case PIPE_QUERY_OCCLUSION_PREDICATE:
363 query->result_size = 16 * rctx->max_db;
364 query->num_cs_dw_begin = 6;
365 query->num_cs_dw_end = 6;
366 query->flags |= R600_QUERY_HW_FLAG_PREDICATE;
367 break;
368 case PIPE_QUERY_TIME_ELAPSED:
369 query->result_size = 16;
370 query->num_cs_dw_begin = 8;
371 query->num_cs_dw_end = 8;
372 query->flags = R600_QUERY_HW_FLAG_TIMER;
373 break;
374 case PIPE_QUERY_TIMESTAMP:
375 query->result_size = 8;
376 query->num_cs_dw_end = 8;
377 query->flags = R600_QUERY_HW_FLAG_TIMER |
378 R600_QUERY_HW_FLAG_NO_START;
379 break;
380 case PIPE_QUERY_PRIMITIVES_EMITTED:
381 case PIPE_QUERY_PRIMITIVES_GENERATED:
382 case PIPE_QUERY_SO_STATISTICS:
383 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
384 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
385 query->result_size = 32;
386 query->num_cs_dw_begin = 6;
387 query->num_cs_dw_end = 6;
388 query->stream = index;
389 query->flags |= R600_QUERY_HW_FLAG_PREDICATE;
390 break;
391 case PIPE_QUERY_PIPELINE_STATISTICS:
392 /* 11 values on EG, 8 on R600. */
393 query->result_size = (rctx->chip_class >= EVERGREEN ? 11 : 8) * 16;
394 query->num_cs_dw_begin = 6;
395 query->num_cs_dw_end = 6;
396 break;
397 default:
398 assert(0);
399 FREE(query);
400 return NULL;
401 }
402
403 if (!r600_query_hw_init(rctx, query)) {
404 FREE(query);
405 return NULL;
406 }
407
408 return (struct pipe_query *)query;
409 }
410
411 static void r600_update_occlusion_query_state(struct r600_common_context *rctx,
412 unsigned type, int diff)
413 {
414 if (type == PIPE_QUERY_OCCLUSION_COUNTER ||
415 type == PIPE_QUERY_OCCLUSION_PREDICATE) {
416 bool old_enable = rctx->num_occlusion_queries != 0;
417 bool enable;
418
419 rctx->num_occlusion_queries += diff;
420 assert(rctx->num_occlusion_queries >= 0);
421
422 enable = rctx->num_occlusion_queries != 0;
423
424 if (enable != old_enable) {
425 rctx->set_occlusion_query_state(&rctx->b, enable);
426 }
427 }
428 }
429
430 static unsigned event_type_for_stream(struct r600_query_hw *query)
431 {
432 switch (query->stream) {
433 default:
434 case 0: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS;
435 case 1: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS1;
436 case 2: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS2;
437 case 3: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS3;
438 }
439 }
440
441 static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
442 struct r600_query_hw *query,
443 struct r600_resource *buffer,
444 uint64_t va)
445 {
446 struct radeon_winsys_cs *cs = ctx->gfx.cs;
447
448 switch (query->b.type) {
449 case PIPE_QUERY_OCCLUSION_COUNTER:
450 case PIPE_QUERY_OCCLUSION_PREDICATE:
451 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
452 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
453 radeon_emit(cs, va);
454 radeon_emit(cs, (va >> 32) & 0xFFFF);
455 break;
456 case PIPE_QUERY_PRIMITIVES_EMITTED:
457 case PIPE_QUERY_PRIMITIVES_GENERATED:
458 case PIPE_QUERY_SO_STATISTICS:
459 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
460 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
461 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | EVENT_INDEX(3));
462 radeon_emit(cs, va);
463 radeon_emit(cs, (va >> 32) & 0xFFFF);
464 break;
465 case PIPE_QUERY_TIME_ELAPSED:
466 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
467 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
468 radeon_emit(cs, va);
469 radeon_emit(cs, (3 << 29) | ((va >> 32) & 0xFFFF));
470 radeon_emit(cs, 0);
471 radeon_emit(cs, 0);
472 break;
473 case PIPE_QUERY_PIPELINE_STATISTICS:
474 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
475 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
476 radeon_emit(cs, va);
477 radeon_emit(cs, (va >> 32) & 0xFFFF);
478 break;
479 default:
480 assert(0);
481 }
482 r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE,
483 RADEON_PRIO_QUERY);
484 }
485
486 static void r600_query_hw_emit_start(struct r600_common_context *ctx,
487 struct r600_query_hw *query)
488 {
489 uint64_t va;
490
491 r600_update_occlusion_query_state(ctx, query->b.type, 1);
492 r600_update_prims_generated_query_state(ctx, query->b.type, 1);
493
494 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw_begin + query->num_cs_dw_end,
495 TRUE);
496
497 /* Get a new query buffer if needed. */
498 if (query->buffer.results_end + query->result_size > query->buffer.buf->b.b.width0) {
499 struct r600_query_buffer *qbuf = MALLOC_STRUCT(r600_query_buffer);
500 *qbuf = query->buffer;
501 query->buffer.buf = r600_new_query_buffer(ctx, query);
502 query->buffer.results_end = 0;
503 query->buffer.previous = qbuf;
504 }
505
506 /* emit begin query */
507 va = query->buffer.buf->gpu_address + query->buffer.results_end;
508
509 query->ops->emit_start(ctx, query, query->buffer.buf, va);
510
511 if (query->flags & R600_QUERY_HW_FLAG_TIMER)
512 ctx->num_cs_dw_timer_queries_suspend += query->num_cs_dw_end;
513 else
514 ctx->num_cs_dw_nontimer_queries_suspend += query->num_cs_dw_end;
515 }
516
517 static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
518 struct r600_query_hw *query,
519 struct r600_resource *buffer,
520 uint64_t va)
521 {
522 struct radeon_winsys_cs *cs = ctx->gfx.cs;
523
524 switch (query->b.type) {
525 case PIPE_QUERY_OCCLUSION_COUNTER:
526 case PIPE_QUERY_OCCLUSION_PREDICATE:
527 va += 8;
528 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
529 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
530 radeon_emit(cs, va);
531 radeon_emit(cs, (va >> 32) & 0xFFFF);
532 break;
533 case PIPE_QUERY_PRIMITIVES_EMITTED:
534 case PIPE_QUERY_PRIMITIVES_GENERATED:
535 case PIPE_QUERY_SO_STATISTICS:
536 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
537 va += query->result_size/2;
538 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
539 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | EVENT_INDEX(3));
540 radeon_emit(cs, va);
541 radeon_emit(cs, (va >> 32) & 0xFFFF);
542 break;
543 case PIPE_QUERY_TIME_ELAPSED:
544 va += query->result_size/2;
545 /* fall through */
546 case PIPE_QUERY_TIMESTAMP:
547 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
548 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
549 radeon_emit(cs, va);
550 radeon_emit(cs, (3 << 29) | ((va >> 32) & 0xFFFF));
551 radeon_emit(cs, 0);
552 radeon_emit(cs, 0);
553 break;
554 case PIPE_QUERY_PIPELINE_STATISTICS:
555 va += query->result_size/2;
556 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
557 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
558 radeon_emit(cs, va);
559 radeon_emit(cs, (va >> 32) & 0xFFFF);
560 break;
561 default:
562 assert(0);
563 }
564 r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE,
565 RADEON_PRIO_QUERY);
566 }
567
568 static void r600_query_hw_emit_stop(struct r600_common_context *ctx,
569 struct r600_query_hw *query)
570 {
571 uint64_t va;
572
573 /* The queries which need begin already called this in begin_query. */
574 if (query->flags & R600_QUERY_HW_FLAG_NO_START) {
575 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw_end, FALSE);
576 }
577
578 /* emit end query */
579 va = query->buffer.buf->gpu_address + query->buffer.results_end;
580
581 query->ops->emit_stop(ctx, query, query->buffer.buf, va);
582
583 query->buffer.results_end += query->result_size;
584
585 if (!(query->flags & R600_QUERY_HW_FLAG_NO_START)) {
586 if (query->flags & R600_QUERY_HW_FLAG_TIMER)
587 ctx->num_cs_dw_timer_queries_suspend -= query->num_cs_dw_end;
588 else
589 ctx->num_cs_dw_nontimer_queries_suspend -= query->num_cs_dw_end;
590 }
591
592 r600_update_occlusion_query_state(ctx, query->b.type, -1);
593 r600_update_prims_generated_query_state(ctx, query->b.type, -1);
594 }
595
596 static void r600_emit_query_predication(struct r600_common_context *ctx,
597 struct r600_atom *atom)
598 {
599 struct radeon_winsys_cs *cs = ctx->gfx.cs;
600 struct r600_query_hw *query = (struct r600_query_hw *)ctx->render_cond;
601 struct r600_query_buffer *qbuf;
602 uint32_t op;
603 bool flag_wait;
604
605 if (!query)
606 return;
607
608 flag_wait = ctx->render_cond_mode == PIPE_RENDER_COND_WAIT ||
609 ctx->render_cond_mode == PIPE_RENDER_COND_BY_REGION_WAIT;
610
611 switch (query->b.type) {
612 case PIPE_QUERY_OCCLUSION_COUNTER:
613 case PIPE_QUERY_OCCLUSION_PREDICATE:
614 op = PRED_OP(PREDICATION_OP_ZPASS);
615 break;
616 case PIPE_QUERY_PRIMITIVES_EMITTED:
617 case PIPE_QUERY_PRIMITIVES_GENERATED:
618 case PIPE_QUERY_SO_STATISTICS:
619 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
620 op = PRED_OP(PREDICATION_OP_PRIMCOUNT);
621 break;
622 default:
623 assert(0);
624 return;
625 }
626
627 /* if true then invert, see GL_ARB_conditional_render_inverted */
628 if (ctx->render_cond_invert)
629 op |= PREDICATION_DRAW_NOT_VISIBLE; /* Draw if not visable/overflow */
630 else
631 op |= PREDICATION_DRAW_VISIBLE; /* Draw if visable/overflow */
632
633 op |= flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW;
634
635 /* emit predicate packets for all data blocks */
636 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
637 unsigned results_base = 0;
638 uint64_t va = qbuf->buf->gpu_address;
639
640 while (results_base < qbuf->results_end) {
641 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
642 radeon_emit(cs, va + results_base);
643 radeon_emit(cs, op | (((va + results_base) >> 32) & 0xFF));
644 r600_emit_reloc(ctx, &ctx->gfx, qbuf->buf, RADEON_USAGE_READ,
645 RADEON_PRIO_QUERY);
646 results_base += query->result_size;
647
648 /* set CONTINUE bit for all packets except the first */
649 op |= PREDICATION_CONTINUE;
650 }
651 }
652 }
653
654 static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type, unsigned index)
655 {
656 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
657
658 if (query_type == PIPE_QUERY_TIMESTAMP_DISJOINT ||
659 query_type == PIPE_QUERY_GPU_FINISHED ||
660 query_type >= PIPE_QUERY_DRIVER_SPECIFIC)
661 return r600_query_sw_create(ctx, query_type);
662
663 return r600_query_hw_create(rctx, query_type, index);
664 }
665
666 static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
667 {
668 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
669 struct r600_query *rquery = (struct r600_query *)query;
670
671 rquery->ops->destroy(rctx, rquery);
672 }
673
674 static boolean r600_begin_query(struct pipe_context *ctx,
675 struct pipe_query *query)
676 {
677 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
678 struct r600_query *rquery = (struct r600_query *)query;
679
680 return rquery->ops->begin(rctx, rquery);
681 }
682
683 static void r600_query_hw_reset_buffers(struct r600_common_context *rctx,
684 struct r600_query_hw *query)
685 {
686 struct r600_query_buffer *prev = query->buffer.previous;
687
688 /* Discard the old query buffers. */
689 while (prev) {
690 struct r600_query_buffer *qbuf = prev;
691 prev = prev->previous;
692 pipe_resource_reference((struct pipe_resource**)&qbuf->buf, NULL);
693 FREE(qbuf);
694 }
695
696 if (query->flags & R600_QUERY_HW_FLAG_PREDICATE) {
697 /* Obtain a new buffer if the current one can't be mapped without a stall. */
698 if (r600_rings_is_buffer_referenced(rctx, query->buffer.buf->buf, RADEON_USAGE_READWRITE) ||
699 !rctx->ws->buffer_wait(query->buffer.buf->buf, 0, RADEON_USAGE_READWRITE)) {
700 pipe_resource_reference((struct pipe_resource**)&query->buffer.buf, NULL);
701 query->buffer.buf = r600_new_query_buffer(rctx, query);
702 } else {
703 query->ops->prepare_buffer(rctx, query, query->buffer.buf);
704 }
705 }
706
707 query->buffer.results_end = 0;
708 query->buffer.previous = NULL;
709 }
710
711 boolean r600_query_hw_begin(struct r600_common_context *rctx,
712 struct r600_query *rquery)
713 {
714 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
715
716 if (query->flags & R600_QUERY_HW_FLAG_NO_START) {
717 assert(0);
718 return false;
719 }
720
721 r600_query_hw_reset_buffers(rctx, query);
722
723 r600_query_hw_emit_start(rctx, query);
724
725 if (query->flags & R600_QUERY_HW_FLAG_TIMER)
726 LIST_ADDTAIL(&query->list, &rctx->active_timer_queries);
727 else
728 LIST_ADDTAIL(&query->list, &rctx->active_nontimer_queries);
729 return true;
730 }
731
732 static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
733 {
734 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
735 struct r600_query *rquery = (struct r600_query *)query;
736
737 rquery->ops->end(rctx, rquery);
738 }
739
740 void r600_query_hw_end(struct r600_common_context *rctx,
741 struct r600_query *rquery)
742 {
743 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
744
745 if (query->flags & R600_QUERY_HW_FLAG_NO_START)
746 r600_query_hw_reset_buffers(rctx, query);
747
748 r600_query_hw_emit_stop(rctx, query);
749
750 if (!(query->flags & R600_QUERY_HW_FLAG_NO_START))
751 LIST_DELINIT(&query->list);
752 }
753
754 static unsigned r600_query_read_result(void *map, unsigned start_index, unsigned end_index,
755 bool test_status_bit)
756 {
757 uint32_t *current_result = (uint32_t*)map;
758 uint64_t start, end;
759
760 start = (uint64_t)current_result[start_index] |
761 (uint64_t)current_result[start_index+1] << 32;
762 end = (uint64_t)current_result[end_index] |
763 (uint64_t)current_result[end_index+1] << 32;
764
765 if (!test_status_bit ||
766 ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) {
767 return end - start;
768 }
769 return 0;
770 }
771
772 static void r600_query_hw_add_result(struct r600_common_context *ctx,
773 struct r600_query_hw *query,
774 void *buffer,
775 union pipe_query_result *result)
776 {
777 switch (query->b.type) {
778 case PIPE_QUERY_OCCLUSION_COUNTER: {
779 unsigned results_base = 0;
780 while (results_base != query->result_size) {
781 result->u64 +=
782 r600_query_read_result(buffer + results_base, 0, 2, true);
783 results_base += 16;
784 }
785 break;
786 }
787 case PIPE_QUERY_OCCLUSION_PREDICATE: {
788 unsigned results_base = 0;
789 while (results_base != query->result_size) {
790 result->b = result->b ||
791 r600_query_read_result(buffer + results_base, 0, 2, true) != 0;
792 results_base += 16;
793 }
794 break;
795 }
796 case PIPE_QUERY_TIME_ELAPSED:
797 result->u64 += r600_query_read_result(buffer, 0, 2, false);
798 break;
799 case PIPE_QUERY_TIMESTAMP:
800 {
801 uint32_t *current_result = (uint32_t*)buffer;
802 result->u64 = (uint64_t)current_result[0] |
803 (uint64_t)current_result[1] << 32;
804 break;
805 }
806 case PIPE_QUERY_PRIMITIVES_EMITTED:
807 /* SAMPLE_STREAMOUTSTATS stores this structure:
808 * {
809 * u64 NumPrimitivesWritten;
810 * u64 PrimitiveStorageNeeded;
811 * }
812 * We only need NumPrimitivesWritten here. */
813 result->u64 += r600_query_read_result(buffer, 2, 6, true);
814 break;
815 case PIPE_QUERY_PRIMITIVES_GENERATED:
816 /* Here we read PrimitiveStorageNeeded. */
817 result->u64 += r600_query_read_result(buffer, 0, 4, true);
818 break;
819 case PIPE_QUERY_SO_STATISTICS:
820 result->so_statistics.num_primitives_written +=
821 r600_query_read_result(buffer, 2, 6, true);
822 result->so_statistics.primitives_storage_needed +=
823 r600_query_read_result(buffer, 0, 4, true);
824 break;
825 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
826 result->b = result->b ||
827 r600_query_read_result(buffer, 2, 6, true) !=
828 r600_query_read_result(buffer, 0, 4, true);
829 break;
830 case PIPE_QUERY_PIPELINE_STATISTICS:
831 if (ctx->chip_class >= EVERGREEN) {
832 result->pipeline_statistics.ps_invocations +=
833 r600_query_read_result(buffer, 0, 22, false);
834 result->pipeline_statistics.c_primitives +=
835 r600_query_read_result(buffer, 2, 24, false);
836 result->pipeline_statistics.c_invocations +=
837 r600_query_read_result(buffer, 4, 26, false);
838 result->pipeline_statistics.vs_invocations +=
839 r600_query_read_result(buffer, 6, 28, false);
840 result->pipeline_statistics.gs_invocations +=
841 r600_query_read_result(buffer, 8, 30, false);
842 result->pipeline_statistics.gs_primitives +=
843 r600_query_read_result(buffer, 10, 32, false);
844 result->pipeline_statistics.ia_primitives +=
845 r600_query_read_result(buffer, 12, 34, false);
846 result->pipeline_statistics.ia_vertices +=
847 r600_query_read_result(buffer, 14, 36, false);
848 result->pipeline_statistics.hs_invocations +=
849 r600_query_read_result(buffer, 16, 38, false);
850 result->pipeline_statistics.ds_invocations +=
851 r600_query_read_result(buffer, 18, 40, false);
852 result->pipeline_statistics.cs_invocations +=
853 r600_query_read_result(buffer, 20, 42, false);
854 } else {
855 result->pipeline_statistics.ps_invocations +=
856 r600_query_read_result(buffer, 0, 16, false);
857 result->pipeline_statistics.c_primitives +=
858 r600_query_read_result(buffer, 2, 18, false);
859 result->pipeline_statistics.c_invocations +=
860 r600_query_read_result(buffer, 4, 20, false);
861 result->pipeline_statistics.vs_invocations +=
862 r600_query_read_result(buffer, 6, 22, false);
863 result->pipeline_statistics.gs_invocations +=
864 r600_query_read_result(buffer, 8, 24, false);
865 result->pipeline_statistics.gs_primitives +=
866 r600_query_read_result(buffer, 10, 26, false);
867 result->pipeline_statistics.ia_primitives +=
868 r600_query_read_result(buffer, 12, 28, false);
869 result->pipeline_statistics.ia_vertices +=
870 r600_query_read_result(buffer, 14, 30, false);
871 }
872 #if 0 /* for testing */
873 printf("Pipeline stats: IA verts=%llu, IA prims=%llu, VS=%llu, HS=%llu, "
874 "DS=%llu, GS=%llu, GS prims=%llu, Clipper=%llu, "
875 "Clipper prims=%llu, PS=%llu, CS=%llu\n",
876 result->pipeline_statistics.ia_vertices,
877 result->pipeline_statistics.ia_primitives,
878 result->pipeline_statistics.vs_invocations,
879 result->pipeline_statistics.hs_invocations,
880 result->pipeline_statistics.ds_invocations,
881 result->pipeline_statistics.gs_invocations,
882 result->pipeline_statistics.gs_primitives,
883 result->pipeline_statistics.c_invocations,
884 result->pipeline_statistics.c_primitives,
885 result->pipeline_statistics.ps_invocations,
886 result->pipeline_statistics.cs_invocations);
887 #endif
888 break;
889 default:
890 assert(0);
891 }
892 }
893
894 static boolean r600_get_query_result(struct pipe_context *ctx,
895 struct pipe_query *query, boolean wait,
896 union pipe_query_result *result)
897 {
898 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
899 struct r600_query *rquery = (struct r600_query *)query;
900
901 return rquery->ops->get_result(rctx, rquery, wait, result);
902 }
903
904 static void r600_query_hw_clear_result(struct r600_query_hw *query,
905 union pipe_query_result *result)
906 {
907 util_query_clear_result(result, query->b.type);
908 }
909
910 boolean r600_query_hw_get_result(struct r600_common_context *rctx,
911 struct r600_query *rquery,
912 boolean wait, union pipe_query_result *result)
913 {
914 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
915 struct r600_query_buffer *qbuf;
916
917 query->ops->clear_result(query, result);
918
919 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
920 unsigned results_base = 0;
921 void *map;
922
923 map = r600_buffer_map_sync_with_rings(rctx, qbuf->buf,
924 PIPE_TRANSFER_READ |
925 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK));
926 if (!map)
927 return FALSE;
928
929 while (results_base != qbuf->results_end) {
930 query->ops->add_result(rctx, query, map + results_base,
931 result);
932 results_base += query->result_size;
933 }
934 }
935
936 /* Convert the time to expected units. */
937 if (rquery->type == PIPE_QUERY_TIME_ELAPSED ||
938 rquery->type == PIPE_QUERY_TIMESTAMP) {
939 result->u64 = (1000000 * result->u64) / rctx->screen->info.r600_clock_crystal_freq;
940 }
941 return TRUE;
942 }
943
944 static void r600_render_condition(struct pipe_context *ctx,
945 struct pipe_query *query,
946 boolean condition,
947 uint mode)
948 {
949 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
950 struct r600_query_hw *rquery = (struct r600_query_hw *)query;
951 struct r600_query_buffer *qbuf;
952 struct r600_atom *atom = &rctx->render_cond_atom;
953
954 rctx->render_cond = query;
955 rctx->render_cond_invert = condition;
956 rctx->render_cond_mode = mode;
957
958 /* Compute the size of SET_PREDICATION packets. */
959 atom->num_dw = 0;
960 if (query) {
961 for (qbuf = &rquery->buffer; qbuf; qbuf = qbuf->previous)
962 atom->num_dw += (qbuf->results_end / rquery->result_size) * 5;
963 }
964
965 rctx->set_atom_dirty(rctx, atom, query != NULL);
966 }
967
968 static void r600_suspend_queries(struct r600_common_context *ctx,
969 struct list_head *query_list,
970 unsigned *num_cs_dw_queries_suspend)
971 {
972 struct r600_query_hw *query;
973
974 LIST_FOR_EACH_ENTRY(query, query_list, list) {
975 r600_query_hw_emit_stop(ctx, query);
976 }
977 assert(*num_cs_dw_queries_suspend == 0);
978 }
979
980 void r600_suspend_nontimer_queries(struct r600_common_context *ctx)
981 {
982 r600_suspend_queries(ctx, &ctx->active_nontimer_queries,
983 &ctx->num_cs_dw_nontimer_queries_suspend);
984 }
985
986 void r600_suspend_timer_queries(struct r600_common_context *ctx)
987 {
988 r600_suspend_queries(ctx, &ctx->active_timer_queries,
989 &ctx->num_cs_dw_timer_queries_suspend);
990 }
991
992 static unsigned r600_queries_num_cs_dw_for_resuming(struct r600_common_context *ctx,
993 struct list_head *query_list)
994 {
995 struct r600_query_hw *query;
996 unsigned num_dw = 0;
997
998 LIST_FOR_EACH_ENTRY(query, query_list, list) {
999 /* begin + end */
1000 num_dw += query->num_cs_dw_begin + query->num_cs_dw_end;
1001
1002 /* Workaround for the fact that
1003 * num_cs_dw_nontimer_queries_suspend is incremented for every
1004 * resumed query, which raises the bar in need_cs_space for
1005 * queries about to be resumed.
1006 */
1007 num_dw += query->num_cs_dw_end;
1008 }
1009 /* primitives generated query */
1010 num_dw += ctx->streamout.enable_atom.num_dw;
1011 /* guess for ZPASS enable or PERFECT_ZPASS_COUNT enable updates */
1012 num_dw += 13;
1013
1014 return num_dw;
1015 }
1016
1017 static void r600_resume_queries(struct r600_common_context *ctx,
1018 struct list_head *query_list,
1019 unsigned *num_cs_dw_queries_suspend)
1020 {
1021 struct r600_query_hw *query;
1022 unsigned num_cs_dw = r600_queries_num_cs_dw_for_resuming(ctx, query_list);
1023
1024 assert(*num_cs_dw_queries_suspend == 0);
1025
1026 /* Check CS space here. Resuming must not be interrupted by flushes. */
1027 ctx->need_gfx_cs_space(&ctx->b, num_cs_dw, TRUE);
1028
1029 LIST_FOR_EACH_ENTRY(query, query_list, list) {
1030 r600_query_hw_emit_start(ctx, query);
1031 }
1032 }
1033
1034 void r600_resume_nontimer_queries(struct r600_common_context *ctx)
1035 {
1036 r600_resume_queries(ctx, &ctx->active_nontimer_queries,
1037 &ctx->num_cs_dw_nontimer_queries_suspend);
1038 }
1039
1040 void r600_resume_timer_queries(struct r600_common_context *ctx)
1041 {
1042 r600_resume_queries(ctx, &ctx->active_timer_queries,
1043 &ctx->num_cs_dw_timer_queries_suspend);
1044 }
1045
1046 /* Get backends mask */
1047 void r600_query_init_backend_mask(struct r600_common_context *ctx)
1048 {
1049 struct radeon_winsys_cs *cs = ctx->gfx.cs;
1050 struct r600_resource *buffer;
1051 uint32_t *results;
1052 unsigned num_backends = ctx->screen->info.r600_num_backends;
1053 unsigned i, mask = 0;
1054
1055 /* if backend_map query is supported by the kernel */
1056 if (ctx->screen->info.r600_backend_map_valid) {
1057 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
1058 unsigned backend_map = ctx->screen->info.r600_backend_map;
1059 unsigned item_width, item_mask;
1060
1061 if (ctx->chip_class >= EVERGREEN) {
1062 item_width = 4;
1063 item_mask = 0x7;
1064 } else {
1065 item_width = 2;
1066 item_mask = 0x3;
1067 }
1068
1069 while(num_tile_pipes--) {
1070 i = backend_map & item_mask;
1071 mask |= (1<<i);
1072 backend_map >>= item_width;
1073 }
1074 if (mask != 0) {
1075 ctx->backend_mask = mask;
1076 return;
1077 }
1078 }
1079
1080 /* otherwise backup path for older kernels */
1081
1082 /* create buffer for event data */
1083 buffer = (struct r600_resource*)
1084 pipe_buffer_create(ctx->b.screen, PIPE_BIND_CUSTOM,
1085 PIPE_USAGE_STAGING, ctx->max_db*16);
1086 if (!buffer)
1087 goto err;
1088
1089 /* initialize buffer with zeroes */
1090 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE);
1091 if (results) {
1092 memset(results, 0, ctx->max_db * 4 * 4);
1093
1094 /* emit EVENT_WRITE for ZPASS_DONE */
1095 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1096 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
1097 radeon_emit(cs, buffer->gpu_address);
1098 radeon_emit(cs, buffer->gpu_address >> 32);
1099
1100 r600_emit_reloc(ctx, &ctx->gfx, buffer,
1101 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
1102
1103 /* analyze results */
1104 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ);
1105 if (results) {
1106 for(i = 0; i < ctx->max_db; i++) {
1107 /* at least highest bit will be set if backend is used */
1108 if (results[i*4 + 1])
1109 mask |= (1<<i);
1110 }
1111 }
1112 }
1113
1114 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
1115
1116 if (mask != 0) {
1117 ctx->backend_mask = mask;
1118 return;
1119 }
1120
1121 err:
1122 /* fallback to old method - set num_backends lower bits to 1 */
1123 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
1124 return;
1125 }
1126
1127 #define XFULL(name_, query_type_, type_, result_type_, group_id_) \
1128 { \
1129 .name = name_, \
1130 .query_type = R600_QUERY_##query_type_, \
1131 .type = PIPE_DRIVER_QUERY_TYPE_##type_, \
1132 .result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_##result_type_, \
1133 .group_id = group_id_ \
1134 }
1135
1136 #define X(name_, query_type_, type_, result_type_) \
1137 XFULL(name_, query_type_, type_, result_type_, ~(unsigned)0)
1138
1139 #define XG(group_, name_, query_type_, type_, result_type_) \
1140 XFULL(name_, query_type_, type_, result_type_, R600_QUERY_GROUP_##group_)
1141
1142 static struct pipe_driver_query_info r600_driver_query_list[] = {
1143 X("num-compilations", NUM_COMPILATIONS, UINT64, CUMULATIVE),
1144 X("num-shaders-created", NUM_SHADERS_CREATED, UINT64, CUMULATIVE),
1145 X("draw-calls", DRAW_CALLS, UINT64, CUMULATIVE),
1146 X("requested-VRAM", REQUESTED_VRAM, BYTES, AVERAGE),
1147 X("requested-GTT", REQUESTED_GTT, BYTES, AVERAGE),
1148 X("buffer-wait-time", BUFFER_WAIT_TIME, MICROSECONDS, CUMULATIVE),
1149 X("num-cs-flushes", NUM_CS_FLUSHES, UINT64, CUMULATIVE),
1150 X("num-bytes-moved", NUM_BYTES_MOVED, BYTES, CUMULATIVE),
1151 X("VRAM-usage", VRAM_USAGE, BYTES, AVERAGE),
1152 X("GTT-usage", GTT_USAGE, BYTES, AVERAGE),
1153
1154 /* GPIN queries are for the benefit of old versions of GPUPerfStudio,
1155 * which use it as a fallback path to detect the GPU type.
1156 *
1157 * Note: The names of these queries are significant for GPUPerfStudio
1158 * (and possibly their order as well). */
1159 XG(GPIN, "GPIN_000", GPIN_ASIC_ID, UINT, AVERAGE),
1160 XG(GPIN, "GPIN_001", GPIN_NUM_SIMD, UINT, AVERAGE),
1161 XG(GPIN, "GPIN_002", GPIN_NUM_RB, UINT, AVERAGE),
1162 XG(GPIN, "GPIN_003", GPIN_NUM_SPI, UINT, AVERAGE),
1163 XG(GPIN, "GPIN_004", GPIN_NUM_SE, UINT, AVERAGE),
1164
1165 /* The following queries must be at the end of the list because their
1166 * availability is adjusted dynamically based on the DRM version. */
1167 X("GPU-load", GPU_LOAD, UINT64, AVERAGE),
1168 X("temperature", GPU_TEMPERATURE, UINT64, AVERAGE),
1169 X("shader-clock", CURRENT_GPU_SCLK, HZ, AVERAGE),
1170 X("memory-clock", CURRENT_GPU_MCLK, HZ, AVERAGE),
1171 };
1172
1173 #undef X
1174 #undef XG
1175 #undef XFULL
1176
1177 static unsigned r600_get_num_queries(struct r600_common_screen *rscreen)
1178 {
1179 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
1180 return Elements(r600_driver_query_list);
1181 else if (rscreen->info.drm_major == 3)
1182 return Elements(r600_driver_query_list) - 3;
1183 else
1184 return Elements(r600_driver_query_list) - 4;
1185 }
1186
1187 static int r600_get_driver_query_info(struct pipe_screen *screen,
1188 unsigned index,
1189 struct pipe_driver_query_info *info)
1190 {
1191 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1192 unsigned num_queries = r600_get_num_queries(rscreen);
1193
1194 if (!info) {
1195 unsigned num_perfcounters =
1196 r600_get_perfcounter_info(rscreen, 0, NULL);
1197
1198 return num_queries + num_perfcounters;
1199 }
1200
1201 if (index >= num_queries)
1202 return r600_get_perfcounter_info(rscreen, index - num_queries, info);
1203
1204 *info = r600_driver_query_list[index];
1205
1206 switch (info->query_type) {
1207 case R600_QUERY_REQUESTED_VRAM:
1208 case R600_QUERY_VRAM_USAGE:
1209 info->max_value.u64 = rscreen->info.vram_size;
1210 break;
1211 case R600_QUERY_REQUESTED_GTT:
1212 case R600_QUERY_GTT_USAGE:
1213 info->max_value.u64 = rscreen->info.gart_size;
1214 break;
1215 case R600_QUERY_GPU_TEMPERATURE:
1216 info->max_value.u64 = 125;
1217 break;
1218 }
1219
1220 if (info->group_id != ~(unsigned)0 && rscreen->perfcounters)
1221 info->group_id += rscreen->perfcounters->num_groups;
1222
1223 return 1;
1224 }
1225
1226 /* Note: Unfortunately, GPUPerfStudio hardcodes the order of hardware
1227 * performance counter groups, so be careful when changing this and related
1228 * functions.
1229 */
1230 static int r600_get_driver_query_group_info(struct pipe_screen *screen,
1231 unsigned index,
1232 struct pipe_driver_query_group_info *info)
1233 {
1234 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
1235 unsigned num_pc_groups = 0;
1236
1237 if (rscreen->perfcounters)
1238 num_pc_groups = rscreen->perfcounters->num_groups;
1239
1240 if (!info)
1241 return num_pc_groups + R600_NUM_SW_QUERY_GROUPS;
1242
1243 if (index < num_pc_groups)
1244 return r600_get_perfcounter_group_info(rscreen, index, info);
1245
1246 index -= num_pc_groups;
1247 if (index >= R600_NUM_SW_QUERY_GROUPS)
1248 return 0;
1249
1250 info->name = "GPIN";
1251 info->max_active_queries = 5;
1252 info->num_queries = 5;
1253 return 1;
1254 }
1255
1256 void r600_query_init(struct r600_common_context *rctx)
1257 {
1258 rctx->b.create_query = r600_create_query;
1259 rctx->b.create_batch_query = r600_create_batch_query;
1260 rctx->b.destroy_query = r600_destroy_query;
1261 rctx->b.begin_query = r600_begin_query;
1262 rctx->b.end_query = r600_end_query;
1263 rctx->b.get_query_result = r600_get_query_result;
1264 rctx->render_cond_atom.emit = r600_emit_query_predication;
1265
1266 if (((struct r600_common_screen*)rctx->b.screen)->info.r600_num_backends > 0)
1267 rctx->b.render_condition = r600_render_condition;
1268
1269 LIST_INITHEAD(&rctx->active_nontimer_queries);
1270 LIST_INITHEAD(&rctx->active_timer_queries);
1271 }
1272
1273 void r600_init_screen_query_functions(struct r600_common_screen *rscreen)
1274 {
1275 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
1276 rscreen->b.get_driver_query_group_info = r600_get_driver_query_group_info;
1277 }