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gallium/radeon: add new GPU-sdma-busy HUD query
[mesa.git] / src / gallium / drivers / radeon / r600_query.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014 Marek Olšák <marek.olsak@amd.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "r600_query.h"
26 #include "r600_cs.h"
27 #include "util/u_memory.h"
28 #include "util/u_upload_mgr.h"
29
30 #include "tgsi/tgsi_text.h"
31
32 struct r600_hw_query_params {
33 unsigned start_offset;
34 unsigned end_offset;
35 unsigned fence_offset;
36 unsigned pair_stride;
37 unsigned pair_count;
38 };
39
40 /* Queries without buffer handling or suspend/resume. */
41 struct r600_query_sw {
42 struct r600_query b;
43
44 uint64_t begin_result;
45 uint64_t end_result;
46 /* Fence for GPU_FINISHED. */
47 struct pipe_fence_handle *fence;
48 };
49
50 static void r600_query_sw_destroy(struct r600_common_context *rctx,
51 struct r600_query *rquery)
52 {
53 struct pipe_screen *screen = rctx->b.screen;
54 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
55
56 screen->fence_reference(screen, &query->fence, NULL);
57 FREE(query);
58 }
59
60 static enum radeon_value_id winsys_id_from_type(unsigned type)
61 {
62 switch (type) {
63 case R600_QUERY_REQUESTED_VRAM: return RADEON_REQUESTED_VRAM_MEMORY;
64 case R600_QUERY_REQUESTED_GTT: return RADEON_REQUESTED_GTT_MEMORY;
65 case R600_QUERY_MAPPED_VRAM: return RADEON_MAPPED_VRAM;
66 case R600_QUERY_MAPPED_GTT: return RADEON_MAPPED_GTT;
67 case R600_QUERY_BUFFER_WAIT_TIME: return RADEON_BUFFER_WAIT_TIME_NS;
68 case R600_QUERY_NUM_MAPPED_BUFFERS: return RADEON_NUM_MAPPED_BUFFERS;
69 case R600_QUERY_NUM_GFX_IBS: return RADEON_NUM_GFX_IBS;
70 case R600_QUERY_NUM_SDMA_IBS: return RADEON_NUM_SDMA_IBS;
71 case R600_QUERY_NUM_BYTES_MOVED: return RADEON_NUM_BYTES_MOVED;
72 case R600_QUERY_NUM_EVICTIONS: return RADEON_NUM_EVICTIONS;
73 case R600_QUERY_VRAM_USAGE: return RADEON_VRAM_USAGE;
74 case R600_QUERY_VRAM_VIS_USAGE: return RADEON_VRAM_VIS_USAGE;
75 case R600_QUERY_GTT_USAGE: return RADEON_GTT_USAGE;
76 case R600_QUERY_GPU_TEMPERATURE: return RADEON_GPU_TEMPERATURE;
77 case R600_QUERY_CURRENT_GPU_SCLK: return RADEON_CURRENT_SCLK;
78 case R600_QUERY_CURRENT_GPU_MCLK: return RADEON_CURRENT_MCLK;
79 default: unreachable("query type does not correspond to winsys id");
80 }
81 }
82
83 static bool r600_query_sw_begin(struct r600_common_context *rctx,
84 struct r600_query *rquery)
85 {
86 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
87
88 switch(query->b.type) {
89 case PIPE_QUERY_TIMESTAMP_DISJOINT:
90 case PIPE_QUERY_GPU_FINISHED:
91 break;
92 case R600_QUERY_DRAW_CALLS:
93 query->begin_result = rctx->num_draw_calls;
94 break;
95 case R600_QUERY_SPILL_DRAW_CALLS:
96 query->begin_result = rctx->num_spill_draw_calls;
97 break;
98 case R600_QUERY_COMPUTE_CALLS:
99 query->begin_result = rctx->num_compute_calls;
100 break;
101 case R600_QUERY_SPILL_COMPUTE_CALLS:
102 query->begin_result = rctx->num_spill_compute_calls;
103 break;
104 case R600_QUERY_DMA_CALLS:
105 query->begin_result = rctx->num_dma_calls;
106 break;
107 case R600_QUERY_CP_DMA_CALLS:
108 query->begin_result = rctx->num_cp_dma_calls;
109 break;
110 case R600_QUERY_NUM_VS_FLUSHES:
111 query->begin_result = rctx->num_vs_flushes;
112 break;
113 case R600_QUERY_NUM_PS_FLUSHES:
114 query->begin_result = rctx->num_ps_flushes;
115 break;
116 case R600_QUERY_NUM_CS_FLUSHES:
117 query->begin_result = rctx->num_cs_flushes;
118 break;
119 case R600_QUERY_NUM_FB_CACHE_FLUSHES:
120 query->begin_result = rctx->num_fb_cache_flushes;
121 break;
122 case R600_QUERY_NUM_L2_INVALIDATES:
123 query->begin_result = rctx->num_L2_invalidates;
124 break;
125 case R600_QUERY_NUM_L2_WRITEBACKS:
126 query->begin_result = rctx->num_L2_writebacks;
127 break;
128 case R600_QUERY_REQUESTED_VRAM:
129 case R600_QUERY_REQUESTED_GTT:
130 case R600_QUERY_MAPPED_VRAM:
131 case R600_QUERY_MAPPED_GTT:
132 case R600_QUERY_VRAM_USAGE:
133 case R600_QUERY_VRAM_VIS_USAGE:
134 case R600_QUERY_GTT_USAGE:
135 case R600_QUERY_GPU_TEMPERATURE:
136 case R600_QUERY_CURRENT_GPU_SCLK:
137 case R600_QUERY_CURRENT_GPU_MCLK:
138 case R600_QUERY_BACK_BUFFER_PS_DRAW_RATIO:
139 case R600_QUERY_NUM_MAPPED_BUFFERS:
140 query->begin_result = 0;
141 break;
142 case R600_QUERY_BUFFER_WAIT_TIME:
143 case R600_QUERY_NUM_GFX_IBS:
144 case R600_QUERY_NUM_SDMA_IBS:
145 case R600_QUERY_NUM_BYTES_MOVED:
146 case R600_QUERY_NUM_EVICTIONS: {
147 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
148 query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
149 break;
150 }
151 case R600_QUERY_GPU_LOAD:
152 case R600_QUERY_GPU_SHADERS_BUSY:
153 case R600_QUERY_GPU_TA_BUSY:
154 case R600_QUERY_GPU_GDS_BUSY:
155 case R600_QUERY_GPU_VGT_BUSY:
156 case R600_QUERY_GPU_IA_BUSY:
157 case R600_QUERY_GPU_SX_BUSY:
158 case R600_QUERY_GPU_WD_BUSY:
159 case R600_QUERY_GPU_BCI_BUSY:
160 case R600_QUERY_GPU_SC_BUSY:
161 case R600_QUERY_GPU_PA_BUSY:
162 case R600_QUERY_GPU_DB_BUSY:
163 case R600_QUERY_GPU_CP_BUSY:
164 case R600_QUERY_GPU_CB_BUSY:
165 case R600_QUERY_GPU_SDMA_BUSY:
166 query->begin_result = r600_begin_counter(rctx->screen,
167 query->b.type);
168 break;
169 case R600_QUERY_NUM_COMPILATIONS:
170 query->begin_result = p_atomic_read(&rctx->screen->num_compilations);
171 break;
172 case R600_QUERY_NUM_SHADERS_CREATED:
173 query->begin_result = p_atomic_read(&rctx->screen->num_shaders_created);
174 break;
175 case R600_QUERY_NUM_SHADER_CACHE_HITS:
176 query->begin_result =
177 p_atomic_read(&rctx->screen->num_shader_cache_hits);
178 break;
179 case R600_QUERY_GPIN_ASIC_ID:
180 case R600_QUERY_GPIN_NUM_SIMD:
181 case R600_QUERY_GPIN_NUM_RB:
182 case R600_QUERY_GPIN_NUM_SPI:
183 case R600_QUERY_GPIN_NUM_SE:
184 break;
185 default:
186 unreachable("r600_query_sw_begin: bad query type");
187 }
188
189 return true;
190 }
191
192 static bool r600_query_sw_end(struct r600_common_context *rctx,
193 struct r600_query *rquery)
194 {
195 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
196
197 switch(query->b.type) {
198 case PIPE_QUERY_TIMESTAMP_DISJOINT:
199 break;
200 case PIPE_QUERY_GPU_FINISHED:
201 rctx->b.flush(&rctx->b, &query->fence, PIPE_FLUSH_DEFERRED);
202 break;
203 case R600_QUERY_DRAW_CALLS:
204 query->end_result = rctx->num_draw_calls;
205 break;
206 case R600_QUERY_SPILL_DRAW_CALLS:
207 query->end_result = rctx->num_spill_draw_calls;
208 break;
209 case R600_QUERY_COMPUTE_CALLS:
210 query->end_result = rctx->num_compute_calls;
211 break;
212 case R600_QUERY_SPILL_COMPUTE_CALLS:
213 query->end_result = rctx->num_spill_compute_calls;
214 break;
215 case R600_QUERY_DMA_CALLS:
216 query->end_result = rctx->num_dma_calls;
217 break;
218 case R600_QUERY_CP_DMA_CALLS:
219 query->end_result = rctx->num_cp_dma_calls;
220 break;
221 case R600_QUERY_NUM_VS_FLUSHES:
222 query->end_result = rctx->num_vs_flushes;
223 break;
224 case R600_QUERY_NUM_PS_FLUSHES:
225 query->end_result = rctx->num_ps_flushes;
226 break;
227 case R600_QUERY_NUM_CS_FLUSHES:
228 query->end_result = rctx->num_cs_flushes;
229 break;
230 case R600_QUERY_NUM_FB_CACHE_FLUSHES:
231 query->end_result = rctx->num_fb_cache_flushes;
232 break;
233 case R600_QUERY_NUM_L2_INVALIDATES:
234 query->end_result = rctx->num_L2_invalidates;
235 break;
236 case R600_QUERY_NUM_L2_WRITEBACKS:
237 query->end_result = rctx->num_L2_writebacks;
238 break;
239 case R600_QUERY_REQUESTED_VRAM:
240 case R600_QUERY_REQUESTED_GTT:
241 case R600_QUERY_MAPPED_VRAM:
242 case R600_QUERY_MAPPED_GTT:
243 case R600_QUERY_VRAM_USAGE:
244 case R600_QUERY_VRAM_VIS_USAGE:
245 case R600_QUERY_GTT_USAGE:
246 case R600_QUERY_GPU_TEMPERATURE:
247 case R600_QUERY_CURRENT_GPU_SCLK:
248 case R600_QUERY_CURRENT_GPU_MCLK:
249 case R600_QUERY_BUFFER_WAIT_TIME:
250 case R600_QUERY_NUM_MAPPED_BUFFERS:
251 case R600_QUERY_NUM_GFX_IBS:
252 case R600_QUERY_NUM_SDMA_IBS:
253 case R600_QUERY_NUM_BYTES_MOVED:
254 case R600_QUERY_NUM_EVICTIONS: {
255 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
256 query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
257 break;
258 }
259 case R600_QUERY_GPU_LOAD:
260 case R600_QUERY_GPU_SHADERS_BUSY:
261 case R600_QUERY_GPU_TA_BUSY:
262 case R600_QUERY_GPU_GDS_BUSY:
263 case R600_QUERY_GPU_VGT_BUSY:
264 case R600_QUERY_GPU_IA_BUSY:
265 case R600_QUERY_GPU_SX_BUSY:
266 case R600_QUERY_GPU_WD_BUSY:
267 case R600_QUERY_GPU_BCI_BUSY:
268 case R600_QUERY_GPU_SC_BUSY:
269 case R600_QUERY_GPU_PA_BUSY:
270 case R600_QUERY_GPU_DB_BUSY:
271 case R600_QUERY_GPU_CP_BUSY:
272 case R600_QUERY_GPU_CB_BUSY:
273 case R600_QUERY_GPU_SDMA_BUSY:
274 query->end_result = r600_end_counter(rctx->screen,
275 query->b.type,
276 query->begin_result);
277 query->begin_result = 0;
278 break;
279 case R600_QUERY_NUM_COMPILATIONS:
280 query->end_result = p_atomic_read(&rctx->screen->num_compilations);
281 break;
282 case R600_QUERY_NUM_SHADERS_CREATED:
283 query->end_result = p_atomic_read(&rctx->screen->num_shaders_created);
284 break;
285 case R600_QUERY_BACK_BUFFER_PS_DRAW_RATIO:
286 query->end_result = rctx->last_tex_ps_draw_ratio;
287 break;
288 case R600_QUERY_NUM_SHADER_CACHE_HITS:
289 query->end_result =
290 p_atomic_read(&rctx->screen->num_shader_cache_hits);
291 break;
292 case R600_QUERY_GPIN_ASIC_ID:
293 case R600_QUERY_GPIN_NUM_SIMD:
294 case R600_QUERY_GPIN_NUM_RB:
295 case R600_QUERY_GPIN_NUM_SPI:
296 case R600_QUERY_GPIN_NUM_SE:
297 break;
298 default:
299 unreachable("r600_query_sw_end: bad query type");
300 }
301
302 return true;
303 }
304
305 static bool r600_query_sw_get_result(struct r600_common_context *rctx,
306 struct r600_query *rquery,
307 bool wait,
308 union pipe_query_result *result)
309 {
310 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
311
312 switch (query->b.type) {
313 case PIPE_QUERY_TIMESTAMP_DISJOINT:
314 /* Convert from cycles per millisecond to cycles per second (Hz). */
315 result->timestamp_disjoint.frequency =
316 (uint64_t)rctx->screen->info.clock_crystal_freq * 1000;
317 result->timestamp_disjoint.disjoint = false;
318 return true;
319 case PIPE_QUERY_GPU_FINISHED: {
320 struct pipe_screen *screen = rctx->b.screen;
321 result->b = screen->fence_finish(screen, &rctx->b, query->fence,
322 wait ? PIPE_TIMEOUT_INFINITE : 0);
323 return result->b;
324 }
325
326 case R600_QUERY_GPIN_ASIC_ID:
327 result->u32 = 0;
328 return true;
329 case R600_QUERY_GPIN_NUM_SIMD:
330 result->u32 = rctx->screen->info.num_good_compute_units;
331 return true;
332 case R600_QUERY_GPIN_NUM_RB:
333 result->u32 = rctx->screen->info.num_render_backends;
334 return true;
335 case R600_QUERY_GPIN_NUM_SPI:
336 result->u32 = 1; /* all supported chips have one SPI per SE */
337 return true;
338 case R600_QUERY_GPIN_NUM_SE:
339 result->u32 = rctx->screen->info.max_se;
340 return true;
341 }
342
343 result->u64 = query->end_result - query->begin_result;
344
345 switch (query->b.type) {
346 case R600_QUERY_BUFFER_WAIT_TIME:
347 case R600_QUERY_GPU_TEMPERATURE:
348 result->u64 /= 1000;
349 break;
350 case R600_QUERY_CURRENT_GPU_SCLK:
351 case R600_QUERY_CURRENT_GPU_MCLK:
352 result->u64 *= 1000000;
353 break;
354 }
355
356 return true;
357 }
358
359
360 static struct r600_query_ops sw_query_ops = {
361 .destroy = r600_query_sw_destroy,
362 .begin = r600_query_sw_begin,
363 .end = r600_query_sw_end,
364 .get_result = r600_query_sw_get_result,
365 .get_result_resource = NULL
366 };
367
368 static struct pipe_query *r600_query_sw_create(struct pipe_context *ctx,
369 unsigned query_type)
370 {
371 struct r600_query_sw *query;
372
373 query = CALLOC_STRUCT(r600_query_sw);
374 if (!query)
375 return NULL;
376
377 query->b.type = query_type;
378 query->b.ops = &sw_query_ops;
379
380 return (struct pipe_query *)query;
381 }
382
383 void r600_query_hw_destroy(struct r600_common_context *rctx,
384 struct r600_query *rquery)
385 {
386 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
387 struct r600_query_buffer *prev = query->buffer.previous;
388
389 /* Release all query buffers. */
390 while (prev) {
391 struct r600_query_buffer *qbuf = prev;
392 prev = prev->previous;
393 r600_resource_reference(&qbuf->buf, NULL);
394 FREE(qbuf);
395 }
396
397 r600_resource_reference(&query->buffer.buf, NULL);
398 FREE(rquery);
399 }
400
401 static struct r600_resource *r600_new_query_buffer(struct r600_common_context *ctx,
402 struct r600_query_hw *query)
403 {
404 unsigned buf_size = MAX2(query->result_size,
405 ctx->screen->info.min_alloc_size);
406
407 /* Queries are normally read by the CPU after
408 * being written by the gpu, hence staging is probably a good
409 * usage pattern.
410 */
411 struct r600_resource *buf = (struct r600_resource*)
412 pipe_buffer_create(ctx->b.screen, 0,
413 PIPE_USAGE_STAGING, buf_size);
414 if (!buf)
415 return NULL;
416
417 if (!query->ops->prepare_buffer(ctx, query, buf)) {
418 r600_resource_reference(&buf, NULL);
419 return NULL;
420 }
421
422 return buf;
423 }
424
425 static bool r600_query_hw_prepare_buffer(struct r600_common_context *ctx,
426 struct r600_query_hw *query,
427 struct r600_resource *buffer)
428 {
429 /* Callers ensure that the buffer is currently unused by the GPU. */
430 uint32_t *results = ctx->ws->buffer_map(buffer->buf, NULL,
431 PIPE_TRANSFER_WRITE |
432 PIPE_TRANSFER_UNSYNCHRONIZED);
433 if (!results)
434 return false;
435
436 memset(results, 0, buffer->b.b.width0);
437
438 if (query->b.type == PIPE_QUERY_OCCLUSION_COUNTER ||
439 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE) {
440 unsigned max_rbs = ctx->screen->info.num_render_backends;
441 unsigned enabled_rb_mask = ctx->screen->info.enabled_rb_mask;
442 unsigned num_results;
443 unsigned i, j;
444
445 /* Set top bits for unused backends. */
446 num_results = buffer->b.b.width0 / query->result_size;
447 for (j = 0; j < num_results; j++) {
448 for (i = 0; i < max_rbs; i++) {
449 if (!(enabled_rb_mask & (1<<i))) {
450 results[(i * 4)+1] = 0x80000000;
451 results[(i * 4)+3] = 0x80000000;
452 }
453 }
454 results += 4 * max_rbs;
455 }
456 }
457
458 return true;
459 }
460
461 static void r600_query_hw_get_result_resource(struct r600_common_context *rctx,
462 struct r600_query *rquery,
463 bool wait,
464 enum pipe_query_value_type result_type,
465 int index,
466 struct pipe_resource *resource,
467 unsigned offset);
468
469 static struct r600_query_ops query_hw_ops = {
470 .destroy = r600_query_hw_destroy,
471 .begin = r600_query_hw_begin,
472 .end = r600_query_hw_end,
473 .get_result = r600_query_hw_get_result,
474 .get_result_resource = r600_query_hw_get_result_resource,
475 };
476
477 static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
478 struct r600_query_hw *query,
479 struct r600_resource *buffer,
480 uint64_t va);
481 static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
482 struct r600_query_hw *query,
483 struct r600_resource *buffer,
484 uint64_t va);
485 static void r600_query_hw_add_result(struct r600_common_context *ctx,
486 struct r600_query_hw *, void *buffer,
487 union pipe_query_result *result);
488 static void r600_query_hw_clear_result(struct r600_query_hw *,
489 union pipe_query_result *);
490
491 static struct r600_query_hw_ops query_hw_default_hw_ops = {
492 .prepare_buffer = r600_query_hw_prepare_buffer,
493 .emit_start = r600_query_hw_do_emit_start,
494 .emit_stop = r600_query_hw_do_emit_stop,
495 .clear_result = r600_query_hw_clear_result,
496 .add_result = r600_query_hw_add_result,
497 };
498
499 bool r600_query_hw_init(struct r600_common_context *rctx,
500 struct r600_query_hw *query)
501 {
502 query->buffer.buf = r600_new_query_buffer(rctx, query);
503 if (!query->buffer.buf)
504 return false;
505
506 return true;
507 }
508
509 static struct pipe_query *r600_query_hw_create(struct r600_common_context *rctx,
510 unsigned query_type,
511 unsigned index)
512 {
513 struct r600_query_hw *query = CALLOC_STRUCT(r600_query_hw);
514 if (!query)
515 return NULL;
516
517 query->b.type = query_type;
518 query->b.ops = &query_hw_ops;
519 query->ops = &query_hw_default_hw_ops;
520
521 switch (query_type) {
522 case PIPE_QUERY_OCCLUSION_COUNTER:
523 case PIPE_QUERY_OCCLUSION_PREDICATE:
524 query->result_size = 16 * rctx->screen->info.num_render_backends;
525 query->result_size += 16; /* for the fence + alignment */
526 query->num_cs_dw_begin = 6;
527 query->num_cs_dw_end = 6 + r600_gfx_write_fence_dwords(rctx->screen);
528 break;
529 case PIPE_QUERY_TIME_ELAPSED:
530 query->result_size = 24;
531 query->num_cs_dw_begin = 8;
532 query->num_cs_dw_end = 8 + r600_gfx_write_fence_dwords(rctx->screen);
533 break;
534 case PIPE_QUERY_TIMESTAMP:
535 query->result_size = 16;
536 query->num_cs_dw_end = 8 + r600_gfx_write_fence_dwords(rctx->screen);
537 query->flags = R600_QUERY_HW_FLAG_NO_START;
538 break;
539 case PIPE_QUERY_PRIMITIVES_EMITTED:
540 case PIPE_QUERY_PRIMITIVES_GENERATED:
541 case PIPE_QUERY_SO_STATISTICS:
542 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
543 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
544 query->result_size = 32;
545 query->num_cs_dw_begin = 6;
546 query->num_cs_dw_end = 6;
547 query->stream = index;
548 break;
549 case PIPE_QUERY_PIPELINE_STATISTICS:
550 /* 11 values on EG, 8 on R600. */
551 query->result_size = (rctx->chip_class >= EVERGREEN ? 11 : 8) * 16;
552 query->result_size += 8; /* for the fence + alignment */
553 query->num_cs_dw_begin = 6;
554 query->num_cs_dw_end = 6 + r600_gfx_write_fence_dwords(rctx->screen);
555 break;
556 default:
557 assert(0);
558 FREE(query);
559 return NULL;
560 }
561
562 if (!r600_query_hw_init(rctx, query)) {
563 FREE(query);
564 return NULL;
565 }
566
567 return (struct pipe_query *)query;
568 }
569
570 static void r600_update_occlusion_query_state(struct r600_common_context *rctx,
571 unsigned type, int diff)
572 {
573 if (type == PIPE_QUERY_OCCLUSION_COUNTER ||
574 type == PIPE_QUERY_OCCLUSION_PREDICATE) {
575 bool old_enable = rctx->num_occlusion_queries != 0;
576 bool old_perfect_enable =
577 rctx->num_perfect_occlusion_queries != 0;
578 bool enable, perfect_enable;
579
580 rctx->num_occlusion_queries += diff;
581 assert(rctx->num_occlusion_queries >= 0);
582
583 if (type == PIPE_QUERY_OCCLUSION_COUNTER) {
584 rctx->num_perfect_occlusion_queries += diff;
585 assert(rctx->num_perfect_occlusion_queries >= 0);
586 }
587
588 enable = rctx->num_occlusion_queries != 0;
589 perfect_enable = rctx->num_perfect_occlusion_queries != 0;
590
591 if (enable != old_enable || perfect_enable != old_perfect_enable) {
592 rctx->set_occlusion_query_state(&rctx->b, enable);
593 }
594 }
595 }
596
597 static unsigned event_type_for_stream(struct r600_query_hw *query)
598 {
599 switch (query->stream) {
600 default:
601 case 0: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS;
602 case 1: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS1;
603 case 2: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS2;
604 case 3: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS3;
605 }
606 }
607
608 static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
609 struct r600_query_hw *query,
610 struct r600_resource *buffer,
611 uint64_t va)
612 {
613 struct radeon_winsys_cs *cs = ctx->gfx.cs;
614
615 switch (query->b.type) {
616 case PIPE_QUERY_OCCLUSION_COUNTER:
617 case PIPE_QUERY_OCCLUSION_PREDICATE:
618 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
619 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
620 radeon_emit(cs, va);
621 radeon_emit(cs, (va >> 32) & 0xFFFF);
622 break;
623 case PIPE_QUERY_PRIMITIVES_EMITTED:
624 case PIPE_QUERY_PRIMITIVES_GENERATED:
625 case PIPE_QUERY_SO_STATISTICS:
626 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
627 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
628 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | EVENT_INDEX(3));
629 radeon_emit(cs, va);
630 radeon_emit(cs, (va >> 32) & 0xFFFF);
631 break;
632 case PIPE_QUERY_TIME_ELAPSED:
633 r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
634 0, 3, NULL, va, 0, 0);
635 break;
636 case PIPE_QUERY_PIPELINE_STATISTICS:
637 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
638 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
639 radeon_emit(cs, va);
640 radeon_emit(cs, (va >> 32) & 0xFFFF);
641 break;
642 default:
643 assert(0);
644 }
645 r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE,
646 RADEON_PRIO_QUERY);
647 }
648
649 static void r600_query_hw_emit_start(struct r600_common_context *ctx,
650 struct r600_query_hw *query)
651 {
652 uint64_t va;
653
654 if (!query->buffer.buf)
655 return; // previous buffer allocation failure
656
657 r600_update_occlusion_query_state(ctx, query->b.type, 1);
658 r600_update_prims_generated_query_state(ctx, query->b.type, 1);
659
660 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw_begin + query->num_cs_dw_end,
661 true);
662
663 /* Get a new query buffer if needed. */
664 if (query->buffer.results_end + query->result_size > query->buffer.buf->b.b.width0) {
665 struct r600_query_buffer *qbuf = MALLOC_STRUCT(r600_query_buffer);
666 *qbuf = query->buffer;
667 query->buffer.results_end = 0;
668 query->buffer.previous = qbuf;
669 query->buffer.buf = r600_new_query_buffer(ctx, query);
670 if (!query->buffer.buf)
671 return;
672 }
673
674 /* emit begin query */
675 va = query->buffer.buf->gpu_address + query->buffer.results_end;
676
677 query->ops->emit_start(ctx, query, query->buffer.buf, va);
678
679 ctx->num_cs_dw_queries_suspend += query->num_cs_dw_end;
680 }
681
682 static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
683 struct r600_query_hw *query,
684 struct r600_resource *buffer,
685 uint64_t va)
686 {
687 struct radeon_winsys_cs *cs = ctx->gfx.cs;
688 uint64_t fence_va = 0;
689
690 switch (query->b.type) {
691 case PIPE_QUERY_OCCLUSION_COUNTER:
692 case PIPE_QUERY_OCCLUSION_PREDICATE:
693 va += 8;
694 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
695 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
696 radeon_emit(cs, va);
697 radeon_emit(cs, (va >> 32) & 0xFFFF);
698
699 fence_va = va + ctx->screen->info.num_render_backends * 16 - 8;
700 break;
701 case PIPE_QUERY_PRIMITIVES_EMITTED:
702 case PIPE_QUERY_PRIMITIVES_GENERATED:
703 case PIPE_QUERY_SO_STATISTICS:
704 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
705 va += query->result_size/2;
706 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
707 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | EVENT_INDEX(3));
708 radeon_emit(cs, va);
709 radeon_emit(cs, (va >> 32) & 0xFFFF);
710 break;
711 case PIPE_QUERY_TIME_ELAPSED:
712 va += 8;
713 /* fall through */
714 case PIPE_QUERY_TIMESTAMP:
715 r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
716 0, 3, NULL, va, 0, 0);
717 fence_va = va + 8;
718 break;
719 case PIPE_QUERY_PIPELINE_STATISTICS: {
720 unsigned sample_size = (query->result_size - 8) / 2;
721
722 va += sample_size;
723 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
724 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
725 radeon_emit(cs, va);
726 radeon_emit(cs, (va >> 32) & 0xFFFF);
727
728 fence_va = va + sample_size;
729 break;
730 }
731 default:
732 assert(0);
733 }
734 r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE,
735 RADEON_PRIO_QUERY);
736
737 if (fence_va)
738 r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0, 1,
739 query->buffer.buf, fence_va, 0, 0x80000000);
740 }
741
742 static void r600_query_hw_emit_stop(struct r600_common_context *ctx,
743 struct r600_query_hw *query)
744 {
745 uint64_t va;
746
747 if (!query->buffer.buf)
748 return; // previous buffer allocation failure
749
750 /* The queries which need begin already called this in begin_query. */
751 if (query->flags & R600_QUERY_HW_FLAG_NO_START) {
752 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw_end, false);
753 }
754
755 /* emit end query */
756 va = query->buffer.buf->gpu_address + query->buffer.results_end;
757
758 query->ops->emit_stop(ctx, query, query->buffer.buf, va);
759
760 query->buffer.results_end += query->result_size;
761
762 if (!(query->flags & R600_QUERY_HW_FLAG_NO_START))
763 ctx->num_cs_dw_queries_suspend -= query->num_cs_dw_end;
764
765 r600_update_occlusion_query_state(ctx, query->b.type, -1);
766 r600_update_prims_generated_query_state(ctx, query->b.type, -1);
767 }
768
769 static void r600_emit_query_predication(struct r600_common_context *ctx,
770 struct r600_atom *atom)
771 {
772 struct radeon_winsys_cs *cs = ctx->gfx.cs;
773 struct r600_query_hw *query = (struct r600_query_hw *)ctx->render_cond;
774 struct r600_query_buffer *qbuf;
775 uint32_t op;
776 bool flag_wait;
777
778 if (!query)
779 return;
780
781 flag_wait = ctx->render_cond_mode == PIPE_RENDER_COND_WAIT ||
782 ctx->render_cond_mode == PIPE_RENDER_COND_BY_REGION_WAIT;
783
784 switch (query->b.type) {
785 case PIPE_QUERY_OCCLUSION_COUNTER:
786 case PIPE_QUERY_OCCLUSION_PREDICATE:
787 op = PRED_OP(PREDICATION_OP_ZPASS);
788 break;
789 case PIPE_QUERY_PRIMITIVES_EMITTED:
790 case PIPE_QUERY_PRIMITIVES_GENERATED:
791 case PIPE_QUERY_SO_STATISTICS:
792 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
793 op = PRED_OP(PREDICATION_OP_PRIMCOUNT);
794 break;
795 default:
796 assert(0);
797 return;
798 }
799
800 /* if true then invert, see GL_ARB_conditional_render_inverted */
801 if (ctx->render_cond_invert)
802 op |= PREDICATION_DRAW_NOT_VISIBLE; /* Draw if not visable/overflow */
803 else
804 op |= PREDICATION_DRAW_VISIBLE; /* Draw if visable/overflow */
805
806 op |= flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW;
807
808 /* emit predicate packets for all data blocks */
809 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
810 unsigned results_base = 0;
811 uint64_t va = qbuf->buf->gpu_address;
812
813 while (results_base < qbuf->results_end) {
814 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
815 radeon_emit(cs, va + results_base);
816 radeon_emit(cs, op | (((va + results_base) >> 32) & 0xFF));
817 r600_emit_reloc(ctx, &ctx->gfx, qbuf->buf, RADEON_USAGE_READ,
818 RADEON_PRIO_QUERY);
819 results_base += query->result_size;
820
821 /* set CONTINUE bit for all packets except the first */
822 op |= PREDICATION_CONTINUE;
823 }
824 }
825 }
826
827 static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type, unsigned index)
828 {
829 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
830
831 if (query_type == PIPE_QUERY_TIMESTAMP_DISJOINT ||
832 query_type == PIPE_QUERY_GPU_FINISHED ||
833 query_type >= PIPE_QUERY_DRIVER_SPECIFIC)
834 return r600_query_sw_create(ctx, query_type);
835
836 return r600_query_hw_create(rctx, query_type, index);
837 }
838
839 static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
840 {
841 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
842 struct r600_query *rquery = (struct r600_query *)query;
843
844 rquery->ops->destroy(rctx, rquery);
845 }
846
847 static boolean r600_begin_query(struct pipe_context *ctx,
848 struct pipe_query *query)
849 {
850 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
851 struct r600_query *rquery = (struct r600_query *)query;
852
853 return rquery->ops->begin(rctx, rquery);
854 }
855
856 void r600_query_hw_reset_buffers(struct r600_common_context *rctx,
857 struct r600_query_hw *query)
858 {
859 struct r600_query_buffer *prev = query->buffer.previous;
860
861 /* Discard the old query buffers. */
862 while (prev) {
863 struct r600_query_buffer *qbuf = prev;
864 prev = prev->previous;
865 r600_resource_reference(&qbuf->buf, NULL);
866 FREE(qbuf);
867 }
868
869 query->buffer.results_end = 0;
870 query->buffer.previous = NULL;
871
872 /* Obtain a new buffer if the current one can't be mapped without a stall. */
873 if (r600_rings_is_buffer_referenced(rctx, query->buffer.buf->buf, RADEON_USAGE_READWRITE) ||
874 !rctx->ws->buffer_wait(query->buffer.buf->buf, 0, RADEON_USAGE_READWRITE)) {
875 r600_resource_reference(&query->buffer.buf, NULL);
876 query->buffer.buf = r600_new_query_buffer(rctx, query);
877 } else {
878 if (!query->ops->prepare_buffer(rctx, query, query->buffer.buf))
879 r600_resource_reference(&query->buffer.buf, NULL);
880 }
881 }
882
883 bool r600_query_hw_begin(struct r600_common_context *rctx,
884 struct r600_query *rquery)
885 {
886 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
887
888 if (query->flags & R600_QUERY_HW_FLAG_NO_START) {
889 assert(0);
890 return false;
891 }
892
893 if (!(query->flags & R600_QUERY_HW_FLAG_BEGIN_RESUMES))
894 r600_query_hw_reset_buffers(rctx, query);
895
896 r600_query_hw_emit_start(rctx, query);
897 if (!query->buffer.buf)
898 return false;
899
900 LIST_ADDTAIL(&query->list, &rctx->active_queries);
901 return true;
902 }
903
904 static bool r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
905 {
906 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
907 struct r600_query *rquery = (struct r600_query *)query;
908
909 return rquery->ops->end(rctx, rquery);
910 }
911
912 bool r600_query_hw_end(struct r600_common_context *rctx,
913 struct r600_query *rquery)
914 {
915 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
916
917 if (query->flags & R600_QUERY_HW_FLAG_NO_START)
918 r600_query_hw_reset_buffers(rctx, query);
919
920 r600_query_hw_emit_stop(rctx, query);
921
922 if (!(query->flags & R600_QUERY_HW_FLAG_NO_START))
923 LIST_DELINIT(&query->list);
924
925 if (!query->buffer.buf)
926 return false;
927
928 return true;
929 }
930
931 static void r600_get_hw_query_params(struct r600_common_context *rctx,
932 struct r600_query_hw *rquery, int index,
933 struct r600_hw_query_params *params)
934 {
935 unsigned max_rbs = rctx->screen->info.num_render_backends;
936
937 params->pair_stride = 0;
938 params->pair_count = 1;
939
940 switch (rquery->b.type) {
941 case PIPE_QUERY_OCCLUSION_COUNTER:
942 case PIPE_QUERY_OCCLUSION_PREDICATE:
943 params->start_offset = 0;
944 params->end_offset = 8;
945 params->fence_offset = max_rbs * 16;
946 params->pair_stride = 16;
947 params->pair_count = max_rbs;
948 break;
949 case PIPE_QUERY_TIME_ELAPSED:
950 params->start_offset = 0;
951 params->end_offset = 8;
952 params->fence_offset = 16;
953 break;
954 case PIPE_QUERY_TIMESTAMP:
955 params->start_offset = 0;
956 params->end_offset = 0;
957 params->fence_offset = 8;
958 break;
959 case PIPE_QUERY_PRIMITIVES_EMITTED:
960 params->start_offset = 8;
961 params->end_offset = 24;
962 params->fence_offset = params->end_offset + 4;
963 break;
964 case PIPE_QUERY_PRIMITIVES_GENERATED:
965 params->start_offset = 0;
966 params->end_offset = 16;
967 params->fence_offset = params->end_offset + 4;
968 break;
969 case PIPE_QUERY_SO_STATISTICS:
970 params->start_offset = 8 - index * 8;
971 params->end_offset = 24 - index * 8;
972 params->fence_offset = params->end_offset + 4;
973 break;
974 case PIPE_QUERY_PIPELINE_STATISTICS:
975 {
976 /* Offsets apply to EG+ */
977 static const unsigned offsets[] = {56, 48, 24, 32, 40, 16, 8, 0, 64, 72, 80};
978 params->start_offset = offsets[index];
979 params->end_offset = 88 + offsets[index];
980 params->fence_offset = 2 * 88;
981 break;
982 }
983 default:
984 unreachable("r600_get_hw_query_params unsupported");
985 }
986 }
987
988 static unsigned r600_query_read_result(void *map, unsigned start_index, unsigned end_index,
989 bool test_status_bit)
990 {
991 uint32_t *current_result = (uint32_t*)map;
992 uint64_t start, end;
993
994 start = (uint64_t)current_result[start_index] |
995 (uint64_t)current_result[start_index+1] << 32;
996 end = (uint64_t)current_result[end_index] |
997 (uint64_t)current_result[end_index+1] << 32;
998
999 if (!test_status_bit ||
1000 ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) {
1001 return end - start;
1002 }
1003 return 0;
1004 }
1005
1006 static void r600_query_hw_add_result(struct r600_common_context *ctx,
1007 struct r600_query_hw *query,
1008 void *buffer,
1009 union pipe_query_result *result)
1010 {
1011 unsigned max_rbs = ctx->screen->info.num_render_backends;
1012
1013 switch (query->b.type) {
1014 case PIPE_QUERY_OCCLUSION_COUNTER: {
1015 for (unsigned i = 0; i < max_rbs; ++i) {
1016 unsigned results_base = i * 16;
1017 result->u64 +=
1018 r600_query_read_result(buffer + results_base, 0, 2, true);
1019 }
1020 break;
1021 }
1022 case PIPE_QUERY_OCCLUSION_PREDICATE: {
1023 for (unsigned i = 0; i < max_rbs; ++i) {
1024 unsigned results_base = i * 16;
1025 result->b = result->b ||
1026 r600_query_read_result(buffer + results_base, 0, 2, true) != 0;
1027 }
1028 break;
1029 }
1030 case PIPE_QUERY_TIME_ELAPSED:
1031 result->u64 += r600_query_read_result(buffer, 0, 2, false);
1032 break;
1033 case PIPE_QUERY_TIMESTAMP:
1034 result->u64 = *(uint64_t*)buffer;
1035 break;
1036 case PIPE_QUERY_PRIMITIVES_EMITTED:
1037 /* SAMPLE_STREAMOUTSTATS stores this structure:
1038 * {
1039 * u64 NumPrimitivesWritten;
1040 * u64 PrimitiveStorageNeeded;
1041 * }
1042 * We only need NumPrimitivesWritten here. */
1043 result->u64 += r600_query_read_result(buffer, 2, 6, true);
1044 break;
1045 case PIPE_QUERY_PRIMITIVES_GENERATED:
1046 /* Here we read PrimitiveStorageNeeded. */
1047 result->u64 += r600_query_read_result(buffer, 0, 4, true);
1048 break;
1049 case PIPE_QUERY_SO_STATISTICS:
1050 result->so_statistics.num_primitives_written +=
1051 r600_query_read_result(buffer, 2, 6, true);
1052 result->so_statistics.primitives_storage_needed +=
1053 r600_query_read_result(buffer, 0, 4, true);
1054 break;
1055 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1056 result->b = result->b ||
1057 r600_query_read_result(buffer, 2, 6, true) !=
1058 r600_query_read_result(buffer, 0, 4, true);
1059 break;
1060 case PIPE_QUERY_PIPELINE_STATISTICS:
1061 if (ctx->chip_class >= EVERGREEN) {
1062 result->pipeline_statistics.ps_invocations +=
1063 r600_query_read_result(buffer, 0, 22, false);
1064 result->pipeline_statistics.c_primitives +=
1065 r600_query_read_result(buffer, 2, 24, false);
1066 result->pipeline_statistics.c_invocations +=
1067 r600_query_read_result(buffer, 4, 26, false);
1068 result->pipeline_statistics.vs_invocations +=
1069 r600_query_read_result(buffer, 6, 28, false);
1070 result->pipeline_statistics.gs_invocations +=
1071 r600_query_read_result(buffer, 8, 30, false);
1072 result->pipeline_statistics.gs_primitives +=
1073 r600_query_read_result(buffer, 10, 32, false);
1074 result->pipeline_statistics.ia_primitives +=
1075 r600_query_read_result(buffer, 12, 34, false);
1076 result->pipeline_statistics.ia_vertices +=
1077 r600_query_read_result(buffer, 14, 36, false);
1078 result->pipeline_statistics.hs_invocations +=
1079 r600_query_read_result(buffer, 16, 38, false);
1080 result->pipeline_statistics.ds_invocations +=
1081 r600_query_read_result(buffer, 18, 40, false);
1082 result->pipeline_statistics.cs_invocations +=
1083 r600_query_read_result(buffer, 20, 42, false);
1084 } else {
1085 result->pipeline_statistics.ps_invocations +=
1086 r600_query_read_result(buffer, 0, 16, false);
1087 result->pipeline_statistics.c_primitives +=
1088 r600_query_read_result(buffer, 2, 18, false);
1089 result->pipeline_statistics.c_invocations +=
1090 r600_query_read_result(buffer, 4, 20, false);
1091 result->pipeline_statistics.vs_invocations +=
1092 r600_query_read_result(buffer, 6, 22, false);
1093 result->pipeline_statistics.gs_invocations +=
1094 r600_query_read_result(buffer, 8, 24, false);
1095 result->pipeline_statistics.gs_primitives +=
1096 r600_query_read_result(buffer, 10, 26, false);
1097 result->pipeline_statistics.ia_primitives +=
1098 r600_query_read_result(buffer, 12, 28, false);
1099 result->pipeline_statistics.ia_vertices +=
1100 r600_query_read_result(buffer, 14, 30, false);
1101 }
1102 #if 0 /* for testing */
1103 printf("Pipeline stats: IA verts=%llu, IA prims=%llu, VS=%llu, HS=%llu, "
1104 "DS=%llu, GS=%llu, GS prims=%llu, Clipper=%llu, "
1105 "Clipper prims=%llu, PS=%llu, CS=%llu\n",
1106 result->pipeline_statistics.ia_vertices,
1107 result->pipeline_statistics.ia_primitives,
1108 result->pipeline_statistics.vs_invocations,
1109 result->pipeline_statistics.hs_invocations,
1110 result->pipeline_statistics.ds_invocations,
1111 result->pipeline_statistics.gs_invocations,
1112 result->pipeline_statistics.gs_primitives,
1113 result->pipeline_statistics.c_invocations,
1114 result->pipeline_statistics.c_primitives,
1115 result->pipeline_statistics.ps_invocations,
1116 result->pipeline_statistics.cs_invocations);
1117 #endif
1118 break;
1119 default:
1120 assert(0);
1121 }
1122 }
1123
1124 static boolean r600_get_query_result(struct pipe_context *ctx,
1125 struct pipe_query *query, boolean wait,
1126 union pipe_query_result *result)
1127 {
1128 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1129 struct r600_query *rquery = (struct r600_query *)query;
1130
1131 return rquery->ops->get_result(rctx, rquery, wait, result);
1132 }
1133
1134 static void r600_get_query_result_resource(struct pipe_context *ctx,
1135 struct pipe_query *query,
1136 boolean wait,
1137 enum pipe_query_value_type result_type,
1138 int index,
1139 struct pipe_resource *resource,
1140 unsigned offset)
1141 {
1142 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1143 struct r600_query *rquery = (struct r600_query *)query;
1144
1145 rquery->ops->get_result_resource(rctx, rquery, wait, result_type, index,
1146 resource, offset);
1147 }
1148
1149 static void r600_query_hw_clear_result(struct r600_query_hw *query,
1150 union pipe_query_result *result)
1151 {
1152 util_query_clear_result(result, query->b.type);
1153 }
1154
1155 bool r600_query_hw_get_result(struct r600_common_context *rctx,
1156 struct r600_query *rquery,
1157 bool wait, union pipe_query_result *result)
1158 {
1159 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
1160 struct r600_query_buffer *qbuf;
1161
1162 query->ops->clear_result(query, result);
1163
1164 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
1165 unsigned results_base = 0;
1166 void *map;
1167
1168 map = r600_buffer_map_sync_with_rings(rctx, qbuf->buf,
1169 PIPE_TRANSFER_READ |
1170 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK));
1171 if (!map)
1172 return false;
1173
1174 while (results_base != qbuf->results_end) {
1175 query->ops->add_result(rctx, query, map + results_base,
1176 result);
1177 results_base += query->result_size;
1178 }
1179 }
1180
1181 /* Convert the time to expected units. */
1182 if (rquery->type == PIPE_QUERY_TIME_ELAPSED ||
1183 rquery->type == PIPE_QUERY_TIMESTAMP) {
1184 result->u64 = (1000000 * result->u64) / rctx->screen->info.clock_crystal_freq;
1185 }
1186 return true;
1187 }
1188
1189 /* Create the compute shader that is used to collect the results.
1190 *
1191 * One compute grid with a single thread is launched for every query result
1192 * buffer. The thread (optionally) reads a previous summary buffer, then
1193 * accumulates data from the query result buffer, and writes the result either
1194 * to a summary buffer to be consumed by the next grid invocation or to the
1195 * user-supplied buffer.
1196 *
1197 * Data layout:
1198 *
1199 * CONST
1200 * 0.x = end_offset
1201 * 0.y = result_stride
1202 * 0.z = result_count
1203 * 0.w = bit field:
1204 * 1: read previously accumulated values
1205 * 2: write accumulated values for chaining
1206 * 4: write result available
1207 * 8: convert result to boolean (0/1)
1208 * 16: only read one dword and use that as result
1209 * 32: apply timestamp conversion
1210 * 64: store full 64 bits result
1211 * 128: store signed 32 bits result
1212 * 1.x = fence_offset
1213 * 1.y = pair_stride
1214 * 1.z = pair_count
1215 *
1216 * BUFFER[0] = query result buffer
1217 * BUFFER[1] = previous summary buffer
1218 * BUFFER[2] = next summary buffer or user-supplied buffer
1219 */
1220 static void r600_create_query_result_shader(struct r600_common_context *rctx)
1221 {
1222 /* TEMP[0].xy = accumulated result so far
1223 * TEMP[0].z = result not available
1224 *
1225 * TEMP[1].x = current result index
1226 * TEMP[1].y = current pair index
1227 */
1228 static const char text_tmpl[] =
1229 "COMP\n"
1230 "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
1231 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
1232 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
1233 "DCL BUFFER[0]\n"
1234 "DCL BUFFER[1]\n"
1235 "DCL BUFFER[2]\n"
1236 "DCL CONST[0..1]\n"
1237 "DCL TEMP[0..5]\n"
1238 "IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n"
1239 "IMM[1] UINT32 {1, 2, 4, 8}\n"
1240 "IMM[2] UINT32 {16, 32, 64, 128}\n"
1241 "IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */
1242
1243 "AND TEMP[5], CONST[0].wwww, IMM[2].xxxx\n"
1244 "UIF TEMP[5]\n"
1245 /* Check result availability. */
1246 "LOAD TEMP[1].x, BUFFER[0], CONST[1].xxxx\n"
1247 "ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n"
1248 "MOV TEMP[1], TEMP[0].zzzz\n"
1249 "NOT TEMP[0].z, TEMP[0].zzzz\n"
1250
1251 /* Load result if available. */
1252 "UIF TEMP[1]\n"
1253 "LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n"
1254 "ENDIF\n"
1255 "ELSE\n"
1256 /* Load previously accumulated result if requested. */
1257 "MOV TEMP[0], IMM[0].xxxx\n"
1258 "AND TEMP[4], CONST[0].wwww, IMM[1].xxxx\n"
1259 "UIF TEMP[4]\n"
1260 "LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n"
1261 "ENDIF\n"
1262
1263 "MOV TEMP[1].x, IMM[0].xxxx\n"
1264 "BGNLOOP\n"
1265 /* Break if accumulated result so far is not available. */
1266 "UIF TEMP[0].zzzz\n"
1267 "BRK\n"
1268 "ENDIF\n"
1269
1270 /* Break if result_index >= result_count. */
1271 "USGE TEMP[5], TEMP[1].xxxx, CONST[0].zzzz\n"
1272 "UIF TEMP[5]\n"
1273 "BRK\n"
1274 "ENDIF\n"
1275
1276 /* Load fence and check result availability */
1277 "UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0].yyyy, CONST[1].xxxx\n"
1278 "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
1279 "ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n"
1280 "NOT TEMP[0].z, TEMP[0].zzzz\n"
1281 "UIF TEMP[0].zzzz\n"
1282 "BRK\n"
1283 "ENDIF\n"
1284
1285 "MOV TEMP[1].y, IMM[0].xxxx\n"
1286 "BGNLOOP\n"
1287 /* Load start and end. */
1288 "UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0].yyyy\n"
1289 "UMAD TEMP[5].x, TEMP[1].yyyy, CONST[1].yyyy, TEMP[5].xxxx\n"
1290 "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
1291
1292 "UADD TEMP[5].x, TEMP[5].xxxx, CONST[0].xxxx\n"
1293 "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].xxxx\n"
1294
1295 "U64ADD TEMP[3].xy, TEMP[3], -TEMP[2]\n"
1296 "U64ADD TEMP[0].xy, TEMP[0], TEMP[3]\n"
1297
1298 /* Increment pair index */
1299 "UADD TEMP[1].y, TEMP[1].yyyy, IMM[1].xxxx\n"
1300 "USGE TEMP[5], TEMP[1].yyyy, CONST[1].zzzz\n"
1301 "UIF TEMP[5]\n"
1302 "BRK\n"
1303 "ENDIF\n"
1304 "ENDLOOP\n"
1305
1306 /* Increment result index */
1307 "UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n"
1308 "ENDLOOP\n"
1309 "ENDIF\n"
1310
1311 "AND TEMP[4], CONST[0].wwww, IMM[1].yyyy\n"
1312 "UIF TEMP[4]\n"
1313 /* Store accumulated data for chaining. */
1314 "STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n"
1315 "ELSE\n"
1316 "AND TEMP[4], CONST[0].wwww, IMM[1].zzzz\n"
1317 "UIF TEMP[4]\n"
1318 /* Store result availability. */
1319 "NOT TEMP[0].z, TEMP[0]\n"
1320 "AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n"
1321 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n"
1322
1323 "AND TEMP[4], CONST[0].wwww, IMM[2].zzzz\n"
1324 "UIF TEMP[4]\n"
1325 "STORE BUFFER[2].y, IMM[0].xxxx, IMM[0].xxxx\n"
1326 "ENDIF\n"
1327 "ELSE\n"
1328 /* Store result if it is available. */
1329 "NOT TEMP[4], TEMP[0].zzzz\n"
1330 "UIF TEMP[4]\n"
1331 /* Apply timestamp conversion */
1332 "AND TEMP[4], CONST[0].wwww, IMM[2].yyyy\n"
1333 "UIF TEMP[4]\n"
1334 "U64MUL TEMP[0].xy, TEMP[0], IMM[3].xyxy\n"
1335 "U64DIV TEMP[0].xy, TEMP[0], IMM[3].zwzw\n"
1336 "ENDIF\n"
1337
1338 /* Convert to boolean */
1339 "AND TEMP[4], CONST[0].wwww, IMM[1].wwww\n"
1340 "UIF TEMP[4]\n"
1341 "U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[0].xxxx\n"
1342 "AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n"
1343 "MOV TEMP[0].y, IMM[0].xxxx\n"
1344 "ENDIF\n"
1345
1346 "AND TEMP[4], CONST[0].wwww, IMM[2].zzzz\n"
1347 "UIF TEMP[4]\n"
1348 "STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0].xyxy\n"
1349 "ELSE\n"
1350 /* Clamping */
1351 "UIF TEMP[0].yyyy\n"
1352 "MOV TEMP[0].x, IMM[0].wwww\n"
1353 "ENDIF\n"
1354
1355 "AND TEMP[4], CONST[0].wwww, IMM[2].wwww\n"
1356 "UIF TEMP[4]\n"
1357 "UMIN TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz\n"
1358 "ENDIF\n"
1359
1360 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n"
1361 "ENDIF\n"
1362 "ENDIF\n"
1363 "ENDIF\n"
1364 "ENDIF\n"
1365
1366 "END\n";
1367
1368 char text[sizeof(text_tmpl) + 32];
1369 struct tgsi_token tokens[1024];
1370 struct pipe_compute_state state = {};
1371
1372 /* Hard code the frequency into the shader so that the backend can
1373 * use the full range of optimizations for divide-by-constant.
1374 */
1375 snprintf(text, sizeof(text), text_tmpl,
1376 rctx->screen->info.clock_crystal_freq);
1377
1378 if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
1379 assert(false);
1380 return;
1381 }
1382
1383 state.ir_type = PIPE_SHADER_IR_TGSI;
1384 state.prog = tokens;
1385
1386 rctx->query_result_shader = rctx->b.create_compute_state(&rctx->b, &state);
1387 }
1388
1389 static void r600_restore_qbo_state(struct r600_common_context *rctx,
1390 struct r600_qbo_state *st)
1391 {
1392 rctx->b.bind_compute_state(&rctx->b, st->saved_compute);
1393
1394 rctx->b.set_constant_buffer(&rctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1395 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1396
1397 rctx->b.set_shader_buffers(&rctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1398 for (unsigned i = 0; i < 3; ++i)
1399 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1400 }
1401
1402 static void r600_query_hw_get_result_resource(struct r600_common_context *rctx,
1403 struct r600_query *rquery,
1404 bool wait,
1405 enum pipe_query_value_type result_type,
1406 int index,
1407 struct pipe_resource *resource,
1408 unsigned offset)
1409 {
1410 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
1411 struct r600_query_buffer *qbuf;
1412 struct r600_query_buffer *qbuf_prev;
1413 struct pipe_resource *tmp_buffer = NULL;
1414 unsigned tmp_buffer_offset = 0;
1415 struct r600_qbo_state saved_state = {};
1416 struct pipe_grid_info grid = {};
1417 struct pipe_constant_buffer constant_buffer = {};
1418 struct pipe_shader_buffer ssbo[3];
1419 struct r600_hw_query_params params;
1420 struct {
1421 uint32_t end_offset;
1422 uint32_t result_stride;
1423 uint32_t result_count;
1424 uint32_t config;
1425 uint32_t fence_offset;
1426 uint32_t pair_stride;
1427 uint32_t pair_count;
1428 } consts;
1429
1430 if (!rctx->query_result_shader) {
1431 r600_create_query_result_shader(rctx);
1432 if (!rctx->query_result_shader)
1433 return;
1434 }
1435
1436 if (query->buffer.previous) {
1437 u_suballocator_alloc(rctx->allocator_zeroed_memory, 16, 16,
1438 &tmp_buffer_offset, &tmp_buffer);
1439 if (!tmp_buffer)
1440 return;
1441 }
1442
1443 rctx->save_qbo_state(&rctx->b, &saved_state);
1444
1445 r600_get_hw_query_params(rctx, query, index >= 0 ? index : 0, &params);
1446 consts.end_offset = params.end_offset - params.start_offset;
1447 consts.fence_offset = params.fence_offset - params.start_offset;
1448 consts.result_stride = query->result_size;
1449 consts.pair_stride = params.pair_stride;
1450 consts.pair_count = params.pair_count;
1451
1452 constant_buffer.buffer_size = sizeof(consts);
1453 constant_buffer.user_buffer = &consts;
1454
1455 ssbo[1].buffer = tmp_buffer;
1456 ssbo[1].buffer_offset = tmp_buffer_offset;
1457 ssbo[1].buffer_size = 16;
1458
1459 ssbo[2] = ssbo[1];
1460
1461 rctx->b.bind_compute_state(&rctx->b, rctx->query_result_shader);
1462
1463 grid.block[0] = 1;
1464 grid.block[1] = 1;
1465 grid.block[2] = 1;
1466 grid.grid[0] = 1;
1467 grid.grid[1] = 1;
1468 grid.grid[2] = 1;
1469
1470 consts.config = 0;
1471 if (index < 0)
1472 consts.config |= 4;
1473 if (query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE ||
1474 query->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE)
1475 consts.config |= 8;
1476 else if (query->b.type == PIPE_QUERY_TIMESTAMP ||
1477 query->b.type == PIPE_QUERY_TIME_ELAPSED)
1478 consts.config |= 32;
1479
1480 switch (result_type) {
1481 case PIPE_QUERY_TYPE_U64:
1482 case PIPE_QUERY_TYPE_I64:
1483 consts.config |= 64;
1484 break;
1485 case PIPE_QUERY_TYPE_I32:
1486 consts.config |= 128;
1487 break;
1488 case PIPE_QUERY_TYPE_U32:
1489 break;
1490 }
1491
1492 rctx->flags |= rctx->screen->barrier_flags.cp_to_L2;
1493
1494 for (qbuf = &query->buffer; qbuf; qbuf = qbuf_prev) {
1495 if (query->b.type != PIPE_QUERY_TIMESTAMP) {
1496 qbuf_prev = qbuf->previous;
1497 consts.result_count = qbuf->results_end / query->result_size;
1498 consts.config &= ~3;
1499 if (qbuf != &query->buffer)
1500 consts.config |= 1;
1501 if (qbuf->previous)
1502 consts.config |= 2;
1503 } else {
1504 /* Only read the last timestamp. */
1505 qbuf_prev = NULL;
1506 consts.result_count = 0;
1507 consts.config |= 16;
1508 params.start_offset += qbuf->results_end - query->result_size;
1509 }
1510
1511 rctx->b.set_constant_buffer(&rctx->b, PIPE_SHADER_COMPUTE, 0, &constant_buffer);
1512
1513 ssbo[0].buffer = &qbuf->buf->b.b;
1514 ssbo[0].buffer_offset = params.start_offset;
1515 ssbo[0].buffer_size = qbuf->results_end - params.start_offset;
1516
1517 if (!qbuf->previous) {
1518 ssbo[2].buffer = resource;
1519 ssbo[2].buffer_offset = offset;
1520 ssbo[2].buffer_size = 8;
1521
1522 ((struct r600_resource *)resource)->TC_L2_dirty = true;
1523 }
1524
1525 rctx->b.set_shader_buffers(&rctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo);
1526
1527 if (wait && qbuf == &query->buffer) {
1528 uint64_t va;
1529
1530 /* Wait for result availability. Wait only for readiness
1531 * of the last entry, since the fence writes should be
1532 * serialized in the CP.
1533 */
1534 va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size;
1535 va += params.fence_offset;
1536
1537 r600_gfx_wait_fence(rctx, va, 0x80000000, 0x80000000);
1538 }
1539
1540 rctx->b.launch_grid(&rctx->b, &grid);
1541 rctx->flags |= rctx->screen->barrier_flags.compute_to_L2;
1542 }
1543
1544 r600_restore_qbo_state(rctx, &saved_state);
1545 pipe_resource_reference(&tmp_buffer, NULL);
1546 }
1547
1548 static void r600_render_condition(struct pipe_context *ctx,
1549 struct pipe_query *query,
1550 boolean condition,
1551 uint mode)
1552 {
1553 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1554 struct r600_query_hw *rquery = (struct r600_query_hw *)query;
1555 struct r600_query_buffer *qbuf;
1556 struct r600_atom *atom = &rctx->render_cond_atom;
1557
1558 rctx->render_cond = query;
1559 rctx->render_cond_invert = condition;
1560 rctx->render_cond_mode = mode;
1561
1562 /* Compute the size of SET_PREDICATION packets. */
1563 atom->num_dw = 0;
1564 if (query) {
1565 for (qbuf = &rquery->buffer; qbuf; qbuf = qbuf->previous)
1566 atom->num_dw += (qbuf->results_end / rquery->result_size) * 5;
1567 }
1568
1569 rctx->set_atom_dirty(rctx, atom, query != NULL);
1570 }
1571
1572 void r600_suspend_queries(struct r600_common_context *ctx)
1573 {
1574 struct r600_query_hw *query;
1575
1576 LIST_FOR_EACH_ENTRY(query, &ctx->active_queries, list) {
1577 r600_query_hw_emit_stop(ctx, query);
1578 }
1579 assert(ctx->num_cs_dw_queries_suspend == 0);
1580 }
1581
1582 static unsigned r600_queries_num_cs_dw_for_resuming(struct r600_common_context *ctx,
1583 struct list_head *query_list)
1584 {
1585 struct r600_query_hw *query;
1586 unsigned num_dw = 0;
1587
1588 LIST_FOR_EACH_ENTRY(query, query_list, list) {
1589 /* begin + end */
1590 num_dw += query->num_cs_dw_begin + query->num_cs_dw_end;
1591
1592 /* Workaround for the fact that
1593 * num_cs_dw_nontimer_queries_suspend is incremented for every
1594 * resumed query, which raises the bar in need_cs_space for
1595 * queries about to be resumed.
1596 */
1597 num_dw += query->num_cs_dw_end;
1598 }
1599 /* primitives generated query */
1600 num_dw += ctx->streamout.enable_atom.num_dw;
1601 /* guess for ZPASS enable or PERFECT_ZPASS_COUNT enable updates */
1602 num_dw += 13;
1603
1604 return num_dw;
1605 }
1606
1607 void r600_resume_queries(struct r600_common_context *ctx)
1608 {
1609 struct r600_query_hw *query;
1610 unsigned num_cs_dw = r600_queries_num_cs_dw_for_resuming(ctx, &ctx->active_queries);
1611
1612 assert(ctx->num_cs_dw_queries_suspend == 0);
1613
1614 /* Check CS space here. Resuming must not be interrupted by flushes. */
1615 ctx->need_gfx_cs_space(&ctx->b, num_cs_dw, true);
1616
1617 LIST_FOR_EACH_ENTRY(query, &ctx->active_queries, list) {
1618 r600_query_hw_emit_start(ctx, query);
1619 }
1620 }
1621
1622 /* Fix radeon_info::enabled_rb_mask for R600, R700, EVERGREEN, NI. */
1623 void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen)
1624 {
1625 struct r600_common_context *ctx =
1626 (struct r600_common_context*)rscreen->aux_context;
1627 struct radeon_winsys_cs *cs = ctx->gfx.cs;
1628 struct r600_resource *buffer;
1629 uint32_t *results;
1630 unsigned i, mask = 0;
1631 unsigned max_rbs = ctx->screen->info.num_render_backends;
1632
1633 assert(rscreen->chip_class <= CAYMAN);
1634
1635 /* if backend_map query is supported by the kernel */
1636 if (rscreen->info.r600_gb_backend_map_valid) {
1637 unsigned num_tile_pipes = rscreen->info.num_tile_pipes;
1638 unsigned backend_map = rscreen->info.r600_gb_backend_map;
1639 unsigned item_width, item_mask;
1640
1641 if (ctx->chip_class >= EVERGREEN) {
1642 item_width = 4;
1643 item_mask = 0x7;
1644 } else {
1645 item_width = 2;
1646 item_mask = 0x3;
1647 }
1648
1649 while (num_tile_pipes--) {
1650 i = backend_map & item_mask;
1651 mask |= (1<<i);
1652 backend_map >>= item_width;
1653 }
1654 if (mask != 0) {
1655 rscreen->info.enabled_rb_mask = mask;
1656 return;
1657 }
1658 }
1659
1660 /* otherwise backup path for older kernels */
1661
1662 /* create buffer for event data */
1663 buffer = (struct r600_resource*)
1664 pipe_buffer_create(ctx->b.screen, 0,
1665 PIPE_USAGE_STAGING, max_rbs * 16);
1666 if (!buffer)
1667 return;
1668
1669 /* initialize buffer with zeroes */
1670 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE);
1671 if (results) {
1672 memset(results, 0, max_rbs * 4 * 4);
1673
1674 /* emit EVENT_WRITE for ZPASS_DONE */
1675 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1676 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
1677 radeon_emit(cs, buffer->gpu_address);
1678 radeon_emit(cs, buffer->gpu_address >> 32);
1679
1680 r600_emit_reloc(ctx, &ctx->gfx, buffer,
1681 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
1682
1683 /* analyze results */
1684 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ);
1685 if (results) {
1686 for(i = 0; i < max_rbs; i++) {
1687 /* at least highest bit will be set if backend is used */
1688 if (results[i*4 + 1])
1689 mask |= (1<<i);
1690 }
1691 }
1692 }
1693
1694 r600_resource_reference(&buffer, NULL);
1695
1696 if (mask)
1697 rscreen->info.enabled_rb_mask = mask;
1698 }
1699
1700 #define XFULL(name_, query_type_, type_, result_type_, group_id_) \
1701 { \
1702 .name = name_, \
1703 .query_type = R600_QUERY_##query_type_, \
1704 .type = PIPE_DRIVER_QUERY_TYPE_##type_, \
1705 .result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_##result_type_, \
1706 .group_id = group_id_ \
1707 }
1708
1709 #define X(name_, query_type_, type_, result_type_) \
1710 XFULL(name_, query_type_, type_, result_type_, ~(unsigned)0)
1711
1712 #define XG(group_, name_, query_type_, type_, result_type_) \
1713 XFULL(name_, query_type_, type_, result_type_, R600_QUERY_GROUP_##group_)
1714
1715 static struct pipe_driver_query_info r600_driver_query_list[] = {
1716 X("num-compilations", NUM_COMPILATIONS, UINT64, CUMULATIVE),
1717 X("num-shaders-created", NUM_SHADERS_CREATED, UINT64, CUMULATIVE),
1718 X("num-shader-cache-hits", NUM_SHADER_CACHE_HITS, UINT64, CUMULATIVE),
1719 X("draw-calls", DRAW_CALLS, UINT64, AVERAGE),
1720 X("spill-draw-calls", SPILL_DRAW_CALLS, UINT64, AVERAGE),
1721 X("compute-calls", COMPUTE_CALLS, UINT64, AVERAGE),
1722 X("spill-compute-calls", SPILL_COMPUTE_CALLS, UINT64, AVERAGE),
1723 X("dma-calls", DMA_CALLS, UINT64, AVERAGE),
1724 X("cp-dma-calls", CP_DMA_CALLS, UINT64, AVERAGE),
1725 X("num-vs-flushes", NUM_VS_FLUSHES, UINT64, AVERAGE),
1726 X("num-ps-flushes", NUM_PS_FLUSHES, UINT64, AVERAGE),
1727 X("num-cs-flushes", NUM_CS_FLUSHES, UINT64, AVERAGE),
1728 X("num-fb-cache-flushes", NUM_FB_CACHE_FLUSHES, UINT64, AVERAGE),
1729 X("num-L2-invalidates", NUM_L2_INVALIDATES, UINT64, AVERAGE),
1730 X("num-L2-writebacks", NUM_L2_WRITEBACKS, UINT64, AVERAGE),
1731 X("requested-VRAM", REQUESTED_VRAM, BYTES, AVERAGE),
1732 X("requested-GTT", REQUESTED_GTT, BYTES, AVERAGE),
1733 X("mapped-VRAM", MAPPED_VRAM, BYTES, AVERAGE),
1734 X("mapped-GTT", MAPPED_GTT, BYTES, AVERAGE),
1735 X("buffer-wait-time", BUFFER_WAIT_TIME, MICROSECONDS, CUMULATIVE),
1736 X("num-mapped-buffers", NUM_MAPPED_BUFFERS, UINT64, AVERAGE),
1737 X("num-GFX-IBs", NUM_GFX_IBS, UINT64, AVERAGE),
1738 X("num-SDMA-IBs", NUM_SDMA_IBS, UINT64, AVERAGE),
1739 X("num-bytes-moved", NUM_BYTES_MOVED, BYTES, CUMULATIVE),
1740 X("num-evictions", NUM_EVICTIONS, UINT64, CUMULATIVE),
1741 X("VRAM-usage", VRAM_USAGE, BYTES, AVERAGE),
1742 X("VRAM-vis-usage", VRAM_VIS_USAGE, BYTES, AVERAGE),
1743 X("GTT-usage", GTT_USAGE, BYTES, AVERAGE),
1744 X("back-buffer-ps-draw-ratio", BACK_BUFFER_PS_DRAW_RATIO, UINT64, AVERAGE),
1745
1746 /* GPIN queries are for the benefit of old versions of GPUPerfStudio,
1747 * which use it as a fallback path to detect the GPU type.
1748 *
1749 * Note: The names of these queries are significant for GPUPerfStudio
1750 * (and possibly their order as well). */
1751 XG(GPIN, "GPIN_000", GPIN_ASIC_ID, UINT, AVERAGE),
1752 XG(GPIN, "GPIN_001", GPIN_NUM_SIMD, UINT, AVERAGE),
1753 XG(GPIN, "GPIN_002", GPIN_NUM_RB, UINT, AVERAGE),
1754 XG(GPIN, "GPIN_003", GPIN_NUM_SPI, UINT, AVERAGE),
1755 XG(GPIN, "GPIN_004", GPIN_NUM_SE, UINT, AVERAGE),
1756
1757 /* The following queries must be at the end of the list because their
1758 * availability is adjusted dynamically based on the DRM version. */
1759 X("GPU-load", GPU_LOAD, UINT64, AVERAGE),
1760 X("GPU-shaders-busy", GPU_SHADERS_BUSY, UINT64, AVERAGE),
1761 X("GPU-ta-busy", GPU_TA_BUSY, UINT64, AVERAGE),
1762 X("GPU-gds-busy", GPU_GDS_BUSY, UINT64, AVERAGE),
1763 X("GPU-vgt-busy", GPU_VGT_BUSY, UINT64, AVERAGE),
1764 X("GPU-ia-busy", GPU_IA_BUSY, UINT64, AVERAGE),
1765 X("GPU-sx-busy", GPU_SX_BUSY, UINT64, AVERAGE),
1766 X("GPU-wd-busy", GPU_WD_BUSY, UINT64, AVERAGE),
1767 X("GPU-bci-busy", GPU_BCI_BUSY, UINT64, AVERAGE),
1768 X("GPU-sc-busy", GPU_SC_BUSY, UINT64, AVERAGE),
1769 X("GPU-pa-busy", GPU_PA_BUSY, UINT64, AVERAGE),
1770 X("GPU-db-busy", GPU_DB_BUSY, UINT64, AVERAGE),
1771 X("GPU-cp-busy", GPU_CP_BUSY, UINT64, AVERAGE),
1772 X("GPU-cb-busy", GPU_CB_BUSY, UINT64, AVERAGE),
1773 X("GPU-sdma-busy", GPU_SDMA_BUSY, UINT64, AVERAGE),
1774
1775 X("temperature", GPU_TEMPERATURE, UINT64, AVERAGE),
1776 X("shader-clock", CURRENT_GPU_SCLK, HZ, AVERAGE),
1777 X("memory-clock", CURRENT_GPU_MCLK, HZ, AVERAGE),
1778 };
1779
1780 #undef X
1781 #undef XG
1782 #undef XFULL
1783
1784 static unsigned r600_get_num_queries(struct r600_common_screen *rscreen)
1785 {
1786 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
1787 return ARRAY_SIZE(r600_driver_query_list);
1788 else if (rscreen->info.drm_major == 3)
1789 return ARRAY_SIZE(r600_driver_query_list) - 3;
1790 else
1791 return ARRAY_SIZE(r600_driver_query_list) - 18;
1792 }
1793
1794 static int r600_get_driver_query_info(struct pipe_screen *screen,
1795 unsigned index,
1796 struct pipe_driver_query_info *info)
1797 {
1798 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1799 unsigned num_queries = r600_get_num_queries(rscreen);
1800
1801 if (!info) {
1802 unsigned num_perfcounters =
1803 r600_get_perfcounter_info(rscreen, 0, NULL);
1804
1805 return num_queries + num_perfcounters;
1806 }
1807
1808 if (index >= num_queries)
1809 return r600_get_perfcounter_info(rscreen, index - num_queries, info);
1810
1811 *info = r600_driver_query_list[index];
1812
1813 switch (info->query_type) {
1814 case R600_QUERY_REQUESTED_VRAM:
1815 case R600_QUERY_VRAM_USAGE:
1816 case R600_QUERY_MAPPED_VRAM:
1817 info->max_value.u64 = rscreen->info.vram_size;
1818 break;
1819 case R600_QUERY_REQUESTED_GTT:
1820 case R600_QUERY_GTT_USAGE:
1821 case R600_QUERY_MAPPED_GTT:
1822 info->max_value.u64 = rscreen->info.gart_size;
1823 break;
1824 case R600_QUERY_GPU_TEMPERATURE:
1825 info->max_value.u64 = 125;
1826 break;
1827 case R600_QUERY_VRAM_VIS_USAGE:
1828 info->max_value.u64 = rscreen->info.vram_vis_size;
1829 break;
1830 }
1831
1832 if (info->group_id != ~(unsigned)0 && rscreen->perfcounters)
1833 info->group_id += rscreen->perfcounters->num_groups;
1834
1835 return 1;
1836 }
1837
1838 /* Note: Unfortunately, GPUPerfStudio hardcodes the order of hardware
1839 * performance counter groups, so be careful when changing this and related
1840 * functions.
1841 */
1842 static int r600_get_driver_query_group_info(struct pipe_screen *screen,
1843 unsigned index,
1844 struct pipe_driver_query_group_info *info)
1845 {
1846 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
1847 unsigned num_pc_groups = 0;
1848
1849 if (rscreen->perfcounters)
1850 num_pc_groups = rscreen->perfcounters->num_groups;
1851
1852 if (!info)
1853 return num_pc_groups + R600_NUM_SW_QUERY_GROUPS;
1854
1855 if (index < num_pc_groups)
1856 return r600_get_perfcounter_group_info(rscreen, index, info);
1857
1858 index -= num_pc_groups;
1859 if (index >= R600_NUM_SW_QUERY_GROUPS)
1860 return 0;
1861
1862 info->name = "GPIN";
1863 info->max_active_queries = 5;
1864 info->num_queries = 5;
1865 return 1;
1866 }
1867
1868 void r600_query_init(struct r600_common_context *rctx)
1869 {
1870 rctx->b.create_query = r600_create_query;
1871 rctx->b.create_batch_query = r600_create_batch_query;
1872 rctx->b.destroy_query = r600_destroy_query;
1873 rctx->b.begin_query = r600_begin_query;
1874 rctx->b.end_query = r600_end_query;
1875 rctx->b.get_query_result = r600_get_query_result;
1876 rctx->b.get_query_result_resource = r600_get_query_result_resource;
1877 rctx->render_cond_atom.emit = r600_emit_query_predication;
1878
1879 if (((struct r600_common_screen*)rctx->b.screen)->info.num_render_backends > 0)
1880 rctx->b.render_condition = r600_render_condition;
1881
1882 LIST_INITHEAD(&rctx->active_queries);
1883 }
1884
1885 void r600_init_screen_query_functions(struct r600_common_screen *rscreen)
1886 {
1887 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
1888 rscreen->b.get_driver_query_group_info = r600_get_driver_query_group_info;
1889 }