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radeon: count cs dwords separately for query begin and end
[mesa.git] / src / gallium / drivers / radeon / r600_query.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014 Marek Olšák <marek.olsak@amd.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "r600_query.h"
26 #include "r600_cs.h"
27 #include "util/u_memory.h"
28
29 /* Queries without buffer handling or suspend/resume. */
30 struct r600_query_sw {
31 struct r600_query b;
32
33 uint64_t begin_result;
34 uint64_t end_result;
35 /* Fence for GPU_FINISHED. */
36 struct pipe_fence_handle *fence;
37 };
38
39 static void r600_query_sw_destroy(struct r600_common_context *rctx,
40 struct r600_query *rquery)
41 {
42 struct pipe_screen *screen = rctx->b.screen;
43 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
44
45 screen->fence_reference(screen, &query->fence, NULL);
46 FREE(query);
47 }
48
49 static enum radeon_value_id winsys_id_from_type(unsigned type)
50 {
51 switch (type) {
52 case R600_QUERY_REQUESTED_VRAM: return RADEON_REQUESTED_VRAM_MEMORY;
53 case R600_QUERY_REQUESTED_GTT: return RADEON_REQUESTED_GTT_MEMORY;
54 case R600_QUERY_BUFFER_WAIT_TIME: return RADEON_BUFFER_WAIT_TIME_NS;
55 case R600_QUERY_NUM_CS_FLUSHES: return RADEON_NUM_CS_FLUSHES;
56 case R600_QUERY_NUM_BYTES_MOVED: return RADEON_NUM_BYTES_MOVED;
57 case R600_QUERY_VRAM_USAGE: return RADEON_VRAM_USAGE;
58 case R600_QUERY_GTT_USAGE: return RADEON_GTT_USAGE;
59 case R600_QUERY_GPU_TEMPERATURE: return RADEON_GPU_TEMPERATURE;
60 case R600_QUERY_CURRENT_GPU_SCLK: return RADEON_CURRENT_SCLK;
61 case R600_QUERY_CURRENT_GPU_MCLK: return RADEON_CURRENT_MCLK;
62 default: unreachable("query type does not correspond to winsys id");
63 }
64 }
65
66 static boolean r600_query_sw_begin(struct r600_common_context *rctx,
67 struct r600_query *rquery)
68 {
69 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
70
71 switch(query->b.type) {
72 case PIPE_QUERY_TIMESTAMP_DISJOINT:
73 case PIPE_QUERY_GPU_FINISHED:
74 break;
75 case R600_QUERY_DRAW_CALLS:
76 query->begin_result = rctx->num_draw_calls;
77 break;
78 case R600_QUERY_REQUESTED_VRAM:
79 case R600_QUERY_REQUESTED_GTT:
80 case R600_QUERY_VRAM_USAGE:
81 case R600_QUERY_GTT_USAGE:
82 case R600_QUERY_GPU_TEMPERATURE:
83 case R600_QUERY_CURRENT_GPU_SCLK:
84 case R600_QUERY_CURRENT_GPU_MCLK:
85 query->begin_result = 0;
86 break;
87 case R600_QUERY_BUFFER_WAIT_TIME:
88 case R600_QUERY_NUM_CS_FLUSHES:
89 case R600_QUERY_NUM_BYTES_MOVED: {
90 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
91 query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
92 break;
93 }
94 case R600_QUERY_GPU_LOAD:
95 query->begin_result = r600_gpu_load_begin(rctx->screen);
96 break;
97 case R600_QUERY_NUM_COMPILATIONS:
98 query->begin_result = p_atomic_read(&rctx->screen->num_compilations);
99 break;
100 case R600_QUERY_NUM_SHADERS_CREATED:
101 query->begin_result = p_atomic_read(&rctx->screen->num_shaders_created);
102 break;
103 default:
104 unreachable("r600_query_sw_begin: bad query type");
105 }
106
107 return TRUE;
108 }
109
110 static void r600_query_sw_end(struct r600_common_context *rctx,
111 struct r600_query *rquery)
112 {
113 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
114
115 switch(query->b.type) {
116 case PIPE_QUERY_TIMESTAMP_DISJOINT:
117 break;
118 case PIPE_QUERY_GPU_FINISHED:
119 rctx->b.flush(&rctx->b, &query->fence, 0);
120 break;
121 case R600_QUERY_DRAW_CALLS:
122 query->begin_result = rctx->num_draw_calls;
123 break;
124 case R600_QUERY_REQUESTED_VRAM:
125 case R600_QUERY_REQUESTED_GTT:
126 case R600_QUERY_VRAM_USAGE:
127 case R600_QUERY_GTT_USAGE:
128 case R600_QUERY_GPU_TEMPERATURE:
129 case R600_QUERY_CURRENT_GPU_SCLK:
130 case R600_QUERY_CURRENT_GPU_MCLK:
131 case R600_QUERY_BUFFER_WAIT_TIME:
132 case R600_QUERY_NUM_CS_FLUSHES:
133 case R600_QUERY_NUM_BYTES_MOVED: {
134 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
135 query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
136 break;
137 }
138 case R600_QUERY_GPU_LOAD:
139 query->end_result = r600_gpu_load_end(rctx->screen,
140 query->begin_result);
141 query->begin_result = 0;
142 break;
143 case R600_QUERY_NUM_COMPILATIONS:
144 query->begin_result = p_atomic_read(&rctx->screen->num_compilations);
145 break;
146 case R600_QUERY_NUM_SHADERS_CREATED:
147 query->begin_result = p_atomic_read(&rctx->screen->num_shaders_created);
148 break;
149 default:
150 unreachable("r600_query_sw_end: bad query type");
151 }
152 }
153
154 static boolean r600_query_sw_get_result(struct r600_common_context *rctx,
155 struct r600_query *rquery,
156 boolean wait,
157 union pipe_query_result *result)
158 {
159 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
160
161 switch (query->b.type) {
162 case PIPE_QUERY_TIMESTAMP_DISJOINT:
163 /* Convert from cycles per millisecond to cycles per second (Hz). */
164 result->timestamp_disjoint.frequency =
165 (uint64_t)rctx->screen->info.r600_clock_crystal_freq * 1000;
166 result->timestamp_disjoint.disjoint = FALSE;
167 return TRUE;
168 case PIPE_QUERY_GPU_FINISHED: {
169 struct pipe_screen *screen = rctx->b.screen;
170 result->b = screen->fence_finish(screen, query->fence,
171 wait ? PIPE_TIMEOUT_INFINITE : 0);
172 return result->b;
173 }
174 }
175
176 result->u64 = query->end_result - query->begin_result;
177
178 switch (query->b.type) {
179 case R600_QUERY_BUFFER_WAIT_TIME:
180 case R600_QUERY_GPU_TEMPERATURE:
181 result->u64 /= 1000;
182 break;
183 case R600_QUERY_CURRENT_GPU_SCLK:
184 case R600_QUERY_CURRENT_GPU_MCLK:
185 result->u64 *= 1000000;
186 break;
187 }
188
189 return TRUE;
190 }
191
192 static struct r600_query_ops sw_query_ops = {
193 .destroy = r600_query_sw_destroy,
194 .begin = r600_query_sw_begin,
195 .end = r600_query_sw_end,
196 .get_result = r600_query_sw_get_result
197 };
198
199 static struct pipe_query *r600_query_sw_create(struct pipe_context *ctx,
200 unsigned query_type)
201 {
202 struct r600_query_sw *query;
203
204 query = CALLOC_STRUCT(r600_query_sw);
205 if (query == NULL)
206 return NULL;
207
208 query->b.type = query_type;
209 query->b.ops = &sw_query_ops;
210
211 return (struct pipe_query *)query;
212 }
213
214 void r600_query_hw_destroy(struct r600_common_context *rctx,
215 struct r600_query *rquery)
216 {
217 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
218 struct r600_query_buffer *prev = query->buffer.previous;
219
220 /* Release all query buffers. */
221 while (prev) {
222 struct r600_query_buffer *qbuf = prev;
223 prev = prev->previous;
224 pipe_resource_reference((struct pipe_resource**)&qbuf->buf, NULL);
225 FREE(qbuf);
226 }
227
228 pipe_resource_reference((struct pipe_resource**)&query->buffer.buf, NULL);
229 FREE(rquery);
230 }
231
232 static struct r600_resource *r600_new_query_buffer(struct r600_common_context *ctx,
233 struct r600_query_hw *query)
234 {
235 unsigned buf_size = 4096;
236
237 /* Queries are normally read by the CPU after
238 * being written by the gpu, hence staging is probably a good
239 * usage pattern.
240 */
241 struct r600_resource *buf = (struct r600_resource*)
242 pipe_buffer_create(ctx->b.screen, PIPE_BIND_CUSTOM,
243 PIPE_USAGE_STAGING, buf_size);
244
245 if (query->ops->prepare_buffer)
246 query->ops->prepare_buffer(ctx, query, buf);
247
248 return buf;
249 }
250
251 static void r600_query_hw_prepare_buffer(struct r600_common_context *ctx,
252 struct r600_query_hw *query,
253 struct r600_resource *buffer)
254 {
255 uint32_t *results;
256
257 if (query->b.type == PIPE_QUERY_TIME_ELAPSED ||
258 query->b.type == PIPE_QUERY_TIMESTAMP)
259 return;
260
261 results = r600_buffer_map_sync_with_rings(ctx, buffer,
262 PIPE_TRANSFER_WRITE);
263
264 memset(results, 0, buffer->b.b.width0);
265
266 if (query->b.type == PIPE_QUERY_OCCLUSION_COUNTER ||
267 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE) {
268 unsigned num_results;
269 unsigned i, j;
270
271 /* Set top bits for unused backends. */
272 num_results = buffer->b.b.width0 / (16 * ctx->max_db);
273 for (j = 0; j < num_results; j++) {
274 for (i = 0; i < ctx->max_db; i++) {
275 if (!(ctx->backend_mask & (1<<i))) {
276 results[(i * 4)+1] = 0x80000000;
277 results[(i * 4)+3] = 0x80000000;
278 }
279 }
280 results += 4 * ctx->max_db;
281 }
282 }
283 }
284
285 static struct r600_query_ops query_hw_ops = {
286 .destroy = r600_query_hw_destroy,
287 .begin = r600_query_hw_begin,
288 .end = r600_query_hw_end,
289 .get_result = r600_query_hw_get_result,
290 };
291
292 static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
293 struct r600_query_hw *query,
294 struct r600_resource *buffer,
295 uint64_t va);
296 static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
297 struct r600_query_hw *query,
298 struct r600_resource *buffer,
299 uint64_t va);
300 static void r600_query_hw_add_result(struct r600_common_context *ctx,
301 struct r600_query_hw *, void *buffer,
302 union pipe_query_result *result);
303 static void r600_query_hw_clear_result(struct r600_query_hw *,
304 union pipe_query_result *);
305
306 static struct r600_query_hw_ops query_hw_default_hw_ops = {
307 .prepare_buffer = r600_query_hw_prepare_buffer,
308 .emit_start = r600_query_hw_do_emit_start,
309 .emit_stop = r600_query_hw_do_emit_stop,
310 .clear_result = r600_query_hw_clear_result,
311 .add_result = r600_query_hw_add_result,
312 };
313
314 boolean r600_query_hw_init(struct r600_common_context *rctx,
315 struct r600_query_hw *query)
316 {
317 query->buffer.buf = r600_new_query_buffer(rctx, query);
318 if (!query->buffer.buf)
319 return FALSE;
320
321 return TRUE;
322 }
323
324 static struct pipe_query *r600_query_hw_create(struct r600_common_context *rctx,
325 unsigned query_type,
326 unsigned index)
327 {
328 struct r600_query_hw *query = CALLOC_STRUCT(r600_query_hw);
329 if (!query)
330 return NULL;
331
332 query->b.type = query_type;
333 query->b.ops = &query_hw_ops;
334 query->ops = &query_hw_default_hw_ops;
335
336 switch (query_type) {
337 case PIPE_QUERY_OCCLUSION_COUNTER:
338 case PIPE_QUERY_OCCLUSION_PREDICATE:
339 query->result_size = 16 * rctx->max_db;
340 query->num_cs_dw_begin = 6;
341 query->num_cs_dw_end = 6;
342 break;
343 case PIPE_QUERY_TIME_ELAPSED:
344 query->result_size = 16;
345 query->num_cs_dw_begin = 8;
346 query->num_cs_dw_end = 8;
347 query->flags = R600_QUERY_HW_FLAG_TIMER;
348 break;
349 case PIPE_QUERY_TIMESTAMP:
350 query->result_size = 8;
351 query->num_cs_dw_end = 8;
352 query->flags = R600_QUERY_HW_FLAG_TIMER |
353 R600_QUERY_HW_FLAG_NO_START;
354 break;
355 case PIPE_QUERY_PRIMITIVES_EMITTED:
356 case PIPE_QUERY_PRIMITIVES_GENERATED:
357 case PIPE_QUERY_SO_STATISTICS:
358 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
359 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
360 query->result_size = 32;
361 query->num_cs_dw_begin = 6;
362 query->num_cs_dw_end = 6;
363 query->stream = index;
364 break;
365 case PIPE_QUERY_PIPELINE_STATISTICS:
366 /* 11 values on EG, 8 on R600. */
367 query->result_size = (rctx->chip_class >= EVERGREEN ? 11 : 8) * 16;
368 query->num_cs_dw_begin = 6;
369 query->num_cs_dw_end = 6;
370 break;
371 default:
372 assert(0);
373 FREE(query);
374 return NULL;
375 }
376
377 if (!r600_query_hw_init(rctx, query)) {
378 FREE(query);
379 return NULL;
380 }
381
382 return (struct pipe_query *)query;
383 }
384
385 static void r600_update_occlusion_query_state(struct r600_common_context *rctx,
386 unsigned type, int diff)
387 {
388 if (type == PIPE_QUERY_OCCLUSION_COUNTER ||
389 type == PIPE_QUERY_OCCLUSION_PREDICATE) {
390 bool old_enable = rctx->num_occlusion_queries != 0;
391 bool enable;
392
393 rctx->num_occlusion_queries += diff;
394 assert(rctx->num_occlusion_queries >= 0);
395
396 enable = rctx->num_occlusion_queries != 0;
397
398 if (enable != old_enable) {
399 rctx->set_occlusion_query_state(&rctx->b, enable);
400 }
401 }
402 }
403
404 static unsigned event_type_for_stream(struct r600_query_hw *query)
405 {
406 switch (query->stream) {
407 default:
408 case 0: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS;
409 case 1: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS1;
410 case 2: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS2;
411 case 3: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS3;
412 }
413 }
414
415 static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
416 struct r600_query_hw *query,
417 struct r600_resource *buffer,
418 uint64_t va)
419 {
420 struct radeon_winsys_cs *cs = ctx->gfx.cs;
421
422 switch (query->b.type) {
423 case PIPE_QUERY_OCCLUSION_COUNTER:
424 case PIPE_QUERY_OCCLUSION_PREDICATE:
425 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
426 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
427 radeon_emit(cs, va);
428 radeon_emit(cs, (va >> 32) & 0xFFFF);
429 break;
430 case PIPE_QUERY_PRIMITIVES_EMITTED:
431 case PIPE_QUERY_PRIMITIVES_GENERATED:
432 case PIPE_QUERY_SO_STATISTICS:
433 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
434 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
435 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | EVENT_INDEX(3));
436 radeon_emit(cs, va);
437 radeon_emit(cs, (va >> 32) & 0xFFFF);
438 break;
439 case PIPE_QUERY_TIME_ELAPSED:
440 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
441 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
442 radeon_emit(cs, va);
443 radeon_emit(cs, (3 << 29) | ((va >> 32) & 0xFFFF));
444 radeon_emit(cs, 0);
445 radeon_emit(cs, 0);
446 break;
447 case PIPE_QUERY_PIPELINE_STATISTICS:
448 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
449 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
450 radeon_emit(cs, va);
451 radeon_emit(cs, (va >> 32) & 0xFFFF);
452 break;
453 default:
454 assert(0);
455 }
456 r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE,
457 RADEON_PRIO_QUERY);
458 }
459
460 static void r600_query_hw_emit_start(struct r600_common_context *ctx,
461 struct r600_query_hw *query)
462 {
463 uint64_t va;
464
465 r600_update_occlusion_query_state(ctx, query->b.type, 1);
466 r600_update_prims_generated_query_state(ctx, query->b.type, 1);
467
468 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw_begin + query->num_cs_dw_end,
469 TRUE);
470
471 /* Get a new query buffer if needed. */
472 if (query->buffer.results_end + query->result_size > query->buffer.buf->b.b.width0) {
473 struct r600_query_buffer *qbuf = MALLOC_STRUCT(r600_query_buffer);
474 *qbuf = query->buffer;
475 query->buffer.buf = r600_new_query_buffer(ctx, query);
476 query->buffer.results_end = 0;
477 query->buffer.previous = qbuf;
478 }
479
480 /* emit begin query */
481 va = query->buffer.buf->gpu_address + query->buffer.results_end;
482
483 query->ops->emit_start(ctx, query, query->buffer.buf, va);
484
485 if (query->flags & R600_QUERY_HW_FLAG_TIMER)
486 ctx->num_cs_dw_timer_queries_suspend += query->num_cs_dw_end;
487 else
488 ctx->num_cs_dw_nontimer_queries_suspend += query->num_cs_dw_end;
489 }
490
491 static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
492 struct r600_query_hw *query,
493 struct r600_resource *buffer,
494 uint64_t va)
495 {
496 struct radeon_winsys_cs *cs = ctx->gfx.cs;
497
498 switch (query->b.type) {
499 case PIPE_QUERY_OCCLUSION_COUNTER:
500 case PIPE_QUERY_OCCLUSION_PREDICATE:
501 va += 8;
502 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
503 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
504 radeon_emit(cs, va);
505 radeon_emit(cs, (va >> 32) & 0xFFFF);
506 break;
507 case PIPE_QUERY_PRIMITIVES_EMITTED:
508 case PIPE_QUERY_PRIMITIVES_GENERATED:
509 case PIPE_QUERY_SO_STATISTICS:
510 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
511 va += query->result_size/2;
512 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
513 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | EVENT_INDEX(3));
514 radeon_emit(cs, va);
515 radeon_emit(cs, (va >> 32) & 0xFFFF);
516 break;
517 case PIPE_QUERY_TIME_ELAPSED:
518 va += query->result_size/2;
519 /* fall through */
520 case PIPE_QUERY_TIMESTAMP:
521 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
522 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
523 radeon_emit(cs, va);
524 radeon_emit(cs, (3 << 29) | ((va >> 32) & 0xFFFF));
525 radeon_emit(cs, 0);
526 radeon_emit(cs, 0);
527 break;
528 case PIPE_QUERY_PIPELINE_STATISTICS:
529 va += query->result_size/2;
530 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
531 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
532 radeon_emit(cs, va);
533 radeon_emit(cs, (va >> 32) & 0xFFFF);
534 break;
535 default:
536 assert(0);
537 }
538 r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE,
539 RADEON_PRIO_QUERY);
540 }
541
542 static void r600_query_hw_emit_stop(struct r600_common_context *ctx,
543 struct r600_query_hw *query)
544 {
545 uint64_t va;
546
547 /* The queries which need begin already called this in begin_query. */
548 if (query->flags & R600_QUERY_HW_FLAG_NO_START) {
549 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw_end, FALSE);
550 }
551
552 /* emit end query */
553 va = query->buffer.buf->gpu_address + query->buffer.results_end;
554
555 query->ops->emit_stop(ctx, query, query->buffer.buf, va);
556
557 query->buffer.results_end += query->result_size;
558
559 if (!(query->flags & R600_QUERY_HW_FLAG_NO_START)) {
560 if (query->flags & R600_QUERY_HW_FLAG_TIMER)
561 ctx->num_cs_dw_timer_queries_suspend -= query->num_cs_dw_end;
562 else
563 ctx->num_cs_dw_nontimer_queries_suspend -= query->num_cs_dw_end;
564 }
565
566 r600_update_occlusion_query_state(ctx, query->b.type, -1);
567 r600_update_prims_generated_query_state(ctx, query->b.type, -1);
568 }
569
570 static void r600_emit_query_predication(struct r600_common_context *ctx,
571 struct r600_atom *atom)
572 {
573 struct radeon_winsys_cs *cs = ctx->gfx.cs;
574 struct r600_query_hw *query = (struct r600_query_hw *)ctx->render_cond;
575 struct r600_query_buffer *qbuf;
576 uint32_t op;
577 bool flag_wait;
578
579 if (!query)
580 return;
581
582 flag_wait = ctx->render_cond_mode == PIPE_RENDER_COND_WAIT ||
583 ctx->render_cond_mode == PIPE_RENDER_COND_BY_REGION_WAIT;
584
585 switch (query->b.type) {
586 case PIPE_QUERY_OCCLUSION_COUNTER:
587 case PIPE_QUERY_OCCLUSION_PREDICATE:
588 op = PRED_OP(PREDICATION_OP_ZPASS);
589 break;
590 case PIPE_QUERY_PRIMITIVES_EMITTED:
591 case PIPE_QUERY_PRIMITIVES_GENERATED:
592 case PIPE_QUERY_SO_STATISTICS:
593 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
594 op = PRED_OP(PREDICATION_OP_PRIMCOUNT);
595 break;
596 default:
597 assert(0);
598 return;
599 }
600
601 /* if true then invert, see GL_ARB_conditional_render_inverted */
602 if (ctx->render_cond_invert)
603 op |= PREDICATION_DRAW_NOT_VISIBLE; /* Draw if not visable/overflow */
604 else
605 op |= PREDICATION_DRAW_VISIBLE; /* Draw if visable/overflow */
606
607 op |= flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW;
608
609 /* emit predicate packets for all data blocks */
610 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
611 unsigned results_base = 0;
612 uint64_t va = qbuf->buf->gpu_address;
613
614 while (results_base < qbuf->results_end) {
615 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
616 radeon_emit(cs, va + results_base);
617 radeon_emit(cs, op | (((va + results_base) >> 32) & 0xFF));
618 r600_emit_reloc(ctx, &ctx->gfx, qbuf->buf, RADEON_USAGE_READ,
619 RADEON_PRIO_QUERY);
620 results_base += query->result_size;
621
622 /* set CONTINUE bit for all packets except the first */
623 op |= PREDICATION_CONTINUE;
624 }
625 }
626 }
627
628 static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type, unsigned index)
629 {
630 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
631
632 if (query_type == PIPE_QUERY_TIMESTAMP_DISJOINT ||
633 query_type == PIPE_QUERY_GPU_FINISHED ||
634 query_type >= PIPE_QUERY_DRIVER_SPECIFIC)
635 return r600_query_sw_create(ctx, query_type);
636
637 return r600_query_hw_create(rctx, query_type, index);
638 }
639
640 static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
641 {
642 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
643 struct r600_query *rquery = (struct r600_query *)query;
644
645 rquery->ops->destroy(rctx, rquery);
646 }
647
648 static boolean r600_begin_query(struct pipe_context *ctx,
649 struct pipe_query *query)
650 {
651 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
652 struct r600_query *rquery = (struct r600_query *)query;
653
654 return rquery->ops->begin(rctx, rquery);
655 }
656
657 boolean r600_query_hw_begin(struct r600_common_context *rctx,
658 struct r600_query *rquery)
659 {
660 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
661 struct r600_query_buffer *prev = query->buffer.previous;
662
663 if (query->flags & R600_QUERY_HW_FLAG_NO_START) {
664 assert(0);
665 return false;
666 }
667
668 /* Discard the old query buffers. */
669 while (prev) {
670 struct r600_query_buffer *qbuf = prev;
671 prev = prev->previous;
672 pipe_resource_reference((struct pipe_resource**)&qbuf->buf, NULL);
673 FREE(qbuf);
674 }
675
676 /* Obtain a new buffer if the current one can't be mapped without a stall. */
677 if (r600_rings_is_buffer_referenced(rctx, query->buffer.buf->cs_buf, RADEON_USAGE_READWRITE) ||
678 !rctx->ws->buffer_wait(query->buffer.buf->buf, 0, RADEON_USAGE_READWRITE)) {
679 pipe_resource_reference((struct pipe_resource**)&query->buffer.buf, NULL);
680 query->buffer.buf = r600_new_query_buffer(rctx, query);
681 }
682
683 query->buffer.results_end = 0;
684 query->buffer.previous = NULL;
685
686 r600_query_hw_emit_start(rctx, query);
687
688 if (query->flags & R600_QUERY_HW_FLAG_TIMER)
689 LIST_ADDTAIL(&query->list, &rctx->active_timer_queries);
690 else
691 LIST_ADDTAIL(&query->list, &rctx->active_nontimer_queries);
692 return true;
693 }
694
695 static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
696 {
697 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
698 struct r600_query *rquery = (struct r600_query *)query;
699
700 rquery->ops->end(rctx, rquery);
701 }
702
703 void r600_query_hw_end(struct r600_common_context *rctx,
704 struct r600_query *rquery)
705 {
706 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
707
708 r600_query_hw_emit_stop(rctx, query);
709
710 if (!(query->flags & R600_QUERY_HW_FLAG_NO_START))
711 LIST_DELINIT(&query->list);
712 }
713
714 static unsigned r600_query_read_result(void *map, unsigned start_index, unsigned end_index,
715 bool test_status_bit)
716 {
717 uint32_t *current_result = (uint32_t*)map;
718 uint64_t start, end;
719
720 start = (uint64_t)current_result[start_index] |
721 (uint64_t)current_result[start_index+1] << 32;
722 end = (uint64_t)current_result[end_index] |
723 (uint64_t)current_result[end_index+1] << 32;
724
725 if (!test_status_bit ||
726 ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) {
727 return end - start;
728 }
729 return 0;
730 }
731
732 static void r600_query_hw_add_result(struct r600_common_context *ctx,
733 struct r600_query_hw *query,
734 void *buffer,
735 union pipe_query_result *result)
736 {
737 switch (query->b.type) {
738 case PIPE_QUERY_OCCLUSION_COUNTER: {
739 unsigned results_base = 0;
740 while (results_base != query->result_size) {
741 result->u64 +=
742 r600_query_read_result(buffer + results_base, 0, 2, true);
743 results_base += 16;
744 }
745 break;
746 }
747 case PIPE_QUERY_OCCLUSION_PREDICATE: {
748 unsigned results_base = 0;
749 while (results_base != query->result_size) {
750 result->b = result->b ||
751 r600_query_read_result(buffer + results_base, 0, 2, true) != 0;
752 results_base += 16;
753 }
754 break;
755 }
756 case PIPE_QUERY_TIME_ELAPSED:
757 result->u64 += r600_query_read_result(buffer, 0, 2, false);
758 break;
759 case PIPE_QUERY_TIMESTAMP:
760 {
761 uint32_t *current_result = (uint32_t*)buffer;
762 result->u64 = (uint64_t)current_result[0] |
763 (uint64_t)current_result[1] << 32;
764 break;
765 }
766 case PIPE_QUERY_PRIMITIVES_EMITTED:
767 /* SAMPLE_STREAMOUTSTATS stores this structure:
768 * {
769 * u64 NumPrimitivesWritten;
770 * u64 PrimitiveStorageNeeded;
771 * }
772 * We only need NumPrimitivesWritten here. */
773 result->u64 += r600_query_read_result(buffer, 2, 6, true);
774 break;
775 case PIPE_QUERY_PRIMITIVES_GENERATED:
776 /* Here we read PrimitiveStorageNeeded. */
777 result->u64 += r600_query_read_result(buffer, 0, 4, true);
778 break;
779 case PIPE_QUERY_SO_STATISTICS:
780 result->so_statistics.num_primitives_written +=
781 r600_query_read_result(buffer, 2, 6, true);
782 result->so_statistics.primitives_storage_needed +=
783 r600_query_read_result(buffer, 0, 4, true);
784 break;
785 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
786 result->b = result->b ||
787 r600_query_read_result(buffer, 2, 6, true) !=
788 r600_query_read_result(buffer, 0, 4, true);
789 break;
790 case PIPE_QUERY_PIPELINE_STATISTICS:
791 if (ctx->chip_class >= EVERGREEN) {
792 result->pipeline_statistics.ps_invocations +=
793 r600_query_read_result(buffer, 0, 22, false);
794 result->pipeline_statistics.c_primitives +=
795 r600_query_read_result(buffer, 2, 24, false);
796 result->pipeline_statistics.c_invocations +=
797 r600_query_read_result(buffer, 4, 26, false);
798 result->pipeline_statistics.vs_invocations +=
799 r600_query_read_result(buffer, 6, 28, false);
800 result->pipeline_statistics.gs_invocations +=
801 r600_query_read_result(buffer, 8, 30, false);
802 result->pipeline_statistics.gs_primitives +=
803 r600_query_read_result(buffer, 10, 32, false);
804 result->pipeline_statistics.ia_primitives +=
805 r600_query_read_result(buffer, 12, 34, false);
806 result->pipeline_statistics.ia_vertices +=
807 r600_query_read_result(buffer, 14, 36, false);
808 result->pipeline_statistics.hs_invocations +=
809 r600_query_read_result(buffer, 16, 38, false);
810 result->pipeline_statistics.ds_invocations +=
811 r600_query_read_result(buffer, 18, 40, false);
812 result->pipeline_statistics.cs_invocations +=
813 r600_query_read_result(buffer, 20, 42, false);
814 } else {
815 result->pipeline_statistics.ps_invocations +=
816 r600_query_read_result(buffer, 0, 16, false);
817 result->pipeline_statistics.c_primitives +=
818 r600_query_read_result(buffer, 2, 18, false);
819 result->pipeline_statistics.c_invocations +=
820 r600_query_read_result(buffer, 4, 20, false);
821 result->pipeline_statistics.vs_invocations +=
822 r600_query_read_result(buffer, 6, 22, false);
823 result->pipeline_statistics.gs_invocations +=
824 r600_query_read_result(buffer, 8, 24, false);
825 result->pipeline_statistics.gs_primitives +=
826 r600_query_read_result(buffer, 10, 26, false);
827 result->pipeline_statistics.ia_primitives +=
828 r600_query_read_result(buffer, 12, 28, false);
829 result->pipeline_statistics.ia_vertices +=
830 r600_query_read_result(buffer, 14, 30, false);
831 }
832 #if 0 /* for testing */
833 printf("Pipeline stats: IA verts=%llu, IA prims=%llu, VS=%llu, HS=%llu, "
834 "DS=%llu, GS=%llu, GS prims=%llu, Clipper=%llu, "
835 "Clipper prims=%llu, PS=%llu, CS=%llu\n",
836 result->pipeline_statistics.ia_vertices,
837 result->pipeline_statistics.ia_primitives,
838 result->pipeline_statistics.vs_invocations,
839 result->pipeline_statistics.hs_invocations,
840 result->pipeline_statistics.ds_invocations,
841 result->pipeline_statistics.gs_invocations,
842 result->pipeline_statistics.gs_primitives,
843 result->pipeline_statistics.c_invocations,
844 result->pipeline_statistics.c_primitives,
845 result->pipeline_statistics.ps_invocations,
846 result->pipeline_statistics.cs_invocations);
847 #endif
848 break;
849 default:
850 assert(0);
851 }
852 }
853
854 static boolean r600_get_query_result(struct pipe_context *ctx,
855 struct pipe_query *query, boolean wait,
856 union pipe_query_result *result)
857 {
858 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
859 struct r600_query *rquery = (struct r600_query *)query;
860
861 return rquery->ops->get_result(rctx, rquery, wait, result);
862 }
863
864 static void r600_query_hw_clear_result(struct r600_query_hw *query,
865 union pipe_query_result *result)
866 {
867 util_query_clear_result(result, query->b.type);
868 }
869
870 boolean r600_query_hw_get_result(struct r600_common_context *rctx,
871 struct r600_query *rquery,
872 boolean wait, union pipe_query_result *result)
873 {
874 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
875 struct r600_query_buffer *qbuf;
876
877 query->ops->clear_result(query, result);
878
879 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
880 unsigned results_base = 0;
881 void *map;
882
883 map = r600_buffer_map_sync_with_rings(rctx, qbuf->buf,
884 PIPE_TRANSFER_READ |
885 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK));
886 if (!map)
887 return FALSE;
888
889 while (results_base != qbuf->results_end) {
890 query->ops->add_result(rctx, query, map + results_base,
891 result);
892 results_base += query->result_size;
893 }
894 }
895
896 /* Convert the time to expected units. */
897 if (rquery->type == PIPE_QUERY_TIME_ELAPSED ||
898 rquery->type == PIPE_QUERY_TIMESTAMP) {
899 result->u64 = (1000000 * result->u64) / rctx->screen->info.r600_clock_crystal_freq;
900 }
901 return TRUE;
902 }
903
904 static void r600_render_condition(struct pipe_context *ctx,
905 struct pipe_query *query,
906 boolean condition,
907 uint mode)
908 {
909 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
910 struct r600_query_hw *rquery = (struct r600_query_hw *)query;
911 struct r600_query_buffer *qbuf;
912 struct r600_atom *atom = &rctx->render_cond_atom;
913
914 rctx->render_cond = query;
915 rctx->render_cond_invert = condition;
916 rctx->render_cond_mode = mode;
917
918 /* Compute the size of SET_PREDICATION packets. */
919 atom->num_dw = 0;
920 if (query) {
921 for (qbuf = &rquery->buffer; qbuf; qbuf = qbuf->previous)
922 atom->num_dw += (qbuf->results_end / rquery->result_size) * 5;
923 }
924
925 rctx->set_atom_dirty(rctx, atom, query != NULL);
926 }
927
928 static void r600_suspend_queries(struct r600_common_context *ctx,
929 struct list_head *query_list,
930 unsigned *num_cs_dw_queries_suspend)
931 {
932 struct r600_query_hw *query;
933
934 LIST_FOR_EACH_ENTRY(query, query_list, list) {
935 r600_query_hw_emit_stop(ctx, query);
936 }
937 assert(*num_cs_dw_queries_suspend == 0);
938 }
939
940 void r600_suspend_nontimer_queries(struct r600_common_context *ctx)
941 {
942 r600_suspend_queries(ctx, &ctx->active_nontimer_queries,
943 &ctx->num_cs_dw_nontimer_queries_suspend);
944 }
945
946 void r600_suspend_timer_queries(struct r600_common_context *ctx)
947 {
948 r600_suspend_queries(ctx, &ctx->active_timer_queries,
949 &ctx->num_cs_dw_timer_queries_suspend);
950 }
951
952 static unsigned r600_queries_num_cs_dw_for_resuming(struct r600_common_context *ctx,
953 struct list_head *query_list)
954 {
955 struct r600_query_hw *query;
956 unsigned num_dw = 0;
957
958 LIST_FOR_EACH_ENTRY(query, query_list, list) {
959 /* begin + end */
960 num_dw += query->num_cs_dw_begin + query->num_cs_dw_end;
961
962 /* Workaround for the fact that
963 * num_cs_dw_nontimer_queries_suspend is incremented for every
964 * resumed query, which raises the bar in need_cs_space for
965 * queries about to be resumed.
966 */
967 num_dw += query->num_cs_dw_end;
968 }
969 /* primitives generated query */
970 num_dw += ctx->streamout.enable_atom.num_dw;
971 /* guess for ZPASS enable or PERFECT_ZPASS_COUNT enable updates */
972 num_dw += 13;
973
974 return num_dw;
975 }
976
977 static void r600_resume_queries(struct r600_common_context *ctx,
978 struct list_head *query_list,
979 unsigned *num_cs_dw_queries_suspend)
980 {
981 struct r600_query_hw *query;
982 unsigned num_cs_dw = r600_queries_num_cs_dw_for_resuming(ctx, query_list);
983
984 assert(*num_cs_dw_queries_suspend == 0);
985
986 /* Check CS space here. Resuming must not be interrupted by flushes. */
987 ctx->need_gfx_cs_space(&ctx->b, num_cs_dw, TRUE);
988
989 LIST_FOR_EACH_ENTRY(query, query_list, list) {
990 r600_query_hw_emit_start(ctx, query);
991 }
992 }
993
994 void r600_resume_nontimer_queries(struct r600_common_context *ctx)
995 {
996 r600_resume_queries(ctx, &ctx->active_nontimer_queries,
997 &ctx->num_cs_dw_nontimer_queries_suspend);
998 }
999
1000 void r600_resume_timer_queries(struct r600_common_context *ctx)
1001 {
1002 r600_resume_queries(ctx, &ctx->active_timer_queries,
1003 &ctx->num_cs_dw_timer_queries_suspend);
1004 }
1005
1006 /* Get backends mask */
1007 void r600_query_init_backend_mask(struct r600_common_context *ctx)
1008 {
1009 struct radeon_winsys_cs *cs = ctx->gfx.cs;
1010 struct r600_resource *buffer;
1011 uint32_t *results;
1012 unsigned num_backends = ctx->screen->info.r600_num_backends;
1013 unsigned i, mask = 0;
1014
1015 /* if backend_map query is supported by the kernel */
1016 if (ctx->screen->info.r600_backend_map_valid) {
1017 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
1018 unsigned backend_map = ctx->screen->info.r600_backend_map;
1019 unsigned item_width, item_mask;
1020
1021 if (ctx->chip_class >= EVERGREEN) {
1022 item_width = 4;
1023 item_mask = 0x7;
1024 } else {
1025 item_width = 2;
1026 item_mask = 0x3;
1027 }
1028
1029 while(num_tile_pipes--) {
1030 i = backend_map & item_mask;
1031 mask |= (1<<i);
1032 backend_map >>= item_width;
1033 }
1034 if (mask != 0) {
1035 ctx->backend_mask = mask;
1036 return;
1037 }
1038 }
1039
1040 /* otherwise backup path for older kernels */
1041
1042 /* create buffer for event data */
1043 buffer = (struct r600_resource*)
1044 pipe_buffer_create(ctx->b.screen, PIPE_BIND_CUSTOM,
1045 PIPE_USAGE_STAGING, ctx->max_db*16);
1046 if (!buffer)
1047 goto err;
1048
1049 /* initialize buffer with zeroes */
1050 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE);
1051 if (results) {
1052 memset(results, 0, ctx->max_db * 4 * 4);
1053
1054 /* emit EVENT_WRITE for ZPASS_DONE */
1055 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1056 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
1057 radeon_emit(cs, buffer->gpu_address);
1058 radeon_emit(cs, buffer->gpu_address >> 32);
1059
1060 r600_emit_reloc(ctx, &ctx->gfx, buffer,
1061 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
1062
1063 /* analyze results */
1064 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ);
1065 if (results) {
1066 for(i = 0; i < ctx->max_db; i++) {
1067 /* at least highest bit will be set if backend is used */
1068 if (results[i*4 + 1])
1069 mask |= (1<<i);
1070 }
1071 }
1072 }
1073
1074 pipe_resource_reference((struct pipe_resource**)&buffer, NULL);
1075
1076 if (mask != 0) {
1077 ctx->backend_mask = mask;
1078 return;
1079 }
1080
1081 err:
1082 /* fallback to old method - set num_backends lower bits to 1 */
1083 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
1084 return;
1085 }
1086
1087 #define X(name_, query_type_, type_, result_type_) \
1088 { \
1089 .name = name_, \
1090 .query_type = R600_QUERY_##query_type_, \
1091 .type = PIPE_DRIVER_QUERY_TYPE_##type_, \
1092 .result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_##result_type_, \
1093 .group_id = ~(unsigned)0 \
1094 }
1095
1096 static struct pipe_driver_query_info r600_driver_query_list[] = {
1097 X("num-compilations", NUM_COMPILATIONS, UINT64, CUMULATIVE),
1098 X("num-shaders-created", NUM_SHADERS_CREATED, UINT64, CUMULATIVE),
1099 X("draw-calls", DRAW_CALLS, UINT64, CUMULATIVE),
1100 X("requested-VRAM", REQUESTED_VRAM, BYTES, AVERAGE),
1101 X("requested-GTT", REQUESTED_GTT, BYTES, AVERAGE),
1102 X("buffer-wait-time", BUFFER_WAIT_TIME, MICROSECONDS, CUMULATIVE),
1103 X("num-cs-flushes", NUM_CS_FLUSHES, UINT64, CUMULATIVE),
1104 X("num-bytes-moved", NUM_BYTES_MOVED, BYTES, CUMULATIVE),
1105 X("VRAM-usage", VRAM_USAGE, BYTES, AVERAGE),
1106 X("GTT-usage", GTT_USAGE, BYTES, AVERAGE),
1107 X("GPU-load", GPU_LOAD, UINT64, AVERAGE),
1108 X("temperature", GPU_TEMPERATURE, UINT64, AVERAGE),
1109 X("shader-clock", CURRENT_GPU_SCLK, HZ, AVERAGE),
1110 X("memory-clock", CURRENT_GPU_MCLK, HZ, AVERAGE),
1111 };
1112
1113 #undef X
1114
1115 static unsigned r600_get_num_queries(struct r600_common_screen *rscreen)
1116 {
1117 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
1118 return Elements(r600_driver_query_list);
1119 else if (rscreen->info.drm_major == 3)
1120 return Elements(r600_driver_query_list) - 3;
1121 else
1122 return Elements(r600_driver_query_list) - 4;
1123 }
1124
1125 static int r600_get_driver_query_info(struct pipe_screen *screen,
1126 unsigned index,
1127 struct pipe_driver_query_info *info)
1128 {
1129 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1130 unsigned num_queries = r600_get_num_queries(rscreen);
1131
1132 if (!info)
1133 return num_queries;
1134
1135 if (index >= num_queries)
1136 return 0;
1137
1138 *info = r600_driver_query_list[index];
1139
1140 switch (info->query_type) {
1141 case R600_QUERY_REQUESTED_VRAM:
1142 case R600_QUERY_VRAM_USAGE:
1143 info->max_value.u64 = rscreen->info.vram_size;
1144 break;
1145 case R600_QUERY_REQUESTED_GTT:
1146 case R600_QUERY_GTT_USAGE:
1147 info->max_value.u64 = rscreen->info.gart_size;
1148 break;
1149 case R600_QUERY_GPU_TEMPERATURE:
1150 info->max_value.u64 = 125;
1151 break;
1152 }
1153
1154 return 1;
1155 }
1156
1157 void r600_query_init(struct r600_common_context *rctx)
1158 {
1159 rctx->b.create_query = r600_create_query;
1160 rctx->b.destroy_query = r600_destroy_query;
1161 rctx->b.begin_query = r600_begin_query;
1162 rctx->b.end_query = r600_end_query;
1163 rctx->b.get_query_result = r600_get_query_result;
1164 rctx->render_cond_atom.emit = r600_emit_query_predication;
1165
1166 if (((struct r600_common_screen*)rctx->b.screen)->info.r600_num_backends > 0)
1167 rctx->b.render_condition = r600_render_condition;
1168
1169 LIST_INITHEAD(&rctx->active_nontimer_queries);
1170 LIST_INITHEAD(&rctx->active_timer_queries);
1171 }
1172
1173 void r600_init_screen_query_functions(struct r600_common_screen *rscreen)
1174 {
1175 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
1176 }