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gallium/radeon: remove r600_common_context::max_db
[mesa.git] / src / gallium / drivers / radeon / r600_query.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014 Marek Olšák <marek.olsak@amd.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "r600_query.h"
26 #include "r600_cs.h"
27 #include "util/u_memory.h"
28 #include "util/u_upload_mgr.h"
29
30 #include "tgsi/tgsi_text.h"
31
32 struct r600_hw_query_params {
33 unsigned start_offset;
34 unsigned end_offset;
35 unsigned fence_offset;
36 unsigned pair_stride;
37 unsigned pair_count;
38 };
39
40 /* Queries without buffer handling or suspend/resume. */
41 struct r600_query_sw {
42 struct r600_query b;
43
44 uint64_t begin_result;
45 uint64_t end_result;
46 /* Fence for GPU_FINISHED. */
47 struct pipe_fence_handle *fence;
48 };
49
50 static void r600_query_sw_destroy(struct r600_common_context *rctx,
51 struct r600_query *rquery)
52 {
53 struct pipe_screen *screen = rctx->b.screen;
54 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
55
56 screen->fence_reference(screen, &query->fence, NULL);
57 FREE(query);
58 }
59
60 static enum radeon_value_id winsys_id_from_type(unsigned type)
61 {
62 switch (type) {
63 case R600_QUERY_REQUESTED_VRAM: return RADEON_REQUESTED_VRAM_MEMORY;
64 case R600_QUERY_REQUESTED_GTT: return RADEON_REQUESTED_GTT_MEMORY;
65 case R600_QUERY_MAPPED_VRAM: return RADEON_MAPPED_VRAM;
66 case R600_QUERY_MAPPED_GTT: return RADEON_MAPPED_GTT;
67 case R600_QUERY_BUFFER_WAIT_TIME: return RADEON_BUFFER_WAIT_TIME_NS;
68 case R600_QUERY_NUM_MAPPED_BUFFERS: return RADEON_NUM_MAPPED_BUFFERS;
69 case R600_QUERY_NUM_GFX_IBS: return RADEON_NUM_GFX_IBS;
70 case R600_QUERY_NUM_SDMA_IBS: return RADEON_NUM_SDMA_IBS;
71 case R600_QUERY_NUM_BYTES_MOVED: return RADEON_NUM_BYTES_MOVED;
72 case R600_QUERY_NUM_EVICTIONS: return RADEON_NUM_EVICTIONS;
73 case R600_QUERY_VRAM_USAGE: return RADEON_VRAM_USAGE;
74 case R600_QUERY_VRAM_VIS_USAGE: return RADEON_VRAM_VIS_USAGE;
75 case R600_QUERY_GTT_USAGE: return RADEON_GTT_USAGE;
76 case R600_QUERY_GPU_TEMPERATURE: return RADEON_GPU_TEMPERATURE;
77 case R600_QUERY_CURRENT_GPU_SCLK: return RADEON_CURRENT_SCLK;
78 case R600_QUERY_CURRENT_GPU_MCLK: return RADEON_CURRENT_MCLK;
79 default: unreachable("query type does not correspond to winsys id");
80 }
81 }
82
83 static bool r600_query_sw_begin(struct r600_common_context *rctx,
84 struct r600_query *rquery)
85 {
86 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
87
88 switch(query->b.type) {
89 case PIPE_QUERY_TIMESTAMP_DISJOINT:
90 case PIPE_QUERY_GPU_FINISHED:
91 break;
92 case R600_QUERY_DRAW_CALLS:
93 query->begin_result = rctx->num_draw_calls;
94 break;
95 case R600_QUERY_SPILL_DRAW_CALLS:
96 query->begin_result = rctx->num_spill_draw_calls;
97 break;
98 case R600_QUERY_COMPUTE_CALLS:
99 query->begin_result = rctx->num_compute_calls;
100 break;
101 case R600_QUERY_SPILL_COMPUTE_CALLS:
102 query->begin_result = rctx->num_spill_compute_calls;
103 break;
104 case R600_QUERY_DMA_CALLS:
105 query->begin_result = rctx->num_dma_calls;
106 break;
107 case R600_QUERY_CP_DMA_CALLS:
108 query->begin_result = rctx->num_cp_dma_calls;
109 break;
110 case R600_QUERY_NUM_VS_FLUSHES:
111 query->begin_result = rctx->num_vs_flushes;
112 break;
113 case R600_QUERY_NUM_PS_FLUSHES:
114 query->begin_result = rctx->num_ps_flushes;
115 break;
116 case R600_QUERY_NUM_CS_FLUSHES:
117 query->begin_result = rctx->num_cs_flushes;
118 break;
119 case R600_QUERY_NUM_FB_CACHE_FLUSHES:
120 query->begin_result = rctx->num_fb_cache_flushes;
121 break;
122 case R600_QUERY_NUM_L2_INVALIDATES:
123 query->begin_result = rctx->num_L2_invalidates;
124 break;
125 case R600_QUERY_NUM_L2_WRITEBACKS:
126 query->begin_result = rctx->num_L2_writebacks;
127 break;
128 case R600_QUERY_REQUESTED_VRAM:
129 case R600_QUERY_REQUESTED_GTT:
130 case R600_QUERY_MAPPED_VRAM:
131 case R600_QUERY_MAPPED_GTT:
132 case R600_QUERY_VRAM_USAGE:
133 case R600_QUERY_VRAM_VIS_USAGE:
134 case R600_QUERY_GTT_USAGE:
135 case R600_QUERY_GPU_TEMPERATURE:
136 case R600_QUERY_CURRENT_GPU_SCLK:
137 case R600_QUERY_CURRENT_GPU_MCLK:
138 case R600_QUERY_BACK_BUFFER_PS_DRAW_RATIO:
139 case R600_QUERY_NUM_MAPPED_BUFFERS:
140 query->begin_result = 0;
141 break;
142 case R600_QUERY_BUFFER_WAIT_TIME:
143 case R600_QUERY_NUM_GFX_IBS:
144 case R600_QUERY_NUM_SDMA_IBS:
145 case R600_QUERY_NUM_BYTES_MOVED:
146 case R600_QUERY_NUM_EVICTIONS: {
147 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
148 query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
149 break;
150 }
151 case R600_QUERY_GPU_LOAD:
152 case R600_QUERY_GPU_SHADERS_BUSY:
153 case R600_QUERY_GPU_TA_BUSY:
154 case R600_QUERY_GPU_GDS_BUSY:
155 case R600_QUERY_GPU_VGT_BUSY:
156 case R600_QUERY_GPU_IA_BUSY:
157 case R600_QUERY_GPU_SX_BUSY:
158 case R600_QUERY_GPU_WD_BUSY:
159 case R600_QUERY_GPU_BCI_BUSY:
160 case R600_QUERY_GPU_SC_BUSY:
161 case R600_QUERY_GPU_PA_BUSY:
162 case R600_QUERY_GPU_DB_BUSY:
163 case R600_QUERY_GPU_CP_BUSY:
164 case R600_QUERY_GPU_CB_BUSY:
165 query->begin_result = r600_begin_counter(rctx->screen,
166 query->b.type);
167 break;
168 case R600_QUERY_NUM_COMPILATIONS:
169 query->begin_result = p_atomic_read(&rctx->screen->num_compilations);
170 break;
171 case R600_QUERY_NUM_SHADERS_CREATED:
172 query->begin_result = p_atomic_read(&rctx->screen->num_shaders_created);
173 break;
174 case R600_QUERY_NUM_SHADER_CACHE_HITS:
175 query->begin_result =
176 p_atomic_read(&rctx->screen->num_shader_cache_hits);
177 break;
178 case R600_QUERY_GPIN_ASIC_ID:
179 case R600_QUERY_GPIN_NUM_SIMD:
180 case R600_QUERY_GPIN_NUM_RB:
181 case R600_QUERY_GPIN_NUM_SPI:
182 case R600_QUERY_GPIN_NUM_SE:
183 break;
184 default:
185 unreachable("r600_query_sw_begin: bad query type");
186 }
187
188 return true;
189 }
190
191 static bool r600_query_sw_end(struct r600_common_context *rctx,
192 struct r600_query *rquery)
193 {
194 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
195
196 switch(query->b.type) {
197 case PIPE_QUERY_TIMESTAMP_DISJOINT:
198 break;
199 case PIPE_QUERY_GPU_FINISHED:
200 rctx->b.flush(&rctx->b, &query->fence, PIPE_FLUSH_DEFERRED);
201 break;
202 case R600_QUERY_DRAW_CALLS:
203 query->end_result = rctx->num_draw_calls;
204 break;
205 case R600_QUERY_SPILL_DRAW_CALLS:
206 query->end_result = rctx->num_spill_draw_calls;
207 break;
208 case R600_QUERY_COMPUTE_CALLS:
209 query->end_result = rctx->num_compute_calls;
210 break;
211 case R600_QUERY_SPILL_COMPUTE_CALLS:
212 query->end_result = rctx->num_spill_compute_calls;
213 break;
214 case R600_QUERY_DMA_CALLS:
215 query->end_result = rctx->num_dma_calls;
216 break;
217 case R600_QUERY_CP_DMA_CALLS:
218 query->end_result = rctx->num_cp_dma_calls;
219 break;
220 case R600_QUERY_NUM_VS_FLUSHES:
221 query->end_result = rctx->num_vs_flushes;
222 break;
223 case R600_QUERY_NUM_PS_FLUSHES:
224 query->end_result = rctx->num_ps_flushes;
225 break;
226 case R600_QUERY_NUM_CS_FLUSHES:
227 query->end_result = rctx->num_cs_flushes;
228 break;
229 case R600_QUERY_NUM_FB_CACHE_FLUSHES:
230 query->end_result = rctx->num_fb_cache_flushes;
231 break;
232 case R600_QUERY_NUM_L2_INVALIDATES:
233 query->end_result = rctx->num_L2_invalidates;
234 break;
235 case R600_QUERY_NUM_L2_WRITEBACKS:
236 query->end_result = rctx->num_L2_writebacks;
237 break;
238 case R600_QUERY_REQUESTED_VRAM:
239 case R600_QUERY_REQUESTED_GTT:
240 case R600_QUERY_MAPPED_VRAM:
241 case R600_QUERY_MAPPED_GTT:
242 case R600_QUERY_VRAM_USAGE:
243 case R600_QUERY_VRAM_VIS_USAGE:
244 case R600_QUERY_GTT_USAGE:
245 case R600_QUERY_GPU_TEMPERATURE:
246 case R600_QUERY_CURRENT_GPU_SCLK:
247 case R600_QUERY_CURRENT_GPU_MCLK:
248 case R600_QUERY_BUFFER_WAIT_TIME:
249 case R600_QUERY_NUM_MAPPED_BUFFERS:
250 case R600_QUERY_NUM_GFX_IBS:
251 case R600_QUERY_NUM_SDMA_IBS:
252 case R600_QUERY_NUM_BYTES_MOVED:
253 case R600_QUERY_NUM_EVICTIONS: {
254 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
255 query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
256 break;
257 }
258 case R600_QUERY_GPU_LOAD:
259 case R600_QUERY_GPU_SHADERS_BUSY:
260 case R600_QUERY_GPU_TA_BUSY:
261 case R600_QUERY_GPU_GDS_BUSY:
262 case R600_QUERY_GPU_VGT_BUSY:
263 case R600_QUERY_GPU_IA_BUSY:
264 case R600_QUERY_GPU_SX_BUSY:
265 case R600_QUERY_GPU_WD_BUSY:
266 case R600_QUERY_GPU_BCI_BUSY:
267 case R600_QUERY_GPU_SC_BUSY:
268 case R600_QUERY_GPU_PA_BUSY:
269 case R600_QUERY_GPU_DB_BUSY:
270 case R600_QUERY_GPU_CP_BUSY:
271 case R600_QUERY_GPU_CB_BUSY:
272 query->end_result = r600_end_counter(rctx->screen,
273 query->b.type,
274 query->begin_result);
275 query->begin_result = 0;
276 break;
277 case R600_QUERY_NUM_COMPILATIONS:
278 query->end_result = p_atomic_read(&rctx->screen->num_compilations);
279 break;
280 case R600_QUERY_NUM_SHADERS_CREATED:
281 query->end_result = p_atomic_read(&rctx->screen->num_shaders_created);
282 break;
283 case R600_QUERY_BACK_BUFFER_PS_DRAW_RATIO:
284 query->end_result = rctx->last_tex_ps_draw_ratio;
285 break;
286 case R600_QUERY_NUM_SHADER_CACHE_HITS:
287 query->end_result =
288 p_atomic_read(&rctx->screen->num_shader_cache_hits);
289 break;
290 case R600_QUERY_GPIN_ASIC_ID:
291 case R600_QUERY_GPIN_NUM_SIMD:
292 case R600_QUERY_GPIN_NUM_RB:
293 case R600_QUERY_GPIN_NUM_SPI:
294 case R600_QUERY_GPIN_NUM_SE:
295 break;
296 default:
297 unreachable("r600_query_sw_end: bad query type");
298 }
299
300 return true;
301 }
302
303 static bool r600_query_sw_get_result(struct r600_common_context *rctx,
304 struct r600_query *rquery,
305 bool wait,
306 union pipe_query_result *result)
307 {
308 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
309
310 switch (query->b.type) {
311 case PIPE_QUERY_TIMESTAMP_DISJOINT:
312 /* Convert from cycles per millisecond to cycles per second (Hz). */
313 result->timestamp_disjoint.frequency =
314 (uint64_t)rctx->screen->info.clock_crystal_freq * 1000;
315 result->timestamp_disjoint.disjoint = false;
316 return true;
317 case PIPE_QUERY_GPU_FINISHED: {
318 struct pipe_screen *screen = rctx->b.screen;
319 result->b = screen->fence_finish(screen, &rctx->b, query->fence,
320 wait ? PIPE_TIMEOUT_INFINITE : 0);
321 return result->b;
322 }
323
324 case R600_QUERY_GPIN_ASIC_ID:
325 result->u32 = 0;
326 return true;
327 case R600_QUERY_GPIN_NUM_SIMD:
328 result->u32 = rctx->screen->info.num_good_compute_units;
329 return true;
330 case R600_QUERY_GPIN_NUM_RB:
331 result->u32 = rctx->screen->info.num_render_backends;
332 return true;
333 case R600_QUERY_GPIN_NUM_SPI:
334 result->u32 = 1; /* all supported chips have one SPI per SE */
335 return true;
336 case R600_QUERY_GPIN_NUM_SE:
337 result->u32 = rctx->screen->info.max_se;
338 return true;
339 }
340
341 result->u64 = query->end_result - query->begin_result;
342
343 switch (query->b.type) {
344 case R600_QUERY_BUFFER_WAIT_TIME:
345 case R600_QUERY_GPU_TEMPERATURE:
346 result->u64 /= 1000;
347 break;
348 case R600_QUERY_CURRENT_GPU_SCLK:
349 case R600_QUERY_CURRENT_GPU_MCLK:
350 result->u64 *= 1000000;
351 break;
352 }
353
354 return true;
355 }
356
357
358 static struct r600_query_ops sw_query_ops = {
359 .destroy = r600_query_sw_destroy,
360 .begin = r600_query_sw_begin,
361 .end = r600_query_sw_end,
362 .get_result = r600_query_sw_get_result,
363 .get_result_resource = NULL
364 };
365
366 static struct pipe_query *r600_query_sw_create(struct pipe_context *ctx,
367 unsigned query_type)
368 {
369 struct r600_query_sw *query;
370
371 query = CALLOC_STRUCT(r600_query_sw);
372 if (!query)
373 return NULL;
374
375 query->b.type = query_type;
376 query->b.ops = &sw_query_ops;
377
378 return (struct pipe_query *)query;
379 }
380
381 void r600_query_hw_destroy(struct r600_common_context *rctx,
382 struct r600_query *rquery)
383 {
384 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
385 struct r600_query_buffer *prev = query->buffer.previous;
386
387 /* Release all query buffers. */
388 while (prev) {
389 struct r600_query_buffer *qbuf = prev;
390 prev = prev->previous;
391 r600_resource_reference(&qbuf->buf, NULL);
392 FREE(qbuf);
393 }
394
395 r600_resource_reference(&query->buffer.buf, NULL);
396 FREE(rquery);
397 }
398
399 static struct r600_resource *r600_new_query_buffer(struct r600_common_context *ctx,
400 struct r600_query_hw *query)
401 {
402 unsigned buf_size = MAX2(query->result_size,
403 ctx->screen->info.min_alloc_size);
404
405 /* Queries are normally read by the CPU after
406 * being written by the gpu, hence staging is probably a good
407 * usage pattern.
408 */
409 struct r600_resource *buf = (struct r600_resource*)
410 pipe_buffer_create(ctx->b.screen, 0,
411 PIPE_USAGE_STAGING, buf_size);
412 if (!buf)
413 return NULL;
414
415 if (!query->ops->prepare_buffer(ctx, query, buf)) {
416 r600_resource_reference(&buf, NULL);
417 return NULL;
418 }
419
420 return buf;
421 }
422
423 static bool r600_query_hw_prepare_buffer(struct r600_common_context *ctx,
424 struct r600_query_hw *query,
425 struct r600_resource *buffer)
426 {
427 /* Callers ensure that the buffer is currently unused by the GPU. */
428 uint32_t *results = ctx->ws->buffer_map(buffer->buf, NULL,
429 PIPE_TRANSFER_WRITE |
430 PIPE_TRANSFER_UNSYNCHRONIZED);
431 if (!results)
432 return false;
433
434 memset(results, 0, buffer->b.b.width0);
435
436 if (query->b.type == PIPE_QUERY_OCCLUSION_COUNTER ||
437 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE) {
438 unsigned max_rbs = ctx->screen->info.num_render_backends;
439 unsigned enabled_rb_mask = ctx->screen->info.enabled_rb_mask;
440 unsigned num_results;
441 unsigned i, j;
442
443 /* Set top bits for unused backends. */
444 num_results = buffer->b.b.width0 / query->result_size;
445 for (j = 0; j < num_results; j++) {
446 for (i = 0; i < max_rbs; i++) {
447 if (!(enabled_rb_mask & (1<<i))) {
448 results[(i * 4)+1] = 0x80000000;
449 results[(i * 4)+3] = 0x80000000;
450 }
451 }
452 results += 4 * max_rbs;
453 }
454 }
455
456 return true;
457 }
458
459 static void r600_query_hw_get_result_resource(struct r600_common_context *rctx,
460 struct r600_query *rquery,
461 bool wait,
462 enum pipe_query_value_type result_type,
463 int index,
464 struct pipe_resource *resource,
465 unsigned offset);
466
467 static struct r600_query_ops query_hw_ops = {
468 .destroy = r600_query_hw_destroy,
469 .begin = r600_query_hw_begin,
470 .end = r600_query_hw_end,
471 .get_result = r600_query_hw_get_result,
472 .get_result_resource = r600_query_hw_get_result_resource,
473 };
474
475 static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
476 struct r600_query_hw *query,
477 struct r600_resource *buffer,
478 uint64_t va);
479 static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
480 struct r600_query_hw *query,
481 struct r600_resource *buffer,
482 uint64_t va);
483 static void r600_query_hw_add_result(struct r600_common_context *ctx,
484 struct r600_query_hw *, void *buffer,
485 union pipe_query_result *result);
486 static void r600_query_hw_clear_result(struct r600_query_hw *,
487 union pipe_query_result *);
488
489 static struct r600_query_hw_ops query_hw_default_hw_ops = {
490 .prepare_buffer = r600_query_hw_prepare_buffer,
491 .emit_start = r600_query_hw_do_emit_start,
492 .emit_stop = r600_query_hw_do_emit_stop,
493 .clear_result = r600_query_hw_clear_result,
494 .add_result = r600_query_hw_add_result,
495 };
496
497 bool r600_query_hw_init(struct r600_common_context *rctx,
498 struct r600_query_hw *query)
499 {
500 query->buffer.buf = r600_new_query_buffer(rctx, query);
501 if (!query->buffer.buf)
502 return false;
503
504 return true;
505 }
506
507 static struct pipe_query *r600_query_hw_create(struct r600_common_context *rctx,
508 unsigned query_type,
509 unsigned index)
510 {
511 struct r600_query_hw *query = CALLOC_STRUCT(r600_query_hw);
512 if (!query)
513 return NULL;
514
515 query->b.type = query_type;
516 query->b.ops = &query_hw_ops;
517 query->ops = &query_hw_default_hw_ops;
518
519 switch (query_type) {
520 case PIPE_QUERY_OCCLUSION_COUNTER:
521 case PIPE_QUERY_OCCLUSION_PREDICATE:
522 query->result_size = 16 * rctx->screen->info.num_render_backends;
523 query->result_size += 16; /* for the fence + alignment */
524 query->num_cs_dw_begin = 6;
525 query->num_cs_dw_end = 6 + r600_gfx_write_fence_dwords(rctx->screen);
526 break;
527 case PIPE_QUERY_TIME_ELAPSED:
528 query->result_size = 24;
529 query->num_cs_dw_begin = 8;
530 query->num_cs_dw_end = 8 + r600_gfx_write_fence_dwords(rctx->screen);
531 break;
532 case PIPE_QUERY_TIMESTAMP:
533 query->result_size = 16;
534 query->num_cs_dw_end = 8 + r600_gfx_write_fence_dwords(rctx->screen);
535 query->flags = R600_QUERY_HW_FLAG_NO_START;
536 break;
537 case PIPE_QUERY_PRIMITIVES_EMITTED:
538 case PIPE_QUERY_PRIMITIVES_GENERATED:
539 case PIPE_QUERY_SO_STATISTICS:
540 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
541 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
542 query->result_size = 32;
543 query->num_cs_dw_begin = 6;
544 query->num_cs_dw_end = 6;
545 query->stream = index;
546 break;
547 case PIPE_QUERY_PIPELINE_STATISTICS:
548 /* 11 values on EG, 8 on R600. */
549 query->result_size = (rctx->chip_class >= EVERGREEN ? 11 : 8) * 16;
550 query->result_size += 8; /* for the fence + alignment */
551 query->num_cs_dw_begin = 6;
552 query->num_cs_dw_end = 6 + r600_gfx_write_fence_dwords(rctx->screen);
553 break;
554 default:
555 assert(0);
556 FREE(query);
557 return NULL;
558 }
559
560 if (!r600_query_hw_init(rctx, query)) {
561 FREE(query);
562 return NULL;
563 }
564
565 return (struct pipe_query *)query;
566 }
567
568 static void r600_update_occlusion_query_state(struct r600_common_context *rctx,
569 unsigned type, int diff)
570 {
571 if (type == PIPE_QUERY_OCCLUSION_COUNTER ||
572 type == PIPE_QUERY_OCCLUSION_PREDICATE) {
573 bool old_enable = rctx->num_occlusion_queries != 0;
574 bool old_perfect_enable =
575 rctx->num_perfect_occlusion_queries != 0;
576 bool enable, perfect_enable;
577
578 rctx->num_occlusion_queries += diff;
579 assert(rctx->num_occlusion_queries >= 0);
580
581 if (type == PIPE_QUERY_OCCLUSION_COUNTER) {
582 rctx->num_perfect_occlusion_queries += diff;
583 assert(rctx->num_perfect_occlusion_queries >= 0);
584 }
585
586 enable = rctx->num_occlusion_queries != 0;
587 perfect_enable = rctx->num_perfect_occlusion_queries != 0;
588
589 if (enable != old_enable || perfect_enable != old_perfect_enable) {
590 rctx->set_occlusion_query_state(&rctx->b, enable);
591 }
592 }
593 }
594
595 static unsigned event_type_for_stream(struct r600_query_hw *query)
596 {
597 switch (query->stream) {
598 default:
599 case 0: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS;
600 case 1: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS1;
601 case 2: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS2;
602 case 3: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS3;
603 }
604 }
605
606 static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
607 struct r600_query_hw *query,
608 struct r600_resource *buffer,
609 uint64_t va)
610 {
611 struct radeon_winsys_cs *cs = ctx->gfx.cs;
612
613 switch (query->b.type) {
614 case PIPE_QUERY_OCCLUSION_COUNTER:
615 case PIPE_QUERY_OCCLUSION_PREDICATE:
616 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
617 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
618 radeon_emit(cs, va);
619 radeon_emit(cs, (va >> 32) & 0xFFFF);
620 break;
621 case PIPE_QUERY_PRIMITIVES_EMITTED:
622 case PIPE_QUERY_PRIMITIVES_GENERATED:
623 case PIPE_QUERY_SO_STATISTICS:
624 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
625 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
626 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | EVENT_INDEX(3));
627 radeon_emit(cs, va);
628 radeon_emit(cs, (va >> 32) & 0xFFFF);
629 break;
630 case PIPE_QUERY_TIME_ELAPSED:
631 r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
632 0, 3, NULL, va, 0, 0);
633 break;
634 case PIPE_QUERY_PIPELINE_STATISTICS:
635 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
636 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
637 radeon_emit(cs, va);
638 radeon_emit(cs, (va >> 32) & 0xFFFF);
639 break;
640 default:
641 assert(0);
642 }
643 r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE,
644 RADEON_PRIO_QUERY);
645 }
646
647 static void r600_query_hw_emit_start(struct r600_common_context *ctx,
648 struct r600_query_hw *query)
649 {
650 uint64_t va;
651
652 if (!query->buffer.buf)
653 return; // previous buffer allocation failure
654
655 r600_update_occlusion_query_state(ctx, query->b.type, 1);
656 r600_update_prims_generated_query_state(ctx, query->b.type, 1);
657
658 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw_begin + query->num_cs_dw_end,
659 true);
660
661 /* Get a new query buffer if needed. */
662 if (query->buffer.results_end + query->result_size > query->buffer.buf->b.b.width0) {
663 struct r600_query_buffer *qbuf = MALLOC_STRUCT(r600_query_buffer);
664 *qbuf = query->buffer;
665 query->buffer.results_end = 0;
666 query->buffer.previous = qbuf;
667 query->buffer.buf = r600_new_query_buffer(ctx, query);
668 if (!query->buffer.buf)
669 return;
670 }
671
672 /* emit begin query */
673 va = query->buffer.buf->gpu_address + query->buffer.results_end;
674
675 query->ops->emit_start(ctx, query, query->buffer.buf, va);
676
677 ctx->num_cs_dw_queries_suspend += query->num_cs_dw_end;
678 }
679
680 static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
681 struct r600_query_hw *query,
682 struct r600_resource *buffer,
683 uint64_t va)
684 {
685 struct radeon_winsys_cs *cs = ctx->gfx.cs;
686 uint64_t fence_va = 0;
687
688 switch (query->b.type) {
689 case PIPE_QUERY_OCCLUSION_COUNTER:
690 case PIPE_QUERY_OCCLUSION_PREDICATE:
691 va += 8;
692 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
693 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
694 radeon_emit(cs, va);
695 radeon_emit(cs, (va >> 32) & 0xFFFF);
696
697 fence_va = va + ctx->screen->info.num_render_backends * 16 - 8;
698 break;
699 case PIPE_QUERY_PRIMITIVES_EMITTED:
700 case PIPE_QUERY_PRIMITIVES_GENERATED:
701 case PIPE_QUERY_SO_STATISTICS:
702 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
703 va += query->result_size/2;
704 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
705 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | EVENT_INDEX(3));
706 radeon_emit(cs, va);
707 radeon_emit(cs, (va >> 32) & 0xFFFF);
708 break;
709 case PIPE_QUERY_TIME_ELAPSED:
710 va += 8;
711 /* fall through */
712 case PIPE_QUERY_TIMESTAMP:
713 r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
714 0, 3, NULL, va, 0, 0);
715 fence_va = va + 8;
716 break;
717 case PIPE_QUERY_PIPELINE_STATISTICS: {
718 unsigned sample_size = (query->result_size - 8) / 2;
719
720 va += sample_size;
721 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
722 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
723 radeon_emit(cs, va);
724 radeon_emit(cs, (va >> 32) & 0xFFFF);
725
726 fence_va = va + sample_size;
727 break;
728 }
729 default:
730 assert(0);
731 }
732 r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE,
733 RADEON_PRIO_QUERY);
734
735 if (fence_va)
736 r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0, 1,
737 query->buffer.buf, fence_va, 0, 0x80000000);
738 }
739
740 static void r600_query_hw_emit_stop(struct r600_common_context *ctx,
741 struct r600_query_hw *query)
742 {
743 uint64_t va;
744
745 if (!query->buffer.buf)
746 return; // previous buffer allocation failure
747
748 /* The queries which need begin already called this in begin_query. */
749 if (query->flags & R600_QUERY_HW_FLAG_NO_START) {
750 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw_end, false);
751 }
752
753 /* emit end query */
754 va = query->buffer.buf->gpu_address + query->buffer.results_end;
755
756 query->ops->emit_stop(ctx, query, query->buffer.buf, va);
757
758 query->buffer.results_end += query->result_size;
759
760 if (!(query->flags & R600_QUERY_HW_FLAG_NO_START))
761 ctx->num_cs_dw_queries_suspend -= query->num_cs_dw_end;
762
763 r600_update_occlusion_query_state(ctx, query->b.type, -1);
764 r600_update_prims_generated_query_state(ctx, query->b.type, -1);
765 }
766
767 static void r600_emit_query_predication(struct r600_common_context *ctx,
768 struct r600_atom *atom)
769 {
770 struct radeon_winsys_cs *cs = ctx->gfx.cs;
771 struct r600_query_hw *query = (struct r600_query_hw *)ctx->render_cond;
772 struct r600_query_buffer *qbuf;
773 uint32_t op;
774 bool flag_wait;
775
776 if (!query)
777 return;
778
779 flag_wait = ctx->render_cond_mode == PIPE_RENDER_COND_WAIT ||
780 ctx->render_cond_mode == PIPE_RENDER_COND_BY_REGION_WAIT;
781
782 switch (query->b.type) {
783 case PIPE_QUERY_OCCLUSION_COUNTER:
784 case PIPE_QUERY_OCCLUSION_PREDICATE:
785 op = PRED_OP(PREDICATION_OP_ZPASS);
786 break;
787 case PIPE_QUERY_PRIMITIVES_EMITTED:
788 case PIPE_QUERY_PRIMITIVES_GENERATED:
789 case PIPE_QUERY_SO_STATISTICS:
790 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
791 op = PRED_OP(PREDICATION_OP_PRIMCOUNT);
792 break;
793 default:
794 assert(0);
795 return;
796 }
797
798 /* if true then invert, see GL_ARB_conditional_render_inverted */
799 if (ctx->render_cond_invert)
800 op |= PREDICATION_DRAW_NOT_VISIBLE; /* Draw if not visable/overflow */
801 else
802 op |= PREDICATION_DRAW_VISIBLE; /* Draw if visable/overflow */
803
804 op |= flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW;
805
806 /* emit predicate packets for all data blocks */
807 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
808 unsigned results_base = 0;
809 uint64_t va = qbuf->buf->gpu_address;
810
811 while (results_base < qbuf->results_end) {
812 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
813 radeon_emit(cs, va + results_base);
814 radeon_emit(cs, op | (((va + results_base) >> 32) & 0xFF));
815 r600_emit_reloc(ctx, &ctx->gfx, qbuf->buf, RADEON_USAGE_READ,
816 RADEON_PRIO_QUERY);
817 results_base += query->result_size;
818
819 /* set CONTINUE bit for all packets except the first */
820 op |= PREDICATION_CONTINUE;
821 }
822 }
823 }
824
825 static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type, unsigned index)
826 {
827 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
828
829 if (query_type == PIPE_QUERY_TIMESTAMP_DISJOINT ||
830 query_type == PIPE_QUERY_GPU_FINISHED ||
831 query_type >= PIPE_QUERY_DRIVER_SPECIFIC)
832 return r600_query_sw_create(ctx, query_type);
833
834 return r600_query_hw_create(rctx, query_type, index);
835 }
836
837 static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
838 {
839 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
840 struct r600_query *rquery = (struct r600_query *)query;
841
842 rquery->ops->destroy(rctx, rquery);
843 }
844
845 static boolean r600_begin_query(struct pipe_context *ctx,
846 struct pipe_query *query)
847 {
848 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
849 struct r600_query *rquery = (struct r600_query *)query;
850
851 return rquery->ops->begin(rctx, rquery);
852 }
853
854 void r600_query_hw_reset_buffers(struct r600_common_context *rctx,
855 struct r600_query_hw *query)
856 {
857 struct r600_query_buffer *prev = query->buffer.previous;
858
859 /* Discard the old query buffers. */
860 while (prev) {
861 struct r600_query_buffer *qbuf = prev;
862 prev = prev->previous;
863 r600_resource_reference(&qbuf->buf, NULL);
864 FREE(qbuf);
865 }
866
867 query->buffer.results_end = 0;
868 query->buffer.previous = NULL;
869
870 /* Obtain a new buffer if the current one can't be mapped without a stall. */
871 if (r600_rings_is_buffer_referenced(rctx, query->buffer.buf->buf, RADEON_USAGE_READWRITE) ||
872 !rctx->ws->buffer_wait(query->buffer.buf->buf, 0, RADEON_USAGE_READWRITE)) {
873 r600_resource_reference(&query->buffer.buf, NULL);
874 query->buffer.buf = r600_new_query_buffer(rctx, query);
875 } else {
876 if (!query->ops->prepare_buffer(rctx, query, query->buffer.buf))
877 r600_resource_reference(&query->buffer.buf, NULL);
878 }
879 }
880
881 bool r600_query_hw_begin(struct r600_common_context *rctx,
882 struct r600_query *rquery)
883 {
884 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
885
886 if (query->flags & R600_QUERY_HW_FLAG_NO_START) {
887 assert(0);
888 return false;
889 }
890
891 if (!(query->flags & R600_QUERY_HW_FLAG_BEGIN_RESUMES))
892 r600_query_hw_reset_buffers(rctx, query);
893
894 r600_query_hw_emit_start(rctx, query);
895 if (!query->buffer.buf)
896 return false;
897
898 LIST_ADDTAIL(&query->list, &rctx->active_queries);
899 return true;
900 }
901
902 static bool r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
903 {
904 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
905 struct r600_query *rquery = (struct r600_query *)query;
906
907 return rquery->ops->end(rctx, rquery);
908 }
909
910 bool r600_query_hw_end(struct r600_common_context *rctx,
911 struct r600_query *rquery)
912 {
913 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
914
915 if (query->flags & R600_QUERY_HW_FLAG_NO_START)
916 r600_query_hw_reset_buffers(rctx, query);
917
918 r600_query_hw_emit_stop(rctx, query);
919
920 if (!(query->flags & R600_QUERY_HW_FLAG_NO_START))
921 LIST_DELINIT(&query->list);
922
923 if (!query->buffer.buf)
924 return false;
925
926 return true;
927 }
928
929 static void r600_get_hw_query_params(struct r600_common_context *rctx,
930 struct r600_query_hw *rquery, int index,
931 struct r600_hw_query_params *params)
932 {
933 unsigned max_rbs = rctx->screen->info.num_render_backends;
934
935 params->pair_stride = 0;
936 params->pair_count = 1;
937
938 switch (rquery->b.type) {
939 case PIPE_QUERY_OCCLUSION_COUNTER:
940 case PIPE_QUERY_OCCLUSION_PREDICATE:
941 params->start_offset = 0;
942 params->end_offset = 8;
943 params->fence_offset = max_rbs * 16;
944 params->pair_stride = 16;
945 params->pair_count = max_rbs;
946 break;
947 case PIPE_QUERY_TIME_ELAPSED:
948 params->start_offset = 0;
949 params->end_offset = 8;
950 params->fence_offset = 16;
951 break;
952 case PIPE_QUERY_TIMESTAMP:
953 params->start_offset = 0;
954 params->end_offset = 0;
955 params->fence_offset = 8;
956 break;
957 case PIPE_QUERY_PRIMITIVES_EMITTED:
958 params->start_offset = 8;
959 params->end_offset = 24;
960 params->fence_offset = params->end_offset + 4;
961 break;
962 case PIPE_QUERY_PRIMITIVES_GENERATED:
963 params->start_offset = 0;
964 params->end_offset = 16;
965 params->fence_offset = params->end_offset + 4;
966 break;
967 case PIPE_QUERY_SO_STATISTICS:
968 params->start_offset = 8 - index * 8;
969 params->end_offset = 24 - index * 8;
970 params->fence_offset = params->end_offset + 4;
971 break;
972 case PIPE_QUERY_PIPELINE_STATISTICS:
973 {
974 /* Offsets apply to EG+ */
975 static const unsigned offsets[] = {56, 48, 24, 32, 40, 16, 8, 0, 64, 72, 80};
976 params->start_offset = offsets[index];
977 params->end_offset = 88 + offsets[index];
978 params->fence_offset = 2 * 88;
979 break;
980 }
981 default:
982 unreachable("r600_get_hw_query_params unsupported");
983 }
984 }
985
986 static unsigned r600_query_read_result(void *map, unsigned start_index, unsigned end_index,
987 bool test_status_bit)
988 {
989 uint32_t *current_result = (uint32_t*)map;
990 uint64_t start, end;
991
992 start = (uint64_t)current_result[start_index] |
993 (uint64_t)current_result[start_index+1] << 32;
994 end = (uint64_t)current_result[end_index] |
995 (uint64_t)current_result[end_index+1] << 32;
996
997 if (!test_status_bit ||
998 ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) {
999 return end - start;
1000 }
1001 return 0;
1002 }
1003
1004 static void r600_query_hw_add_result(struct r600_common_context *ctx,
1005 struct r600_query_hw *query,
1006 void *buffer,
1007 union pipe_query_result *result)
1008 {
1009 unsigned max_rbs = ctx->screen->info.num_render_backends;
1010
1011 switch (query->b.type) {
1012 case PIPE_QUERY_OCCLUSION_COUNTER: {
1013 for (unsigned i = 0; i < max_rbs; ++i) {
1014 unsigned results_base = i * 16;
1015 result->u64 +=
1016 r600_query_read_result(buffer + results_base, 0, 2, true);
1017 }
1018 break;
1019 }
1020 case PIPE_QUERY_OCCLUSION_PREDICATE: {
1021 for (unsigned i = 0; i < max_rbs; ++i) {
1022 unsigned results_base = i * 16;
1023 result->b = result->b ||
1024 r600_query_read_result(buffer + results_base, 0, 2, true) != 0;
1025 }
1026 break;
1027 }
1028 case PIPE_QUERY_TIME_ELAPSED:
1029 result->u64 += r600_query_read_result(buffer, 0, 2, false);
1030 break;
1031 case PIPE_QUERY_TIMESTAMP:
1032 result->u64 = *(uint64_t*)buffer;
1033 break;
1034 case PIPE_QUERY_PRIMITIVES_EMITTED:
1035 /* SAMPLE_STREAMOUTSTATS stores this structure:
1036 * {
1037 * u64 NumPrimitivesWritten;
1038 * u64 PrimitiveStorageNeeded;
1039 * }
1040 * We only need NumPrimitivesWritten here. */
1041 result->u64 += r600_query_read_result(buffer, 2, 6, true);
1042 break;
1043 case PIPE_QUERY_PRIMITIVES_GENERATED:
1044 /* Here we read PrimitiveStorageNeeded. */
1045 result->u64 += r600_query_read_result(buffer, 0, 4, true);
1046 break;
1047 case PIPE_QUERY_SO_STATISTICS:
1048 result->so_statistics.num_primitives_written +=
1049 r600_query_read_result(buffer, 2, 6, true);
1050 result->so_statistics.primitives_storage_needed +=
1051 r600_query_read_result(buffer, 0, 4, true);
1052 break;
1053 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1054 result->b = result->b ||
1055 r600_query_read_result(buffer, 2, 6, true) !=
1056 r600_query_read_result(buffer, 0, 4, true);
1057 break;
1058 case PIPE_QUERY_PIPELINE_STATISTICS:
1059 if (ctx->chip_class >= EVERGREEN) {
1060 result->pipeline_statistics.ps_invocations +=
1061 r600_query_read_result(buffer, 0, 22, false);
1062 result->pipeline_statistics.c_primitives +=
1063 r600_query_read_result(buffer, 2, 24, false);
1064 result->pipeline_statistics.c_invocations +=
1065 r600_query_read_result(buffer, 4, 26, false);
1066 result->pipeline_statistics.vs_invocations +=
1067 r600_query_read_result(buffer, 6, 28, false);
1068 result->pipeline_statistics.gs_invocations +=
1069 r600_query_read_result(buffer, 8, 30, false);
1070 result->pipeline_statistics.gs_primitives +=
1071 r600_query_read_result(buffer, 10, 32, false);
1072 result->pipeline_statistics.ia_primitives +=
1073 r600_query_read_result(buffer, 12, 34, false);
1074 result->pipeline_statistics.ia_vertices +=
1075 r600_query_read_result(buffer, 14, 36, false);
1076 result->pipeline_statistics.hs_invocations +=
1077 r600_query_read_result(buffer, 16, 38, false);
1078 result->pipeline_statistics.ds_invocations +=
1079 r600_query_read_result(buffer, 18, 40, false);
1080 result->pipeline_statistics.cs_invocations +=
1081 r600_query_read_result(buffer, 20, 42, false);
1082 } else {
1083 result->pipeline_statistics.ps_invocations +=
1084 r600_query_read_result(buffer, 0, 16, false);
1085 result->pipeline_statistics.c_primitives +=
1086 r600_query_read_result(buffer, 2, 18, false);
1087 result->pipeline_statistics.c_invocations +=
1088 r600_query_read_result(buffer, 4, 20, false);
1089 result->pipeline_statistics.vs_invocations +=
1090 r600_query_read_result(buffer, 6, 22, false);
1091 result->pipeline_statistics.gs_invocations +=
1092 r600_query_read_result(buffer, 8, 24, false);
1093 result->pipeline_statistics.gs_primitives +=
1094 r600_query_read_result(buffer, 10, 26, false);
1095 result->pipeline_statistics.ia_primitives +=
1096 r600_query_read_result(buffer, 12, 28, false);
1097 result->pipeline_statistics.ia_vertices +=
1098 r600_query_read_result(buffer, 14, 30, false);
1099 }
1100 #if 0 /* for testing */
1101 printf("Pipeline stats: IA verts=%llu, IA prims=%llu, VS=%llu, HS=%llu, "
1102 "DS=%llu, GS=%llu, GS prims=%llu, Clipper=%llu, "
1103 "Clipper prims=%llu, PS=%llu, CS=%llu\n",
1104 result->pipeline_statistics.ia_vertices,
1105 result->pipeline_statistics.ia_primitives,
1106 result->pipeline_statistics.vs_invocations,
1107 result->pipeline_statistics.hs_invocations,
1108 result->pipeline_statistics.ds_invocations,
1109 result->pipeline_statistics.gs_invocations,
1110 result->pipeline_statistics.gs_primitives,
1111 result->pipeline_statistics.c_invocations,
1112 result->pipeline_statistics.c_primitives,
1113 result->pipeline_statistics.ps_invocations,
1114 result->pipeline_statistics.cs_invocations);
1115 #endif
1116 break;
1117 default:
1118 assert(0);
1119 }
1120 }
1121
1122 static boolean r600_get_query_result(struct pipe_context *ctx,
1123 struct pipe_query *query, boolean wait,
1124 union pipe_query_result *result)
1125 {
1126 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1127 struct r600_query *rquery = (struct r600_query *)query;
1128
1129 return rquery->ops->get_result(rctx, rquery, wait, result);
1130 }
1131
1132 static void r600_get_query_result_resource(struct pipe_context *ctx,
1133 struct pipe_query *query,
1134 boolean wait,
1135 enum pipe_query_value_type result_type,
1136 int index,
1137 struct pipe_resource *resource,
1138 unsigned offset)
1139 {
1140 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1141 struct r600_query *rquery = (struct r600_query *)query;
1142
1143 rquery->ops->get_result_resource(rctx, rquery, wait, result_type, index,
1144 resource, offset);
1145 }
1146
1147 static void r600_query_hw_clear_result(struct r600_query_hw *query,
1148 union pipe_query_result *result)
1149 {
1150 util_query_clear_result(result, query->b.type);
1151 }
1152
1153 bool r600_query_hw_get_result(struct r600_common_context *rctx,
1154 struct r600_query *rquery,
1155 bool wait, union pipe_query_result *result)
1156 {
1157 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
1158 struct r600_query_buffer *qbuf;
1159
1160 query->ops->clear_result(query, result);
1161
1162 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
1163 unsigned results_base = 0;
1164 void *map;
1165
1166 map = r600_buffer_map_sync_with_rings(rctx, qbuf->buf,
1167 PIPE_TRANSFER_READ |
1168 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK));
1169 if (!map)
1170 return false;
1171
1172 while (results_base != qbuf->results_end) {
1173 query->ops->add_result(rctx, query, map + results_base,
1174 result);
1175 results_base += query->result_size;
1176 }
1177 }
1178
1179 /* Convert the time to expected units. */
1180 if (rquery->type == PIPE_QUERY_TIME_ELAPSED ||
1181 rquery->type == PIPE_QUERY_TIMESTAMP) {
1182 result->u64 = (1000000 * result->u64) / rctx->screen->info.clock_crystal_freq;
1183 }
1184 return true;
1185 }
1186
1187 /* Create the compute shader that is used to collect the results.
1188 *
1189 * One compute grid with a single thread is launched for every query result
1190 * buffer. The thread (optionally) reads a previous summary buffer, then
1191 * accumulates data from the query result buffer, and writes the result either
1192 * to a summary buffer to be consumed by the next grid invocation or to the
1193 * user-supplied buffer.
1194 *
1195 * Data layout:
1196 *
1197 * CONST
1198 * 0.x = end_offset
1199 * 0.y = result_stride
1200 * 0.z = result_count
1201 * 0.w = bit field:
1202 * 1: read previously accumulated values
1203 * 2: write accumulated values for chaining
1204 * 4: write result available
1205 * 8: convert result to boolean (0/1)
1206 * 16: only read one dword and use that as result
1207 * 32: apply timestamp conversion
1208 * 64: store full 64 bits result
1209 * 128: store signed 32 bits result
1210 * 1.x = fence_offset
1211 * 1.y = pair_stride
1212 * 1.z = pair_count
1213 *
1214 * BUFFER[0] = query result buffer
1215 * BUFFER[1] = previous summary buffer
1216 * BUFFER[2] = next summary buffer or user-supplied buffer
1217 */
1218 static void r600_create_query_result_shader(struct r600_common_context *rctx)
1219 {
1220 /* TEMP[0].xy = accumulated result so far
1221 * TEMP[0].z = result not available
1222 *
1223 * TEMP[1].x = current result index
1224 * TEMP[1].y = current pair index
1225 */
1226 static const char text_tmpl[] =
1227 "COMP\n"
1228 "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
1229 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
1230 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
1231 "DCL BUFFER[0]\n"
1232 "DCL BUFFER[1]\n"
1233 "DCL BUFFER[2]\n"
1234 "DCL CONST[0..1]\n"
1235 "DCL TEMP[0..5]\n"
1236 "IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n"
1237 "IMM[1] UINT32 {1, 2, 4, 8}\n"
1238 "IMM[2] UINT32 {16, 32, 64, 128}\n"
1239 "IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */
1240
1241 "AND TEMP[5], CONST[0].wwww, IMM[2].xxxx\n"
1242 "UIF TEMP[5]\n"
1243 /* Check result availability. */
1244 "LOAD TEMP[1].x, BUFFER[0], CONST[1].xxxx\n"
1245 "ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n"
1246 "MOV TEMP[1], TEMP[0].zzzz\n"
1247 "NOT TEMP[0].z, TEMP[0].zzzz\n"
1248
1249 /* Load result if available. */
1250 "UIF TEMP[1]\n"
1251 "LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n"
1252 "ENDIF\n"
1253 "ELSE\n"
1254 /* Load previously accumulated result if requested. */
1255 "MOV TEMP[0], IMM[0].xxxx\n"
1256 "AND TEMP[4], CONST[0].wwww, IMM[1].xxxx\n"
1257 "UIF TEMP[4]\n"
1258 "LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n"
1259 "ENDIF\n"
1260
1261 "MOV TEMP[1].x, IMM[0].xxxx\n"
1262 "BGNLOOP\n"
1263 /* Break if accumulated result so far is not available. */
1264 "UIF TEMP[0].zzzz\n"
1265 "BRK\n"
1266 "ENDIF\n"
1267
1268 /* Break if result_index >= result_count. */
1269 "USGE TEMP[5], TEMP[1].xxxx, CONST[0].zzzz\n"
1270 "UIF TEMP[5]\n"
1271 "BRK\n"
1272 "ENDIF\n"
1273
1274 /* Load fence and check result availability */
1275 "UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0].yyyy, CONST[1].xxxx\n"
1276 "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
1277 "ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n"
1278 "NOT TEMP[0].z, TEMP[0].zzzz\n"
1279 "UIF TEMP[0].zzzz\n"
1280 "BRK\n"
1281 "ENDIF\n"
1282
1283 "MOV TEMP[1].y, IMM[0].xxxx\n"
1284 "BGNLOOP\n"
1285 /* Load start and end. */
1286 "UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0].yyyy\n"
1287 "UMAD TEMP[5].x, TEMP[1].yyyy, CONST[1].yyyy, TEMP[5].xxxx\n"
1288 "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
1289
1290 "UADD TEMP[5].x, TEMP[5].xxxx, CONST[0].xxxx\n"
1291 "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].xxxx\n"
1292
1293 "U64ADD TEMP[3].xy, TEMP[3], -TEMP[2]\n"
1294 "U64ADD TEMP[0].xy, TEMP[0], TEMP[3]\n"
1295
1296 /* Increment pair index */
1297 "UADD TEMP[1].y, TEMP[1].yyyy, IMM[1].xxxx\n"
1298 "USGE TEMP[5], TEMP[1].yyyy, CONST[1].zzzz\n"
1299 "UIF TEMP[5]\n"
1300 "BRK\n"
1301 "ENDIF\n"
1302 "ENDLOOP\n"
1303
1304 /* Increment result index */
1305 "UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n"
1306 "ENDLOOP\n"
1307 "ENDIF\n"
1308
1309 "AND TEMP[4], CONST[0].wwww, IMM[1].yyyy\n"
1310 "UIF TEMP[4]\n"
1311 /* Store accumulated data for chaining. */
1312 "STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n"
1313 "ELSE\n"
1314 "AND TEMP[4], CONST[0].wwww, IMM[1].zzzz\n"
1315 "UIF TEMP[4]\n"
1316 /* Store result availability. */
1317 "NOT TEMP[0].z, TEMP[0]\n"
1318 "AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n"
1319 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n"
1320
1321 "AND TEMP[4], CONST[0].wwww, IMM[2].zzzz\n"
1322 "UIF TEMP[4]\n"
1323 "STORE BUFFER[2].y, IMM[0].xxxx, IMM[0].xxxx\n"
1324 "ENDIF\n"
1325 "ELSE\n"
1326 /* Store result if it is available. */
1327 "NOT TEMP[4], TEMP[0].zzzz\n"
1328 "UIF TEMP[4]\n"
1329 /* Apply timestamp conversion */
1330 "AND TEMP[4], CONST[0].wwww, IMM[2].yyyy\n"
1331 "UIF TEMP[4]\n"
1332 "U64MUL TEMP[0].xy, TEMP[0], IMM[3].xyxy\n"
1333 "U64DIV TEMP[0].xy, TEMP[0], IMM[3].zwzw\n"
1334 "ENDIF\n"
1335
1336 /* Convert to boolean */
1337 "AND TEMP[4], CONST[0].wwww, IMM[1].wwww\n"
1338 "UIF TEMP[4]\n"
1339 "U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[0].xxxx\n"
1340 "AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n"
1341 "MOV TEMP[0].y, IMM[0].xxxx\n"
1342 "ENDIF\n"
1343
1344 "AND TEMP[4], CONST[0].wwww, IMM[2].zzzz\n"
1345 "UIF TEMP[4]\n"
1346 "STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0].xyxy\n"
1347 "ELSE\n"
1348 /* Clamping */
1349 "UIF TEMP[0].yyyy\n"
1350 "MOV TEMP[0].x, IMM[0].wwww\n"
1351 "ENDIF\n"
1352
1353 "AND TEMP[4], CONST[0].wwww, IMM[2].wwww\n"
1354 "UIF TEMP[4]\n"
1355 "UMIN TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz\n"
1356 "ENDIF\n"
1357
1358 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n"
1359 "ENDIF\n"
1360 "ENDIF\n"
1361 "ENDIF\n"
1362 "ENDIF\n"
1363
1364 "END\n";
1365
1366 char text[sizeof(text_tmpl) + 32];
1367 struct tgsi_token tokens[1024];
1368 struct pipe_compute_state state = {};
1369
1370 /* Hard code the frequency into the shader so that the backend can
1371 * use the full range of optimizations for divide-by-constant.
1372 */
1373 snprintf(text, sizeof(text), text_tmpl,
1374 rctx->screen->info.clock_crystal_freq);
1375
1376 if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
1377 assert(false);
1378 return;
1379 }
1380
1381 state.ir_type = PIPE_SHADER_IR_TGSI;
1382 state.prog = tokens;
1383
1384 rctx->query_result_shader = rctx->b.create_compute_state(&rctx->b, &state);
1385 }
1386
1387 static void r600_restore_qbo_state(struct r600_common_context *rctx,
1388 struct r600_qbo_state *st)
1389 {
1390 rctx->b.bind_compute_state(&rctx->b, st->saved_compute);
1391
1392 rctx->b.set_constant_buffer(&rctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1393 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1394
1395 rctx->b.set_shader_buffers(&rctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1396 for (unsigned i = 0; i < 3; ++i)
1397 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1398 }
1399
1400 static void r600_query_hw_get_result_resource(struct r600_common_context *rctx,
1401 struct r600_query *rquery,
1402 bool wait,
1403 enum pipe_query_value_type result_type,
1404 int index,
1405 struct pipe_resource *resource,
1406 unsigned offset)
1407 {
1408 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
1409 struct r600_query_buffer *qbuf;
1410 struct r600_query_buffer *qbuf_prev;
1411 struct pipe_resource *tmp_buffer = NULL;
1412 unsigned tmp_buffer_offset = 0;
1413 struct r600_qbo_state saved_state = {};
1414 struct pipe_grid_info grid = {};
1415 struct pipe_constant_buffer constant_buffer = {};
1416 struct pipe_shader_buffer ssbo[3];
1417 struct r600_hw_query_params params;
1418 struct {
1419 uint32_t end_offset;
1420 uint32_t result_stride;
1421 uint32_t result_count;
1422 uint32_t config;
1423 uint32_t fence_offset;
1424 uint32_t pair_stride;
1425 uint32_t pair_count;
1426 } consts;
1427
1428 if (!rctx->query_result_shader) {
1429 r600_create_query_result_shader(rctx);
1430 if (!rctx->query_result_shader)
1431 return;
1432 }
1433
1434 if (query->buffer.previous) {
1435 u_suballocator_alloc(rctx->allocator_zeroed_memory, 16, 16,
1436 &tmp_buffer_offset, &tmp_buffer);
1437 if (!tmp_buffer)
1438 return;
1439 }
1440
1441 rctx->save_qbo_state(&rctx->b, &saved_state);
1442
1443 r600_get_hw_query_params(rctx, query, index >= 0 ? index : 0, &params);
1444 consts.end_offset = params.end_offset - params.start_offset;
1445 consts.fence_offset = params.fence_offset - params.start_offset;
1446 consts.result_stride = query->result_size;
1447 consts.pair_stride = params.pair_stride;
1448 consts.pair_count = params.pair_count;
1449
1450 constant_buffer.buffer_size = sizeof(consts);
1451 constant_buffer.user_buffer = &consts;
1452
1453 ssbo[1].buffer = tmp_buffer;
1454 ssbo[1].buffer_offset = tmp_buffer_offset;
1455 ssbo[1].buffer_size = 16;
1456
1457 ssbo[2] = ssbo[1];
1458
1459 rctx->b.bind_compute_state(&rctx->b, rctx->query_result_shader);
1460
1461 grid.block[0] = 1;
1462 grid.block[1] = 1;
1463 grid.block[2] = 1;
1464 grid.grid[0] = 1;
1465 grid.grid[1] = 1;
1466 grid.grid[2] = 1;
1467
1468 consts.config = 0;
1469 if (index < 0)
1470 consts.config |= 4;
1471 if (query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE ||
1472 query->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE)
1473 consts.config |= 8;
1474 else if (query->b.type == PIPE_QUERY_TIMESTAMP ||
1475 query->b.type == PIPE_QUERY_TIME_ELAPSED)
1476 consts.config |= 32;
1477
1478 switch (result_type) {
1479 case PIPE_QUERY_TYPE_U64:
1480 case PIPE_QUERY_TYPE_I64:
1481 consts.config |= 64;
1482 break;
1483 case PIPE_QUERY_TYPE_I32:
1484 consts.config |= 128;
1485 break;
1486 case PIPE_QUERY_TYPE_U32:
1487 break;
1488 }
1489
1490 rctx->flags |= rctx->screen->barrier_flags.cp_to_L2;
1491
1492 for (qbuf = &query->buffer; qbuf; qbuf = qbuf_prev) {
1493 if (query->b.type != PIPE_QUERY_TIMESTAMP) {
1494 qbuf_prev = qbuf->previous;
1495 consts.result_count = qbuf->results_end / query->result_size;
1496 consts.config &= ~3;
1497 if (qbuf != &query->buffer)
1498 consts.config |= 1;
1499 if (qbuf->previous)
1500 consts.config |= 2;
1501 } else {
1502 /* Only read the last timestamp. */
1503 qbuf_prev = NULL;
1504 consts.result_count = 0;
1505 consts.config |= 16;
1506 params.start_offset += qbuf->results_end - query->result_size;
1507 }
1508
1509 rctx->b.set_constant_buffer(&rctx->b, PIPE_SHADER_COMPUTE, 0, &constant_buffer);
1510
1511 ssbo[0].buffer = &qbuf->buf->b.b;
1512 ssbo[0].buffer_offset = params.start_offset;
1513 ssbo[0].buffer_size = qbuf->results_end - params.start_offset;
1514
1515 if (!qbuf->previous) {
1516 ssbo[2].buffer = resource;
1517 ssbo[2].buffer_offset = offset;
1518 ssbo[2].buffer_size = 8;
1519
1520 ((struct r600_resource *)resource)->TC_L2_dirty = true;
1521 }
1522
1523 rctx->b.set_shader_buffers(&rctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo);
1524
1525 if (wait && qbuf == &query->buffer) {
1526 uint64_t va;
1527
1528 /* Wait for result availability. Wait only for readiness
1529 * of the last entry, since the fence writes should be
1530 * serialized in the CP.
1531 */
1532 va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size;
1533 va += params.fence_offset;
1534
1535 r600_gfx_wait_fence(rctx, va, 0x80000000, 0x80000000);
1536 }
1537
1538 rctx->b.launch_grid(&rctx->b, &grid);
1539 rctx->flags |= rctx->screen->barrier_flags.compute_to_L2;
1540 }
1541
1542 r600_restore_qbo_state(rctx, &saved_state);
1543 pipe_resource_reference(&tmp_buffer, NULL);
1544 }
1545
1546 static void r600_render_condition(struct pipe_context *ctx,
1547 struct pipe_query *query,
1548 boolean condition,
1549 uint mode)
1550 {
1551 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1552 struct r600_query_hw *rquery = (struct r600_query_hw *)query;
1553 struct r600_query_buffer *qbuf;
1554 struct r600_atom *atom = &rctx->render_cond_atom;
1555
1556 rctx->render_cond = query;
1557 rctx->render_cond_invert = condition;
1558 rctx->render_cond_mode = mode;
1559
1560 /* Compute the size of SET_PREDICATION packets. */
1561 atom->num_dw = 0;
1562 if (query) {
1563 for (qbuf = &rquery->buffer; qbuf; qbuf = qbuf->previous)
1564 atom->num_dw += (qbuf->results_end / rquery->result_size) * 5;
1565 }
1566
1567 rctx->set_atom_dirty(rctx, atom, query != NULL);
1568 }
1569
1570 void r600_suspend_queries(struct r600_common_context *ctx)
1571 {
1572 struct r600_query_hw *query;
1573
1574 LIST_FOR_EACH_ENTRY(query, &ctx->active_queries, list) {
1575 r600_query_hw_emit_stop(ctx, query);
1576 }
1577 assert(ctx->num_cs_dw_queries_suspend == 0);
1578 }
1579
1580 static unsigned r600_queries_num_cs_dw_for_resuming(struct r600_common_context *ctx,
1581 struct list_head *query_list)
1582 {
1583 struct r600_query_hw *query;
1584 unsigned num_dw = 0;
1585
1586 LIST_FOR_EACH_ENTRY(query, query_list, list) {
1587 /* begin + end */
1588 num_dw += query->num_cs_dw_begin + query->num_cs_dw_end;
1589
1590 /* Workaround for the fact that
1591 * num_cs_dw_nontimer_queries_suspend is incremented for every
1592 * resumed query, which raises the bar in need_cs_space for
1593 * queries about to be resumed.
1594 */
1595 num_dw += query->num_cs_dw_end;
1596 }
1597 /* primitives generated query */
1598 num_dw += ctx->streamout.enable_atom.num_dw;
1599 /* guess for ZPASS enable or PERFECT_ZPASS_COUNT enable updates */
1600 num_dw += 13;
1601
1602 return num_dw;
1603 }
1604
1605 void r600_resume_queries(struct r600_common_context *ctx)
1606 {
1607 struct r600_query_hw *query;
1608 unsigned num_cs_dw = r600_queries_num_cs_dw_for_resuming(ctx, &ctx->active_queries);
1609
1610 assert(ctx->num_cs_dw_queries_suspend == 0);
1611
1612 /* Check CS space here. Resuming must not be interrupted by flushes. */
1613 ctx->need_gfx_cs_space(&ctx->b, num_cs_dw, true);
1614
1615 LIST_FOR_EACH_ENTRY(query, &ctx->active_queries, list) {
1616 r600_query_hw_emit_start(ctx, query);
1617 }
1618 }
1619
1620 /* Fix radeon_info::enabled_rb_mask for R600, R700, EVERGREEN, NI. */
1621 void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen)
1622 {
1623 struct r600_common_context *ctx =
1624 (struct r600_common_context*)rscreen->aux_context;
1625 struct radeon_winsys_cs *cs = ctx->gfx.cs;
1626 struct r600_resource *buffer;
1627 uint32_t *results;
1628 unsigned i, mask = 0;
1629 unsigned max_rbs = ctx->screen->info.num_render_backends;
1630
1631 assert(rscreen->chip_class <= CAYMAN);
1632
1633 /* if backend_map query is supported by the kernel */
1634 if (rscreen->info.r600_gb_backend_map_valid) {
1635 unsigned num_tile_pipes = rscreen->info.num_tile_pipes;
1636 unsigned backend_map = rscreen->info.r600_gb_backend_map;
1637 unsigned item_width, item_mask;
1638
1639 if (ctx->chip_class >= EVERGREEN) {
1640 item_width = 4;
1641 item_mask = 0x7;
1642 } else {
1643 item_width = 2;
1644 item_mask = 0x3;
1645 }
1646
1647 while (num_tile_pipes--) {
1648 i = backend_map & item_mask;
1649 mask |= (1<<i);
1650 backend_map >>= item_width;
1651 }
1652 if (mask != 0) {
1653 rscreen->info.enabled_rb_mask = mask;
1654 return;
1655 }
1656 }
1657
1658 /* otherwise backup path for older kernels */
1659
1660 /* create buffer for event data */
1661 buffer = (struct r600_resource*)
1662 pipe_buffer_create(ctx->b.screen, 0,
1663 PIPE_USAGE_STAGING, max_rbs * 16);
1664 if (!buffer)
1665 return;
1666
1667 /* initialize buffer with zeroes */
1668 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE);
1669 if (results) {
1670 memset(results, 0, max_rbs * 4 * 4);
1671
1672 /* emit EVENT_WRITE for ZPASS_DONE */
1673 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1674 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
1675 radeon_emit(cs, buffer->gpu_address);
1676 radeon_emit(cs, buffer->gpu_address >> 32);
1677
1678 r600_emit_reloc(ctx, &ctx->gfx, buffer,
1679 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
1680
1681 /* analyze results */
1682 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ);
1683 if (results) {
1684 for(i = 0; i < max_rbs; i++) {
1685 /* at least highest bit will be set if backend is used */
1686 if (results[i*4 + 1])
1687 mask |= (1<<i);
1688 }
1689 }
1690 }
1691
1692 r600_resource_reference(&buffer, NULL);
1693
1694 if (mask)
1695 rscreen->info.enabled_rb_mask = mask;
1696 }
1697
1698 #define XFULL(name_, query_type_, type_, result_type_, group_id_) \
1699 { \
1700 .name = name_, \
1701 .query_type = R600_QUERY_##query_type_, \
1702 .type = PIPE_DRIVER_QUERY_TYPE_##type_, \
1703 .result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_##result_type_, \
1704 .group_id = group_id_ \
1705 }
1706
1707 #define X(name_, query_type_, type_, result_type_) \
1708 XFULL(name_, query_type_, type_, result_type_, ~(unsigned)0)
1709
1710 #define XG(group_, name_, query_type_, type_, result_type_) \
1711 XFULL(name_, query_type_, type_, result_type_, R600_QUERY_GROUP_##group_)
1712
1713 static struct pipe_driver_query_info r600_driver_query_list[] = {
1714 X("num-compilations", NUM_COMPILATIONS, UINT64, CUMULATIVE),
1715 X("num-shaders-created", NUM_SHADERS_CREATED, UINT64, CUMULATIVE),
1716 X("num-shader-cache-hits", NUM_SHADER_CACHE_HITS, UINT64, CUMULATIVE),
1717 X("draw-calls", DRAW_CALLS, UINT64, AVERAGE),
1718 X("spill-draw-calls", SPILL_DRAW_CALLS, UINT64, AVERAGE),
1719 X("compute-calls", COMPUTE_CALLS, UINT64, AVERAGE),
1720 X("spill-compute-calls", SPILL_COMPUTE_CALLS, UINT64, AVERAGE),
1721 X("dma-calls", DMA_CALLS, UINT64, AVERAGE),
1722 X("cp-dma-calls", CP_DMA_CALLS, UINT64, AVERAGE),
1723 X("num-vs-flushes", NUM_VS_FLUSHES, UINT64, AVERAGE),
1724 X("num-ps-flushes", NUM_PS_FLUSHES, UINT64, AVERAGE),
1725 X("num-cs-flushes", NUM_CS_FLUSHES, UINT64, AVERAGE),
1726 X("num-fb-cache-flushes", NUM_FB_CACHE_FLUSHES, UINT64, AVERAGE),
1727 X("num-L2-invalidates", NUM_L2_INVALIDATES, UINT64, AVERAGE),
1728 X("num-L2-writebacks", NUM_L2_WRITEBACKS, UINT64, AVERAGE),
1729 X("requested-VRAM", REQUESTED_VRAM, BYTES, AVERAGE),
1730 X("requested-GTT", REQUESTED_GTT, BYTES, AVERAGE),
1731 X("mapped-VRAM", MAPPED_VRAM, BYTES, AVERAGE),
1732 X("mapped-GTT", MAPPED_GTT, BYTES, AVERAGE),
1733 X("buffer-wait-time", BUFFER_WAIT_TIME, MICROSECONDS, CUMULATIVE),
1734 X("num-mapped-buffers", NUM_MAPPED_BUFFERS, UINT64, AVERAGE),
1735 X("num-GFX-IBs", NUM_GFX_IBS, UINT64, AVERAGE),
1736 X("num-SDMA-IBs", NUM_SDMA_IBS, UINT64, AVERAGE),
1737 X("num-bytes-moved", NUM_BYTES_MOVED, BYTES, CUMULATIVE),
1738 X("num-evictions", NUM_EVICTIONS, UINT64, CUMULATIVE),
1739 X("VRAM-usage", VRAM_USAGE, BYTES, AVERAGE),
1740 X("VRAM-vis-usage", VRAM_VIS_USAGE, BYTES, AVERAGE),
1741 X("GTT-usage", GTT_USAGE, BYTES, AVERAGE),
1742 X("back-buffer-ps-draw-ratio", BACK_BUFFER_PS_DRAW_RATIO, UINT64, AVERAGE),
1743
1744 /* GPIN queries are for the benefit of old versions of GPUPerfStudio,
1745 * which use it as a fallback path to detect the GPU type.
1746 *
1747 * Note: The names of these queries are significant for GPUPerfStudio
1748 * (and possibly their order as well). */
1749 XG(GPIN, "GPIN_000", GPIN_ASIC_ID, UINT, AVERAGE),
1750 XG(GPIN, "GPIN_001", GPIN_NUM_SIMD, UINT, AVERAGE),
1751 XG(GPIN, "GPIN_002", GPIN_NUM_RB, UINT, AVERAGE),
1752 XG(GPIN, "GPIN_003", GPIN_NUM_SPI, UINT, AVERAGE),
1753 XG(GPIN, "GPIN_004", GPIN_NUM_SE, UINT, AVERAGE),
1754
1755 /* The following queries must be at the end of the list because their
1756 * availability is adjusted dynamically based on the DRM version. */
1757 X("GPU-load", GPU_LOAD, UINT64, AVERAGE),
1758 X("GPU-shaders-busy", GPU_SHADERS_BUSY, UINT64, AVERAGE),
1759 X("GPU-ta-busy", GPU_TA_BUSY, UINT64, AVERAGE),
1760 X("GPU-gds-busy", GPU_GDS_BUSY, UINT64, AVERAGE),
1761 X("GPU-vgt-busy", GPU_VGT_BUSY, UINT64, AVERAGE),
1762 X("GPU-ia-busy", GPU_IA_BUSY, UINT64, AVERAGE),
1763 X("GPU-sx-busy", GPU_SX_BUSY, UINT64, AVERAGE),
1764 X("GPU-wd-busy", GPU_WD_BUSY, UINT64, AVERAGE),
1765 X("GPU-bci-busy", GPU_BCI_BUSY, UINT64, AVERAGE),
1766 X("GPU-sc-busy", GPU_SC_BUSY, UINT64, AVERAGE),
1767 X("GPU-pa-busy", GPU_PA_BUSY, UINT64, AVERAGE),
1768 X("GPU-db-busy", GPU_DB_BUSY, UINT64, AVERAGE),
1769 X("GPU-cp-busy", GPU_CP_BUSY, UINT64, AVERAGE),
1770 X("GPU-cb-busy", GPU_CB_BUSY, UINT64, AVERAGE),
1771
1772 X("temperature", GPU_TEMPERATURE, UINT64, AVERAGE),
1773 X("shader-clock", CURRENT_GPU_SCLK, HZ, AVERAGE),
1774 X("memory-clock", CURRENT_GPU_MCLK, HZ, AVERAGE),
1775 };
1776
1777 #undef X
1778 #undef XG
1779 #undef XFULL
1780
1781 static unsigned r600_get_num_queries(struct r600_common_screen *rscreen)
1782 {
1783 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
1784 return ARRAY_SIZE(r600_driver_query_list);
1785 else if (rscreen->info.drm_major == 3)
1786 return ARRAY_SIZE(r600_driver_query_list) - 3;
1787 else
1788 return ARRAY_SIZE(r600_driver_query_list) - 17;
1789 }
1790
1791 static int r600_get_driver_query_info(struct pipe_screen *screen,
1792 unsigned index,
1793 struct pipe_driver_query_info *info)
1794 {
1795 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1796 unsigned num_queries = r600_get_num_queries(rscreen);
1797
1798 if (!info) {
1799 unsigned num_perfcounters =
1800 r600_get_perfcounter_info(rscreen, 0, NULL);
1801
1802 return num_queries + num_perfcounters;
1803 }
1804
1805 if (index >= num_queries)
1806 return r600_get_perfcounter_info(rscreen, index - num_queries, info);
1807
1808 *info = r600_driver_query_list[index];
1809
1810 switch (info->query_type) {
1811 case R600_QUERY_REQUESTED_VRAM:
1812 case R600_QUERY_VRAM_USAGE:
1813 case R600_QUERY_MAPPED_VRAM:
1814 info->max_value.u64 = rscreen->info.vram_size;
1815 break;
1816 case R600_QUERY_REQUESTED_GTT:
1817 case R600_QUERY_GTT_USAGE:
1818 case R600_QUERY_MAPPED_GTT:
1819 info->max_value.u64 = rscreen->info.gart_size;
1820 break;
1821 case R600_QUERY_GPU_TEMPERATURE:
1822 info->max_value.u64 = 125;
1823 break;
1824 case R600_QUERY_VRAM_VIS_USAGE:
1825 info->max_value.u64 = rscreen->info.vram_vis_size;
1826 break;
1827 }
1828
1829 if (info->group_id != ~(unsigned)0 && rscreen->perfcounters)
1830 info->group_id += rscreen->perfcounters->num_groups;
1831
1832 return 1;
1833 }
1834
1835 /* Note: Unfortunately, GPUPerfStudio hardcodes the order of hardware
1836 * performance counter groups, so be careful when changing this and related
1837 * functions.
1838 */
1839 static int r600_get_driver_query_group_info(struct pipe_screen *screen,
1840 unsigned index,
1841 struct pipe_driver_query_group_info *info)
1842 {
1843 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
1844 unsigned num_pc_groups = 0;
1845
1846 if (rscreen->perfcounters)
1847 num_pc_groups = rscreen->perfcounters->num_groups;
1848
1849 if (!info)
1850 return num_pc_groups + R600_NUM_SW_QUERY_GROUPS;
1851
1852 if (index < num_pc_groups)
1853 return r600_get_perfcounter_group_info(rscreen, index, info);
1854
1855 index -= num_pc_groups;
1856 if (index >= R600_NUM_SW_QUERY_GROUPS)
1857 return 0;
1858
1859 info->name = "GPIN";
1860 info->max_active_queries = 5;
1861 info->num_queries = 5;
1862 return 1;
1863 }
1864
1865 void r600_query_init(struct r600_common_context *rctx)
1866 {
1867 rctx->b.create_query = r600_create_query;
1868 rctx->b.create_batch_query = r600_create_batch_query;
1869 rctx->b.destroy_query = r600_destroy_query;
1870 rctx->b.begin_query = r600_begin_query;
1871 rctx->b.end_query = r600_end_query;
1872 rctx->b.get_query_result = r600_get_query_result;
1873 rctx->b.get_query_result_resource = r600_get_query_result_resource;
1874 rctx->render_cond_atom.emit = r600_emit_query_predication;
1875
1876 if (((struct r600_common_screen*)rctx->b.screen)->info.num_render_backends > 0)
1877 rctx->b.render_condition = r600_render_condition;
1878
1879 LIST_INITHEAD(&rctx->active_queries);
1880 }
1881
1882 void r600_init_screen_query_functions(struct r600_common_screen *rscreen)
1883 {
1884 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
1885 rscreen->b.get_driver_query_group_info = r600_get_driver_query_group_info;
1886 }