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gallium/radeon: pass old_(perfect_)enable to set_occlusion_query_state
[mesa.git] / src / gallium / drivers / radeon / r600_query.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014 Marek Olšák <marek.olsak@amd.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "r600_query.h"
26 #include "r600_cs.h"
27 #include "util/u_memory.h"
28 #include "util/u_upload_mgr.h"
29 #include "os/os_time.h"
30 #include "tgsi/tgsi_text.h"
31
32 #define R600_MAX_STREAMS 4
33
34 struct r600_hw_query_params {
35 unsigned start_offset;
36 unsigned end_offset;
37 unsigned fence_offset;
38 unsigned pair_stride;
39 unsigned pair_count;
40 };
41
42 /* Queries without buffer handling or suspend/resume. */
43 struct r600_query_sw {
44 struct r600_query b;
45
46 uint64_t begin_result;
47 uint64_t end_result;
48
49 uint64_t begin_time;
50 uint64_t end_time;
51
52 /* Fence for GPU_FINISHED. */
53 struct pipe_fence_handle *fence;
54 };
55
56 static void r600_query_sw_destroy(struct r600_common_screen *rscreen,
57 struct r600_query *rquery)
58 {
59 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
60
61 rscreen->b.fence_reference(&rscreen->b, &query->fence, NULL);
62 FREE(query);
63 }
64
65 static enum radeon_value_id winsys_id_from_type(unsigned type)
66 {
67 switch (type) {
68 case R600_QUERY_REQUESTED_VRAM: return RADEON_REQUESTED_VRAM_MEMORY;
69 case R600_QUERY_REQUESTED_GTT: return RADEON_REQUESTED_GTT_MEMORY;
70 case R600_QUERY_MAPPED_VRAM: return RADEON_MAPPED_VRAM;
71 case R600_QUERY_MAPPED_GTT: return RADEON_MAPPED_GTT;
72 case R600_QUERY_BUFFER_WAIT_TIME: return RADEON_BUFFER_WAIT_TIME_NS;
73 case R600_QUERY_NUM_MAPPED_BUFFERS: return RADEON_NUM_MAPPED_BUFFERS;
74 case R600_QUERY_NUM_GFX_IBS: return RADEON_NUM_GFX_IBS;
75 case R600_QUERY_NUM_SDMA_IBS: return RADEON_NUM_SDMA_IBS;
76 case R600_QUERY_GFX_BO_LIST_SIZE: return RADEON_GFX_BO_LIST_COUNTER;
77 case R600_QUERY_NUM_BYTES_MOVED: return RADEON_NUM_BYTES_MOVED;
78 case R600_QUERY_NUM_EVICTIONS: return RADEON_NUM_EVICTIONS;
79 case R600_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: return RADEON_NUM_VRAM_CPU_PAGE_FAULTS;
80 case R600_QUERY_VRAM_USAGE: return RADEON_VRAM_USAGE;
81 case R600_QUERY_VRAM_VIS_USAGE: return RADEON_VRAM_VIS_USAGE;
82 case R600_QUERY_GTT_USAGE: return RADEON_GTT_USAGE;
83 case R600_QUERY_GPU_TEMPERATURE: return RADEON_GPU_TEMPERATURE;
84 case R600_QUERY_CURRENT_GPU_SCLK: return RADEON_CURRENT_SCLK;
85 case R600_QUERY_CURRENT_GPU_MCLK: return RADEON_CURRENT_MCLK;
86 case R600_QUERY_CS_THREAD_BUSY: return RADEON_CS_THREAD_TIME;
87 default: unreachable("query type does not correspond to winsys id");
88 }
89 }
90
91 static bool r600_query_sw_begin(struct r600_common_context *rctx,
92 struct r600_query *rquery)
93 {
94 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
95 enum radeon_value_id ws_id;
96
97 switch(query->b.type) {
98 case PIPE_QUERY_TIMESTAMP_DISJOINT:
99 case PIPE_QUERY_GPU_FINISHED:
100 break;
101 case R600_QUERY_DRAW_CALLS:
102 query->begin_result = rctx->num_draw_calls;
103 break;
104 case R600_QUERY_DECOMPRESS_CALLS:
105 query->begin_result = rctx->num_decompress_calls;
106 break;
107 case R600_QUERY_MRT_DRAW_CALLS:
108 query->begin_result = rctx->num_mrt_draw_calls;
109 break;
110 case R600_QUERY_PRIM_RESTART_CALLS:
111 query->begin_result = rctx->num_prim_restart_calls;
112 break;
113 case R600_QUERY_SPILL_DRAW_CALLS:
114 query->begin_result = rctx->num_spill_draw_calls;
115 break;
116 case R600_QUERY_COMPUTE_CALLS:
117 query->begin_result = rctx->num_compute_calls;
118 break;
119 case R600_QUERY_SPILL_COMPUTE_CALLS:
120 query->begin_result = rctx->num_spill_compute_calls;
121 break;
122 case R600_QUERY_DMA_CALLS:
123 query->begin_result = rctx->num_dma_calls;
124 break;
125 case R600_QUERY_CP_DMA_CALLS:
126 query->begin_result = rctx->num_cp_dma_calls;
127 break;
128 case R600_QUERY_NUM_VS_FLUSHES:
129 query->begin_result = rctx->num_vs_flushes;
130 break;
131 case R600_QUERY_NUM_PS_FLUSHES:
132 query->begin_result = rctx->num_ps_flushes;
133 break;
134 case R600_QUERY_NUM_CS_FLUSHES:
135 query->begin_result = rctx->num_cs_flushes;
136 break;
137 case R600_QUERY_NUM_CB_CACHE_FLUSHES:
138 query->begin_result = rctx->num_cb_cache_flushes;
139 break;
140 case R600_QUERY_NUM_DB_CACHE_FLUSHES:
141 query->begin_result = rctx->num_db_cache_flushes;
142 break;
143 case R600_QUERY_NUM_L2_INVALIDATES:
144 query->begin_result = rctx->num_L2_invalidates;
145 break;
146 case R600_QUERY_NUM_L2_WRITEBACKS:
147 query->begin_result = rctx->num_L2_writebacks;
148 break;
149 case R600_QUERY_NUM_RESIDENT_HANDLES:
150 query->begin_result = rctx->num_resident_handles;
151 break;
152 case R600_QUERY_TC_OFFLOADED_SLOTS:
153 query->begin_result = rctx->tc ? rctx->tc->num_offloaded_slots : 0;
154 break;
155 case R600_QUERY_TC_DIRECT_SLOTS:
156 query->begin_result = rctx->tc ? rctx->tc->num_direct_slots : 0;
157 break;
158 case R600_QUERY_TC_NUM_SYNCS:
159 query->begin_result = rctx->tc ? rctx->tc->num_syncs : 0;
160 break;
161 case R600_QUERY_REQUESTED_VRAM:
162 case R600_QUERY_REQUESTED_GTT:
163 case R600_QUERY_MAPPED_VRAM:
164 case R600_QUERY_MAPPED_GTT:
165 case R600_QUERY_VRAM_USAGE:
166 case R600_QUERY_VRAM_VIS_USAGE:
167 case R600_QUERY_GTT_USAGE:
168 case R600_QUERY_GPU_TEMPERATURE:
169 case R600_QUERY_CURRENT_GPU_SCLK:
170 case R600_QUERY_CURRENT_GPU_MCLK:
171 case R600_QUERY_BACK_BUFFER_PS_DRAW_RATIO:
172 case R600_QUERY_NUM_MAPPED_BUFFERS:
173 query->begin_result = 0;
174 break;
175 case R600_QUERY_BUFFER_WAIT_TIME:
176 case R600_QUERY_NUM_GFX_IBS:
177 case R600_QUERY_NUM_SDMA_IBS:
178 case R600_QUERY_NUM_BYTES_MOVED:
179 case R600_QUERY_NUM_EVICTIONS:
180 case R600_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: {
181 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
182 query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
183 break;
184 }
185 case R600_QUERY_GFX_BO_LIST_SIZE:
186 ws_id = winsys_id_from_type(query->b.type);
187 query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
188 query->begin_time = rctx->ws->query_value(rctx->ws,
189 RADEON_NUM_GFX_IBS);
190 break;
191 case R600_QUERY_CS_THREAD_BUSY:
192 ws_id = winsys_id_from_type(query->b.type);
193 query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
194 query->begin_time = os_time_get_nano();
195 break;
196 case R600_QUERY_GALLIUM_THREAD_BUSY:
197 query->begin_result =
198 rctx->tc ? util_queue_get_thread_time_nano(&rctx->tc->queue, 0) : 0;
199 query->begin_time = os_time_get_nano();
200 break;
201 case R600_QUERY_GPU_LOAD:
202 case R600_QUERY_GPU_SHADERS_BUSY:
203 case R600_QUERY_GPU_TA_BUSY:
204 case R600_QUERY_GPU_GDS_BUSY:
205 case R600_QUERY_GPU_VGT_BUSY:
206 case R600_QUERY_GPU_IA_BUSY:
207 case R600_QUERY_GPU_SX_BUSY:
208 case R600_QUERY_GPU_WD_BUSY:
209 case R600_QUERY_GPU_BCI_BUSY:
210 case R600_QUERY_GPU_SC_BUSY:
211 case R600_QUERY_GPU_PA_BUSY:
212 case R600_QUERY_GPU_DB_BUSY:
213 case R600_QUERY_GPU_CP_BUSY:
214 case R600_QUERY_GPU_CB_BUSY:
215 case R600_QUERY_GPU_SDMA_BUSY:
216 case R600_QUERY_GPU_PFP_BUSY:
217 case R600_QUERY_GPU_MEQ_BUSY:
218 case R600_QUERY_GPU_ME_BUSY:
219 case R600_QUERY_GPU_SURF_SYNC_BUSY:
220 case R600_QUERY_GPU_CP_DMA_BUSY:
221 case R600_QUERY_GPU_SCRATCH_RAM_BUSY:
222 query->begin_result = r600_begin_counter(rctx->screen,
223 query->b.type);
224 break;
225 case R600_QUERY_NUM_COMPILATIONS:
226 query->begin_result = p_atomic_read(&rctx->screen->num_compilations);
227 break;
228 case R600_QUERY_NUM_SHADERS_CREATED:
229 query->begin_result = p_atomic_read(&rctx->screen->num_shaders_created);
230 break;
231 case R600_QUERY_NUM_SHADER_CACHE_HITS:
232 query->begin_result =
233 p_atomic_read(&rctx->screen->num_shader_cache_hits);
234 break;
235 case R600_QUERY_GPIN_ASIC_ID:
236 case R600_QUERY_GPIN_NUM_SIMD:
237 case R600_QUERY_GPIN_NUM_RB:
238 case R600_QUERY_GPIN_NUM_SPI:
239 case R600_QUERY_GPIN_NUM_SE:
240 break;
241 default:
242 unreachable("r600_query_sw_begin: bad query type");
243 }
244
245 return true;
246 }
247
248 static bool r600_query_sw_end(struct r600_common_context *rctx,
249 struct r600_query *rquery)
250 {
251 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
252 enum radeon_value_id ws_id;
253
254 switch(query->b.type) {
255 case PIPE_QUERY_TIMESTAMP_DISJOINT:
256 break;
257 case PIPE_QUERY_GPU_FINISHED:
258 rctx->b.flush(&rctx->b, &query->fence, PIPE_FLUSH_DEFERRED);
259 break;
260 case R600_QUERY_DRAW_CALLS:
261 query->end_result = rctx->num_draw_calls;
262 break;
263 case R600_QUERY_DECOMPRESS_CALLS:
264 query->end_result = rctx->num_decompress_calls;
265 break;
266 case R600_QUERY_MRT_DRAW_CALLS:
267 query->end_result = rctx->num_mrt_draw_calls;
268 break;
269 case R600_QUERY_PRIM_RESTART_CALLS:
270 query->end_result = rctx->num_prim_restart_calls;
271 break;
272 case R600_QUERY_SPILL_DRAW_CALLS:
273 query->end_result = rctx->num_spill_draw_calls;
274 break;
275 case R600_QUERY_COMPUTE_CALLS:
276 query->end_result = rctx->num_compute_calls;
277 break;
278 case R600_QUERY_SPILL_COMPUTE_CALLS:
279 query->end_result = rctx->num_spill_compute_calls;
280 break;
281 case R600_QUERY_DMA_CALLS:
282 query->end_result = rctx->num_dma_calls;
283 break;
284 case R600_QUERY_CP_DMA_CALLS:
285 query->end_result = rctx->num_cp_dma_calls;
286 break;
287 case R600_QUERY_NUM_VS_FLUSHES:
288 query->end_result = rctx->num_vs_flushes;
289 break;
290 case R600_QUERY_NUM_PS_FLUSHES:
291 query->end_result = rctx->num_ps_flushes;
292 break;
293 case R600_QUERY_NUM_CS_FLUSHES:
294 query->end_result = rctx->num_cs_flushes;
295 break;
296 case R600_QUERY_NUM_CB_CACHE_FLUSHES:
297 query->end_result = rctx->num_cb_cache_flushes;
298 break;
299 case R600_QUERY_NUM_DB_CACHE_FLUSHES:
300 query->end_result = rctx->num_db_cache_flushes;
301 break;
302 case R600_QUERY_NUM_L2_INVALIDATES:
303 query->end_result = rctx->num_L2_invalidates;
304 break;
305 case R600_QUERY_NUM_L2_WRITEBACKS:
306 query->end_result = rctx->num_L2_writebacks;
307 break;
308 case R600_QUERY_NUM_RESIDENT_HANDLES:
309 query->end_result = rctx->num_resident_handles;
310 break;
311 case R600_QUERY_TC_OFFLOADED_SLOTS:
312 query->end_result = rctx->tc ? rctx->tc->num_offloaded_slots : 0;
313 break;
314 case R600_QUERY_TC_DIRECT_SLOTS:
315 query->end_result = rctx->tc ? rctx->tc->num_direct_slots : 0;
316 break;
317 case R600_QUERY_TC_NUM_SYNCS:
318 query->end_result = rctx->tc ? rctx->tc->num_syncs : 0;
319 break;
320 case R600_QUERY_REQUESTED_VRAM:
321 case R600_QUERY_REQUESTED_GTT:
322 case R600_QUERY_MAPPED_VRAM:
323 case R600_QUERY_MAPPED_GTT:
324 case R600_QUERY_VRAM_USAGE:
325 case R600_QUERY_VRAM_VIS_USAGE:
326 case R600_QUERY_GTT_USAGE:
327 case R600_QUERY_GPU_TEMPERATURE:
328 case R600_QUERY_CURRENT_GPU_SCLK:
329 case R600_QUERY_CURRENT_GPU_MCLK:
330 case R600_QUERY_BUFFER_WAIT_TIME:
331 case R600_QUERY_NUM_MAPPED_BUFFERS:
332 case R600_QUERY_NUM_GFX_IBS:
333 case R600_QUERY_NUM_SDMA_IBS:
334 case R600_QUERY_NUM_BYTES_MOVED:
335 case R600_QUERY_NUM_EVICTIONS:
336 case R600_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: {
337 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
338 query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
339 break;
340 }
341 case R600_QUERY_GFX_BO_LIST_SIZE:
342 ws_id = winsys_id_from_type(query->b.type);
343 query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
344 query->end_time = rctx->ws->query_value(rctx->ws,
345 RADEON_NUM_GFX_IBS);
346 break;
347 case R600_QUERY_CS_THREAD_BUSY:
348 ws_id = winsys_id_from_type(query->b.type);
349 query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
350 query->end_time = os_time_get_nano();
351 break;
352 case R600_QUERY_GALLIUM_THREAD_BUSY:
353 query->end_result =
354 rctx->tc ? util_queue_get_thread_time_nano(&rctx->tc->queue, 0) : 0;
355 query->end_time = os_time_get_nano();
356 break;
357 case R600_QUERY_GPU_LOAD:
358 case R600_QUERY_GPU_SHADERS_BUSY:
359 case R600_QUERY_GPU_TA_BUSY:
360 case R600_QUERY_GPU_GDS_BUSY:
361 case R600_QUERY_GPU_VGT_BUSY:
362 case R600_QUERY_GPU_IA_BUSY:
363 case R600_QUERY_GPU_SX_BUSY:
364 case R600_QUERY_GPU_WD_BUSY:
365 case R600_QUERY_GPU_BCI_BUSY:
366 case R600_QUERY_GPU_SC_BUSY:
367 case R600_QUERY_GPU_PA_BUSY:
368 case R600_QUERY_GPU_DB_BUSY:
369 case R600_QUERY_GPU_CP_BUSY:
370 case R600_QUERY_GPU_CB_BUSY:
371 case R600_QUERY_GPU_SDMA_BUSY:
372 case R600_QUERY_GPU_PFP_BUSY:
373 case R600_QUERY_GPU_MEQ_BUSY:
374 case R600_QUERY_GPU_ME_BUSY:
375 case R600_QUERY_GPU_SURF_SYNC_BUSY:
376 case R600_QUERY_GPU_CP_DMA_BUSY:
377 case R600_QUERY_GPU_SCRATCH_RAM_BUSY:
378 query->end_result = r600_end_counter(rctx->screen,
379 query->b.type,
380 query->begin_result);
381 query->begin_result = 0;
382 break;
383 case R600_QUERY_NUM_COMPILATIONS:
384 query->end_result = p_atomic_read(&rctx->screen->num_compilations);
385 break;
386 case R600_QUERY_NUM_SHADERS_CREATED:
387 query->end_result = p_atomic_read(&rctx->screen->num_shaders_created);
388 break;
389 case R600_QUERY_BACK_BUFFER_PS_DRAW_RATIO:
390 query->end_result = rctx->last_tex_ps_draw_ratio;
391 break;
392 case R600_QUERY_NUM_SHADER_CACHE_HITS:
393 query->end_result =
394 p_atomic_read(&rctx->screen->num_shader_cache_hits);
395 break;
396 case R600_QUERY_GPIN_ASIC_ID:
397 case R600_QUERY_GPIN_NUM_SIMD:
398 case R600_QUERY_GPIN_NUM_RB:
399 case R600_QUERY_GPIN_NUM_SPI:
400 case R600_QUERY_GPIN_NUM_SE:
401 break;
402 default:
403 unreachable("r600_query_sw_end: bad query type");
404 }
405
406 return true;
407 }
408
409 static bool r600_query_sw_get_result(struct r600_common_context *rctx,
410 struct r600_query *rquery,
411 bool wait,
412 union pipe_query_result *result)
413 {
414 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
415
416 switch (query->b.type) {
417 case PIPE_QUERY_TIMESTAMP_DISJOINT:
418 /* Convert from cycles per millisecond to cycles per second (Hz). */
419 result->timestamp_disjoint.frequency =
420 (uint64_t)rctx->screen->info.clock_crystal_freq * 1000;
421 result->timestamp_disjoint.disjoint = false;
422 return true;
423 case PIPE_QUERY_GPU_FINISHED: {
424 struct pipe_screen *screen = rctx->b.screen;
425 struct pipe_context *ctx = rquery->b.flushed ? NULL : &rctx->b;
426
427 result->b = screen->fence_finish(screen, ctx, query->fence,
428 wait ? PIPE_TIMEOUT_INFINITE : 0);
429 return result->b;
430 }
431
432 case R600_QUERY_GFX_BO_LIST_SIZE:
433 result->u64 = (query->end_result - query->begin_result) /
434 (query->end_time - query->begin_time);
435 return true;
436 case R600_QUERY_CS_THREAD_BUSY:
437 case R600_QUERY_GALLIUM_THREAD_BUSY:
438 result->u64 = (query->end_result - query->begin_result) * 100 /
439 (query->end_time - query->begin_time);
440 return true;
441 case R600_QUERY_GPIN_ASIC_ID:
442 result->u32 = 0;
443 return true;
444 case R600_QUERY_GPIN_NUM_SIMD:
445 result->u32 = rctx->screen->info.num_good_compute_units;
446 return true;
447 case R600_QUERY_GPIN_NUM_RB:
448 result->u32 = rctx->screen->info.num_render_backends;
449 return true;
450 case R600_QUERY_GPIN_NUM_SPI:
451 result->u32 = 1; /* all supported chips have one SPI per SE */
452 return true;
453 case R600_QUERY_GPIN_NUM_SE:
454 result->u32 = rctx->screen->info.max_se;
455 return true;
456 }
457
458 result->u64 = query->end_result - query->begin_result;
459
460 switch (query->b.type) {
461 case R600_QUERY_BUFFER_WAIT_TIME:
462 case R600_QUERY_GPU_TEMPERATURE:
463 result->u64 /= 1000;
464 break;
465 case R600_QUERY_CURRENT_GPU_SCLK:
466 case R600_QUERY_CURRENT_GPU_MCLK:
467 result->u64 *= 1000000;
468 break;
469 }
470
471 return true;
472 }
473
474
475 static struct r600_query_ops sw_query_ops = {
476 .destroy = r600_query_sw_destroy,
477 .begin = r600_query_sw_begin,
478 .end = r600_query_sw_end,
479 .get_result = r600_query_sw_get_result,
480 .get_result_resource = NULL
481 };
482
483 static struct pipe_query *r600_query_sw_create(unsigned query_type)
484 {
485 struct r600_query_sw *query;
486
487 query = CALLOC_STRUCT(r600_query_sw);
488 if (!query)
489 return NULL;
490
491 query->b.type = query_type;
492 query->b.ops = &sw_query_ops;
493
494 return (struct pipe_query *)query;
495 }
496
497 void r600_query_hw_destroy(struct r600_common_screen *rscreen,
498 struct r600_query *rquery)
499 {
500 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
501 struct r600_query_buffer *prev = query->buffer.previous;
502
503 /* Release all query buffers. */
504 while (prev) {
505 struct r600_query_buffer *qbuf = prev;
506 prev = prev->previous;
507 r600_resource_reference(&qbuf->buf, NULL);
508 FREE(qbuf);
509 }
510
511 r600_resource_reference(&query->buffer.buf, NULL);
512 r600_resource_reference(&query->workaround_buf, NULL);
513 FREE(rquery);
514 }
515
516 static struct r600_resource *r600_new_query_buffer(struct r600_common_screen *rscreen,
517 struct r600_query_hw *query)
518 {
519 unsigned buf_size = MAX2(query->result_size,
520 rscreen->info.min_alloc_size);
521
522 /* Queries are normally read by the CPU after
523 * being written by the gpu, hence staging is probably a good
524 * usage pattern.
525 */
526 struct r600_resource *buf = (struct r600_resource*)
527 pipe_buffer_create(&rscreen->b, 0,
528 PIPE_USAGE_STAGING, buf_size);
529 if (!buf)
530 return NULL;
531
532 if (!query->ops->prepare_buffer(rscreen, query, buf)) {
533 r600_resource_reference(&buf, NULL);
534 return NULL;
535 }
536
537 return buf;
538 }
539
540 static bool r600_query_hw_prepare_buffer(struct r600_common_screen *rscreen,
541 struct r600_query_hw *query,
542 struct r600_resource *buffer)
543 {
544 /* Callers ensure that the buffer is currently unused by the GPU. */
545 uint32_t *results = rscreen->ws->buffer_map(buffer->buf, NULL,
546 PIPE_TRANSFER_WRITE |
547 PIPE_TRANSFER_UNSYNCHRONIZED);
548 if (!results)
549 return false;
550
551 memset(results, 0, buffer->b.b.width0);
552
553 if (query->b.type == PIPE_QUERY_OCCLUSION_COUNTER ||
554 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE ||
555 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
556 unsigned max_rbs = rscreen->info.num_render_backends;
557 unsigned enabled_rb_mask = rscreen->info.enabled_rb_mask;
558 unsigned num_results;
559 unsigned i, j;
560
561 /* Set top bits for unused backends. */
562 num_results = buffer->b.b.width0 / query->result_size;
563 for (j = 0; j < num_results; j++) {
564 for (i = 0; i < max_rbs; i++) {
565 if (!(enabled_rb_mask & (1<<i))) {
566 results[(i * 4)+1] = 0x80000000;
567 results[(i * 4)+3] = 0x80000000;
568 }
569 }
570 results += 4 * max_rbs;
571 }
572 }
573
574 return true;
575 }
576
577 static void r600_query_hw_get_result_resource(struct r600_common_context *rctx,
578 struct r600_query *rquery,
579 bool wait,
580 enum pipe_query_value_type result_type,
581 int index,
582 struct pipe_resource *resource,
583 unsigned offset);
584
585 static struct r600_query_ops query_hw_ops = {
586 .destroy = r600_query_hw_destroy,
587 .begin = r600_query_hw_begin,
588 .end = r600_query_hw_end,
589 .get_result = r600_query_hw_get_result,
590 .get_result_resource = r600_query_hw_get_result_resource,
591 };
592
593 static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
594 struct r600_query_hw *query,
595 struct r600_resource *buffer,
596 uint64_t va);
597 static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
598 struct r600_query_hw *query,
599 struct r600_resource *buffer,
600 uint64_t va);
601 static void r600_query_hw_add_result(struct r600_common_screen *rscreen,
602 struct r600_query_hw *, void *buffer,
603 union pipe_query_result *result);
604 static void r600_query_hw_clear_result(struct r600_query_hw *,
605 union pipe_query_result *);
606
607 static struct r600_query_hw_ops query_hw_default_hw_ops = {
608 .prepare_buffer = r600_query_hw_prepare_buffer,
609 .emit_start = r600_query_hw_do_emit_start,
610 .emit_stop = r600_query_hw_do_emit_stop,
611 .clear_result = r600_query_hw_clear_result,
612 .add_result = r600_query_hw_add_result,
613 };
614
615 bool r600_query_hw_init(struct r600_common_screen *rscreen,
616 struct r600_query_hw *query)
617 {
618 query->buffer.buf = r600_new_query_buffer(rscreen, query);
619 if (!query->buffer.buf)
620 return false;
621
622 return true;
623 }
624
625 static struct pipe_query *r600_query_hw_create(struct r600_common_screen *rscreen,
626 unsigned query_type,
627 unsigned index)
628 {
629 struct r600_query_hw *query = CALLOC_STRUCT(r600_query_hw);
630 if (!query)
631 return NULL;
632
633 query->b.type = query_type;
634 query->b.ops = &query_hw_ops;
635 query->ops = &query_hw_default_hw_ops;
636
637 switch (query_type) {
638 case PIPE_QUERY_OCCLUSION_COUNTER:
639 case PIPE_QUERY_OCCLUSION_PREDICATE:
640 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
641 query->result_size = 16 * rscreen->info.num_render_backends;
642 query->result_size += 16; /* for the fence + alignment */
643 query->num_cs_dw_begin = 6;
644 query->num_cs_dw_end = 6 + r600_gfx_write_fence_dwords(rscreen);
645 break;
646 case PIPE_QUERY_TIME_ELAPSED:
647 query->result_size = 24;
648 query->num_cs_dw_begin = 8;
649 query->num_cs_dw_end = 8 + r600_gfx_write_fence_dwords(rscreen);
650 break;
651 case PIPE_QUERY_TIMESTAMP:
652 query->result_size = 16;
653 query->num_cs_dw_end = 8 + r600_gfx_write_fence_dwords(rscreen);
654 query->flags = R600_QUERY_HW_FLAG_NO_START;
655 break;
656 case PIPE_QUERY_PRIMITIVES_EMITTED:
657 case PIPE_QUERY_PRIMITIVES_GENERATED:
658 case PIPE_QUERY_SO_STATISTICS:
659 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
660 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
661 query->result_size = 32;
662 query->num_cs_dw_begin = 6;
663 query->num_cs_dw_end = 6;
664 query->stream = index;
665 break;
666 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
667 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
668 query->result_size = 32 * R600_MAX_STREAMS;
669 query->num_cs_dw_begin = 6 * R600_MAX_STREAMS;
670 query->num_cs_dw_end = 6 * R600_MAX_STREAMS;
671 break;
672 case PIPE_QUERY_PIPELINE_STATISTICS:
673 /* 11 values on EG, 8 on R600. */
674 query->result_size = (rscreen->chip_class >= EVERGREEN ? 11 : 8) * 16;
675 query->result_size += 8; /* for the fence + alignment */
676 query->num_cs_dw_begin = 6;
677 query->num_cs_dw_end = 6 + r600_gfx_write_fence_dwords(rscreen);
678 break;
679 default:
680 assert(0);
681 FREE(query);
682 return NULL;
683 }
684
685 if (!r600_query_hw_init(rscreen, query)) {
686 FREE(query);
687 return NULL;
688 }
689
690 return (struct pipe_query *)query;
691 }
692
693 static void r600_update_occlusion_query_state(struct r600_common_context *rctx,
694 unsigned type, int diff)
695 {
696 if (type == PIPE_QUERY_OCCLUSION_COUNTER ||
697 type == PIPE_QUERY_OCCLUSION_PREDICATE ||
698 type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
699 bool old_enable = rctx->num_occlusion_queries != 0;
700 bool old_perfect_enable =
701 rctx->num_perfect_occlusion_queries != 0;
702 bool enable, perfect_enable;
703
704 rctx->num_occlusion_queries += diff;
705 assert(rctx->num_occlusion_queries >= 0);
706
707 if (type != PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
708 rctx->num_perfect_occlusion_queries += diff;
709 assert(rctx->num_perfect_occlusion_queries >= 0);
710 }
711
712 enable = rctx->num_occlusion_queries != 0;
713 perfect_enable = rctx->num_perfect_occlusion_queries != 0;
714
715 if (enable != old_enable || perfect_enable != old_perfect_enable) {
716 rctx->set_occlusion_query_state(&rctx->b, old_enable,
717 old_perfect_enable);
718 }
719 }
720 }
721
722 static unsigned event_type_for_stream(unsigned stream)
723 {
724 switch (stream) {
725 default:
726 case 0: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS;
727 case 1: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS1;
728 case 2: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS2;
729 case 3: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS3;
730 }
731 }
732
733 static void emit_sample_streamout(struct radeon_winsys_cs *cs, uint64_t va,
734 unsigned stream)
735 {
736 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
737 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(stream)) | EVENT_INDEX(3));
738 radeon_emit(cs, va);
739 radeon_emit(cs, va >> 32);
740 }
741
742 static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
743 struct r600_query_hw *query,
744 struct r600_resource *buffer,
745 uint64_t va)
746 {
747 struct radeon_winsys_cs *cs = ctx->gfx.cs;
748
749 switch (query->b.type) {
750 case PIPE_QUERY_OCCLUSION_COUNTER:
751 case PIPE_QUERY_OCCLUSION_PREDICATE:
752 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
753 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
754 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
755 radeon_emit(cs, va);
756 radeon_emit(cs, va >> 32);
757 break;
758 case PIPE_QUERY_PRIMITIVES_EMITTED:
759 case PIPE_QUERY_PRIMITIVES_GENERATED:
760 case PIPE_QUERY_SO_STATISTICS:
761 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
762 emit_sample_streamout(cs, va, query->stream);
763 break;
764 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
765 for (unsigned stream = 0; stream < R600_MAX_STREAMS; ++stream)
766 emit_sample_streamout(cs, va + 32 * stream, stream);
767 break;
768 case PIPE_QUERY_TIME_ELAPSED:
769 if (ctx->chip_class >= SI) {
770 /* Write the timestamp from the CP not waiting for
771 * outstanding draws (top-of-pipe).
772 */
773 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
774 radeon_emit(cs, COPY_DATA_COUNT_SEL |
775 COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
776 COPY_DATA_DST_SEL(COPY_DATA_MEM_ASYNC));
777 radeon_emit(cs, 0);
778 radeon_emit(cs, 0);
779 radeon_emit(cs, va);
780 radeon_emit(cs, va >> 32);
781 } else {
782 /* Write the timestamp after the last draw is done.
783 * (bottom-of-pipe)
784 */
785 r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
786 0, EOP_DATA_SEL_TIMESTAMP,
787 NULL, va, 0, query->b.type);
788 }
789 break;
790 case PIPE_QUERY_PIPELINE_STATISTICS:
791 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
792 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
793 radeon_emit(cs, va);
794 radeon_emit(cs, va >> 32);
795 break;
796 default:
797 assert(0);
798 }
799 r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE,
800 RADEON_PRIO_QUERY);
801 }
802
803 static void r600_query_hw_emit_start(struct r600_common_context *ctx,
804 struct r600_query_hw *query)
805 {
806 uint64_t va;
807
808 if (!query->buffer.buf)
809 return; // previous buffer allocation failure
810
811 r600_update_occlusion_query_state(ctx, query->b.type, 1);
812 r600_update_prims_generated_query_state(ctx, query->b.type, 1);
813
814 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw_begin + query->num_cs_dw_end,
815 true);
816
817 /* Get a new query buffer if needed. */
818 if (query->buffer.results_end + query->result_size > query->buffer.buf->b.b.width0) {
819 struct r600_query_buffer *qbuf = MALLOC_STRUCT(r600_query_buffer);
820 *qbuf = query->buffer;
821 query->buffer.results_end = 0;
822 query->buffer.previous = qbuf;
823 query->buffer.buf = r600_new_query_buffer(ctx->screen, query);
824 if (!query->buffer.buf)
825 return;
826 }
827
828 /* emit begin query */
829 va = query->buffer.buf->gpu_address + query->buffer.results_end;
830
831 query->ops->emit_start(ctx, query, query->buffer.buf, va);
832
833 ctx->num_cs_dw_queries_suspend += query->num_cs_dw_end;
834 }
835
836 static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
837 struct r600_query_hw *query,
838 struct r600_resource *buffer,
839 uint64_t va)
840 {
841 struct radeon_winsys_cs *cs = ctx->gfx.cs;
842 uint64_t fence_va = 0;
843
844 switch (query->b.type) {
845 case PIPE_QUERY_OCCLUSION_COUNTER:
846 case PIPE_QUERY_OCCLUSION_PREDICATE:
847 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
848 va += 8;
849 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
850 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
851 radeon_emit(cs, va);
852 radeon_emit(cs, va >> 32);
853
854 fence_va = va + ctx->screen->info.num_render_backends * 16 - 8;
855 break;
856 case PIPE_QUERY_PRIMITIVES_EMITTED:
857 case PIPE_QUERY_PRIMITIVES_GENERATED:
858 case PIPE_QUERY_SO_STATISTICS:
859 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
860 va += 16;
861 emit_sample_streamout(cs, va, query->stream);
862 break;
863 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
864 va += 16;
865 for (unsigned stream = 0; stream < R600_MAX_STREAMS; ++stream)
866 emit_sample_streamout(cs, va + 32 * stream, stream);
867 break;
868 case PIPE_QUERY_TIME_ELAPSED:
869 va += 8;
870 /* fall through */
871 case PIPE_QUERY_TIMESTAMP:
872 r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
873 0, EOP_DATA_SEL_TIMESTAMP, NULL, va,
874 0, query->b.type);
875 fence_va = va + 8;
876 break;
877 case PIPE_QUERY_PIPELINE_STATISTICS: {
878 unsigned sample_size = (query->result_size - 8) / 2;
879
880 va += sample_size;
881 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
882 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
883 radeon_emit(cs, va);
884 radeon_emit(cs, va >> 32);
885
886 fence_va = va + sample_size;
887 break;
888 }
889 default:
890 assert(0);
891 }
892 r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE,
893 RADEON_PRIO_QUERY);
894
895 if (fence_va)
896 r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
897 EOP_DATA_SEL_VALUE_32BIT,
898 query->buffer.buf, fence_va, 0x80000000,
899 query->b.type);
900 }
901
902 static void r600_query_hw_emit_stop(struct r600_common_context *ctx,
903 struct r600_query_hw *query)
904 {
905 uint64_t va;
906
907 if (!query->buffer.buf)
908 return; // previous buffer allocation failure
909
910 /* The queries which need begin already called this in begin_query. */
911 if (query->flags & R600_QUERY_HW_FLAG_NO_START) {
912 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw_end, false);
913 }
914
915 /* emit end query */
916 va = query->buffer.buf->gpu_address + query->buffer.results_end;
917
918 query->ops->emit_stop(ctx, query, query->buffer.buf, va);
919
920 query->buffer.results_end += query->result_size;
921
922 if (!(query->flags & R600_QUERY_HW_FLAG_NO_START))
923 ctx->num_cs_dw_queries_suspend -= query->num_cs_dw_end;
924
925 r600_update_occlusion_query_state(ctx, query->b.type, -1);
926 r600_update_prims_generated_query_state(ctx, query->b.type, -1);
927 }
928
929 static void emit_set_predicate(struct r600_common_context *ctx,
930 struct r600_resource *buf, uint64_t va,
931 uint32_t op)
932 {
933 struct radeon_winsys_cs *cs = ctx->gfx.cs;
934
935 if (ctx->chip_class >= GFX9) {
936 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
937 radeon_emit(cs, op);
938 radeon_emit(cs, va);
939 radeon_emit(cs, va >> 32);
940 } else {
941 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
942 radeon_emit(cs, va);
943 radeon_emit(cs, op | ((va >> 32) & 0xFF));
944 }
945 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_READ,
946 RADEON_PRIO_QUERY);
947 }
948
949 static void r600_emit_query_predication(struct r600_common_context *ctx,
950 struct r600_atom *atom)
951 {
952 struct r600_query_hw *query = (struct r600_query_hw *)ctx->render_cond;
953 struct r600_query_buffer *qbuf;
954 uint32_t op;
955 bool flag_wait, invert;
956
957 if (!query)
958 return;
959
960 invert = ctx->render_cond_invert;
961 flag_wait = ctx->render_cond_mode == PIPE_RENDER_COND_WAIT ||
962 ctx->render_cond_mode == PIPE_RENDER_COND_BY_REGION_WAIT;
963
964 if (query->workaround_buf) {
965 op = PRED_OP(PREDICATION_OP_BOOL64);
966 } else {
967 switch (query->b.type) {
968 case PIPE_QUERY_OCCLUSION_COUNTER:
969 case PIPE_QUERY_OCCLUSION_PREDICATE:
970 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
971 op = PRED_OP(PREDICATION_OP_ZPASS);
972 break;
973 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
974 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
975 op = PRED_OP(PREDICATION_OP_PRIMCOUNT);
976 invert = !invert;
977 break;
978 default:
979 assert(0);
980 return;
981 }
982 }
983
984 /* if true then invert, see GL_ARB_conditional_render_inverted */
985 if (invert)
986 op |= PREDICATION_DRAW_NOT_VISIBLE; /* Draw if not visible or overflow */
987 else
988 op |= PREDICATION_DRAW_VISIBLE; /* Draw if visible or no overflow */
989
990 /* Use the value written by compute shader as a workaround. Note that
991 * the wait flag does not apply in this predication mode.
992 *
993 * The shader outputs the result value to L2. Workarounds only affect VI
994 * and later, where the CP reads data from L2, so we don't need an
995 * additional flush.
996 */
997 if (query->workaround_buf) {
998 uint64_t va = query->workaround_buf->gpu_address + query->workaround_offset;
999 emit_set_predicate(ctx, query->workaround_buf, va, op);
1000 return;
1001 }
1002
1003 op |= flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW;
1004
1005 /* emit predicate packets for all data blocks */
1006 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
1007 unsigned results_base = 0;
1008 uint64_t va_base = qbuf->buf->gpu_address;
1009
1010 while (results_base < qbuf->results_end) {
1011 uint64_t va = va_base + results_base;
1012
1013 if (query->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE) {
1014 for (unsigned stream = 0; stream < R600_MAX_STREAMS; ++stream) {
1015 emit_set_predicate(ctx, qbuf->buf, va + 32 * stream, op);
1016
1017 /* set CONTINUE bit for all packets except the first */
1018 op |= PREDICATION_CONTINUE;
1019 }
1020 } else {
1021 emit_set_predicate(ctx, qbuf->buf, va, op);
1022 op |= PREDICATION_CONTINUE;
1023 }
1024
1025 results_base += query->result_size;
1026 }
1027 }
1028 }
1029
1030 static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type, unsigned index)
1031 {
1032 struct r600_common_screen *rscreen =
1033 (struct r600_common_screen *)ctx->screen;
1034
1035 if (query_type == PIPE_QUERY_TIMESTAMP_DISJOINT ||
1036 query_type == PIPE_QUERY_GPU_FINISHED ||
1037 query_type >= PIPE_QUERY_DRIVER_SPECIFIC)
1038 return r600_query_sw_create(query_type);
1039
1040 return r600_query_hw_create(rscreen, query_type, index);
1041 }
1042
1043 static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
1044 {
1045 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1046 struct r600_query *rquery = (struct r600_query *)query;
1047
1048 rquery->ops->destroy(rctx->screen, rquery);
1049 }
1050
1051 static boolean r600_begin_query(struct pipe_context *ctx,
1052 struct pipe_query *query)
1053 {
1054 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1055 struct r600_query *rquery = (struct r600_query *)query;
1056
1057 return rquery->ops->begin(rctx, rquery);
1058 }
1059
1060 void r600_query_hw_reset_buffers(struct r600_common_context *rctx,
1061 struct r600_query_hw *query)
1062 {
1063 struct r600_query_buffer *prev = query->buffer.previous;
1064
1065 /* Discard the old query buffers. */
1066 while (prev) {
1067 struct r600_query_buffer *qbuf = prev;
1068 prev = prev->previous;
1069 r600_resource_reference(&qbuf->buf, NULL);
1070 FREE(qbuf);
1071 }
1072
1073 query->buffer.results_end = 0;
1074 query->buffer.previous = NULL;
1075
1076 /* Obtain a new buffer if the current one can't be mapped without a stall. */
1077 if (r600_rings_is_buffer_referenced(rctx, query->buffer.buf->buf, RADEON_USAGE_READWRITE) ||
1078 !rctx->ws->buffer_wait(query->buffer.buf->buf, 0, RADEON_USAGE_READWRITE)) {
1079 r600_resource_reference(&query->buffer.buf, NULL);
1080 query->buffer.buf = r600_new_query_buffer(rctx->screen, query);
1081 } else {
1082 if (!query->ops->prepare_buffer(rctx->screen, query, query->buffer.buf))
1083 r600_resource_reference(&query->buffer.buf, NULL);
1084 }
1085 }
1086
1087 bool r600_query_hw_begin(struct r600_common_context *rctx,
1088 struct r600_query *rquery)
1089 {
1090 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
1091
1092 if (query->flags & R600_QUERY_HW_FLAG_NO_START) {
1093 assert(0);
1094 return false;
1095 }
1096
1097 if (!(query->flags & R600_QUERY_HW_FLAG_BEGIN_RESUMES))
1098 r600_query_hw_reset_buffers(rctx, query);
1099
1100 r600_resource_reference(&query->workaround_buf, NULL);
1101
1102 r600_query_hw_emit_start(rctx, query);
1103 if (!query->buffer.buf)
1104 return false;
1105
1106 LIST_ADDTAIL(&query->list, &rctx->active_queries);
1107 return true;
1108 }
1109
1110 static bool r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
1111 {
1112 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1113 struct r600_query *rquery = (struct r600_query *)query;
1114
1115 return rquery->ops->end(rctx, rquery);
1116 }
1117
1118 bool r600_query_hw_end(struct r600_common_context *rctx,
1119 struct r600_query *rquery)
1120 {
1121 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
1122
1123 if (query->flags & R600_QUERY_HW_FLAG_NO_START)
1124 r600_query_hw_reset_buffers(rctx, query);
1125
1126 r600_query_hw_emit_stop(rctx, query);
1127
1128 if (!(query->flags & R600_QUERY_HW_FLAG_NO_START))
1129 LIST_DELINIT(&query->list);
1130
1131 if (!query->buffer.buf)
1132 return false;
1133
1134 return true;
1135 }
1136
1137 static void r600_get_hw_query_params(struct r600_common_context *rctx,
1138 struct r600_query_hw *rquery, int index,
1139 struct r600_hw_query_params *params)
1140 {
1141 unsigned max_rbs = rctx->screen->info.num_render_backends;
1142
1143 params->pair_stride = 0;
1144 params->pair_count = 1;
1145
1146 switch (rquery->b.type) {
1147 case PIPE_QUERY_OCCLUSION_COUNTER:
1148 case PIPE_QUERY_OCCLUSION_PREDICATE:
1149 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1150 params->start_offset = 0;
1151 params->end_offset = 8;
1152 params->fence_offset = max_rbs * 16;
1153 params->pair_stride = 16;
1154 params->pair_count = max_rbs;
1155 break;
1156 case PIPE_QUERY_TIME_ELAPSED:
1157 params->start_offset = 0;
1158 params->end_offset = 8;
1159 params->fence_offset = 16;
1160 break;
1161 case PIPE_QUERY_TIMESTAMP:
1162 params->start_offset = 0;
1163 params->end_offset = 0;
1164 params->fence_offset = 8;
1165 break;
1166 case PIPE_QUERY_PRIMITIVES_EMITTED:
1167 params->start_offset = 8;
1168 params->end_offset = 24;
1169 params->fence_offset = params->end_offset + 4;
1170 break;
1171 case PIPE_QUERY_PRIMITIVES_GENERATED:
1172 params->start_offset = 0;
1173 params->end_offset = 16;
1174 params->fence_offset = params->end_offset + 4;
1175 break;
1176 case PIPE_QUERY_SO_STATISTICS:
1177 params->start_offset = 8 - index * 8;
1178 params->end_offset = 24 - index * 8;
1179 params->fence_offset = params->end_offset + 4;
1180 break;
1181 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
1182 params->pair_count = R600_MAX_STREAMS;
1183 params->pair_stride = 32;
1184 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1185 params->start_offset = 0;
1186 params->end_offset = 16;
1187
1188 /* We can re-use the high dword of the last 64-bit value as a
1189 * fence: it is initialized as 0, and the high bit is set by
1190 * the write of the streamout stats event.
1191 */
1192 params->fence_offset = rquery->result_size - 4;
1193 break;
1194 case PIPE_QUERY_PIPELINE_STATISTICS:
1195 {
1196 /* Offsets apply to EG+ */
1197 static const unsigned offsets[] = {56, 48, 24, 32, 40, 16, 8, 0, 64, 72, 80};
1198 params->start_offset = offsets[index];
1199 params->end_offset = 88 + offsets[index];
1200 params->fence_offset = 2 * 88;
1201 break;
1202 }
1203 default:
1204 unreachable("r600_get_hw_query_params unsupported");
1205 }
1206 }
1207
1208 static unsigned r600_query_read_result(void *map, unsigned start_index, unsigned end_index,
1209 bool test_status_bit)
1210 {
1211 uint32_t *current_result = (uint32_t*)map;
1212 uint64_t start, end;
1213
1214 start = (uint64_t)current_result[start_index] |
1215 (uint64_t)current_result[start_index+1] << 32;
1216 end = (uint64_t)current_result[end_index] |
1217 (uint64_t)current_result[end_index+1] << 32;
1218
1219 if (!test_status_bit ||
1220 ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) {
1221 return end - start;
1222 }
1223 return 0;
1224 }
1225
1226 static void r600_query_hw_add_result(struct r600_common_screen *rscreen,
1227 struct r600_query_hw *query,
1228 void *buffer,
1229 union pipe_query_result *result)
1230 {
1231 unsigned max_rbs = rscreen->info.num_render_backends;
1232
1233 switch (query->b.type) {
1234 case PIPE_QUERY_OCCLUSION_COUNTER: {
1235 for (unsigned i = 0; i < max_rbs; ++i) {
1236 unsigned results_base = i * 16;
1237 result->u64 +=
1238 r600_query_read_result(buffer + results_base, 0, 2, true);
1239 }
1240 break;
1241 }
1242 case PIPE_QUERY_OCCLUSION_PREDICATE:
1243 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: {
1244 for (unsigned i = 0; i < max_rbs; ++i) {
1245 unsigned results_base = i * 16;
1246 result->b = result->b ||
1247 r600_query_read_result(buffer + results_base, 0, 2, true) != 0;
1248 }
1249 break;
1250 }
1251 case PIPE_QUERY_TIME_ELAPSED:
1252 result->u64 += r600_query_read_result(buffer, 0, 2, false);
1253 break;
1254 case PIPE_QUERY_TIMESTAMP:
1255 result->u64 = *(uint64_t*)buffer;
1256 break;
1257 case PIPE_QUERY_PRIMITIVES_EMITTED:
1258 /* SAMPLE_STREAMOUTSTATS stores this structure:
1259 * {
1260 * u64 NumPrimitivesWritten;
1261 * u64 PrimitiveStorageNeeded;
1262 * }
1263 * We only need NumPrimitivesWritten here. */
1264 result->u64 += r600_query_read_result(buffer, 2, 6, true);
1265 break;
1266 case PIPE_QUERY_PRIMITIVES_GENERATED:
1267 /* Here we read PrimitiveStorageNeeded. */
1268 result->u64 += r600_query_read_result(buffer, 0, 4, true);
1269 break;
1270 case PIPE_QUERY_SO_STATISTICS:
1271 result->so_statistics.num_primitives_written +=
1272 r600_query_read_result(buffer, 2, 6, true);
1273 result->so_statistics.primitives_storage_needed +=
1274 r600_query_read_result(buffer, 0, 4, true);
1275 break;
1276 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1277 result->b = result->b ||
1278 r600_query_read_result(buffer, 2, 6, true) !=
1279 r600_query_read_result(buffer, 0, 4, true);
1280 break;
1281 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
1282 for (unsigned stream = 0; stream < R600_MAX_STREAMS; ++stream) {
1283 result->b = result->b ||
1284 r600_query_read_result(buffer, 2, 6, true) !=
1285 r600_query_read_result(buffer, 0, 4, true);
1286 buffer = (char *)buffer + 32;
1287 }
1288 break;
1289 case PIPE_QUERY_PIPELINE_STATISTICS:
1290 if (rscreen->chip_class >= EVERGREEN) {
1291 result->pipeline_statistics.ps_invocations +=
1292 r600_query_read_result(buffer, 0, 22, false);
1293 result->pipeline_statistics.c_primitives +=
1294 r600_query_read_result(buffer, 2, 24, false);
1295 result->pipeline_statistics.c_invocations +=
1296 r600_query_read_result(buffer, 4, 26, false);
1297 result->pipeline_statistics.vs_invocations +=
1298 r600_query_read_result(buffer, 6, 28, false);
1299 result->pipeline_statistics.gs_invocations +=
1300 r600_query_read_result(buffer, 8, 30, false);
1301 result->pipeline_statistics.gs_primitives +=
1302 r600_query_read_result(buffer, 10, 32, false);
1303 result->pipeline_statistics.ia_primitives +=
1304 r600_query_read_result(buffer, 12, 34, false);
1305 result->pipeline_statistics.ia_vertices +=
1306 r600_query_read_result(buffer, 14, 36, false);
1307 result->pipeline_statistics.hs_invocations +=
1308 r600_query_read_result(buffer, 16, 38, false);
1309 result->pipeline_statistics.ds_invocations +=
1310 r600_query_read_result(buffer, 18, 40, false);
1311 result->pipeline_statistics.cs_invocations +=
1312 r600_query_read_result(buffer, 20, 42, false);
1313 } else {
1314 result->pipeline_statistics.ps_invocations +=
1315 r600_query_read_result(buffer, 0, 16, false);
1316 result->pipeline_statistics.c_primitives +=
1317 r600_query_read_result(buffer, 2, 18, false);
1318 result->pipeline_statistics.c_invocations +=
1319 r600_query_read_result(buffer, 4, 20, false);
1320 result->pipeline_statistics.vs_invocations +=
1321 r600_query_read_result(buffer, 6, 22, false);
1322 result->pipeline_statistics.gs_invocations +=
1323 r600_query_read_result(buffer, 8, 24, false);
1324 result->pipeline_statistics.gs_primitives +=
1325 r600_query_read_result(buffer, 10, 26, false);
1326 result->pipeline_statistics.ia_primitives +=
1327 r600_query_read_result(buffer, 12, 28, false);
1328 result->pipeline_statistics.ia_vertices +=
1329 r600_query_read_result(buffer, 14, 30, false);
1330 }
1331 #if 0 /* for testing */
1332 printf("Pipeline stats: IA verts=%llu, IA prims=%llu, VS=%llu, HS=%llu, "
1333 "DS=%llu, GS=%llu, GS prims=%llu, Clipper=%llu, "
1334 "Clipper prims=%llu, PS=%llu, CS=%llu\n",
1335 result->pipeline_statistics.ia_vertices,
1336 result->pipeline_statistics.ia_primitives,
1337 result->pipeline_statistics.vs_invocations,
1338 result->pipeline_statistics.hs_invocations,
1339 result->pipeline_statistics.ds_invocations,
1340 result->pipeline_statistics.gs_invocations,
1341 result->pipeline_statistics.gs_primitives,
1342 result->pipeline_statistics.c_invocations,
1343 result->pipeline_statistics.c_primitives,
1344 result->pipeline_statistics.ps_invocations,
1345 result->pipeline_statistics.cs_invocations);
1346 #endif
1347 break;
1348 default:
1349 assert(0);
1350 }
1351 }
1352
1353 static boolean r600_get_query_result(struct pipe_context *ctx,
1354 struct pipe_query *query, boolean wait,
1355 union pipe_query_result *result)
1356 {
1357 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1358 struct r600_query *rquery = (struct r600_query *)query;
1359
1360 return rquery->ops->get_result(rctx, rquery, wait, result);
1361 }
1362
1363 static void r600_get_query_result_resource(struct pipe_context *ctx,
1364 struct pipe_query *query,
1365 boolean wait,
1366 enum pipe_query_value_type result_type,
1367 int index,
1368 struct pipe_resource *resource,
1369 unsigned offset)
1370 {
1371 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1372 struct r600_query *rquery = (struct r600_query *)query;
1373
1374 rquery->ops->get_result_resource(rctx, rquery, wait, result_type, index,
1375 resource, offset);
1376 }
1377
1378 static void r600_query_hw_clear_result(struct r600_query_hw *query,
1379 union pipe_query_result *result)
1380 {
1381 util_query_clear_result(result, query->b.type);
1382 }
1383
1384 bool r600_query_hw_get_result(struct r600_common_context *rctx,
1385 struct r600_query *rquery,
1386 bool wait, union pipe_query_result *result)
1387 {
1388 struct r600_common_screen *rscreen = rctx->screen;
1389 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
1390 struct r600_query_buffer *qbuf;
1391
1392 query->ops->clear_result(query, result);
1393
1394 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
1395 unsigned usage = PIPE_TRANSFER_READ |
1396 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK);
1397 unsigned results_base = 0;
1398 void *map;
1399
1400 if (rquery->b.flushed)
1401 map = rctx->ws->buffer_map(qbuf->buf->buf, NULL, usage);
1402 else
1403 map = r600_buffer_map_sync_with_rings(rctx, qbuf->buf, usage);
1404
1405 if (!map)
1406 return false;
1407
1408 while (results_base != qbuf->results_end) {
1409 query->ops->add_result(rscreen, query, map + results_base,
1410 result);
1411 results_base += query->result_size;
1412 }
1413 }
1414
1415 /* Convert the time to expected units. */
1416 if (rquery->type == PIPE_QUERY_TIME_ELAPSED ||
1417 rquery->type == PIPE_QUERY_TIMESTAMP) {
1418 result->u64 = (1000000 * result->u64) / rscreen->info.clock_crystal_freq;
1419 }
1420 return true;
1421 }
1422
1423 /* Create the compute shader that is used to collect the results.
1424 *
1425 * One compute grid with a single thread is launched for every query result
1426 * buffer. The thread (optionally) reads a previous summary buffer, then
1427 * accumulates data from the query result buffer, and writes the result either
1428 * to a summary buffer to be consumed by the next grid invocation or to the
1429 * user-supplied buffer.
1430 *
1431 * Data layout:
1432 *
1433 * CONST
1434 * 0.x = end_offset
1435 * 0.y = result_stride
1436 * 0.z = result_count
1437 * 0.w = bit field:
1438 * 1: read previously accumulated values
1439 * 2: write accumulated values for chaining
1440 * 4: write result available
1441 * 8: convert result to boolean (0/1)
1442 * 16: only read one dword and use that as result
1443 * 32: apply timestamp conversion
1444 * 64: store full 64 bits result
1445 * 128: store signed 32 bits result
1446 * 256: SO_OVERFLOW mode: take the difference of two successive half-pairs
1447 * 1.x = fence_offset
1448 * 1.y = pair_stride
1449 * 1.z = pair_count
1450 *
1451 * BUFFER[0] = query result buffer
1452 * BUFFER[1] = previous summary buffer
1453 * BUFFER[2] = next summary buffer or user-supplied buffer
1454 */
1455 static void r600_create_query_result_shader(struct r600_common_context *rctx)
1456 {
1457 /* TEMP[0].xy = accumulated result so far
1458 * TEMP[0].z = result not available
1459 *
1460 * TEMP[1].x = current result index
1461 * TEMP[1].y = current pair index
1462 */
1463 static const char text_tmpl[] =
1464 "COMP\n"
1465 "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
1466 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
1467 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
1468 "DCL BUFFER[0]\n"
1469 "DCL BUFFER[1]\n"
1470 "DCL BUFFER[2]\n"
1471 "DCL CONST[0][0..1]\n"
1472 "DCL TEMP[0..5]\n"
1473 "IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n"
1474 "IMM[1] UINT32 {1, 2, 4, 8}\n"
1475 "IMM[2] UINT32 {16, 32, 64, 128}\n"
1476 "IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */
1477 "IMM[4] UINT32 {256, 0, 0, 0}\n"
1478
1479 "AND TEMP[5], CONST[0][0].wwww, IMM[2].xxxx\n"
1480 "UIF TEMP[5]\n"
1481 /* Check result availability. */
1482 "LOAD TEMP[1].x, BUFFER[0], CONST[0][1].xxxx\n"
1483 "ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n"
1484 "MOV TEMP[1], TEMP[0].zzzz\n"
1485 "NOT TEMP[0].z, TEMP[0].zzzz\n"
1486
1487 /* Load result if available. */
1488 "UIF TEMP[1]\n"
1489 "LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n"
1490 "ENDIF\n"
1491 "ELSE\n"
1492 /* Load previously accumulated result if requested. */
1493 "MOV TEMP[0], IMM[0].xxxx\n"
1494 "AND TEMP[4], CONST[0][0].wwww, IMM[1].xxxx\n"
1495 "UIF TEMP[4]\n"
1496 "LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n"
1497 "ENDIF\n"
1498
1499 "MOV TEMP[1].x, IMM[0].xxxx\n"
1500 "BGNLOOP\n"
1501 /* Break if accumulated result so far is not available. */
1502 "UIF TEMP[0].zzzz\n"
1503 "BRK\n"
1504 "ENDIF\n"
1505
1506 /* Break if result_index >= result_count. */
1507 "USGE TEMP[5], TEMP[1].xxxx, CONST[0][0].zzzz\n"
1508 "UIF TEMP[5]\n"
1509 "BRK\n"
1510 "ENDIF\n"
1511
1512 /* Load fence and check result availability */
1513 "UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy, CONST[0][1].xxxx\n"
1514 "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
1515 "ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n"
1516 "NOT TEMP[0].z, TEMP[0].zzzz\n"
1517 "UIF TEMP[0].zzzz\n"
1518 "BRK\n"
1519 "ENDIF\n"
1520
1521 "MOV TEMP[1].y, IMM[0].xxxx\n"
1522 "BGNLOOP\n"
1523 /* Load start and end. */
1524 "UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy\n"
1525 "UMAD TEMP[5].x, TEMP[1].yyyy, CONST[0][1].yyyy, TEMP[5].xxxx\n"
1526 "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
1527
1528 "UADD TEMP[5].y, TEMP[5].xxxx, CONST[0][0].xxxx\n"
1529 "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
1530
1531 "U64ADD TEMP[4].xy, TEMP[3], -TEMP[2]\n"
1532
1533 "AND TEMP[5].z, CONST[0][0].wwww, IMM[4].xxxx\n"
1534 "UIF TEMP[5].zzzz\n"
1535 /* Load second start/end half-pair and
1536 * take the difference
1537 */
1538 "UADD TEMP[5].xy, TEMP[5], IMM[1].wwww\n"
1539 "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
1540 "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
1541
1542 "U64ADD TEMP[3].xy, TEMP[3], -TEMP[2]\n"
1543 "U64ADD TEMP[4].xy, TEMP[4], -TEMP[3]\n"
1544 "ENDIF\n"
1545
1546 "U64ADD TEMP[0].xy, TEMP[0], TEMP[4]\n"
1547
1548 /* Increment pair index */
1549 "UADD TEMP[1].y, TEMP[1].yyyy, IMM[1].xxxx\n"
1550 "USGE TEMP[5], TEMP[1].yyyy, CONST[0][1].zzzz\n"
1551 "UIF TEMP[5]\n"
1552 "BRK\n"
1553 "ENDIF\n"
1554 "ENDLOOP\n"
1555
1556 /* Increment result index */
1557 "UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n"
1558 "ENDLOOP\n"
1559 "ENDIF\n"
1560
1561 "AND TEMP[4], CONST[0][0].wwww, IMM[1].yyyy\n"
1562 "UIF TEMP[4]\n"
1563 /* Store accumulated data for chaining. */
1564 "STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n"
1565 "ELSE\n"
1566 "AND TEMP[4], CONST[0][0].wwww, IMM[1].zzzz\n"
1567 "UIF TEMP[4]\n"
1568 /* Store result availability. */
1569 "NOT TEMP[0].z, TEMP[0]\n"
1570 "AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n"
1571 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n"
1572
1573 "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
1574 "UIF TEMP[4]\n"
1575 "STORE BUFFER[2].y, IMM[0].xxxx, IMM[0].xxxx\n"
1576 "ENDIF\n"
1577 "ELSE\n"
1578 /* Store result if it is available. */
1579 "NOT TEMP[4], TEMP[0].zzzz\n"
1580 "UIF TEMP[4]\n"
1581 /* Apply timestamp conversion */
1582 "AND TEMP[4], CONST[0][0].wwww, IMM[2].yyyy\n"
1583 "UIF TEMP[4]\n"
1584 "U64MUL TEMP[0].xy, TEMP[0], IMM[3].xyxy\n"
1585 "U64DIV TEMP[0].xy, TEMP[0], IMM[3].zwzw\n"
1586 "ENDIF\n"
1587
1588 /* Convert to boolean */
1589 "AND TEMP[4], CONST[0][0].wwww, IMM[1].wwww\n"
1590 "UIF TEMP[4]\n"
1591 "U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[4].zwzw\n"
1592 "AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n"
1593 "MOV TEMP[0].y, IMM[0].xxxx\n"
1594 "ENDIF\n"
1595
1596 "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
1597 "UIF TEMP[4]\n"
1598 "STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0].xyxy\n"
1599 "ELSE\n"
1600 /* Clamping */
1601 "UIF TEMP[0].yyyy\n"
1602 "MOV TEMP[0].x, IMM[0].wwww\n"
1603 "ENDIF\n"
1604
1605 "AND TEMP[4], CONST[0][0].wwww, IMM[2].wwww\n"
1606 "UIF TEMP[4]\n"
1607 "UMIN TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz\n"
1608 "ENDIF\n"
1609
1610 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n"
1611 "ENDIF\n"
1612 "ENDIF\n"
1613 "ENDIF\n"
1614 "ENDIF\n"
1615
1616 "END\n";
1617
1618 char text[sizeof(text_tmpl) + 32];
1619 struct tgsi_token tokens[1024];
1620 struct pipe_compute_state state = {};
1621
1622 /* Hard code the frequency into the shader so that the backend can
1623 * use the full range of optimizations for divide-by-constant.
1624 */
1625 snprintf(text, sizeof(text), text_tmpl,
1626 rctx->screen->info.clock_crystal_freq);
1627
1628 if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
1629 assert(false);
1630 return;
1631 }
1632
1633 state.ir_type = PIPE_SHADER_IR_TGSI;
1634 state.prog = tokens;
1635
1636 rctx->query_result_shader = rctx->b.create_compute_state(&rctx->b, &state);
1637 }
1638
1639 static void r600_restore_qbo_state(struct r600_common_context *rctx,
1640 struct r600_qbo_state *st)
1641 {
1642 rctx->b.bind_compute_state(&rctx->b, st->saved_compute);
1643
1644 rctx->b.set_constant_buffer(&rctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1645 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1646
1647 rctx->b.set_shader_buffers(&rctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1648 for (unsigned i = 0; i < 3; ++i)
1649 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1650 }
1651
1652 static void r600_query_hw_get_result_resource(struct r600_common_context *rctx,
1653 struct r600_query *rquery,
1654 bool wait,
1655 enum pipe_query_value_type result_type,
1656 int index,
1657 struct pipe_resource *resource,
1658 unsigned offset)
1659 {
1660 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
1661 struct r600_query_buffer *qbuf;
1662 struct r600_query_buffer *qbuf_prev;
1663 struct pipe_resource *tmp_buffer = NULL;
1664 unsigned tmp_buffer_offset = 0;
1665 struct r600_qbo_state saved_state = {};
1666 struct pipe_grid_info grid = {};
1667 struct pipe_constant_buffer constant_buffer = {};
1668 struct pipe_shader_buffer ssbo[3];
1669 struct r600_hw_query_params params;
1670 struct {
1671 uint32_t end_offset;
1672 uint32_t result_stride;
1673 uint32_t result_count;
1674 uint32_t config;
1675 uint32_t fence_offset;
1676 uint32_t pair_stride;
1677 uint32_t pair_count;
1678 } consts;
1679
1680 if (!rctx->query_result_shader) {
1681 r600_create_query_result_shader(rctx);
1682 if (!rctx->query_result_shader)
1683 return;
1684 }
1685
1686 if (query->buffer.previous) {
1687 u_suballocator_alloc(rctx->allocator_zeroed_memory, 16, 16,
1688 &tmp_buffer_offset, &tmp_buffer);
1689 if (!tmp_buffer)
1690 return;
1691 }
1692
1693 rctx->save_qbo_state(&rctx->b, &saved_state);
1694
1695 r600_get_hw_query_params(rctx, query, index >= 0 ? index : 0, &params);
1696 consts.end_offset = params.end_offset - params.start_offset;
1697 consts.fence_offset = params.fence_offset - params.start_offset;
1698 consts.result_stride = query->result_size;
1699 consts.pair_stride = params.pair_stride;
1700 consts.pair_count = params.pair_count;
1701
1702 constant_buffer.buffer_size = sizeof(consts);
1703 constant_buffer.user_buffer = &consts;
1704
1705 ssbo[1].buffer = tmp_buffer;
1706 ssbo[1].buffer_offset = tmp_buffer_offset;
1707 ssbo[1].buffer_size = 16;
1708
1709 ssbo[2] = ssbo[1];
1710
1711 rctx->b.bind_compute_state(&rctx->b, rctx->query_result_shader);
1712
1713 grid.block[0] = 1;
1714 grid.block[1] = 1;
1715 grid.block[2] = 1;
1716 grid.grid[0] = 1;
1717 grid.grid[1] = 1;
1718 grid.grid[2] = 1;
1719
1720 consts.config = 0;
1721 if (index < 0)
1722 consts.config |= 4;
1723 if (query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE ||
1724 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE)
1725 consts.config |= 8;
1726 else if (query->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE ||
1727 query->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE)
1728 consts.config |= 8 | 256;
1729 else if (query->b.type == PIPE_QUERY_TIMESTAMP ||
1730 query->b.type == PIPE_QUERY_TIME_ELAPSED)
1731 consts.config |= 32;
1732
1733 switch (result_type) {
1734 case PIPE_QUERY_TYPE_U64:
1735 case PIPE_QUERY_TYPE_I64:
1736 consts.config |= 64;
1737 break;
1738 case PIPE_QUERY_TYPE_I32:
1739 consts.config |= 128;
1740 break;
1741 case PIPE_QUERY_TYPE_U32:
1742 break;
1743 }
1744
1745 rctx->flags |= rctx->screen->barrier_flags.cp_to_L2;
1746
1747 for (qbuf = &query->buffer; qbuf; qbuf = qbuf_prev) {
1748 if (query->b.type != PIPE_QUERY_TIMESTAMP) {
1749 qbuf_prev = qbuf->previous;
1750 consts.result_count = qbuf->results_end / query->result_size;
1751 consts.config &= ~3;
1752 if (qbuf != &query->buffer)
1753 consts.config |= 1;
1754 if (qbuf->previous)
1755 consts.config |= 2;
1756 } else {
1757 /* Only read the last timestamp. */
1758 qbuf_prev = NULL;
1759 consts.result_count = 0;
1760 consts.config |= 16;
1761 params.start_offset += qbuf->results_end - query->result_size;
1762 }
1763
1764 rctx->b.set_constant_buffer(&rctx->b, PIPE_SHADER_COMPUTE, 0, &constant_buffer);
1765
1766 ssbo[0].buffer = &qbuf->buf->b.b;
1767 ssbo[0].buffer_offset = params.start_offset;
1768 ssbo[0].buffer_size = qbuf->results_end - params.start_offset;
1769
1770 if (!qbuf->previous) {
1771 ssbo[2].buffer = resource;
1772 ssbo[2].buffer_offset = offset;
1773 ssbo[2].buffer_size = 8;
1774
1775 ((struct r600_resource *)resource)->TC_L2_dirty = true;
1776 }
1777
1778 rctx->b.set_shader_buffers(&rctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo);
1779
1780 if (wait && qbuf == &query->buffer) {
1781 uint64_t va;
1782
1783 /* Wait for result availability. Wait only for readiness
1784 * of the last entry, since the fence writes should be
1785 * serialized in the CP.
1786 */
1787 va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size;
1788 va += params.fence_offset;
1789
1790 r600_gfx_wait_fence(rctx, va, 0x80000000, 0x80000000);
1791 }
1792
1793 rctx->b.launch_grid(&rctx->b, &grid);
1794 rctx->flags |= rctx->screen->barrier_flags.compute_to_L2;
1795 }
1796
1797 r600_restore_qbo_state(rctx, &saved_state);
1798 pipe_resource_reference(&tmp_buffer, NULL);
1799 }
1800
1801 static void r600_render_condition(struct pipe_context *ctx,
1802 struct pipe_query *query,
1803 boolean condition,
1804 enum pipe_render_cond_flag mode)
1805 {
1806 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1807 struct r600_query_hw *rquery = (struct r600_query_hw *)query;
1808 struct r600_query_buffer *qbuf;
1809 struct r600_atom *atom = &rctx->render_cond_atom;
1810
1811 /* Compute the size of SET_PREDICATION packets. */
1812 atom->num_dw = 0;
1813 if (query) {
1814 bool needs_workaround = false;
1815
1816 /* There was a firmware regression in VI which causes successive
1817 * SET_PREDICATION packets to give the wrong answer for
1818 * non-inverted stream overflow predication.
1819 */
1820 if (((rctx->chip_class == VI && rctx->screen->info.pfp_fw_feature < 49) ||
1821 (rctx->chip_class == GFX9 && rctx->screen->info.pfp_fw_feature < 38)) &&
1822 !condition &&
1823 (rquery->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE ||
1824 (rquery->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE &&
1825 (rquery->buffer.previous ||
1826 rquery->buffer.results_end > rquery->result_size)))) {
1827 needs_workaround = true;
1828 }
1829
1830 if (needs_workaround && !rquery->workaround_buf) {
1831 bool old_force_off = rctx->render_cond_force_off;
1832 rctx->render_cond_force_off = true;
1833
1834 u_suballocator_alloc(
1835 rctx->allocator_zeroed_memory, 8, 8,
1836 &rquery->workaround_offset,
1837 (struct pipe_resource **)&rquery->workaround_buf);
1838
1839 /* Reset to NULL to avoid a redundant SET_PREDICATION
1840 * from launching the compute grid.
1841 */
1842 rctx->render_cond = NULL;
1843
1844 ctx->get_query_result_resource(
1845 ctx, query, true, PIPE_QUERY_TYPE_U64, 0,
1846 &rquery->workaround_buf->b.b, rquery->workaround_offset);
1847
1848 /* Settings this in the render cond atom is too late,
1849 * so set it here. */
1850 rctx->flags |= rctx->screen->barrier_flags.L2_to_cp |
1851 R600_CONTEXT_FLUSH_FOR_RENDER_COND;
1852
1853 rctx->render_cond_force_off = old_force_off;
1854 }
1855
1856 if (needs_workaround) {
1857 atom->num_dw = 5;
1858 } else {
1859 for (qbuf = &rquery->buffer; qbuf; qbuf = qbuf->previous)
1860 atom->num_dw += (qbuf->results_end / rquery->result_size) * 5;
1861
1862 if (rquery->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE)
1863 atom->num_dw *= R600_MAX_STREAMS;
1864 }
1865 }
1866
1867 rctx->render_cond = query;
1868 rctx->render_cond_invert = condition;
1869 rctx->render_cond_mode = mode;
1870
1871 rctx->set_atom_dirty(rctx, atom, query != NULL);
1872 }
1873
1874 void r600_suspend_queries(struct r600_common_context *ctx)
1875 {
1876 struct r600_query_hw *query;
1877
1878 LIST_FOR_EACH_ENTRY(query, &ctx->active_queries, list) {
1879 r600_query_hw_emit_stop(ctx, query);
1880 }
1881 assert(ctx->num_cs_dw_queries_suspend == 0);
1882 }
1883
1884 static unsigned r600_queries_num_cs_dw_for_resuming(struct r600_common_context *ctx,
1885 struct list_head *query_list)
1886 {
1887 struct r600_query_hw *query;
1888 unsigned num_dw = 0;
1889
1890 LIST_FOR_EACH_ENTRY(query, query_list, list) {
1891 /* begin + end */
1892 num_dw += query->num_cs_dw_begin + query->num_cs_dw_end;
1893
1894 /* Workaround for the fact that
1895 * num_cs_dw_nontimer_queries_suspend is incremented for every
1896 * resumed query, which raises the bar in need_cs_space for
1897 * queries about to be resumed.
1898 */
1899 num_dw += query->num_cs_dw_end;
1900 }
1901 /* primitives generated query */
1902 num_dw += ctx->streamout.enable_atom.num_dw;
1903 /* guess for ZPASS enable or PERFECT_ZPASS_COUNT enable updates */
1904 num_dw += 13;
1905
1906 return num_dw;
1907 }
1908
1909 void r600_resume_queries(struct r600_common_context *ctx)
1910 {
1911 struct r600_query_hw *query;
1912 unsigned num_cs_dw = r600_queries_num_cs_dw_for_resuming(ctx, &ctx->active_queries);
1913
1914 assert(ctx->num_cs_dw_queries_suspend == 0);
1915
1916 /* Check CS space here. Resuming must not be interrupted by flushes. */
1917 ctx->need_gfx_cs_space(&ctx->b, num_cs_dw, true);
1918
1919 LIST_FOR_EACH_ENTRY(query, &ctx->active_queries, list) {
1920 r600_query_hw_emit_start(ctx, query);
1921 }
1922 }
1923
1924 /* Fix radeon_info::enabled_rb_mask for R600, R700, EVERGREEN, NI. */
1925 void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen)
1926 {
1927 struct r600_common_context *ctx =
1928 (struct r600_common_context*)rscreen->aux_context;
1929 struct radeon_winsys_cs *cs = ctx->gfx.cs;
1930 struct r600_resource *buffer;
1931 uint32_t *results;
1932 unsigned i, mask = 0;
1933 unsigned max_rbs = ctx->screen->info.num_render_backends;
1934
1935 assert(rscreen->chip_class <= CAYMAN);
1936
1937 /* if backend_map query is supported by the kernel */
1938 if (rscreen->info.r600_gb_backend_map_valid) {
1939 unsigned num_tile_pipes = rscreen->info.num_tile_pipes;
1940 unsigned backend_map = rscreen->info.r600_gb_backend_map;
1941 unsigned item_width, item_mask;
1942
1943 if (ctx->chip_class >= EVERGREEN) {
1944 item_width = 4;
1945 item_mask = 0x7;
1946 } else {
1947 item_width = 2;
1948 item_mask = 0x3;
1949 }
1950
1951 while (num_tile_pipes--) {
1952 i = backend_map & item_mask;
1953 mask |= (1<<i);
1954 backend_map >>= item_width;
1955 }
1956 if (mask != 0) {
1957 rscreen->info.enabled_rb_mask = mask;
1958 return;
1959 }
1960 }
1961
1962 /* otherwise backup path for older kernels */
1963
1964 /* create buffer for event data */
1965 buffer = (struct r600_resource*)
1966 pipe_buffer_create(ctx->b.screen, 0,
1967 PIPE_USAGE_STAGING, max_rbs * 16);
1968 if (!buffer)
1969 return;
1970
1971 /* initialize buffer with zeroes */
1972 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE);
1973 if (results) {
1974 memset(results, 0, max_rbs * 4 * 4);
1975
1976 /* emit EVENT_WRITE for ZPASS_DONE */
1977 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1978 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
1979 radeon_emit(cs, buffer->gpu_address);
1980 radeon_emit(cs, buffer->gpu_address >> 32);
1981
1982 r600_emit_reloc(ctx, &ctx->gfx, buffer,
1983 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
1984
1985 /* analyze results */
1986 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ);
1987 if (results) {
1988 for(i = 0; i < max_rbs; i++) {
1989 /* at least highest bit will be set if backend is used */
1990 if (results[i*4 + 1])
1991 mask |= (1<<i);
1992 }
1993 }
1994 }
1995
1996 r600_resource_reference(&buffer, NULL);
1997
1998 if (mask)
1999 rscreen->info.enabled_rb_mask = mask;
2000 }
2001
2002 #define XFULL(name_, query_type_, type_, result_type_, group_id_) \
2003 { \
2004 .name = name_, \
2005 .query_type = R600_QUERY_##query_type_, \
2006 .type = PIPE_DRIVER_QUERY_TYPE_##type_, \
2007 .result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_##result_type_, \
2008 .group_id = group_id_ \
2009 }
2010
2011 #define X(name_, query_type_, type_, result_type_) \
2012 XFULL(name_, query_type_, type_, result_type_, ~(unsigned)0)
2013
2014 #define XG(group_, name_, query_type_, type_, result_type_) \
2015 XFULL(name_, query_type_, type_, result_type_, R600_QUERY_GROUP_##group_)
2016
2017 static struct pipe_driver_query_info r600_driver_query_list[] = {
2018 X("num-compilations", NUM_COMPILATIONS, UINT64, CUMULATIVE),
2019 X("num-shaders-created", NUM_SHADERS_CREATED, UINT64, CUMULATIVE),
2020 X("num-shader-cache-hits", NUM_SHADER_CACHE_HITS, UINT64, CUMULATIVE),
2021 X("draw-calls", DRAW_CALLS, UINT64, AVERAGE),
2022 X("decompress-calls", DECOMPRESS_CALLS, UINT64, AVERAGE),
2023 X("MRT-draw-calls", MRT_DRAW_CALLS, UINT64, AVERAGE),
2024 X("prim-restart-calls", PRIM_RESTART_CALLS, UINT64, AVERAGE),
2025 X("spill-draw-calls", SPILL_DRAW_CALLS, UINT64, AVERAGE),
2026 X("compute-calls", COMPUTE_CALLS, UINT64, AVERAGE),
2027 X("spill-compute-calls", SPILL_COMPUTE_CALLS, UINT64, AVERAGE),
2028 X("dma-calls", DMA_CALLS, UINT64, AVERAGE),
2029 X("cp-dma-calls", CP_DMA_CALLS, UINT64, AVERAGE),
2030 X("num-vs-flushes", NUM_VS_FLUSHES, UINT64, AVERAGE),
2031 X("num-ps-flushes", NUM_PS_FLUSHES, UINT64, AVERAGE),
2032 X("num-cs-flushes", NUM_CS_FLUSHES, UINT64, AVERAGE),
2033 X("num-CB-cache-flushes", NUM_CB_CACHE_FLUSHES, UINT64, AVERAGE),
2034 X("num-DB-cache-flushes", NUM_DB_CACHE_FLUSHES, UINT64, AVERAGE),
2035 X("num-L2-invalidates", NUM_L2_INVALIDATES, UINT64, AVERAGE),
2036 X("num-L2-writebacks", NUM_L2_WRITEBACKS, UINT64, AVERAGE),
2037 X("num-resident-handles", NUM_RESIDENT_HANDLES, UINT64, AVERAGE),
2038 X("tc-offloaded-slots", TC_OFFLOADED_SLOTS, UINT64, AVERAGE),
2039 X("tc-direct-slots", TC_DIRECT_SLOTS, UINT64, AVERAGE),
2040 X("tc-num-syncs", TC_NUM_SYNCS, UINT64, AVERAGE),
2041 X("CS-thread-busy", CS_THREAD_BUSY, UINT64, AVERAGE),
2042 X("gallium-thread-busy", GALLIUM_THREAD_BUSY, UINT64, AVERAGE),
2043 X("requested-VRAM", REQUESTED_VRAM, BYTES, AVERAGE),
2044 X("requested-GTT", REQUESTED_GTT, BYTES, AVERAGE),
2045 X("mapped-VRAM", MAPPED_VRAM, BYTES, AVERAGE),
2046 X("mapped-GTT", MAPPED_GTT, BYTES, AVERAGE),
2047 X("buffer-wait-time", BUFFER_WAIT_TIME, MICROSECONDS, CUMULATIVE),
2048 X("num-mapped-buffers", NUM_MAPPED_BUFFERS, UINT64, AVERAGE),
2049 X("num-GFX-IBs", NUM_GFX_IBS, UINT64, AVERAGE),
2050 X("num-SDMA-IBs", NUM_SDMA_IBS, UINT64, AVERAGE),
2051 X("GFX-BO-list-size", GFX_BO_LIST_SIZE, UINT64, AVERAGE),
2052 X("num-bytes-moved", NUM_BYTES_MOVED, BYTES, CUMULATIVE),
2053 X("num-evictions", NUM_EVICTIONS, UINT64, CUMULATIVE),
2054 X("VRAM-CPU-page-faults", NUM_VRAM_CPU_PAGE_FAULTS, UINT64, CUMULATIVE),
2055 X("VRAM-usage", VRAM_USAGE, BYTES, AVERAGE),
2056 X("VRAM-vis-usage", VRAM_VIS_USAGE, BYTES, AVERAGE),
2057 X("GTT-usage", GTT_USAGE, BYTES, AVERAGE),
2058 X("back-buffer-ps-draw-ratio", BACK_BUFFER_PS_DRAW_RATIO, UINT64, AVERAGE),
2059
2060 /* GPIN queries are for the benefit of old versions of GPUPerfStudio,
2061 * which use it as a fallback path to detect the GPU type.
2062 *
2063 * Note: The names of these queries are significant for GPUPerfStudio
2064 * (and possibly their order as well). */
2065 XG(GPIN, "GPIN_000", GPIN_ASIC_ID, UINT, AVERAGE),
2066 XG(GPIN, "GPIN_001", GPIN_NUM_SIMD, UINT, AVERAGE),
2067 XG(GPIN, "GPIN_002", GPIN_NUM_RB, UINT, AVERAGE),
2068 XG(GPIN, "GPIN_003", GPIN_NUM_SPI, UINT, AVERAGE),
2069 XG(GPIN, "GPIN_004", GPIN_NUM_SE, UINT, AVERAGE),
2070
2071 X("temperature", GPU_TEMPERATURE, UINT64, AVERAGE),
2072 X("shader-clock", CURRENT_GPU_SCLK, HZ, AVERAGE),
2073 X("memory-clock", CURRENT_GPU_MCLK, HZ, AVERAGE),
2074
2075 /* The following queries must be at the end of the list because their
2076 * availability is adjusted dynamically based on the DRM version. */
2077 X("GPU-load", GPU_LOAD, UINT64, AVERAGE),
2078 X("GPU-shaders-busy", GPU_SHADERS_BUSY, UINT64, AVERAGE),
2079 X("GPU-ta-busy", GPU_TA_BUSY, UINT64, AVERAGE),
2080 X("GPU-gds-busy", GPU_GDS_BUSY, UINT64, AVERAGE),
2081 X("GPU-vgt-busy", GPU_VGT_BUSY, UINT64, AVERAGE),
2082 X("GPU-ia-busy", GPU_IA_BUSY, UINT64, AVERAGE),
2083 X("GPU-sx-busy", GPU_SX_BUSY, UINT64, AVERAGE),
2084 X("GPU-wd-busy", GPU_WD_BUSY, UINT64, AVERAGE),
2085 X("GPU-bci-busy", GPU_BCI_BUSY, UINT64, AVERAGE),
2086 X("GPU-sc-busy", GPU_SC_BUSY, UINT64, AVERAGE),
2087 X("GPU-pa-busy", GPU_PA_BUSY, UINT64, AVERAGE),
2088 X("GPU-db-busy", GPU_DB_BUSY, UINT64, AVERAGE),
2089 X("GPU-cp-busy", GPU_CP_BUSY, UINT64, AVERAGE),
2090 X("GPU-cb-busy", GPU_CB_BUSY, UINT64, AVERAGE),
2091 X("GPU-sdma-busy", GPU_SDMA_BUSY, UINT64, AVERAGE),
2092 X("GPU-pfp-busy", GPU_PFP_BUSY, UINT64, AVERAGE),
2093 X("GPU-meq-busy", GPU_MEQ_BUSY, UINT64, AVERAGE),
2094 X("GPU-me-busy", GPU_ME_BUSY, UINT64, AVERAGE),
2095 X("GPU-surf-sync-busy", GPU_SURF_SYNC_BUSY, UINT64, AVERAGE),
2096 X("GPU-cp-dma-busy", GPU_CP_DMA_BUSY, UINT64, AVERAGE),
2097 X("GPU-scratch-ram-busy", GPU_SCRATCH_RAM_BUSY, UINT64, AVERAGE),
2098 };
2099
2100 #undef X
2101 #undef XG
2102 #undef XFULL
2103
2104 static unsigned r600_get_num_queries(struct r600_common_screen *rscreen)
2105 {
2106 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
2107 return ARRAY_SIZE(r600_driver_query_list);
2108 else if (rscreen->info.drm_major == 3) {
2109 if (rscreen->chip_class >= VI)
2110 return ARRAY_SIZE(r600_driver_query_list);
2111 else
2112 return ARRAY_SIZE(r600_driver_query_list) - 7;
2113 }
2114 else
2115 return ARRAY_SIZE(r600_driver_query_list) - 25;
2116 }
2117
2118 static int r600_get_driver_query_info(struct pipe_screen *screen,
2119 unsigned index,
2120 struct pipe_driver_query_info *info)
2121 {
2122 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
2123 unsigned num_queries = r600_get_num_queries(rscreen);
2124
2125 if (!info) {
2126 unsigned num_perfcounters =
2127 r600_get_perfcounter_info(rscreen, 0, NULL);
2128
2129 return num_queries + num_perfcounters;
2130 }
2131
2132 if (index >= num_queries)
2133 return r600_get_perfcounter_info(rscreen, index - num_queries, info);
2134
2135 *info = r600_driver_query_list[index];
2136
2137 switch (info->query_type) {
2138 case R600_QUERY_REQUESTED_VRAM:
2139 case R600_QUERY_VRAM_USAGE:
2140 case R600_QUERY_MAPPED_VRAM:
2141 info->max_value.u64 = rscreen->info.vram_size;
2142 break;
2143 case R600_QUERY_REQUESTED_GTT:
2144 case R600_QUERY_GTT_USAGE:
2145 case R600_QUERY_MAPPED_GTT:
2146 info->max_value.u64 = rscreen->info.gart_size;
2147 break;
2148 case R600_QUERY_GPU_TEMPERATURE:
2149 info->max_value.u64 = 125;
2150 break;
2151 case R600_QUERY_VRAM_VIS_USAGE:
2152 info->max_value.u64 = rscreen->info.vram_vis_size;
2153 break;
2154 }
2155
2156 if (info->group_id != ~(unsigned)0 && rscreen->perfcounters)
2157 info->group_id += rscreen->perfcounters->num_groups;
2158
2159 return 1;
2160 }
2161
2162 /* Note: Unfortunately, GPUPerfStudio hardcodes the order of hardware
2163 * performance counter groups, so be careful when changing this and related
2164 * functions.
2165 */
2166 static int r600_get_driver_query_group_info(struct pipe_screen *screen,
2167 unsigned index,
2168 struct pipe_driver_query_group_info *info)
2169 {
2170 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
2171 unsigned num_pc_groups = 0;
2172
2173 if (rscreen->perfcounters)
2174 num_pc_groups = rscreen->perfcounters->num_groups;
2175
2176 if (!info)
2177 return num_pc_groups + R600_NUM_SW_QUERY_GROUPS;
2178
2179 if (index < num_pc_groups)
2180 return r600_get_perfcounter_group_info(rscreen, index, info);
2181
2182 index -= num_pc_groups;
2183 if (index >= R600_NUM_SW_QUERY_GROUPS)
2184 return 0;
2185
2186 info->name = "GPIN";
2187 info->max_active_queries = 5;
2188 info->num_queries = 5;
2189 return 1;
2190 }
2191
2192 void r600_query_init(struct r600_common_context *rctx)
2193 {
2194 rctx->b.create_query = r600_create_query;
2195 rctx->b.create_batch_query = r600_create_batch_query;
2196 rctx->b.destroy_query = r600_destroy_query;
2197 rctx->b.begin_query = r600_begin_query;
2198 rctx->b.end_query = r600_end_query;
2199 rctx->b.get_query_result = r600_get_query_result;
2200 rctx->b.get_query_result_resource = r600_get_query_result_resource;
2201 rctx->render_cond_atom.emit = r600_emit_query_predication;
2202
2203 if (((struct r600_common_screen*)rctx->b.screen)->info.num_render_backends > 0)
2204 rctx->b.render_condition = r600_render_condition;
2205
2206 LIST_INITHEAD(&rctx->active_queries);
2207 }
2208
2209 void r600_init_screen_query_functions(struct r600_common_screen *rscreen)
2210 {
2211 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
2212 rscreen->b.get_driver_query_group_info = r600_get_driver_query_group_info;
2213 }