2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014 Marek Olšák <marek.olsak@amd.com>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "r600_query.h"
27 #include "util/u_memory.h"
28 #include "util/u_upload_mgr.h"
29 #include "os/os_time.h"
30 #include "tgsi/tgsi_text.h"
32 struct r600_hw_query_params
{
33 unsigned start_offset
;
35 unsigned fence_offset
;
40 /* Queries without buffer handling or suspend/resume. */
41 struct r600_query_sw
{
44 uint64_t begin_result
;
50 /* Fence for GPU_FINISHED. */
51 struct pipe_fence_handle
*fence
;
54 static void r600_query_sw_destroy(struct r600_common_context
*rctx
,
55 struct r600_query
*rquery
)
57 struct pipe_screen
*screen
= rctx
->b
.screen
;
58 struct r600_query_sw
*query
= (struct r600_query_sw
*)rquery
;
60 screen
->fence_reference(screen
, &query
->fence
, NULL
);
64 static enum radeon_value_id
winsys_id_from_type(unsigned type
)
67 case R600_QUERY_REQUESTED_VRAM
: return RADEON_REQUESTED_VRAM_MEMORY
;
68 case R600_QUERY_REQUESTED_GTT
: return RADEON_REQUESTED_GTT_MEMORY
;
69 case R600_QUERY_MAPPED_VRAM
: return RADEON_MAPPED_VRAM
;
70 case R600_QUERY_MAPPED_GTT
: return RADEON_MAPPED_GTT
;
71 case R600_QUERY_BUFFER_WAIT_TIME
: return RADEON_BUFFER_WAIT_TIME_NS
;
72 case R600_QUERY_NUM_MAPPED_BUFFERS
: return RADEON_NUM_MAPPED_BUFFERS
;
73 case R600_QUERY_NUM_GFX_IBS
: return RADEON_NUM_GFX_IBS
;
74 case R600_QUERY_NUM_SDMA_IBS
: return RADEON_NUM_SDMA_IBS
;
75 case R600_QUERY_NUM_BYTES_MOVED
: return RADEON_NUM_BYTES_MOVED
;
76 case R600_QUERY_NUM_EVICTIONS
: return RADEON_NUM_EVICTIONS
;
77 case R600_QUERY_VRAM_USAGE
: return RADEON_VRAM_USAGE
;
78 case R600_QUERY_VRAM_VIS_USAGE
: return RADEON_VRAM_VIS_USAGE
;
79 case R600_QUERY_GTT_USAGE
: return RADEON_GTT_USAGE
;
80 case R600_QUERY_GPU_TEMPERATURE
: return RADEON_GPU_TEMPERATURE
;
81 case R600_QUERY_CURRENT_GPU_SCLK
: return RADEON_CURRENT_SCLK
;
82 case R600_QUERY_CURRENT_GPU_MCLK
: return RADEON_CURRENT_MCLK
;
83 case R600_QUERY_CS_THREAD_BUSY
: return RADEON_CS_THREAD_TIME
;
84 default: unreachable("query type does not correspond to winsys id");
88 static bool r600_query_sw_begin(struct r600_common_context
*rctx
,
89 struct r600_query
*rquery
)
91 struct r600_query_sw
*query
= (struct r600_query_sw
*)rquery
;
92 enum radeon_value_id ws_id
;
94 switch(query
->b
.type
) {
95 case PIPE_QUERY_TIMESTAMP_DISJOINT
:
96 case PIPE_QUERY_GPU_FINISHED
:
98 case R600_QUERY_DRAW_CALLS
:
99 query
->begin_result
= rctx
->num_draw_calls
;
101 case R600_QUERY_SPILL_DRAW_CALLS
:
102 query
->begin_result
= rctx
->num_spill_draw_calls
;
104 case R600_QUERY_COMPUTE_CALLS
:
105 query
->begin_result
= rctx
->num_compute_calls
;
107 case R600_QUERY_SPILL_COMPUTE_CALLS
:
108 query
->begin_result
= rctx
->num_spill_compute_calls
;
110 case R600_QUERY_DMA_CALLS
:
111 query
->begin_result
= rctx
->num_dma_calls
;
113 case R600_QUERY_CP_DMA_CALLS
:
114 query
->begin_result
= rctx
->num_cp_dma_calls
;
116 case R600_QUERY_NUM_VS_FLUSHES
:
117 query
->begin_result
= rctx
->num_vs_flushes
;
119 case R600_QUERY_NUM_PS_FLUSHES
:
120 query
->begin_result
= rctx
->num_ps_flushes
;
122 case R600_QUERY_NUM_CS_FLUSHES
:
123 query
->begin_result
= rctx
->num_cs_flushes
;
125 case R600_QUERY_NUM_FB_CACHE_FLUSHES
:
126 query
->begin_result
= rctx
->num_fb_cache_flushes
;
128 case R600_QUERY_NUM_L2_INVALIDATES
:
129 query
->begin_result
= rctx
->num_L2_invalidates
;
131 case R600_QUERY_NUM_L2_WRITEBACKS
:
132 query
->begin_result
= rctx
->num_L2_writebacks
;
134 case R600_QUERY_REQUESTED_VRAM
:
135 case R600_QUERY_REQUESTED_GTT
:
136 case R600_QUERY_MAPPED_VRAM
:
137 case R600_QUERY_MAPPED_GTT
:
138 case R600_QUERY_VRAM_USAGE
:
139 case R600_QUERY_VRAM_VIS_USAGE
:
140 case R600_QUERY_GTT_USAGE
:
141 case R600_QUERY_GPU_TEMPERATURE
:
142 case R600_QUERY_CURRENT_GPU_SCLK
:
143 case R600_QUERY_CURRENT_GPU_MCLK
:
144 case R600_QUERY_BACK_BUFFER_PS_DRAW_RATIO
:
145 case R600_QUERY_NUM_MAPPED_BUFFERS
:
146 query
->begin_result
= 0;
148 case R600_QUERY_BUFFER_WAIT_TIME
:
149 case R600_QUERY_NUM_GFX_IBS
:
150 case R600_QUERY_NUM_SDMA_IBS
:
151 case R600_QUERY_NUM_BYTES_MOVED
:
152 case R600_QUERY_NUM_EVICTIONS
: {
153 enum radeon_value_id ws_id
= winsys_id_from_type(query
->b
.type
);
154 query
->begin_result
= rctx
->ws
->query_value(rctx
->ws
, ws_id
);
157 case R600_QUERY_CS_THREAD_BUSY
:
158 ws_id
= winsys_id_from_type(query
->b
.type
);
159 query
->begin_result
= rctx
->ws
->query_value(rctx
->ws
, ws_id
);
160 query
->begin_time
= os_time_get_nano();
162 case R600_QUERY_GPU_LOAD
:
163 case R600_QUERY_GPU_SHADERS_BUSY
:
164 case R600_QUERY_GPU_TA_BUSY
:
165 case R600_QUERY_GPU_GDS_BUSY
:
166 case R600_QUERY_GPU_VGT_BUSY
:
167 case R600_QUERY_GPU_IA_BUSY
:
168 case R600_QUERY_GPU_SX_BUSY
:
169 case R600_QUERY_GPU_WD_BUSY
:
170 case R600_QUERY_GPU_BCI_BUSY
:
171 case R600_QUERY_GPU_SC_BUSY
:
172 case R600_QUERY_GPU_PA_BUSY
:
173 case R600_QUERY_GPU_DB_BUSY
:
174 case R600_QUERY_GPU_CP_BUSY
:
175 case R600_QUERY_GPU_CB_BUSY
:
176 case R600_QUERY_GPU_SDMA_BUSY
:
177 case R600_QUERY_GPU_PFP_BUSY
:
178 case R600_QUERY_GPU_MEQ_BUSY
:
179 case R600_QUERY_GPU_ME_BUSY
:
180 case R600_QUERY_GPU_SURF_SYNC_BUSY
:
181 case R600_QUERY_GPU_DMA_BUSY
:
182 case R600_QUERY_GPU_SCRATCH_RAM_BUSY
:
183 case R600_QUERY_GPU_CE_BUSY
:
184 query
->begin_result
= r600_begin_counter(rctx
->screen
,
187 case R600_QUERY_NUM_COMPILATIONS
:
188 query
->begin_result
= p_atomic_read(&rctx
->screen
->num_compilations
);
190 case R600_QUERY_NUM_SHADERS_CREATED
:
191 query
->begin_result
= p_atomic_read(&rctx
->screen
->num_shaders_created
);
193 case R600_QUERY_NUM_SHADER_CACHE_HITS
:
194 query
->begin_result
=
195 p_atomic_read(&rctx
->screen
->num_shader_cache_hits
);
197 case R600_QUERY_GPIN_ASIC_ID
:
198 case R600_QUERY_GPIN_NUM_SIMD
:
199 case R600_QUERY_GPIN_NUM_RB
:
200 case R600_QUERY_GPIN_NUM_SPI
:
201 case R600_QUERY_GPIN_NUM_SE
:
204 unreachable("r600_query_sw_begin: bad query type");
210 static bool r600_query_sw_end(struct r600_common_context
*rctx
,
211 struct r600_query
*rquery
)
213 struct r600_query_sw
*query
= (struct r600_query_sw
*)rquery
;
214 enum radeon_value_id ws_id
;
216 switch(query
->b
.type
) {
217 case PIPE_QUERY_TIMESTAMP_DISJOINT
:
219 case PIPE_QUERY_GPU_FINISHED
:
220 rctx
->b
.flush(&rctx
->b
, &query
->fence
, PIPE_FLUSH_DEFERRED
);
222 case R600_QUERY_DRAW_CALLS
:
223 query
->end_result
= rctx
->num_draw_calls
;
225 case R600_QUERY_SPILL_DRAW_CALLS
:
226 query
->end_result
= rctx
->num_spill_draw_calls
;
228 case R600_QUERY_COMPUTE_CALLS
:
229 query
->end_result
= rctx
->num_compute_calls
;
231 case R600_QUERY_SPILL_COMPUTE_CALLS
:
232 query
->end_result
= rctx
->num_spill_compute_calls
;
234 case R600_QUERY_DMA_CALLS
:
235 query
->end_result
= rctx
->num_dma_calls
;
237 case R600_QUERY_CP_DMA_CALLS
:
238 query
->end_result
= rctx
->num_cp_dma_calls
;
240 case R600_QUERY_NUM_VS_FLUSHES
:
241 query
->end_result
= rctx
->num_vs_flushes
;
243 case R600_QUERY_NUM_PS_FLUSHES
:
244 query
->end_result
= rctx
->num_ps_flushes
;
246 case R600_QUERY_NUM_CS_FLUSHES
:
247 query
->end_result
= rctx
->num_cs_flushes
;
249 case R600_QUERY_NUM_FB_CACHE_FLUSHES
:
250 query
->end_result
= rctx
->num_fb_cache_flushes
;
252 case R600_QUERY_NUM_L2_INVALIDATES
:
253 query
->end_result
= rctx
->num_L2_invalidates
;
255 case R600_QUERY_NUM_L2_WRITEBACKS
:
256 query
->end_result
= rctx
->num_L2_writebacks
;
258 case R600_QUERY_REQUESTED_VRAM
:
259 case R600_QUERY_REQUESTED_GTT
:
260 case R600_QUERY_MAPPED_VRAM
:
261 case R600_QUERY_MAPPED_GTT
:
262 case R600_QUERY_VRAM_USAGE
:
263 case R600_QUERY_VRAM_VIS_USAGE
:
264 case R600_QUERY_GTT_USAGE
:
265 case R600_QUERY_GPU_TEMPERATURE
:
266 case R600_QUERY_CURRENT_GPU_SCLK
:
267 case R600_QUERY_CURRENT_GPU_MCLK
:
268 case R600_QUERY_BUFFER_WAIT_TIME
:
269 case R600_QUERY_NUM_MAPPED_BUFFERS
:
270 case R600_QUERY_NUM_GFX_IBS
:
271 case R600_QUERY_NUM_SDMA_IBS
:
272 case R600_QUERY_NUM_BYTES_MOVED
:
273 case R600_QUERY_NUM_EVICTIONS
: {
274 enum radeon_value_id ws_id
= winsys_id_from_type(query
->b
.type
);
275 query
->end_result
= rctx
->ws
->query_value(rctx
->ws
, ws_id
);
278 case R600_QUERY_CS_THREAD_BUSY
:
279 ws_id
= winsys_id_from_type(query
->b
.type
);
280 query
->end_result
= rctx
->ws
->query_value(rctx
->ws
, ws_id
);
281 query
->end_time
= os_time_get_nano();
283 case R600_QUERY_GPU_LOAD
:
284 case R600_QUERY_GPU_SHADERS_BUSY
:
285 case R600_QUERY_GPU_TA_BUSY
:
286 case R600_QUERY_GPU_GDS_BUSY
:
287 case R600_QUERY_GPU_VGT_BUSY
:
288 case R600_QUERY_GPU_IA_BUSY
:
289 case R600_QUERY_GPU_SX_BUSY
:
290 case R600_QUERY_GPU_WD_BUSY
:
291 case R600_QUERY_GPU_BCI_BUSY
:
292 case R600_QUERY_GPU_SC_BUSY
:
293 case R600_QUERY_GPU_PA_BUSY
:
294 case R600_QUERY_GPU_DB_BUSY
:
295 case R600_QUERY_GPU_CP_BUSY
:
296 case R600_QUERY_GPU_CB_BUSY
:
297 case R600_QUERY_GPU_SDMA_BUSY
:
298 case R600_QUERY_GPU_PFP_BUSY
:
299 case R600_QUERY_GPU_MEQ_BUSY
:
300 case R600_QUERY_GPU_ME_BUSY
:
301 case R600_QUERY_GPU_SURF_SYNC_BUSY
:
302 case R600_QUERY_GPU_DMA_BUSY
:
303 case R600_QUERY_GPU_SCRATCH_RAM_BUSY
:
304 case R600_QUERY_GPU_CE_BUSY
:
305 query
->end_result
= r600_end_counter(rctx
->screen
,
307 query
->begin_result
);
308 query
->begin_result
= 0;
310 case R600_QUERY_NUM_COMPILATIONS
:
311 query
->end_result
= p_atomic_read(&rctx
->screen
->num_compilations
);
313 case R600_QUERY_NUM_SHADERS_CREATED
:
314 query
->end_result
= p_atomic_read(&rctx
->screen
->num_shaders_created
);
316 case R600_QUERY_BACK_BUFFER_PS_DRAW_RATIO
:
317 query
->end_result
= rctx
->last_tex_ps_draw_ratio
;
319 case R600_QUERY_NUM_SHADER_CACHE_HITS
:
321 p_atomic_read(&rctx
->screen
->num_shader_cache_hits
);
323 case R600_QUERY_GPIN_ASIC_ID
:
324 case R600_QUERY_GPIN_NUM_SIMD
:
325 case R600_QUERY_GPIN_NUM_RB
:
326 case R600_QUERY_GPIN_NUM_SPI
:
327 case R600_QUERY_GPIN_NUM_SE
:
330 unreachable("r600_query_sw_end: bad query type");
336 static bool r600_query_sw_get_result(struct r600_common_context
*rctx
,
337 struct r600_query
*rquery
,
339 union pipe_query_result
*result
)
341 struct r600_query_sw
*query
= (struct r600_query_sw
*)rquery
;
343 switch (query
->b
.type
) {
344 case PIPE_QUERY_TIMESTAMP_DISJOINT
:
345 /* Convert from cycles per millisecond to cycles per second (Hz). */
346 result
->timestamp_disjoint
.frequency
=
347 (uint64_t)rctx
->screen
->info
.clock_crystal_freq
* 1000;
348 result
->timestamp_disjoint
.disjoint
= false;
350 case PIPE_QUERY_GPU_FINISHED
: {
351 struct pipe_screen
*screen
= rctx
->b
.screen
;
352 result
->b
= screen
->fence_finish(screen
, &rctx
->b
, query
->fence
,
353 wait
? PIPE_TIMEOUT_INFINITE
: 0);
357 case R600_QUERY_CS_THREAD_BUSY
:
358 result
->u64
= (query
->end_result
- query
->begin_result
) * 100 /
359 (query
->end_time
- query
->begin_time
);
361 case R600_QUERY_GPIN_ASIC_ID
:
364 case R600_QUERY_GPIN_NUM_SIMD
:
365 result
->u32
= rctx
->screen
->info
.num_good_compute_units
;
367 case R600_QUERY_GPIN_NUM_RB
:
368 result
->u32
= rctx
->screen
->info
.num_render_backends
;
370 case R600_QUERY_GPIN_NUM_SPI
:
371 result
->u32
= 1; /* all supported chips have one SPI per SE */
373 case R600_QUERY_GPIN_NUM_SE
:
374 result
->u32
= rctx
->screen
->info
.max_se
;
378 result
->u64
= query
->end_result
- query
->begin_result
;
380 switch (query
->b
.type
) {
381 case R600_QUERY_BUFFER_WAIT_TIME
:
382 case R600_QUERY_GPU_TEMPERATURE
:
385 case R600_QUERY_CURRENT_GPU_SCLK
:
386 case R600_QUERY_CURRENT_GPU_MCLK
:
387 result
->u64
*= 1000000;
395 static struct r600_query_ops sw_query_ops
= {
396 .destroy
= r600_query_sw_destroy
,
397 .begin
= r600_query_sw_begin
,
398 .end
= r600_query_sw_end
,
399 .get_result
= r600_query_sw_get_result
,
400 .get_result_resource
= NULL
403 static struct pipe_query
*r600_query_sw_create(unsigned query_type
)
405 struct r600_query_sw
*query
;
407 query
= CALLOC_STRUCT(r600_query_sw
);
411 query
->b
.type
= query_type
;
412 query
->b
.ops
= &sw_query_ops
;
414 return (struct pipe_query
*)query
;
417 void r600_query_hw_destroy(struct r600_common_context
*rctx
,
418 struct r600_query
*rquery
)
420 struct r600_query_hw
*query
= (struct r600_query_hw
*)rquery
;
421 struct r600_query_buffer
*prev
= query
->buffer
.previous
;
423 /* Release all query buffers. */
425 struct r600_query_buffer
*qbuf
= prev
;
426 prev
= prev
->previous
;
427 r600_resource_reference(&qbuf
->buf
, NULL
);
431 r600_resource_reference(&query
->buffer
.buf
, NULL
);
435 static struct r600_resource
*r600_new_query_buffer(struct r600_common_screen
*rscreen
,
436 struct r600_query_hw
*query
)
438 unsigned buf_size
= MAX2(query
->result_size
,
439 rscreen
->info
.min_alloc_size
);
441 /* Queries are normally read by the CPU after
442 * being written by the gpu, hence staging is probably a good
445 struct r600_resource
*buf
= (struct r600_resource
*)
446 pipe_buffer_create(&rscreen
->b
, 0,
447 PIPE_USAGE_STAGING
, buf_size
);
451 if (!query
->ops
->prepare_buffer(rscreen
, query
, buf
)) {
452 r600_resource_reference(&buf
, NULL
);
459 static bool r600_query_hw_prepare_buffer(struct r600_common_screen
*rscreen
,
460 struct r600_query_hw
*query
,
461 struct r600_resource
*buffer
)
463 /* Callers ensure that the buffer is currently unused by the GPU. */
464 uint32_t *results
= rscreen
->ws
->buffer_map(buffer
->buf
, NULL
,
465 PIPE_TRANSFER_WRITE
|
466 PIPE_TRANSFER_UNSYNCHRONIZED
);
470 memset(results
, 0, buffer
->b
.b
.width0
);
472 if (query
->b
.type
== PIPE_QUERY_OCCLUSION_COUNTER
||
473 query
->b
.type
== PIPE_QUERY_OCCLUSION_PREDICATE
) {
474 unsigned max_rbs
= rscreen
->info
.num_render_backends
;
475 unsigned enabled_rb_mask
= rscreen
->info
.enabled_rb_mask
;
476 unsigned num_results
;
479 /* Set top bits for unused backends. */
480 num_results
= buffer
->b
.b
.width0
/ query
->result_size
;
481 for (j
= 0; j
< num_results
; j
++) {
482 for (i
= 0; i
< max_rbs
; i
++) {
483 if (!(enabled_rb_mask
& (1<<i
))) {
484 results
[(i
* 4)+1] = 0x80000000;
485 results
[(i
* 4)+3] = 0x80000000;
488 results
+= 4 * max_rbs
;
495 static void r600_query_hw_get_result_resource(struct r600_common_context
*rctx
,
496 struct r600_query
*rquery
,
498 enum pipe_query_value_type result_type
,
500 struct pipe_resource
*resource
,
503 static struct r600_query_ops query_hw_ops
= {
504 .destroy
= r600_query_hw_destroy
,
505 .begin
= r600_query_hw_begin
,
506 .end
= r600_query_hw_end
,
507 .get_result
= r600_query_hw_get_result
,
508 .get_result_resource
= r600_query_hw_get_result_resource
,
511 static void r600_query_hw_do_emit_start(struct r600_common_context
*ctx
,
512 struct r600_query_hw
*query
,
513 struct r600_resource
*buffer
,
515 static void r600_query_hw_do_emit_stop(struct r600_common_context
*ctx
,
516 struct r600_query_hw
*query
,
517 struct r600_resource
*buffer
,
519 static void r600_query_hw_add_result(struct r600_common_context
*ctx
,
520 struct r600_query_hw
*, void *buffer
,
521 union pipe_query_result
*result
);
522 static void r600_query_hw_clear_result(struct r600_query_hw
*,
523 union pipe_query_result
*);
525 static struct r600_query_hw_ops query_hw_default_hw_ops
= {
526 .prepare_buffer
= r600_query_hw_prepare_buffer
,
527 .emit_start
= r600_query_hw_do_emit_start
,
528 .emit_stop
= r600_query_hw_do_emit_stop
,
529 .clear_result
= r600_query_hw_clear_result
,
530 .add_result
= r600_query_hw_add_result
,
533 bool r600_query_hw_init(struct r600_common_screen
*rscreen
,
534 struct r600_query_hw
*query
)
536 query
->buffer
.buf
= r600_new_query_buffer(rscreen
, query
);
537 if (!query
->buffer
.buf
)
543 static struct pipe_query
*r600_query_hw_create(struct r600_common_screen
*rscreen
,
547 struct r600_query_hw
*query
= CALLOC_STRUCT(r600_query_hw
);
551 query
->b
.type
= query_type
;
552 query
->b
.ops
= &query_hw_ops
;
553 query
->ops
= &query_hw_default_hw_ops
;
555 switch (query_type
) {
556 case PIPE_QUERY_OCCLUSION_COUNTER
:
557 case PIPE_QUERY_OCCLUSION_PREDICATE
:
558 query
->result_size
= 16 * rscreen
->info
.num_render_backends
;
559 query
->result_size
+= 16; /* for the fence + alignment */
560 query
->num_cs_dw_begin
= 6;
561 query
->num_cs_dw_end
= 6 + r600_gfx_write_fence_dwords(rscreen
);
563 case PIPE_QUERY_TIME_ELAPSED
:
564 query
->result_size
= 24;
565 query
->num_cs_dw_begin
= 8;
566 query
->num_cs_dw_end
= 8 + r600_gfx_write_fence_dwords(rscreen
);
568 case PIPE_QUERY_TIMESTAMP
:
569 query
->result_size
= 16;
570 query
->num_cs_dw_end
= 8 + r600_gfx_write_fence_dwords(rscreen
);
571 query
->flags
= R600_QUERY_HW_FLAG_NO_START
;
573 case PIPE_QUERY_PRIMITIVES_EMITTED
:
574 case PIPE_QUERY_PRIMITIVES_GENERATED
:
575 case PIPE_QUERY_SO_STATISTICS
:
576 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
577 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
578 query
->result_size
= 32;
579 query
->num_cs_dw_begin
= 6;
580 query
->num_cs_dw_end
= 6;
581 query
->stream
= index
;
583 case PIPE_QUERY_PIPELINE_STATISTICS
:
584 /* 11 values on EG, 8 on R600. */
585 query
->result_size
= (rscreen
->chip_class
>= EVERGREEN
? 11 : 8) * 16;
586 query
->result_size
+= 8; /* for the fence + alignment */
587 query
->num_cs_dw_begin
= 6;
588 query
->num_cs_dw_end
= 6 + r600_gfx_write_fence_dwords(rscreen
);
596 if (!r600_query_hw_init(rscreen
, query
)) {
601 return (struct pipe_query
*)query
;
604 static void r600_update_occlusion_query_state(struct r600_common_context
*rctx
,
605 unsigned type
, int diff
)
607 if (type
== PIPE_QUERY_OCCLUSION_COUNTER
||
608 type
== PIPE_QUERY_OCCLUSION_PREDICATE
) {
609 bool old_enable
= rctx
->num_occlusion_queries
!= 0;
610 bool old_perfect_enable
=
611 rctx
->num_perfect_occlusion_queries
!= 0;
612 bool enable
, perfect_enable
;
614 rctx
->num_occlusion_queries
+= diff
;
615 assert(rctx
->num_occlusion_queries
>= 0);
617 if (type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
618 rctx
->num_perfect_occlusion_queries
+= diff
;
619 assert(rctx
->num_perfect_occlusion_queries
>= 0);
622 enable
= rctx
->num_occlusion_queries
!= 0;
623 perfect_enable
= rctx
->num_perfect_occlusion_queries
!= 0;
625 if (enable
!= old_enable
|| perfect_enable
!= old_perfect_enable
) {
626 rctx
->set_occlusion_query_state(&rctx
->b
, enable
);
631 static unsigned event_type_for_stream(struct r600_query_hw
*query
)
633 switch (query
->stream
) {
635 case 0: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS
;
636 case 1: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS1
;
637 case 2: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS2
;
638 case 3: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS3
;
642 static void r600_query_hw_do_emit_start(struct r600_common_context
*ctx
,
643 struct r600_query_hw
*query
,
644 struct r600_resource
*buffer
,
647 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
649 switch (query
->b
.type
) {
650 case PIPE_QUERY_OCCLUSION_COUNTER
:
651 case PIPE_QUERY_OCCLUSION_PREDICATE
:
652 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
653 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE
) | EVENT_INDEX(1));
655 radeon_emit(cs
, (va
>> 32) & 0xFFFF);
657 case PIPE_QUERY_PRIMITIVES_EMITTED
:
658 case PIPE_QUERY_PRIMITIVES_GENERATED
:
659 case PIPE_QUERY_SO_STATISTICS
:
660 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
661 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
662 radeon_emit(cs
, EVENT_TYPE(event_type_for_stream(query
)) | EVENT_INDEX(3));
664 radeon_emit(cs
, (va
>> 32) & 0xFFFF);
666 case PIPE_QUERY_TIME_ELAPSED
:
667 r600_gfx_write_event_eop(ctx
, EVENT_TYPE_BOTTOM_OF_PIPE_TS
,
668 0, 3, NULL
, va
, 0, 0);
670 case PIPE_QUERY_PIPELINE_STATISTICS
:
671 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
672 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT
) | EVENT_INDEX(2));
674 radeon_emit(cs
, (va
>> 32) & 0xFFFF);
679 r600_emit_reloc(ctx
, &ctx
->gfx
, query
->buffer
.buf
, RADEON_USAGE_WRITE
,
683 static void r600_query_hw_emit_start(struct r600_common_context
*ctx
,
684 struct r600_query_hw
*query
)
688 if (!query
->buffer
.buf
)
689 return; // previous buffer allocation failure
691 r600_update_occlusion_query_state(ctx
, query
->b
.type
, 1);
692 r600_update_prims_generated_query_state(ctx
, query
->b
.type
, 1);
694 ctx
->need_gfx_cs_space(&ctx
->b
, query
->num_cs_dw_begin
+ query
->num_cs_dw_end
,
697 /* Get a new query buffer if needed. */
698 if (query
->buffer
.results_end
+ query
->result_size
> query
->buffer
.buf
->b
.b
.width0
) {
699 struct r600_query_buffer
*qbuf
= MALLOC_STRUCT(r600_query_buffer
);
700 *qbuf
= query
->buffer
;
701 query
->buffer
.results_end
= 0;
702 query
->buffer
.previous
= qbuf
;
703 query
->buffer
.buf
= r600_new_query_buffer(ctx
->screen
, query
);
704 if (!query
->buffer
.buf
)
708 /* emit begin query */
709 va
= query
->buffer
.buf
->gpu_address
+ query
->buffer
.results_end
;
711 query
->ops
->emit_start(ctx
, query
, query
->buffer
.buf
, va
);
713 ctx
->num_cs_dw_queries_suspend
+= query
->num_cs_dw_end
;
716 static void r600_query_hw_do_emit_stop(struct r600_common_context
*ctx
,
717 struct r600_query_hw
*query
,
718 struct r600_resource
*buffer
,
721 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
722 uint64_t fence_va
= 0;
724 switch (query
->b
.type
) {
725 case PIPE_QUERY_OCCLUSION_COUNTER
:
726 case PIPE_QUERY_OCCLUSION_PREDICATE
:
728 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
729 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE
) | EVENT_INDEX(1));
731 radeon_emit(cs
, (va
>> 32) & 0xFFFF);
733 fence_va
= va
+ ctx
->screen
->info
.num_render_backends
* 16 - 8;
735 case PIPE_QUERY_PRIMITIVES_EMITTED
:
736 case PIPE_QUERY_PRIMITIVES_GENERATED
:
737 case PIPE_QUERY_SO_STATISTICS
:
738 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
739 va
+= query
->result_size
/2;
740 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
741 radeon_emit(cs
, EVENT_TYPE(event_type_for_stream(query
)) | EVENT_INDEX(3));
743 radeon_emit(cs
, (va
>> 32) & 0xFFFF);
745 case PIPE_QUERY_TIME_ELAPSED
:
748 case PIPE_QUERY_TIMESTAMP
:
749 r600_gfx_write_event_eop(ctx
, EVENT_TYPE_BOTTOM_OF_PIPE_TS
,
750 0, 3, NULL
, va
, 0, 0);
753 case PIPE_QUERY_PIPELINE_STATISTICS
: {
754 unsigned sample_size
= (query
->result_size
- 8) / 2;
757 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
758 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT
) | EVENT_INDEX(2));
760 radeon_emit(cs
, (va
>> 32) & 0xFFFF);
762 fence_va
= va
+ sample_size
;
768 r600_emit_reloc(ctx
, &ctx
->gfx
, query
->buffer
.buf
, RADEON_USAGE_WRITE
,
772 r600_gfx_write_event_eop(ctx
, EVENT_TYPE_BOTTOM_OF_PIPE_TS
, 0, 1,
773 query
->buffer
.buf
, fence_va
, 0, 0x80000000);
776 static void r600_query_hw_emit_stop(struct r600_common_context
*ctx
,
777 struct r600_query_hw
*query
)
781 if (!query
->buffer
.buf
)
782 return; // previous buffer allocation failure
784 /* The queries which need begin already called this in begin_query. */
785 if (query
->flags
& R600_QUERY_HW_FLAG_NO_START
) {
786 ctx
->need_gfx_cs_space(&ctx
->b
, query
->num_cs_dw_end
, false);
790 va
= query
->buffer
.buf
->gpu_address
+ query
->buffer
.results_end
;
792 query
->ops
->emit_stop(ctx
, query
, query
->buffer
.buf
, va
);
794 query
->buffer
.results_end
+= query
->result_size
;
796 if (!(query
->flags
& R600_QUERY_HW_FLAG_NO_START
))
797 ctx
->num_cs_dw_queries_suspend
-= query
->num_cs_dw_end
;
799 r600_update_occlusion_query_state(ctx
, query
->b
.type
, -1);
800 r600_update_prims_generated_query_state(ctx
, query
->b
.type
, -1);
803 static void r600_emit_query_predication(struct r600_common_context
*ctx
,
804 struct r600_atom
*atom
)
806 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
807 struct r600_query_hw
*query
= (struct r600_query_hw
*)ctx
->render_cond
;
808 struct r600_query_buffer
*qbuf
;
815 flag_wait
= ctx
->render_cond_mode
== PIPE_RENDER_COND_WAIT
||
816 ctx
->render_cond_mode
== PIPE_RENDER_COND_BY_REGION_WAIT
;
818 switch (query
->b
.type
) {
819 case PIPE_QUERY_OCCLUSION_COUNTER
:
820 case PIPE_QUERY_OCCLUSION_PREDICATE
:
821 op
= PRED_OP(PREDICATION_OP_ZPASS
);
823 case PIPE_QUERY_PRIMITIVES_EMITTED
:
824 case PIPE_QUERY_PRIMITIVES_GENERATED
:
825 case PIPE_QUERY_SO_STATISTICS
:
826 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
827 op
= PRED_OP(PREDICATION_OP_PRIMCOUNT
);
834 /* if true then invert, see GL_ARB_conditional_render_inverted */
835 if (ctx
->render_cond_invert
)
836 op
|= PREDICATION_DRAW_NOT_VISIBLE
; /* Draw if not visable/overflow */
838 op
|= PREDICATION_DRAW_VISIBLE
; /* Draw if visable/overflow */
840 op
|= flag_wait
? PREDICATION_HINT_WAIT
: PREDICATION_HINT_NOWAIT_DRAW
;
842 /* emit predicate packets for all data blocks */
843 for (qbuf
= &query
->buffer
; qbuf
; qbuf
= qbuf
->previous
) {
844 unsigned results_base
= 0;
845 uint64_t va
= qbuf
->buf
->gpu_address
;
847 while (results_base
< qbuf
->results_end
) {
848 radeon_emit(cs
, PKT3(PKT3_SET_PREDICATION
, 1, 0));
849 radeon_emit(cs
, va
+ results_base
);
850 radeon_emit(cs
, op
| (((va
+ results_base
) >> 32) & 0xFF));
851 r600_emit_reloc(ctx
, &ctx
->gfx
, qbuf
->buf
, RADEON_USAGE_READ
,
853 results_base
+= query
->result_size
;
855 /* set CONTINUE bit for all packets except the first */
856 op
|= PREDICATION_CONTINUE
;
861 static struct pipe_query
*r600_create_query(struct pipe_context
*ctx
, unsigned query_type
, unsigned index
)
863 struct r600_common_screen
*rscreen
=
864 (struct r600_common_screen
*)ctx
->screen
;
866 if (query_type
== PIPE_QUERY_TIMESTAMP_DISJOINT
||
867 query_type
== PIPE_QUERY_GPU_FINISHED
||
868 query_type
>= PIPE_QUERY_DRIVER_SPECIFIC
)
869 return r600_query_sw_create(query_type
);
871 return r600_query_hw_create(rscreen
, query_type
, index
);
874 static void r600_destroy_query(struct pipe_context
*ctx
, struct pipe_query
*query
)
876 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
877 struct r600_query
*rquery
= (struct r600_query
*)query
;
879 rquery
->ops
->destroy(rctx
, rquery
);
882 static boolean
r600_begin_query(struct pipe_context
*ctx
,
883 struct pipe_query
*query
)
885 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
886 struct r600_query
*rquery
= (struct r600_query
*)query
;
888 return rquery
->ops
->begin(rctx
, rquery
);
891 void r600_query_hw_reset_buffers(struct r600_common_context
*rctx
,
892 struct r600_query_hw
*query
)
894 struct r600_query_buffer
*prev
= query
->buffer
.previous
;
896 /* Discard the old query buffers. */
898 struct r600_query_buffer
*qbuf
= prev
;
899 prev
= prev
->previous
;
900 r600_resource_reference(&qbuf
->buf
, NULL
);
904 query
->buffer
.results_end
= 0;
905 query
->buffer
.previous
= NULL
;
907 /* Obtain a new buffer if the current one can't be mapped without a stall. */
908 if (r600_rings_is_buffer_referenced(rctx
, query
->buffer
.buf
->buf
, RADEON_USAGE_READWRITE
) ||
909 !rctx
->ws
->buffer_wait(query
->buffer
.buf
->buf
, 0, RADEON_USAGE_READWRITE
)) {
910 r600_resource_reference(&query
->buffer
.buf
, NULL
);
911 query
->buffer
.buf
= r600_new_query_buffer(rctx
->screen
, query
);
913 if (!query
->ops
->prepare_buffer(rctx
->screen
, query
, query
->buffer
.buf
))
914 r600_resource_reference(&query
->buffer
.buf
, NULL
);
918 bool r600_query_hw_begin(struct r600_common_context
*rctx
,
919 struct r600_query
*rquery
)
921 struct r600_query_hw
*query
= (struct r600_query_hw
*)rquery
;
923 if (query
->flags
& R600_QUERY_HW_FLAG_NO_START
) {
928 if (!(query
->flags
& R600_QUERY_HW_FLAG_BEGIN_RESUMES
))
929 r600_query_hw_reset_buffers(rctx
, query
);
931 r600_query_hw_emit_start(rctx
, query
);
932 if (!query
->buffer
.buf
)
935 LIST_ADDTAIL(&query
->list
, &rctx
->active_queries
);
939 static bool r600_end_query(struct pipe_context
*ctx
, struct pipe_query
*query
)
941 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
942 struct r600_query
*rquery
= (struct r600_query
*)query
;
944 return rquery
->ops
->end(rctx
, rquery
);
947 bool r600_query_hw_end(struct r600_common_context
*rctx
,
948 struct r600_query
*rquery
)
950 struct r600_query_hw
*query
= (struct r600_query_hw
*)rquery
;
952 if (query
->flags
& R600_QUERY_HW_FLAG_NO_START
)
953 r600_query_hw_reset_buffers(rctx
, query
);
955 r600_query_hw_emit_stop(rctx
, query
);
957 if (!(query
->flags
& R600_QUERY_HW_FLAG_NO_START
))
958 LIST_DELINIT(&query
->list
);
960 if (!query
->buffer
.buf
)
966 static void r600_get_hw_query_params(struct r600_common_context
*rctx
,
967 struct r600_query_hw
*rquery
, int index
,
968 struct r600_hw_query_params
*params
)
970 unsigned max_rbs
= rctx
->screen
->info
.num_render_backends
;
972 params
->pair_stride
= 0;
973 params
->pair_count
= 1;
975 switch (rquery
->b
.type
) {
976 case PIPE_QUERY_OCCLUSION_COUNTER
:
977 case PIPE_QUERY_OCCLUSION_PREDICATE
:
978 params
->start_offset
= 0;
979 params
->end_offset
= 8;
980 params
->fence_offset
= max_rbs
* 16;
981 params
->pair_stride
= 16;
982 params
->pair_count
= max_rbs
;
984 case PIPE_QUERY_TIME_ELAPSED
:
985 params
->start_offset
= 0;
986 params
->end_offset
= 8;
987 params
->fence_offset
= 16;
989 case PIPE_QUERY_TIMESTAMP
:
990 params
->start_offset
= 0;
991 params
->end_offset
= 0;
992 params
->fence_offset
= 8;
994 case PIPE_QUERY_PRIMITIVES_EMITTED
:
995 params
->start_offset
= 8;
996 params
->end_offset
= 24;
997 params
->fence_offset
= params
->end_offset
+ 4;
999 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1000 params
->start_offset
= 0;
1001 params
->end_offset
= 16;
1002 params
->fence_offset
= params
->end_offset
+ 4;
1004 case PIPE_QUERY_SO_STATISTICS
:
1005 params
->start_offset
= 8 - index
* 8;
1006 params
->end_offset
= 24 - index
* 8;
1007 params
->fence_offset
= params
->end_offset
+ 4;
1009 case PIPE_QUERY_PIPELINE_STATISTICS
:
1011 /* Offsets apply to EG+ */
1012 static const unsigned offsets
[] = {56, 48, 24, 32, 40, 16, 8, 0, 64, 72, 80};
1013 params
->start_offset
= offsets
[index
];
1014 params
->end_offset
= 88 + offsets
[index
];
1015 params
->fence_offset
= 2 * 88;
1019 unreachable("r600_get_hw_query_params unsupported");
1023 static unsigned r600_query_read_result(void *map
, unsigned start_index
, unsigned end_index
,
1024 bool test_status_bit
)
1026 uint32_t *current_result
= (uint32_t*)map
;
1027 uint64_t start
, end
;
1029 start
= (uint64_t)current_result
[start_index
] |
1030 (uint64_t)current_result
[start_index
+1] << 32;
1031 end
= (uint64_t)current_result
[end_index
] |
1032 (uint64_t)current_result
[end_index
+1] << 32;
1034 if (!test_status_bit
||
1035 ((start
& 0x8000000000000000UL
) && (end
& 0x8000000000000000UL
))) {
1041 static void r600_query_hw_add_result(struct r600_common_context
*ctx
,
1042 struct r600_query_hw
*query
,
1044 union pipe_query_result
*result
)
1046 unsigned max_rbs
= ctx
->screen
->info
.num_render_backends
;
1048 switch (query
->b
.type
) {
1049 case PIPE_QUERY_OCCLUSION_COUNTER
: {
1050 for (unsigned i
= 0; i
< max_rbs
; ++i
) {
1051 unsigned results_base
= i
* 16;
1053 r600_query_read_result(buffer
+ results_base
, 0, 2, true);
1057 case PIPE_QUERY_OCCLUSION_PREDICATE
: {
1058 for (unsigned i
= 0; i
< max_rbs
; ++i
) {
1059 unsigned results_base
= i
* 16;
1060 result
->b
= result
->b
||
1061 r600_query_read_result(buffer
+ results_base
, 0, 2, true) != 0;
1065 case PIPE_QUERY_TIME_ELAPSED
:
1066 result
->u64
+= r600_query_read_result(buffer
, 0, 2, false);
1068 case PIPE_QUERY_TIMESTAMP
:
1069 result
->u64
= *(uint64_t*)buffer
;
1071 case PIPE_QUERY_PRIMITIVES_EMITTED
:
1072 /* SAMPLE_STREAMOUTSTATS stores this structure:
1074 * u64 NumPrimitivesWritten;
1075 * u64 PrimitiveStorageNeeded;
1077 * We only need NumPrimitivesWritten here. */
1078 result
->u64
+= r600_query_read_result(buffer
, 2, 6, true);
1080 case PIPE_QUERY_PRIMITIVES_GENERATED
:
1081 /* Here we read PrimitiveStorageNeeded. */
1082 result
->u64
+= r600_query_read_result(buffer
, 0, 4, true);
1084 case PIPE_QUERY_SO_STATISTICS
:
1085 result
->so_statistics
.num_primitives_written
+=
1086 r600_query_read_result(buffer
, 2, 6, true);
1087 result
->so_statistics
.primitives_storage_needed
+=
1088 r600_query_read_result(buffer
, 0, 4, true);
1090 case PIPE_QUERY_SO_OVERFLOW_PREDICATE
:
1091 result
->b
= result
->b
||
1092 r600_query_read_result(buffer
, 2, 6, true) !=
1093 r600_query_read_result(buffer
, 0, 4, true);
1095 case PIPE_QUERY_PIPELINE_STATISTICS
:
1096 if (ctx
->chip_class
>= EVERGREEN
) {
1097 result
->pipeline_statistics
.ps_invocations
+=
1098 r600_query_read_result(buffer
, 0, 22, false);
1099 result
->pipeline_statistics
.c_primitives
+=
1100 r600_query_read_result(buffer
, 2, 24, false);
1101 result
->pipeline_statistics
.c_invocations
+=
1102 r600_query_read_result(buffer
, 4, 26, false);
1103 result
->pipeline_statistics
.vs_invocations
+=
1104 r600_query_read_result(buffer
, 6, 28, false);
1105 result
->pipeline_statistics
.gs_invocations
+=
1106 r600_query_read_result(buffer
, 8, 30, false);
1107 result
->pipeline_statistics
.gs_primitives
+=
1108 r600_query_read_result(buffer
, 10, 32, false);
1109 result
->pipeline_statistics
.ia_primitives
+=
1110 r600_query_read_result(buffer
, 12, 34, false);
1111 result
->pipeline_statistics
.ia_vertices
+=
1112 r600_query_read_result(buffer
, 14, 36, false);
1113 result
->pipeline_statistics
.hs_invocations
+=
1114 r600_query_read_result(buffer
, 16, 38, false);
1115 result
->pipeline_statistics
.ds_invocations
+=
1116 r600_query_read_result(buffer
, 18, 40, false);
1117 result
->pipeline_statistics
.cs_invocations
+=
1118 r600_query_read_result(buffer
, 20, 42, false);
1120 result
->pipeline_statistics
.ps_invocations
+=
1121 r600_query_read_result(buffer
, 0, 16, false);
1122 result
->pipeline_statistics
.c_primitives
+=
1123 r600_query_read_result(buffer
, 2, 18, false);
1124 result
->pipeline_statistics
.c_invocations
+=
1125 r600_query_read_result(buffer
, 4, 20, false);
1126 result
->pipeline_statistics
.vs_invocations
+=
1127 r600_query_read_result(buffer
, 6, 22, false);
1128 result
->pipeline_statistics
.gs_invocations
+=
1129 r600_query_read_result(buffer
, 8, 24, false);
1130 result
->pipeline_statistics
.gs_primitives
+=
1131 r600_query_read_result(buffer
, 10, 26, false);
1132 result
->pipeline_statistics
.ia_primitives
+=
1133 r600_query_read_result(buffer
, 12, 28, false);
1134 result
->pipeline_statistics
.ia_vertices
+=
1135 r600_query_read_result(buffer
, 14, 30, false);
1137 #if 0 /* for testing */
1138 printf("Pipeline stats: IA verts=%llu, IA prims=%llu, VS=%llu, HS=%llu, "
1139 "DS=%llu, GS=%llu, GS prims=%llu, Clipper=%llu, "
1140 "Clipper prims=%llu, PS=%llu, CS=%llu\n",
1141 result
->pipeline_statistics
.ia_vertices
,
1142 result
->pipeline_statistics
.ia_primitives
,
1143 result
->pipeline_statistics
.vs_invocations
,
1144 result
->pipeline_statistics
.hs_invocations
,
1145 result
->pipeline_statistics
.ds_invocations
,
1146 result
->pipeline_statistics
.gs_invocations
,
1147 result
->pipeline_statistics
.gs_primitives
,
1148 result
->pipeline_statistics
.c_invocations
,
1149 result
->pipeline_statistics
.c_primitives
,
1150 result
->pipeline_statistics
.ps_invocations
,
1151 result
->pipeline_statistics
.cs_invocations
);
1159 static boolean
r600_get_query_result(struct pipe_context
*ctx
,
1160 struct pipe_query
*query
, boolean wait
,
1161 union pipe_query_result
*result
)
1163 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1164 struct r600_query
*rquery
= (struct r600_query
*)query
;
1166 return rquery
->ops
->get_result(rctx
, rquery
, wait
, result
);
1169 static void r600_get_query_result_resource(struct pipe_context
*ctx
,
1170 struct pipe_query
*query
,
1172 enum pipe_query_value_type result_type
,
1174 struct pipe_resource
*resource
,
1177 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1178 struct r600_query
*rquery
= (struct r600_query
*)query
;
1180 rquery
->ops
->get_result_resource(rctx
, rquery
, wait
, result_type
, index
,
1184 static void r600_query_hw_clear_result(struct r600_query_hw
*query
,
1185 union pipe_query_result
*result
)
1187 util_query_clear_result(result
, query
->b
.type
);
1190 bool r600_query_hw_get_result(struct r600_common_context
*rctx
,
1191 struct r600_query
*rquery
,
1192 bool wait
, union pipe_query_result
*result
)
1194 struct r600_query_hw
*query
= (struct r600_query_hw
*)rquery
;
1195 struct r600_query_buffer
*qbuf
;
1197 query
->ops
->clear_result(query
, result
);
1199 for (qbuf
= &query
->buffer
; qbuf
; qbuf
= qbuf
->previous
) {
1200 unsigned results_base
= 0;
1203 map
= r600_buffer_map_sync_with_rings(rctx
, qbuf
->buf
,
1204 PIPE_TRANSFER_READ
|
1205 (wait
? 0 : PIPE_TRANSFER_DONTBLOCK
));
1209 while (results_base
!= qbuf
->results_end
) {
1210 query
->ops
->add_result(rctx
, query
, map
+ results_base
,
1212 results_base
+= query
->result_size
;
1216 /* Convert the time to expected units. */
1217 if (rquery
->type
== PIPE_QUERY_TIME_ELAPSED
||
1218 rquery
->type
== PIPE_QUERY_TIMESTAMP
) {
1219 result
->u64
= (1000000 * result
->u64
) / rctx
->screen
->info
.clock_crystal_freq
;
1224 /* Create the compute shader that is used to collect the results.
1226 * One compute grid with a single thread is launched for every query result
1227 * buffer. The thread (optionally) reads a previous summary buffer, then
1228 * accumulates data from the query result buffer, and writes the result either
1229 * to a summary buffer to be consumed by the next grid invocation or to the
1230 * user-supplied buffer.
1236 * 0.y = result_stride
1237 * 0.z = result_count
1239 * 1: read previously accumulated values
1240 * 2: write accumulated values for chaining
1241 * 4: write result available
1242 * 8: convert result to boolean (0/1)
1243 * 16: only read one dword and use that as result
1244 * 32: apply timestamp conversion
1245 * 64: store full 64 bits result
1246 * 128: store signed 32 bits result
1247 * 1.x = fence_offset
1251 * BUFFER[0] = query result buffer
1252 * BUFFER[1] = previous summary buffer
1253 * BUFFER[2] = next summary buffer or user-supplied buffer
1255 static void r600_create_query_result_shader(struct r600_common_context
*rctx
)
1257 /* TEMP[0].xy = accumulated result so far
1258 * TEMP[0].z = result not available
1260 * TEMP[1].x = current result index
1261 * TEMP[1].y = current pair index
1263 static const char text_tmpl
[] =
1265 "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
1266 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
1267 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
1273 "IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n"
1274 "IMM[1] UINT32 {1, 2, 4, 8}\n"
1275 "IMM[2] UINT32 {16, 32, 64, 128}\n"
1276 "IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */
1278 "AND TEMP[5], CONST[0].wwww, IMM[2].xxxx\n"
1280 /* Check result availability. */
1281 "LOAD TEMP[1].x, BUFFER[0], CONST[1].xxxx\n"
1282 "ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n"
1283 "MOV TEMP[1], TEMP[0].zzzz\n"
1284 "NOT TEMP[0].z, TEMP[0].zzzz\n"
1286 /* Load result if available. */
1288 "LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n"
1291 /* Load previously accumulated result if requested. */
1292 "MOV TEMP[0], IMM[0].xxxx\n"
1293 "AND TEMP[4], CONST[0].wwww, IMM[1].xxxx\n"
1295 "LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n"
1298 "MOV TEMP[1].x, IMM[0].xxxx\n"
1300 /* Break if accumulated result so far is not available. */
1301 "UIF TEMP[0].zzzz\n"
1305 /* Break if result_index >= result_count. */
1306 "USGE TEMP[5], TEMP[1].xxxx, CONST[0].zzzz\n"
1311 /* Load fence and check result availability */
1312 "UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0].yyyy, CONST[1].xxxx\n"
1313 "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
1314 "ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n"
1315 "NOT TEMP[0].z, TEMP[0].zzzz\n"
1316 "UIF TEMP[0].zzzz\n"
1320 "MOV TEMP[1].y, IMM[0].xxxx\n"
1322 /* Load start and end. */
1323 "UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0].yyyy\n"
1324 "UMAD TEMP[5].x, TEMP[1].yyyy, CONST[1].yyyy, TEMP[5].xxxx\n"
1325 "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
1327 "UADD TEMP[5].x, TEMP[5].xxxx, CONST[0].xxxx\n"
1328 "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].xxxx\n"
1330 "U64ADD TEMP[3].xy, TEMP[3], -TEMP[2]\n"
1331 "U64ADD TEMP[0].xy, TEMP[0], TEMP[3]\n"
1333 /* Increment pair index */
1334 "UADD TEMP[1].y, TEMP[1].yyyy, IMM[1].xxxx\n"
1335 "USGE TEMP[5], TEMP[1].yyyy, CONST[1].zzzz\n"
1341 /* Increment result index */
1342 "UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n"
1346 "AND TEMP[4], CONST[0].wwww, IMM[1].yyyy\n"
1348 /* Store accumulated data for chaining. */
1349 "STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n"
1351 "AND TEMP[4], CONST[0].wwww, IMM[1].zzzz\n"
1353 /* Store result availability. */
1354 "NOT TEMP[0].z, TEMP[0]\n"
1355 "AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n"
1356 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n"
1358 "AND TEMP[4], CONST[0].wwww, IMM[2].zzzz\n"
1360 "STORE BUFFER[2].y, IMM[0].xxxx, IMM[0].xxxx\n"
1363 /* Store result if it is available. */
1364 "NOT TEMP[4], TEMP[0].zzzz\n"
1366 /* Apply timestamp conversion */
1367 "AND TEMP[4], CONST[0].wwww, IMM[2].yyyy\n"
1369 "U64MUL TEMP[0].xy, TEMP[0], IMM[3].xyxy\n"
1370 "U64DIV TEMP[0].xy, TEMP[0], IMM[3].zwzw\n"
1373 /* Convert to boolean */
1374 "AND TEMP[4], CONST[0].wwww, IMM[1].wwww\n"
1376 "U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[0].xxxx\n"
1377 "AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n"
1378 "MOV TEMP[0].y, IMM[0].xxxx\n"
1381 "AND TEMP[4], CONST[0].wwww, IMM[2].zzzz\n"
1383 "STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0].xyxy\n"
1386 "UIF TEMP[0].yyyy\n"
1387 "MOV TEMP[0].x, IMM[0].wwww\n"
1390 "AND TEMP[4], CONST[0].wwww, IMM[2].wwww\n"
1392 "UMIN TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz\n"
1395 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n"
1403 char text
[sizeof(text_tmpl
) + 32];
1404 struct tgsi_token tokens
[1024];
1405 struct pipe_compute_state state
= {};
1407 /* Hard code the frequency into the shader so that the backend can
1408 * use the full range of optimizations for divide-by-constant.
1410 snprintf(text
, sizeof(text
), text_tmpl
,
1411 rctx
->screen
->info
.clock_crystal_freq
);
1413 if (!tgsi_text_translate(text
, tokens
, ARRAY_SIZE(tokens
))) {
1418 state
.ir_type
= PIPE_SHADER_IR_TGSI
;
1419 state
.prog
= tokens
;
1421 rctx
->query_result_shader
= rctx
->b
.create_compute_state(&rctx
->b
, &state
);
1424 static void r600_restore_qbo_state(struct r600_common_context
*rctx
,
1425 struct r600_qbo_state
*st
)
1427 rctx
->b
.bind_compute_state(&rctx
->b
, st
->saved_compute
);
1429 rctx
->b
.set_constant_buffer(&rctx
->b
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1430 pipe_resource_reference(&st
->saved_const0
.buffer
, NULL
);
1432 rctx
->b
.set_shader_buffers(&rctx
->b
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1433 for (unsigned i
= 0; i
< 3; ++i
)
1434 pipe_resource_reference(&st
->saved_ssbo
[i
].buffer
, NULL
);
1437 static void r600_query_hw_get_result_resource(struct r600_common_context
*rctx
,
1438 struct r600_query
*rquery
,
1440 enum pipe_query_value_type result_type
,
1442 struct pipe_resource
*resource
,
1445 struct r600_query_hw
*query
= (struct r600_query_hw
*)rquery
;
1446 struct r600_query_buffer
*qbuf
;
1447 struct r600_query_buffer
*qbuf_prev
;
1448 struct pipe_resource
*tmp_buffer
= NULL
;
1449 unsigned tmp_buffer_offset
= 0;
1450 struct r600_qbo_state saved_state
= {};
1451 struct pipe_grid_info grid
= {};
1452 struct pipe_constant_buffer constant_buffer
= {};
1453 struct pipe_shader_buffer ssbo
[3];
1454 struct r600_hw_query_params params
;
1456 uint32_t end_offset
;
1457 uint32_t result_stride
;
1458 uint32_t result_count
;
1460 uint32_t fence_offset
;
1461 uint32_t pair_stride
;
1462 uint32_t pair_count
;
1465 if (!rctx
->query_result_shader
) {
1466 r600_create_query_result_shader(rctx
);
1467 if (!rctx
->query_result_shader
)
1471 if (query
->buffer
.previous
) {
1472 u_suballocator_alloc(rctx
->allocator_zeroed_memory
, 16, 16,
1473 &tmp_buffer_offset
, &tmp_buffer
);
1478 rctx
->save_qbo_state(&rctx
->b
, &saved_state
);
1480 r600_get_hw_query_params(rctx
, query
, index
>= 0 ? index
: 0, ¶ms
);
1481 consts
.end_offset
= params
.end_offset
- params
.start_offset
;
1482 consts
.fence_offset
= params
.fence_offset
- params
.start_offset
;
1483 consts
.result_stride
= query
->result_size
;
1484 consts
.pair_stride
= params
.pair_stride
;
1485 consts
.pair_count
= params
.pair_count
;
1487 constant_buffer
.buffer_size
= sizeof(consts
);
1488 constant_buffer
.user_buffer
= &consts
;
1490 ssbo
[1].buffer
= tmp_buffer
;
1491 ssbo
[1].buffer_offset
= tmp_buffer_offset
;
1492 ssbo
[1].buffer_size
= 16;
1496 rctx
->b
.bind_compute_state(&rctx
->b
, rctx
->query_result_shader
);
1508 if (query
->b
.type
== PIPE_QUERY_OCCLUSION_PREDICATE
||
1509 query
->b
.type
== PIPE_QUERY_SO_OVERFLOW_PREDICATE
)
1511 else if (query
->b
.type
== PIPE_QUERY_TIMESTAMP
||
1512 query
->b
.type
== PIPE_QUERY_TIME_ELAPSED
)
1513 consts
.config
|= 32;
1515 switch (result_type
) {
1516 case PIPE_QUERY_TYPE_U64
:
1517 case PIPE_QUERY_TYPE_I64
:
1518 consts
.config
|= 64;
1520 case PIPE_QUERY_TYPE_I32
:
1521 consts
.config
|= 128;
1523 case PIPE_QUERY_TYPE_U32
:
1527 rctx
->flags
|= rctx
->screen
->barrier_flags
.cp_to_L2
;
1529 for (qbuf
= &query
->buffer
; qbuf
; qbuf
= qbuf_prev
) {
1530 if (query
->b
.type
!= PIPE_QUERY_TIMESTAMP
) {
1531 qbuf_prev
= qbuf
->previous
;
1532 consts
.result_count
= qbuf
->results_end
/ query
->result_size
;
1533 consts
.config
&= ~3;
1534 if (qbuf
!= &query
->buffer
)
1539 /* Only read the last timestamp. */
1541 consts
.result_count
= 0;
1542 consts
.config
|= 16;
1543 params
.start_offset
+= qbuf
->results_end
- query
->result_size
;
1546 rctx
->b
.set_constant_buffer(&rctx
->b
, PIPE_SHADER_COMPUTE
, 0, &constant_buffer
);
1548 ssbo
[0].buffer
= &qbuf
->buf
->b
.b
;
1549 ssbo
[0].buffer_offset
= params
.start_offset
;
1550 ssbo
[0].buffer_size
= qbuf
->results_end
- params
.start_offset
;
1552 if (!qbuf
->previous
) {
1553 ssbo
[2].buffer
= resource
;
1554 ssbo
[2].buffer_offset
= offset
;
1555 ssbo
[2].buffer_size
= 8;
1557 ((struct r600_resource
*)resource
)->TC_L2_dirty
= true;
1560 rctx
->b
.set_shader_buffers(&rctx
->b
, PIPE_SHADER_COMPUTE
, 0, 3, ssbo
);
1562 if (wait
&& qbuf
== &query
->buffer
) {
1565 /* Wait for result availability. Wait only for readiness
1566 * of the last entry, since the fence writes should be
1567 * serialized in the CP.
1569 va
= qbuf
->buf
->gpu_address
+ qbuf
->results_end
- query
->result_size
;
1570 va
+= params
.fence_offset
;
1572 r600_gfx_wait_fence(rctx
, va
, 0x80000000, 0x80000000);
1575 rctx
->b
.launch_grid(&rctx
->b
, &grid
);
1576 rctx
->flags
|= rctx
->screen
->barrier_flags
.compute_to_L2
;
1579 r600_restore_qbo_state(rctx
, &saved_state
);
1580 pipe_resource_reference(&tmp_buffer
, NULL
);
1583 static void r600_render_condition(struct pipe_context
*ctx
,
1584 struct pipe_query
*query
,
1586 enum pipe_render_cond_flag mode
)
1588 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1589 struct r600_query_hw
*rquery
= (struct r600_query_hw
*)query
;
1590 struct r600_query_buffer
*qbuf
;
1591 struct r600_atom
*atom
= &rctx
->render_cond_atom
;
1593 rctx
->render_cond
= query
;
1594 rctx
->render_cond_invert
= condition
;
1595 rctx
->render_cond_mode
= mode
;
1597 /* Compute the size of SET_PREDICATION packets. */
1600 for (qbuf
= &rquery
->buffer
; qbuf
; qbuf
= qbuf
->previous
)
1601 atom
->num_dw
+= (qbuf
->results_end
/ rquery
->result_size
) * 5;
1604 rctx
->set_atom_dirty(rctx
, atom
, query
!= NULL
);
1607 void r600_suspend_queries(struct r600_common_context
*ctx
)
1609 struct r600_query_hw
*query
;
1611 LIST_FOR_EACH_ENTRY(query
, &ctx
->active_queries
, list
) {
1612 r600_query_hw_emit_stop(ctx
, query
);
1614 assert(ctx
->num_cs_dw_queries_suspend
== 0);
1617 static unsigned r600_queries_num_cs_dw_for_resuming(struct r600_common_context
*ctx
,
1618 struct list_head
*query_list
)
1620 struct r600_query_hw
*query
;
1621 unsigned num_dw
= 0;
1623 LIST_FOR_EACH_ENTRY(query
, query_list
, list
) {
1625 num_dw
+= query
->num_cs_dw_begin
+ query
->num_cs_dw_end
;
1627 /* Workaround for the fact that
1628 * num_cs_dw_nontimer_queries_suspend is incremented for every
1629 * resumed query, which raises the bar in need_cs_space for
1630 * queries about to be resumed.
1632 num_dw
+= query
->num_cs_dw_end
;
1634 /* primitives generated query */
1635 num_dw
+= ctx
->streamout
.enable_atom
.num_dw
;
1636 /* guess for ZPASS enable or PERFECT_ZPASS_COUNT enable updates */
1642 void r600_resume_queries(struct r600_common_context
*ctx
)
1644 struct r600_query_hw
*query
;
1645 unsigned num_cs_dw
= r600_queries_num_cs_dw_for_resuming(ctx
, &ctx
->active_queries
);
1647 assert(ctx
->num_cs_dw_queries_suspend
== 0);
1649 /* Check CS space here. Resuming must not be interrupted by flushes. */
1650 ctx
->need_gfx_cs_space(&ctx
->b
, num_cs_dw
, true);
1652 LIST_FOR_EACH_ENTRY(query
, &ctx
->active_queries
, list
) {
1653 r600_query_hw_emit_start(ctx
, query
);
1657 /* Fix radeon_info::enabled_rb_mask for R600, R700, EVERGREEN, NI. */
1658 void r600_query_fix_enabled_rb_mask(struct r600_common_screen
*rscreen
)
1660 struct r600_common_context
*ctx
=
1661 (struct r600_common_context
*)rscreen
->aux_context
;
1662 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
1663 struct r600_resource
*buffer
;
1665 unsigned i
, mask
= 0;
1666 unsigned max_rbs
= ctx
->screen
->info
.num_render_backends
;
1668 assert(rscreen
->chip_class
<= CAYMAN
);
1670 /* if backend_map query is supported by the kernel */
1671 if (rscreen
->info
.r600_gb_backend_map_valid
) {
1672 unsigned num_tile_pipes
= rscreen
->info
.num_tile_pipes
;
1673 unsigned backend_map
= rscreen
->info
.r600_gb_backend_map
;
1674 unsigned item_width
, item_mask
;
1676 if (ctx
->chip_class
>= EVERGREEN
) {
1684 while (num_tile_pipes
--) {
1685 i
= backend_map
& item_mask
;
1687 backend_map
>>= item_width
;
1690 rscreen
->info
.enabled_rb_mask
= mask
;
1695 /* otherwise backup path for older kernels */
1697 /* create buffer for event data */
1698 buffer
= (struct r600_resource
*)
1699 pipe_buffer_create(ctx
->b
.screen
, 0,
1700 PIPE_USAGE_STAGING
, max_rbs
* 16);
1704 /* initialize buffer with zeroes */
1705 results
= r600_buffer_map_sync_with_rings(ctx
, buffer
, PIPE_TRANSFER_WRITE
);
1707 memset(results
, 0, max_rbs
* 4 * 4);
1709 /* emit EVENT_WRITE for ZPASS_DONE */
1710 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 2, 0));
1711 radeon_emit(cs
, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE
) | EVENT_INDEX(1));
1712 radeon_emit(cs
, buffer
->gpu_address
);
1713 radeon_emit(cs
, buffer
->gpu_address
>> 32);
1715 r600_emit_reloc(ctx
, &ctx
->gfx
, buffer
,
1716 RADEON_USAGE_WRITE
, RADEON_PRIO_QUERY
);
1718 /* analyze results */
1719 results
= r600_buffer_map_sync_with_rings(ctx
, buffer
, PIPE_TRANSFER_READ
);
1721 for(i
= 0; i
< max_rbs
; i
++) {
1722 /* at least highest bit will be set if backend is used */
1723 if (results
[i
*4 + 1])
1729 r600_resource_reference(&buffer
, NULL
);
1732 rscreen
->info
.enabled_rb_mask
= mask
;
1735 #define XFULL(name_, query_type_, type_, result_type_, group_id_) \
1738 .query_type = R600_QUERY_##query_type_, \
1739 .type = PIPE_DRIVER_QUERY_TYPE_##type_, \
1740 .result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_##result_type_, \
1741 .group_id = group_id_ \
1744 #define X(name_, query_type_, type_, result_type_) \
1745 XFULL(name_, query_type_, type_, result_type_, ~(unsigned)0)
1747 #define XG(group_, name_, query_type_, type_, result_type_) \
1748 XFULL(name_, query_type_, type_, result_type_, R600_QUERY_GROUP_##group_)
1750 static struct pipe_driver_query_info r600_driver_query_list
[] = {
1751 X("num-compilations", NUM_COMPILATIONS
, UINT64
, CUMULATIVE
),
1752 X("num-shaders-created", NUM_SHADERS_CREATED
, UINT64
, CUMULATIVE
),
1753 X("num-shader-cache-hits", NUM_SHADER_CACHE_HITS
, UINT64
, CUMULATIVE
),
1754 X("draw-calls", DRAW_CALLS
, UINT64
, AVERAGE
),
1755 X("spill-draw-calls", SPILL_DRAW_CALLS
, UINT64
, AVERAGE
),
1756 X("compute-calls", COMPUTE_CALLS
, UINT64
, AVERAGE
),
1757 X("spill-compute-calls", SPILL_COMPUTE_CALLS
, UINT64
, AVERAGE
),
1758 X("dma-calls", DMA_CALLS
, UINT64
, AVERAGE
),
1759 X("cp-dma-calls", CP_DMA_CALLS
, UINT64
, AVERAGE
),
1760 X("num-vs-flushes", NUM_VS_FLUSHES
, UINT64
, AVERAGE
),
1761 X("num-ps-flushes", NUM_PS_FLUSHES
, UINT64
, AVERAGE
),
1762 X("num-cs-flushes", NUM_CS_FLUSHES
, UINT64
, AVERAGE
),
1763 X("num-fb-cache-flushes", NUM_FB_CACHE_FLUSHES
, UINT64
, AVERAGE
),
1764 X("num-L2-invalidates", NUM_L2_INVALIDATES
, UINT64
, AVERAGE
),
1765 X("num-L2-writebacks", NUM_L2_WRITEBACKS
, UINT64
, AVERAGE
),
1766 X("CS-thread-busy", CS_THREAD_BUSY
, UINT64
, AVERAGE
),
1767 X("requested-VRAM", REQUESTED_VRAM
, BYTES
, AVERAGE
),
1768 X("requested-GTT", REQUESTED_GTT
, BYTES
, AVERAGE
),
1769 X("mapped-VRAM", MAPPED_VRAM
, BYTES
, AVERAGE
),
1770 X("mapped-GTT", MAPPED_GTT
, BYTES
, AVERAGE
),
1771 X("buffer-wait-time", BUFFER_WAIT_TIME
, MICROSECONDS
, CUMULATIVE
),
1772 X("num-mapped-buffers", NUM_MAPPED_BUFFERS
, UINT64
, AVERAGE
),
1773 X("num-GFX-IBs", NUM_GFX_IBS
, UINT64
, AVERAGE
),
1774 X("num-SDMA-IBs", NUM_SDMA_IBS
, UINT64
, AVERAGE
),
1775 X("num-bytes-moved", NUM_BYTES_MOVED
, BYTES
, CUMULATIVE
),
1776 X("num-evictions", NUM_EVICTIONS
, UINT64
, CUMULATIVE
),
1777 X("VRAM-usage", VRAM_USAGE
, BYTES
, AVERAGE
),
1778 X("VRAM-vis-usage", VRAM_VIS_USAGE
, BYTES
, AVERAGE
),
1779 X("GTT-usage", GTT_USAGE
, BYTES
, AVERAGE
),
1780 X("back-buffer-ps-draw-ratio", BACK_BUFFER_PS_DRAW_RATIO
, UINT64
, AVERAGE
),
1782 /* GPIN queries are for the benefit of old versions of GPUPerfStudio,
1783 * which use it as a fallback path to detect the GPU type.
1785 * Note: The names of these queries are significant for GPUPerfStudio
1786 * (and possibly their order as well). */
1787 XG(GPIN
, "GPIN_000", GPIN_ASIC_ID
, UINT
, AVERAGE
),
1788 XG(GPIN
, "GPIN_001", GPIN_NUM_SIMD
, UINT
, AVERAGE
),
1789 XG(GPIN
, "GPIN_002", GPIN_NUM_RB
, UINT
, AVERAGE
),
1790 XG(GPIN
, "GPIN_003", GPIN_NUM_SPI
, UINT
, AVERAGE
),
1791 XG(GPIN
, "GPIN_004", GPIN_NUM_SE
, UINT
, AVERAGE
),
1793 /* The following queries must be at the end of the list because their
1794 * availability is adjusted dynamically based on the DRM version. */
1795 X("GPU-load", GPU_LOAD
, UINT64
, AVERAGE
),
1796 X("GPU-shaders-busy", GPU_SHADERS_BUSY
, UINT64
, AVERAGE
),
1797 X("GPU-ta-busy", GPU_TA_BUSY
, UINT64
, AVERAGE
),
1798 X("GPU-gds-busy", GPU_GDS_BUSY
, UINT64
, AVERAGE
),
1799 X("GPU-vgt-busy", GPU_VGT_BUSY
, UINT64
, AVERAGE
),
1800 X("GPU-ia-busy", GPU_IA_BUSY
, UINT64
, AVERAGE
),
1801 X("GPU-sx-busy", GPU_SX_BUSY
, UINT64
, AVERAGE
),
1802 X("GPU-wd-busy", GPU_WD_BUSY
, UINT64
, AVERAGE
),
1803 X("GPU-bci-busy", GPU_BCI_BUSY
, UINT64
, AVERAGE
),
1804 X("GPU-sc-busy", GPU_SC_BUSY
, UINT64
, AVERAGE
),
1805 X("GPU-pa-busy", GPU_PA_BUSY
, UINT64
, AVERAGE
),
1806 X("GPU-db-busy", GPU_DB_BUSY
, UINT64
, AVERAGE
),
1807 X("GPU-cp-busy", GPU_CP_BUSY
, UINT64
, AVERAGE
),
1808 X("GPU-cb-busy", GPU_CB_BUSY
, UINT64
, AVERAGE
),
1809 X("GPU-sdma-busy", GPU_SDMA_BUSY
, UINT64
, AVERAGE
),
1810 X("GPU-pfp-busy", GPU_PFP_BUSY
, UINT64
, AVERAGE
),
1811 X("GPU-meq-busy", GPU_MEQ_BUSY
, UINT64
, AVERAGE
),
1812 X("GPU-me-busy", GPU_ME_BUSY
, UINT64
, AVERAGE
),
1813 X("GPU-surf-sync-busy", GPU_SURF_SYNC_BUSY
, UINT64
, AVERAGE
),
1814 X("GPU-dma-busy", GPU_DMA_BUSY
, UINT64
, AVERAGE
),
1815 X("GPU-scratch-ram-busy", GPU_SCRATCH_RAM_BUSY
, UINT64
, AVERAGE
),
1816 X("GPU-ce-busy", GPU_CE_BUSY
, UINT64
, AVERAGE
),
1818 X("temperature", GPU_TEMPERATURE
, UINT64
, AVERAGE
),
1819 X("shader-clock", CURRENT_GPU_SCLK
, HZ
, AVERAGE
),
1820 X("memory-clock", CURRENT_GPU_MCLK
, HZ
, AVERAGE
),
1827 static unsigned r600_get_num_queries(struct r600_common_screen
*rscreen
)
1829 if (rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
>= 42)
1830 return ARRAY_SIZE(r600_driver_query_list
);
1831 else if (rscreen
->info
.drm_major
== 3) {
1832 if (rscreen
->chip_class
>= VI
)
1833 return ARRAY_SIZE(r600_driver_query_list
) - 3;
1835 return ARRAY_SIZE(r600_driver_query_list
) - 10;
1838 return ARRAY_SIZE(r600_driver_query_list
) - 25;
1841 static int r600_get_driver_query_info(struct pipe_screen
*screen
,
1843 struct pipe_driver_query_info
*info
)
1845 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1846 unsigned num_queries
= r600_get_num_queries(rscreen
);
1849 unsigned num_perfcounters
=
1850 r600_get_perfcounter_info(rscreen
, 0, NULL
);
1852 return num_queries
+ num_perfcounters
;
1855 if (index
>= num_queries
)
1856 return r600_get_perfcounter_info(rscreen
, index
- num_queries
, info
);
1858 *info
= r600_driver_query_list
[index
];
1860 switch (info
->query_type
) {
1861 case R600_QUERY_REQUESTED_VRAM
:
1862 case R600_QUERY_VRAM_USAGE
:
1863 case R600_QUERY_MAPPED_VRAM
:
1864 info
->max_value
.u64
= rscreen
->info
.vram_size
;
1866 case R600_QUERY_REQUESTED_GTT
:
1867 case R600_QUERY_GTT_USAGE
:
1868 case R600_QUERY_MAPPED_GTT
:
1869 info
->max_value
.u64
= rscreen
->info
.gart_size
;
1871 case R600_QUERY_GPU_TEMPERATURE
:
1872 info
->max_value
.u64
= 125;
1874 case R600_QUERY_VRAM_VIS_USAGE
:
1875 info
->max_value
.u64
= rscreen
->info
.vram_vis_size
;
1879 if (info
->group_id
!= ~(unsigned)0 && rscreen
->perfcounters
)
1880 info
->group_id
+= rscreen
->perfcounters
->num_groups
;
1885 /* Note: Unfortunately, GPUPerfStudio hardcodes the order of hardware
1886 * performance counter groups, so be careful when changing this and related
1889 static int r600_get_driver_query_group_info(struct pipe_screen
*screen
,
1891 struct pipe_driver_query_group_info
*info
)
1893 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1894 unsigned num_pc_groups
= 0;
1896 if (rscreen
->perfcounters
)
1897 num_pc_groups
= rscreen
->perfcounters
->num_groups
;
1900 return num_pc_groups
+ R600_NUM_SW_QUERY_GROUPS
;
1902 if (index
< num_pc_groups
)
1903 return r600_get_perfcounter_group_info(rscreen
, index
, info
);
1905 index
-= num_pc_groups
;
1906 if (index
>= R600_NUM_SW_QUERY_GROUPS
)
1909 info
->name
= "GPIN";
1910 info
->max_active_queries
= 5;
1911 info
->num_queries
= 5;
1915 void r600_query_init(struct r600_common_context
*rctx
)
1917 rctx
->b
.create_query
= r600_create_query
;
1918 rctx
->b
.create_batch_query
= r600_create_batch_query
;
1919 rctx
->b
.destroy_query
= r600_destroy_query
;
1920 rctx
->b
.begin_query
= r600_begin_query
;
1921 rctx
->b
.end_query
= r600_end_query
;
1922 rctx
->b
.get_query_result
= r600_get_query_result
;
1923 rctx
->b
.get_query_result_resource
= r600_get_query_result_resource
;
1924 rctx
->render_cond_atom
.emit
= r600_emit_query_predication
;
1926 if (((struct r600_common_screen
*)rctx
->b
.screen
)->info
.num_render_backends
> 0)
1927 rctx
->b
.render_condition
= r600_render_condition
;
1929 LIST_INITHEAD(&rctx
->active_queries
);
1932 void r600_init_screen_query_functions(struct r600_common_screen
*rscreen
)
1934 rscreen
->b
.get_driver_query_info
= r600_get_driver_query_info
;
1935 rscreen
->b
.get_driver_query_group_info
= r600_get_driver_query_group_info
;