src/gallium/drivers/radeon/r600_streamout.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 #include "r600_pipe_common.h"
  28 #include "r600_cs.h"
  29
  30 #include "util/u_memory.h"
  31
  32 static struct pipe_stream_output_target *
  33 r600_create_so_target(struct pipe_context *ctx,
  34                       struct pipe_resource *buffer,
  35                       unsigned buffer_offset,
  36                       unsigned buffer_size)
  37 {
  38         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
  39         struct r600_so_target *t;
  40         struct r600_resource *rbuffer = (struct r600_resource*)buffer;
  41
  42         t = CALLOC_STRUCT(r600_so_target);
  43         if (!t) {
  44                 return NULL;
  45         }
  46
  47         u_suballocator_alloc(rctx->allocator_so_filled_size, 4,
  48                              &t->buf_filled_size_offset,
  49                              (struct pipe_resource**)&t->buf_filled_size);
  50         if (!t->buf_filled_size) {
  51                 FREE(t);
  52                 return NULL;
  53         }
  54
  55         t->b.reference.count = 1;
  56         t->b.context = ctx;
  57         pipe_resource_reference(&t->b.buffer, buffer);
  58         t->b.buffer_offset = buffer_offset;
  59         t->b.buffer_size = buffer_size;
  60
  61         util_range_add(&rbuffer->valid_buffer_range, buffer_offset,
  62                        buffer_offset + buffer_size);
  63         return &t->b;
  64 }
  65
  66 static void r600_so_target_destroy(struct pipe_context *ctx,
  67                                    struct pipe_stream_output_target *target)
  68 {
  69         struct r600_so_target *t = (struct r600_so_target*)target;
  70         pipe_resource_reference(&t->b.buffer, NULL);
  71         pipe_resource_reference((struct pipe_resource**)&t->buf_filled_size, NULL);
  72         FREE(t);
  73 }
  74
  75 void r600_streamout_buffers_dirty(struct r600_common_context *rctx)
  76 {
  77         struct r600_atom *begin = &rctx->streamout.begin_atom;
  78         unsigned num_bufs = util_bitcount(rctx->streamout.enabled_mask);
  79         unsigned num_bufs_appended = util_bitcount(rctx->streamout.enabled_mask &
  80                                                    rctx->streamout.append_bitmask);
  81
  82         rctx->streamout.num_dw_for_end =
  83                 12 + /* flush_vgt_streamout */
  84                 num_bufs * 8 + /* STRMOUT_BUFFER_UPDATE */
  85                 3 /* set_streamout_enable(0) */;
  86
  87         begin->num_dw = 12 + /* flush_vgt_streamout */
  88                         6; /* set_streamout_enable */
  89
  90         if (rctx->chip_class >= SI) {
  91                 begin->num_dw += num_bufs * 4; /* SET_CONTEXT_REG */
  92         } else {
  93                 begin->num_dw += num_bufs * 7; /* SET_CONTEXT_REG */
  94
  95                 if (rctx->family >= CHIP_RS780 && rctx->family <= CHIP_RV740)
  96                         begin->num_dw += num_bufs * 5; /* STRMOUT_BASE_UPDATE */
  97         }
  98
  99         begin->num_dw +=
 100                 num_bufs_appended * 8 + /* STRMOUT_BUFFER_UPDATE */
 101                 (num_bufs - num_bufs_appended) * 6 + /* STRMOUT_BUFFER_UPDATE */
 102                 (rctx->family > CHIP_R600 && rctx->family < CHIP_RS780 ? 2 : 0) + /* SURFACE_BASE_UPDATE */
 103                 rctx->streamout.num_dw_for_end;
 104
 105         begin->dirty = true;
 106 }
 107
 108 void r600_set_streamout_targets(struct pipe_context *ctx,
 109                                 unsigned num_targets,
 110                                 struct pipe_stream_output_target **targets,
 111                                 unsigned append_bitmask)
 112 {
 113         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 114         unsigned i;
 115
 116         /* Stop streamout. */
 117         if (rctx->streamout.num_targets && rctx->streamout.begin_emitted) {
 118                 r600_emit_streamout_end(rctx);
 119         }
 120
 121         /* Set the new targets. */
 122         for (i = 0; i < num_targets; i++) {
 123                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], targets[i]);
 124                 r600_context_add_resource_size(ctx, targets[i]->buffer);
 125         }
 126         for (; i < rctx->streamout.num_targets; i++) {
 127                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], NULL);
 128         }
 129
 130         rctx->streamout.enabled_mask = (num_targets >= 1 && targets[0] ? 1 : 0) |
 131                                        (num_targets >= 2 && targets[1] ? 2 : 0) |
 132                                        (num_targets >= 3 && targets[2] ? 4 : 0) |
 133                                        (num_targets >= 4 && targets[3] ? 8 : 0);
 134
 135         rctx->streamout.num_targets = num_targets;
 136         rctx->streamout.append_bitmask = append_bitmask;
 137
 138         if (num_targets) {
 139                 r600_streamout_buffers_dirty(rctx);
 140         }
 141 }
 142
 143 static void r600_flush_vgt_streamout(struct r600_common_context *rctx)
 144 {
 145         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 146
 147         r600_write_config_reg(cs, R_008490_CP_STRMOUT_CNTL, 0);
 148
 149         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 150         radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
 151
 152         radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
 153         radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
 154         radeon_emit(cs, R_008490_CP_STRMOUT_CNTL >> 2);  /* register */
 155         radeon_emit(cs, 0);
 156         radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* reference value */
 157         radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* mask */
 158         radeon_emit(cs, 4); /* poll interval */
 159 }
 160
 161 static void evergreen_flush_vgt_streamout(struct r600_common_context *rctx)
 162 {
 163         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 164
 165         r600_write_config_reg(cs, R_0084FC_CP_STRMOUT_CNTL, 0);
 166
 167         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 168         radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
 169
 170         radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
 171         radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
 172         radeon_emit(cs, R_0084FC_CP_STRMOUT_CNTL >> 2);  /* register */
 173         radeon_emit(cs, 0);
 174         radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
 175         radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
 176         radeon_emit(cs, 4); /* poll interval */
 177 }
 178
 179 static void r600_set_streamout_enable(struct r600_common_context *rctx, unsigned buffer_enable_bit)
 180 {
 181         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 182
 183         if (buffer_enable_bit) {
 184                 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(1));
 185                 r600_write_context_reg(cs, R_028B20_VGT_STRMOUT_BUFFER_EN, buffer_enable_bit);
 186         } else {
 187                 r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(0));
 188         }
 189 }
 190
 191 static void evergreen_set_streamout_enable(struct r600_common_context *rctx, unsigned buffer_enable_bit)
 192 {
 193         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 194
 195         if (buffer_enable_bit) {
 196                 r600_write_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
 197                 radeon_emit(cs, S_028B94_STREAMOUT_0_EN(1)); /* R_028B94_VGT_STRMOUT_CONFIG */
 198                 radeon_emit(cs, S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit)); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
 199         } else {
 200                 r600_write_context_reg(cs, R_028B94_VGT_STRMOUT_CONFIG, S_028B94_STREAMOUT_0_EN(0));
 201         }
 202 }
 203
 204 static void r600_emit_reloc(struct r600_common_context *rctx,
 205                             struct r600_ring *ring, struct r600_resource *rbo,
 206                             enum radeon_bo_usage usage)
 207 {
 208         struct radeon_winsys_cs *cs = ring->cs;
 209         bool has_vm = ((struct r600_common_screen*)rctx->b.screen)->info.r600_virtual_address;
 210         unsigned reloc = r600_context_bo_reloc(rctx, ring, rbo, usage);
 211
 212         if (!has_vm) {
 213                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
 214                 radeon_emit(cs, reloc);
 215         }
 216 }
 217
 218 static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r600_atom *atom)
 219 {
 220         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 221         struct r600_so_target **t = rctx->streamout.targets;
 222         unsigned *stride_in_dw = rctx->streamout.stride_in_dw;
 223         unsigned i, update_flags = 0;
 224
 225         if (rctx->chip_class >= EVERGREEN) {
 226                 evergreen_flush_vgt_streamout(rctx);
 227                 evergreen_set_streamout_enable(rctx, rctx->streamout.enabled_mask);
 228         } else {
 229                 r600_flush_vgt_streamout(rctx);
 230                 r600_set_streamout_enable(rctx, rctx->streamout.enabled_mask);
 231         }
 232
 233         for (i = 0; i < rctx->streamout.num_targets; i++) {
 234                 if (!t[i])
 235                         continue;
 236
 237                 t[i]->stride_in_dw = stride_in_dw[i];
 238
 239                 if (rctx->chip_class >= SI) {
 240                         /* SI binds streamout buffers as shader resources.
 241                          * VGT only counts primitives and tells the shader
 242                          * through SGPRs what to do. */
 243                         r600_write_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
 244                         radeon_emit(cs, (t[i]->b.buffer_offset +
 245                                          t[i]->b.buffer_size) >> 2);    /* BUFFER_SIZE (in DW) */
 246                         radeon_emit(cs, stride_in_dw[i]);               /* VTX_STRIDE (in DW) */
 247                 } else {
 248                         uint64_t va = r600_resource_va(rctx->b.screen,
 249                                                        (void*)t[i]->b.buffer);
 250
 251                         update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
 252
 253                         r600_write_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
 254                         radeon_emit(cs, (t[i]->b.buffer_offset +
 255                                          t[i]->b.buffer_size) >> 2);    /* BUFFER_SIZE (in DW) */
 256                         radeon_emit(cs, stride_in_dw[i]);               /* VTX_STRIDE (in DW) */
 257                         radeon_emit(cs, va >> 8);                       /* BUFFER_BASE */
 258
 259                         r600_emit_reloc(rctx, &rctx->rings.gfx, r600_resource(t[i]->b.buffer),
 260                                         RADEON_USAGE_WRITE);
 261
 262                         /* R7xx requires this packet after updating BUFFER_BASE.
 263                          * Without this, R7xx locks up. */
 264                         if (rctx->family >= CHIP_RS780 && rctx->family <= CHIP_RV740) {
 265                                 radeon_emit(cs, PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0));
 266                                 radeon_emit(cs, i);
 267                                 radeon_emit(cs, va >> 8);
 268
 269                                 r600_emit_reloc(rctx, &rctx->rings.gfx, r600_resource(t[i]->b.buffer),
 270                                                 RADEON_USAGE_WRITE);
 271                         }
 272                 }
 273
 274                 if (rctx->streamout.append_bitmask & (1 << i)) {
 275                         uint64_t va = r600_resource_va(rctx->b.screen,
 276                                                        (void*)t[i]->buf_filled_size) +
 277                                       t[i]->buf_filled_size_offset;
 278
 279                         /* Append. */
 280                         radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
 281                         radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
 282                                     STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
 283                         radeon_emit(cs, 0); /* unused */
 284                         radeon_emit(cs, 0); /* unused */
 285                         radeon_emit(cs, va); /* src address lo */
 286                         radeon_emit(cs, va >> 32); /* src address hi */
 287
 288                         r600_emit_reloc(rctx,  &rctx->rings.gfx, t[i]->buf_filled_size,
 289                                         RADEON_USAGE_READ);
 290                 } else {
 291                         /* Start from the beginning. */
 292                         radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
 293                         radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
 294                                     STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
 295                         radeon_emit(cs, 0); /* unused */
 296                         radeon_emit(cs, 0); /* unused */
 297                         radeon_emit(cs, t[i]->b.buffer_offset >> 2); /* buffer offset in DW */
 298                         radeon_emit(cs, 0); /* unused */
 299                 }
 300         }
 301
 302         if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770) {
 303                 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
 304                 radeon_emit(cs, update_flags);
 305         }
 306         rctx->streamout.begin_emitted = true;
 307 }
 308
 309 void r600_emit_streamout_end(struct r600_common_context *rctx)
 310 {
 311         struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 312         struct r600_so_target **t = rctx->streamout.targets;
 313         unsigned i;
 314         uint64_t va;
 315
 316         if (rctx->chip_class >= EVERGREEN) {
 317                 evergreen_flush_vgt_streamout(rctx);
 318         } else {
 319                 r600_flush_vgt_streamout(rctx);
 320         }
 321
 322         for (i = 0; i < rctx->streamout.num_targets; i++) {
 323                 if (!t[i])
 324                         continue;
 325
 326                 va = r600_resource_va(rctx->b.screen,
 327                                       (void*)t[i]->buf_filled_size) + t[i]->buf_filled_size_offset;
 328                 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
 329                 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
 330                             STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
 331                             STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
 332                 radeon_emit(cs, va);     /* dst address lo */
 333                 radeon_emit(cs, va >> 32); /* dst address hi */
 334                 radeon_emit(cs, 0); /* unused */
 335                 radeon_emit(cs, 0); /* unused */
 336
 337                 r600_emit_reloc(rctx,  &rctx->rings.gfx, t[i]->buf_filled_size,
 338                                 RADEON_USAGE_WRITE);
 339         }
 340
 341         if (rctx->chip_class >= EVERGREEN) {
 342                 evergreen_set_streamout_enable(rctx, 0);
 343         } else {
 344                 r600_set_streamout_enable(rctx, 0);
 345         }
 346
 347         rctx->streamout.begin_emitted = false;
 348
 349         if (rctx->chip_class >= R700) {
 350                 rctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
 351         } else {
 352                 rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
 353         }
 354 }
 355
 356 void r600_streamout_init(struct r600_common_context *rctx)
 357 {
 358         rctx->b.create_stream_output_target = r600_create_so_target;
 359         rctx->b.stream_output_target_destroy = r600_so_target_destroy;
 360         rctx->streamout.begin_atom.emit = r600_emit_streamout_begin;
 361 }