src/gallium/drivers/radeon/r600_streamout.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  *
  25  */
  26
  27 #include "r600_pipe_common.h"
  28 #include "r600_cs.h"
  29
  30 #include "util/u_memory.h"
  31
  32 static void r600_set_streamout_enable(struct r600_common_context *rctx, bool enable);
  33
  34 static struct pipe_stream_output_target *
  35 r600_create_so_target(struct pipe_context *ctx,
  36                       struct pipe_resource *buffer,
  37                       unsigned buffer_offset,
  38                       unsigned buffer_size)
  39 {
  40         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
  41         struct r600_so_target *t;
  42         struct r600_resource *rbuffer = (struct r600_resource*)buffer;
  43
  44         t = CALLOC_STRUCT(r600_so_target);
  45         if (!t) {
  46                 return NULL;
  47         }
  48
  49         u_suballocator_alloc(rctx->allocator_so_filled_size, 4,
  50                              &t->buf_filled_size_offset,
  51                              (struct pipe_resource**)&t->buf_filled_size);
  52         if (!t->buf_filled_size) {
  53                 FREE(t);
  54                 return NULL;
  55         }
  56
  57         t->b.reference.count = 1;
  58         t->b.context = ctx;
  59         pipe_resource_reference(&t->b.buffer, buffer);
  60         t->b.buffer_offset = buffer_offset;
  61         t->b.buffer_size = buffer_size;
  62
  63         util_range_add(&rbuffer->valid_buffer_range, buffer_offset,
  64                        buffer_offset + buffer_size);
  65         return &t->b;
  66 }
  67
  68 static void r600_so_target_destroy(struct pipe_context *ctx,
  69                                    struct pipe_stream_output_target *target)
  70 {
  71         struct r600_so_target *t = (struct r600_so_target*)target;
  72         pipe_resource_reference(&t->b.buffer, NULL);
  73         pipe_resource_reference((struct pipe_resource**)&t->buf_filled_size, NULL);
  74         FREE(t);
  75 }
  76
  77 void r600_streamout_buffers_dirty(struct r600_common_context *rctx)
  78 {
  79         struct r600_atom *begin = &rctx->streamout.begin_atom;
  80         unsigned num_bufs = util_bitcount(rctx->streamout.enabled_mask);
  81         unsigned num_bufs_appended = util_bitcount(rctx->streamout.enabled_mask &
  82                                                    rctx->streamout.append_bitmask);
  83
  84         if (!num_bufs)
  85                 return;
  86
  87         rctx->streamout.num_dw_for_end =
  88                 12 + /* flush_vgt_streamout */
  89                 num_bufs * 11; /* STRMOUT_BUFFER_UPDATE, BUFFER_SIZE */
  90
  91         begin->num_dw = 12; /* flush_vgt_streamout */
  92
  93         if (rctx->chip_class >= SI) {
  94                 begin->num_dw += num_bufs * 4; /* SET_CONTEXT_REG */
  95         } else {
  96                 begin->num_dw += num_bufs * 7; /* SET_CONTEXT_REG */
  97
  98                 if (rctx->family >= CHIP_RS780 && rctx->family <= CHIP_RV740)
  99                         begin->num_dw += num_bufs * 5; /* STRMOUT_BASE_UPDATE */
 100         }
 101
 102         begin->num_dw +=
 103                 num_bufs_appended * 8 + /* STRMOUT_BUFFER_UPDATE */
 104                 (num_bufs - num_bufs_appended) * 6 + /* STRMOUT_BUFFER_UPDATE */
 105                 (rctx->family > CHIP_R600 && rctx->family < CHIP_RS780 ? 2 : 0); /* SURFACE_BASE_UPDATE */
 106
 107         rctx->set_atom_dirty(rctx, begin, true);
 108
 109         r600_set_streamout_enable(rctx, true);
 110 }
 111
 112 void r600_set_streamout_targets(struct pipe_context *ctx,
 113                                 unsigned num_targets,
 114                                 struct pipe_stream_output_target **targets,
 115                                 const unsigned *offsets)
 116 {
 117         struct r600_common_context *rctx = (struct r600_common_context *)ctx;
 118         unsigned i;
 119         unsigned append_bitmask = 0;
 120
 121         /* Stop streamout. */
 122         if (rctx->streamout.num_targets && rctx->streamout.begin_emitted) {
 123                 r600_emit_streamout_end(rctx);
 124         }
 125
 126         /* Set the new targets. */
 127         for (i = 0; i < num_targets; i++) {
 128                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], targets[i]);
 129                 r600_context_add_resource_size(ctx, targets[i]->buffer);
 130                 if (offsets[i] == ((unsigned)-1))
 131                         append_bitmask |=  1 << i;
 132         }
 133         for (; i < rctx->streamout.num_targets; i++) {
 134                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], NULL);
 135         }
 136
 137         rctx->streamout.enabled_mask = (num_targets >= 1 && targets[0] ? 1 : 0) |
 138                                        (num_targets >= 2 && targets[1] ? 2 : 0) |
 139                                        (num_targets >= 3 && targets[2] ? 4 : 0) |
 140                                        (num_targets >= 4 && targets[3] ? 8 : 0);
 141
 142         rctx->streamout.num_targets = num_targets;
 143         rctx->streamout.append_bitmask = append_bitmask;
 144
 145         if (num_targets) {
 146                 r600_streamout_buffers_dirty(rctx);
 147         } else {
 148                 rctx->set_atom_dirty(rctx, &rctx->streamout.begin_atom, false);
 149                 r600_set_streamout_enable(rctx, false);
 150         }
 151 }
 152
 153 static void r600_flush_vgt_streamout(struct r600_common_context *rctx)
 154 {
 155         struct radeon_winsys_cs *cs = rctx->gfx.cs;
 156         unsigned reg_strmout_cntl;
 157
 158         /* The register is at different places on different ASICs. */
 159         if (rctx->chip_class >= CIK) {
 160                 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
 161         } else if (rctx->chip_class >= EVERGREEN) {
 162                 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
 163         } else {
 164                 reg_strmout_cntl = R_008490_CP_STRMOUT_CNTL;
 165         }
 166
 167         if (rctx->chip_class >= CIK) {
 168                 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
 169         } else {
 170                 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
 171         }
 172
 173         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 174         radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
 175
 176         radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
 177         radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
 178         radeon_emit(cs, reg_strmout_cntl >> 2);  /* register */
 179         radeon_emit(cs, 0);
 180         radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* reference value */
 181         radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* mask */
 182         radeon_emit(cs, 4); /* poll interval */
 183 }
 184
 185 static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r600_atom *atom)
 186 {
 187         struct radeon_winsys_cs *cs = rctx->gfx.cs;
 188         struct r600_so_target **t = rctx->streamout.targets;
 189         unsigned *stride_in_dw = rctx->streamout.stride_in_dw;
 190         unsigned i, update_flags = 0;
 191
 192         r600_flush_vgt_streamout(rctx);
 193
 194         for (i = 0; i < rctx->streamout.num_targets; i++) {
 195                 if (!t[i])
 196                         continue;
 197
 198                 t[i]->stride_in_dw = stride_in_dw[i];
 199
 200                 if (rctx->chip_class >= SI) {
 201                         /* SI binds streamout buffers as shader resources.
 202                          * VGT only counts primitives and tells the shader
 203                          * through SGPRs what to do. */
 204                         radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
 205                         radeon_emit(cs, (t[i]->b.buffer_offset +
 206                                          t[i]->b.buffer_size) >> 2);    /* BUFFER_SIZE (in DW) */
 207                         radeon_emit(cs, stride_in_dw[i]);               /* VTX_STRIDE (in DW) */
 208                 } else {
 209                         uint64_t va = r600_resource(t[i]->b.buffer)->gpu_address;
 210
 211                         update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
 212
 213                         radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
 214                         radeon_emit(cs, (t[i]->b.buffer_offset +
 215                                          t[i]->b.buffer_size) >> 2);    /* BUFFER_SIZE (in DW) */
 216                         radeon_emit(cs, stride_in_dw[i]);               /* VTX_STRIDE (in DW) */
 217                         radeon_emit(cs, va >> 8);                       /* BUFFER_BASE */
 218
 219                         r600_emit_reloc(rctx, &rctx->gfx, r600_resource(t[i]->b.buffer),
 220                                         RADEON_USAGE_WRITE, RADEON_PRIO_RINGS_STREAMOUT);
 221
 222                         /* R7xx requires this packet after updating BUFFER_BASE.
 223                          * Without this, R7xx locks up. */
 224                         if (rctx->family >= CHIP_RS780 && rctx->family <= CHIP_RV740) {
 225                                 radeon_emit(cs, PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0));
 226                                 radeon_emit(cs, i);
 227                                 radeon_emit(cs, va >> 8);
 228
 229                                 r600_emit_reloc(rctx, &rctx->gfx, r600_resource(t[i]->b.buffer),
 230                                                 RADEON_USAGE_WRITE, RADEON_PRIO_RINGS_STREAMOUT);
 231                         }
 232                 }
 233
 234                 if (rctx->streamout.append_bitmask & (1 << i) && t[i]->buf_filled_size_valid) {
 235                         uint64_t va = t[i]->buf_filled_size->gpu_address +
 236                                       t[i]->buf_filled_size_offset;
 237
 238                         /* Append. */
 239                         radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
 240                         radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
 241                                     STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
 242                         radeon_emit(cs, 0); /* unused */
 243                         radeon_emit(cs, 0); /* unused */
 244                         radeon_emit(cs, va); /* src address lo */
 245                         radeon_emit(cs, va >> 32); /* src address hi */
 246
 247                         r600_emit_reloc(rctx,  &rctx->gfx, t[i]->buf_filled_size,
 248                                         RADEON_USAGE_READ, RADEON_PRIO_SO_FILLED_SIZE);
 249                 } else {
 250                         /* Start from the beginning. */
 251                         radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
 252                         radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
 253                                     STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
 254                         radeon_emit(cs, 0); /* unused */
 255                         radeon_emit(cs, 0); /* unused */
 256                         radeon_emit(cs, t[i]->b.buffer_offset >> 2); /* buffer offset in DW */
 257                         radeon_emit(cs, 0); /* unused */
 258                 }
 259         }
 260
 261         if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770) {
 262                 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
 263                 radeon_emit(cs, update_flags);
 264         }
 265         rctx->streamout.begin_emitted = true;
 266 }
 267
 268 void r600_emit_streamout_end(struct r600_common_context *rctx)
 269 {
 270         struct radeon_winsys_cs *cs = rctx->gfx.cs;
 271         struct r600_so_target **t = rctx->streamout.targets;
 272         unsigned i;
 273         uint64_t va;
 274
 275         r600_flush_vgt_streamout(rctx);
 276
 277         for (i = 0; i < rctx->streamout.num_targets; i++) {
 278                 if (!t[i])
 279                         continue;
 280
 281                 va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
 282                 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
 283                 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
 284                             STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
 285                             STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
 286                 radeon_emit(cs, va);     /* dst address lo */
 287                 radeon_emit(cs, va >> 32); /* dst address hi */
 288                 radeon_emit(cs, 0); /* unused */
 289                 radeon_emit(cs, 0); /* unused */
 290
 291                 r600_emit_reloc(rctx,  &rctx->gfx, t[i]->buf_filled_size,
 292                                 RADEON_USAGE_WRITE, RADEON_PRIO_SO_FILLED_SIZE);
 293
 294                 /* Zero the buffer size. The counters (primitives generated,
 295                  * primitives emitted) may be enabled even if there is not
 296                  * buffer bound. This ensures that the primitives-emitted query
 297                  * won't increment. */
 298                 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
 299
 300                 t[i]->buf_filled_size_valid = true;
 301         }
 302
 303         rctx->streamout.begin_emitted = false;
 304         rctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
 305 }
 306
 307 /* STREAMOUT CONFIG DERIVED STATE
 308  *
 309  * Streamout must be enabled for the PRIMITIVES_GENERATED query to work.
 310  * The buffer mask is an independent state, so no writes occur if there
 311  * are no buffers bound.
 312  */
 313
 314 static bool r600_get_strmout_en(struct r600_common_context *rctx)
 315 {
 316         return rctx->streamout.streamout_enabled ||
 317                rctx->streamout.prims_gen_query_enabled;
 318 }
 319
 320 static void r600_emit_streamout_enable(struct r600_common_context *rctx,
 321                                        struct r600_atom *atom)
 322 {
 323         unsigned strmout_config_reg = R_028AB0_VGT_STRMOUT_EN;
 324         unsigned strmout_config_val = S_028B94_STREAMOUT_0_EN(r600_get_strmout_en(rctx));
 325         unsigned strmout_buffer_reg = R_028B20_VGT_STRMOUT_BUFFER_EN;
 326         unsigned strmout_buffer_val = rctx->streamout.hw_enabled_mask &
 327                                       rctx->streamout.enabled_stream_buffers_mask;
 328
 329         if (rctx->chip_class >= EVERGREEN) {
 330                 strmout_buffer_reg = R_028B98_VGT_STRMOUT_BUFFER_CONFIG;
 331
 332                 strmout_config_reg = R_028B94_VGT_STRMOUT_CONFIG;
 333                 strmout_config_val |=
 334                         S_028B94_RAST_STREAM(0) |
 335                         S_028B94_STREAMOUT_1_EN(r600_get_strmout_en(rctx)) |
 336                         S_028B94_STREAMOUT_2_EN(r600_get_strmout_en(rctx)) |
 337                         S_028B94_STREAMOUT_3_EN(r600_get_strmout_en(rctx));
 338         }
 339         radeon_set_context_reg(rctx->gfx.cs, strmout_buffer_reg, strmout_buffer_val);
 340         radeon_set_context_reg(rctx->gfx.cs, strmout_config_reg, strmout_config_val);
 341 }
 342
 343 static void r600_set_streamout_enable(struct r600_common_context *rctx, bool enable)
 344 {
 345         bool old_strmout_en = r600_get_strmout_en(rctx);
 346         unsigned old_hw_enabled_mask = rctx->streamout.hw_enabled_mask;
 347
 348         rctx->streamout.streamout_enabled = enable;
 349
 350         rctx->streamout.hw_enabled_mask = rctx->streamout.enabled_mask |
 351                                           (rctx->streamout.enabled_mask << 4) |
 352                                           (rctx->streamout.enabled_mask << 8) |
 353                                           (rctx->streamout.enabled_mask << 12);
 354
 355         if ((old_strmout_en != r600_get_strmout_en(rctx)) ||
 356             (old_hw_enabled_mask != rctx->streamout.hw_enabled_mask)) {
 357                 rctx->set_atom_dirty(rctx, &rctx->streamout.enable_atom, true);
 358         }
 359 }
 360
 361 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
 362                                              unsigned type, int diff)
 363 {
 364         if (type == PIPE_QUERY_PRIMITIVES_GENERATED) {
 365                 bool old_strmout_en = r600_get_strmout_en(rctx);
 366
 367                 rctx->streamout.num_prims_gen_queries += diff;
 368                 assert(rctx->streamout.num_prims_gen_queries >= 0);
 369
 370                 rctx->streamout.prims_gen_query_enabled =
 371                         rctx->streamout.num_prims_gen_queries != 0;
 372
 373                 if (old_strmout_en != r600_get_strmout_en(rctx)) {
 374                         rctx->set_atom_dirty(rctx, &rctx->streamout.enable_atom, true);
 375                 }
 376         }
 377 }
 378
 379 void r600_streamout_init(struct r600_common_context *rctx)
 380 {
 381         rctx->b.create_stream_output_target = r600_create_so_target;
 382         rctx->b.stream_output_target_destroy = r600_so_target_destroy;
 383         rctx->streamout.begin_atom.emit = r600_emit_streamout_begin;
 384         rctx->streamout.enable_atom.emit = r600_emit_streamout_enable;
 385         rctx->streamout.enable_atom.num_dw = 6;
 386 }