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radeonsi: allocate DCC in the same backing buffer as the texture
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include <errno.h>
33 #include <inttypes.h>
34
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context *pipe,
37 struct pipe_resource *dst,
38 unsigned dst_level,
39 unsigned dstx, unsigned dsty, unsigned dstz,
40 struct pipe_resource *src,
41 unsigned src_level,
42 const struct pipe_box *src_box)
43 {
44 struct pipe_blit_info blit;
45
46 memset(&blit, 0, sizeof(blit));
47 blit.src.resource = src;
48 blit.src.format = src->format;
49 blit.src.level = src_level;
50 blit.src.box = *src_box;
51 blit.dst.resource = dst;
52 blit.dst.format = dst->format;
53 blit.dst.level = dst_level;
54 blit.dst.box.x = dstx;
55 blit.dst.box.y = dsty;
56 blit.dst.box.z = dstz;
57 blit.dst.box.width = src_box->width;
58 blit.dst.box.height = src_box->height;
59 blit.dst.box.depth = src_box->depth;
60 blit.mask = util_format_get_mask(src->format) &
61 util_format_get_mask(dst->format);
62 blit.filter = PIPE_TEX_FILTER_NEAREST;
63
64 if (blit.mask) {
65 pipe->blit(pipe, &blit);
66 }
67 }
68
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
71 {
72 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
73 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
74 struct pipe_resource *dst = &rtransfer->staging->b.b;
75 struct pipe_resource *src = transfer->resource;
76
77 if (src->nr_samples > 1) {
78 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
79 src, transfer->level, &transfer->box);
80 return;
81 }
82
83 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
84 &transfer->box);
85 }
86
87 /* Copy from a transfer's staging texture to a full GPU one. */
88 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
89 {
90 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
91 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
92 struct pipe_resource *dst = transfer->resource;
93 struct pipe_resource *src = &rtransfer->staging->b.b;
94 struct pipe_box sbox;
95
96 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
97
98 if (dst->nr_samples > 1) {
99 r600_copy_region_with_blit(ctx, dst, transfer->level,
100 transfer->box.x, transfer->box.y, transfer->box.z,
101 src, 0, &sbox);
102 return;
103 }
104
105 rctx->dma_copy(ctx, dst, transfer->level,
106 transfer->box.x, transfer->box.y, transfer->box.z,
107 src, 0, &sbox);
108 }
109
110 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
111 const struct pipe_box *box)
112 {
113 enum pipe_format format = rtex->resource.b.b.format;
114
115 return rtex->surface.level[level].offset +
116 box->z * rtex->surface.level[level].slice_size +
117 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
118 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
119 }
120
121 static int r600_init_surface(struct r600_common_screen *rscreen,
122 struct radeon_surf *surface,
123 const struct pipe_resource *ptex,
124 unsigned array_mode,
125 bool is_flushed_depth)
126 {
127 const struct util_format_description *desc =
128 util_format_description(ptex->format);
129 bool is_depth, is_stencil;
130
131 is_depth = util_format_has_depth(desc);
132 is_stencil = util_format_has_stencil(desc);
133
134 surface->npix_x = ptex->width0;
135 surface->npix_y = ptex->height0;
136 surface->npix_z = ptex->depth0;
137 surface->blk_w = util_format_get_blockwidth(ptex->format);
138 surface->blk_h = util_format_get_blockheight(ptex->format);
139 surface->blk_d = 1;
140 surface->array_size = 1;
141 surface->last_level = ptex->last_level;
142
143 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
144 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
145 surface->bpe = 4; /* stencil is allocated separately on evergreen */
146 } else {
147 surface->bpe = util_format_get_blocksize(ptex->format);
148 /* align byte per element on dword */
149 if (surface->bpe == 3) {
150 surface->bpe = 4;
151 }
152 }
153
154 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
155 surface->flags = RADEON_SURF_SET(array_mode, MODE);
156
157 switch (ptex->target) {
158 case PIPE_TEXTURE_1D:
159 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
160 break;
161 case PIPE_TEXTURE_RECT:
162 case PIPE_TEXTURE_2D:
163 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
164 break;
165 case PIPE_TEXTURE_3D:
166 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
167 break;
168 case PIPE_TEXTURE_1D_ARRAY:
169 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
170 surface->array_size = ptex->array_size;
171 break;
172 case PIPE_TEXTURE_2D_ARRAY:
173 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
175 surface->array_size = ptex->array_size;
176 break;
177 case PIPE_TEXTURE_CUBE:
178 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
179 break;
180 case PIPE_BUFFER:
181 default:
182 return -EINVAL;
183 }
184 if (ptex->bind & PIPE_BIND_SCANOUT) {
185 surface->flags |= RADEON_SURF_SCANOUT;
186 }
187
188 if (!is_flushed_depth && is_depth) {
189 surface->flags |= RADEON_SURF_ZBUFFER;
190
191 if (is_stencil) {
192 surface->flags |= RADEON_SURF_SBUFFER |
193 RADEON_SURF_HAS_SBUFFER_MIPTREE;
194 }
195 }
196 if (rscreen->chip_class >= SI) {
197 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
198 }
199 return 0;
200 }
201
202 static int r600_setup_surface(struct pipe_screen *screen,
203 struct r600_texture *rtex,
204 unsigned pitch_in_bytes_override)
205 {
206 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
207 int r;
208
209 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
210 if (r) {
211 return r;
212 }
213
214 rtex->size = rtex->surface.bo_size;
215
216 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
217 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
218 * for those
219 */
220 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
221 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
222 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
223 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
224 rtex->surface.stencil_offset =
225 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
226 }
227 }
228 return 0;
229 }
230
231 static void r600_texture_init_metadata(struct r600_texture *rtex,
232 struct radeon_bo_metadata *metadata)
233 {
234 struct radeon_surf *surface = &rtex->surface;
235
236 memset(metadata, 0, sizeof(*metadata));
237 metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
238 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
239 metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
240 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
241 metadata->pipe_config = surface->pipe_config;
242 metadata->bankw = surface->bankw;
243 metadata->bankh = surface->bankh;
244 metadata->tile_split = surface->tile_split;
245 metadata->stencil_tile_split = surface->stencil_tile_split;
246 metadata->mtilea = surface->mtilea;
247 metadata->num_banks = surface->num_banks;
248 metadata->stride = surface->level[0].pitch_bytes;
249 metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
250 }
251
252 static void r600_dirty_all_framebuffer_states(struct r600_common_screen *rscreen)
253 {
254 p_atomic_inc(&rscreen->dirty_fb_counter);
255 }
256
257 static void r600_eliminate_fast_color_clear(struct r600_common_screen *rscreen,
258 struct r600_texture *rtex)
259 {
260 struct pipe_context *ctx = rscreen->aux_context;
261
262 pipe_mutex_lock(rscreen->aux_context_lock);
263 ctx->flush_resource(ctx, &rtex->resource.b.b);
264 ctx->flush(ctx, NULL, 0);
265 pipe_mutex_unlock(rscreen->aux_context_lock);
266 }
267
268 static void r600_texture_disable_cmask(struct r600_common_screen *rscreen,
269 struct r600_texture *rtex)
270 {
271 if (!rtex->cmask.size)
272 return;
273
274 assert(rtex->resource.b.b.nr_samples <= 1);
275
276 /* Disable CMASK. */
277 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
278 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
279
280 if (rscreen->chip_class >= SI)
281 rtex->cb_color_info &= ~SI_S_028C70_FAST_CLEAR(1);
282 else
283 rtex->cb_color_info &= ~EG_S_028C70_FAST_CLEAR(1);
284
285 if (rtex->cmask_buffer != &rtex->resource)
286 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
287
288 /* Notify all contexts about the change. */
289 r600_dirty_all_framebuffer_states(rscreen);
290 }
291
292 static boolean r600_texture_get_handle(struct pipe_screen* screen,
293 struct pipe_resource *resource,
294 struct winsys_handle *whandle,
295 unsigned usage)
296 {
297 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
298 struct r600_resource *res = (struct r600_resource*)resource;
299 struct r600_texture *rtex = (struct r600_texture*)resource;
300 struct radeon_bo_metadata metadata;
301
302 /* This is not supported now, but it might be required for OpenCL
303 * interop in the future.
304 */
305 if (resource->target != PIPE_BUFFER &&
306 (resource->nr_samples > 1 || rtex->is_depth))
307 return NULL;
308
309 if (!res->is_shared) {
310 res->is_shared = true;
311 res->external_usage = usage;
312
313 if (resource->target != PIPE_BUFFER) {
314 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) {
315 /* Eliminate fast clear (both CMASK and DCC) */
316 r600_eliminate_fast_color_clear(rscreen, rtex);
317
318 /* Disable CMASK if flush_resource isn't going
319 * to be called.
320 */
321 r600_texture_disable_cmask(rscreen, rtex);
322 }
323
324 r600_texture_init_metadata(rtex, &metadata);
325 rscreen->ws->buffer_set_metadata(res->buf, &metadata);
326 }
327 } else {
328 assert(res->external_usage == usage);
329 }
330
331 return rscreen->ws->buffer_get_handle(res->buf,
332 rtex->surface.level[0].pitch_bytes,
333 whandle);
334 }
335
336 static void r600_texture_destroy(struct pipe_screen *screen,
337 struct pipe_resource *ptex)
338 {
339 struct r600_texture *rtex = (struct r600_texture*)ptex;
340 struct r600_resource *resource = &rtex->resource;
341
342 if (rtex->flushed_depth_texture)
343 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
344
345 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
346 if (rtex->cmask_buffer != &rtex->resource) {
347 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
348 }
349 pb_reference(&resource->buf, NULL);
350 FREE(rtex);
351 }
352
353 static const struct u_resource_vtbl r600_texture_vtbl;
354
355 /* The number of samples can be specified independently of the texture. */
356 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
357 struct r600_texture *rtex,
358 unsigned nr_samples,
359 struct r600_fmask_info *out)
360 {
361 /* FMASK is allocated like an ordinary texture. */
362 struct radeon_surf fmask = rtex->surface;
363
364 memset(out, 0, sizeof(*out));
365
366 fmask.bo_alignment = 0;
367 fmask.bo_size = 0;
368 fmask.nsamples = 1;
369 fmask.flags |= RADEON_SURF_FMASK;
370
371 /* Force 2D tiling if it wasn't set. This may occur when creating
372 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
373 * destination buffer must have an FMASK too. */
374 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
375 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
376
377 if (rscreen->chip_class >= SI) {
378 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
379 }
380
381 switch (nr_samples) {
382 case 2:
383 case 4:
384 fmask.bpe = 1;
385 if (rscreen->chip_class <= CAYMAN) {
386 fmask.bankh = 4;
387 }
388 break;
389 case 8:
390 fmask.bpe = 4;
391 break;
392 default:
393 R600_ERR("Invalid sample count for FMASK allocation.\n");
394 return;
395 }
396
397 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
398 * This can be fixed by writing a separate FMASK allocator specifically
399 * for R600-R700 asics. */
400 if (rscreen->chip_class <= R700) {
401 fmask.bpe *= 2;
402 }
403
404 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
405 R600_ERR("Got error in surface_init while allocating FMASK.\n");
406 return;
407 }
408
409 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
410
411 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
412 if (out->slice_tile_max)
413 out->slice_tile_max -= 1;
414
415 out->tile_mode_index = fmask.tiling_index[0];
416 out->pitch_in_pixels = fmask.level[0].nblk_x;
417 out->bank_height = fmask.bankh;
418 out->alignment = MAX2(256, fmask.bo_alignment);
419 out->size = fmask.bo_size;
420 }
421
422 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
423 struct r600_texture *rtex)
424 {
425 r600_texture_get_fmask_info(rscreen, rtex,
426 rtex->resource.b.b.nr_samples, &rtex->fmask);
427
428 rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
429 rtex->size = rtex->fmask.offset + rtex->fmask.size;
430 }
431
432 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
433 struct r600_texture *rtex,
434 struct r600_cmask_info *out)
435 {
436 unsigned cmask_tile_width = 8;
437 unsigned cmask_tile_height = 8;
438 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
439 unsigned element_bits = 4;
440 unsigned cmask_cache_bits = 1024;
441 unsigned num_pipes = rscreen->info.num_tile_pipes;
442 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
443
444 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
445 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
446 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
447 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
448 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
449
450 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
451 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
452
453 unsigned base_align = num_pipes * pipe_interleave_bytes;
454 unsigned slice_bytes =
455 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
456
457 assert(macro_tile_width % 128 == 0);
458 assert(macro_tile_height % 128 == 0);
459
460 out->pitch = pitch_elements;
461 out->height = height;
462 out->xalign = macro_tile_width;
463 out->yalign = macro_tile_height;
464 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
465 out->alignment = MAX2(256, base_align);
466 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
467 align(slice_bytes, base_align);
468 }
469
470 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
471 struct r600_texture *rtex,
472 struct r600_cmask_info *out)
473 {
474 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
475 unsigned num_pipes = rscreen->info.num_tile_pipes;
476 unsigned cl_width, cl_height;
477
478 switch (num_pipes) {
479 case 2:
480 cl_width = 32;
481 cl_height = 16;
482 break;
483 case 4:
484 cl_width = 32;
485 cl_height = 32;
486 break;
487 case 8:
488 cl_width = 64;
489 cl_height = 32;
490 break;
491 case 16: /* Hawaii */
492 cl_width = 64;
493 cl_height = 64;
494 break;
495 default:
496 assert(0);
497 return;
498 }
499
500 unsigned base_align = num_pipes * pipe_interleave_bytes;
501
502 unsigned width = align(rtex->surface.npix_x, cl_width*8);
503 unsigned height = align(rtex->surface.npix_y, cl_height*8);
504 unsigned slice_elements = (width * height) / (8*8);
505
506 /* Each element of CMASK is a nibble. */
507 unsigned slice_bytes = slice_elements / 2;
508
509 out->pitch = width;
510 out->height = height;
511 out->xalign = cl_width * 8;
512 out->yalign = cl_height * 8;
513 out->slice_tile_max = (width * height) / (128*128);
514 if (out->slice_tile_max)
515 out->slice_tile_max -= 1;
516
517 out->alignment = MAX2(256, base_align);
518 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
519 align(slice_bytes, base_align);
520 }
521
522 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
523 struct r600_texture *rtex)
524 {
525 if (rscreen->chip_class >= SI) {
526 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
527 } else {
528 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
529 }
530
531 rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
532 rtex->size = rtex->cmask.offset + rtex->cmask.size;
533
534 if (rscreen->chip_class >= SI)
535 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
536 else
537 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
538 }
539
540 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
541 struct r600_texture *rtex)
542 {
543 if (rtex->cmask_buffer)
544 return;
545
546 assert(rtex->cmask.size == 0);
547
548 if (rscreen->chip_class >= SI) {
549 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
550 } else {
551 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
552 }
553
554 rtex->cmask_buffer = (struct r600_resource *)
555 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
556 PIPE_USAGE_DEFAULT, rtex->cmask.size);
557 if (rtex->cmask_buffer == NULL) {
558 rtex->cmask.size = 0;
559 return;
560 }
561
562 /* update colorbuffer state bits */
563 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
564
565 if (rscreen->chip_class >= SI)
566 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
567 else
568 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
569 }
570
571 static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
572 struct r600_texture *rtex)
573 {
574 unsigned cl_width, cl_height, width, height;
575 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
576 unsigned num_pipes = rscreen->info.num_tile_pipes;
577
578 if (rscreen->chip_class <= EVERGREEN &&
579 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
580 return 0;
581
582 /* HW bug on R6xx. */
583 if (rscreen->chip_class == R600 &&
584 (rtex->surface.level[0].npix_x > 7680 ||
585 rtex->surface.level[0].npix_y > 7680))
586 return 0;
587
588 /* HTILE is broken with 1D tiling on old kernels and CIK. */
589 if (rscreen->chip_class >= CIK &&
590 rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
591 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
592 return 0;
593
594 /* Overalign HTILE on Stoney to fix piglit/depthstencil-render-miplevels 585. */
595 if (rscreen->family == CHIP_STONEY)
596 num_pipes = 4;
597
598 switch (num_pipes) {
599 case 1:
600 cl_width = 32;
601 cl_height = 16;
602 break;
603 case 2:
604 cl_width = 32;
605 cl_height = 32;
606 break;
607 case 4:
608 cl_width = 64;
609 cl_height = 32;
610 break;
611 case 8:
612 cl_width = 64;
613 cl_height = 64;
614 break;
615 case 16:
616 cl_width = 128;
617 cl_height = 64;
618 break;
619 default:
620 assert(0);
621 return 0;
622 }
623
624 width = align(rtex->surface.npix_x, cl_width * 8);
625 height = align(rtex->surface.npix_y, cl_height * 8);
626
627 slice_elements = (width * height) / (8 * 8);
628 slice_bytes = slice_elements * 4;
629
630 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
631 base_align = num_pipes * pipe_interleave_bytes;
632
633 rtex->htile.pitch = width;
634 rtex->htile.height = height;
635 rtex->htile.xalign = cl_width * 8;
636 rtex->htile.yalign = cl_height * 8;
637
638 return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
639 align(slice_bytes, base_align);
640 }
641
642 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
643 struct r600_texture *rtex)
644 {
645 unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex);
646
647 if (!htile_size)
648 return;
649
650 rtex->htile_buffer = (struct r600_resource*)
651 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
652 PIPE_USAGE_DEFAULT, htile_size);
653 if (rtex->htile_buffer == NULL) {
654 /* this is not a fatal error as we can still keep rendering
655 * without htile buffer */
656 R600_ERR("Failed to create buffer object for htile buffer.\n");
657 } else {
658 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0,
659 htile_size, 0, true);
660 }
661 }
662
663 void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
664 {
665 int i;
666
667 fprintf(f, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
668 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
669 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
670 rtex->surface.npix_x, rtex->surface.npix_y,
671 rtex->surface.npix_z, rtex->surface.blk_w,
672 rtex->surface.blk_h, rtex->surface.blk_d,
673 rtex->surface.array_size, rtex->surface.last_level,
674 rtex->surface.bpe, rtex->surface.nsamples,
675 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
676
677 fprintf(f, " Layout: size=%"PRIu64", alignment=%"PRIu64", bankw=%u, "
678 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
679 rtex->surface.bo_size, rtex->surface.bo_alignment, rtex->surface.bankw,
680 rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
681 rtex->surface.tile_split, rtex->surface.pipe_config,
682 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
683
684 if (rtex->fmask.size)
685 fprintf(f, " FMask: offset=%u, size=%u, alignment=%u, pitch_in_pixels=%u, "
686 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
687 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
688 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
689 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
690
691 if (rtex->cmask.size)
692 fprintf(f, " CMask: offset=%u, size=%u, alignment=%u, pitch=%u, "
693 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
694 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
695 rtex->cmask.pitch, rtex->cmask.height, rtex->cmask.xalign,
696 rtex->cmask.yalign, rtex->cmask.slice_tile_max);
697
698 if (rtex->htile_buffer)
699 fprintf(f, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
700 "xalign=%u, yalign=%u\n",
701 rtex->htile_buffer->b.b.width0,
702 rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
703 rtex->htile.height, rtex->htile.xalign, rtex->htile.yalign);
704
705 if (rtex->dcc_offset) {
706 fprintf(f, " DCC: offset=%u, size=%"PRIu64", alignment=%"PRIu64"\n",
707 rtex->dcc_offset, rtex->surface.dcc_size,
708 rtex->surface.dcc_alignment);
709 for (i = 0; i <= rtex->surface.last_level; i++)
710 fprintf(f, " DCCLevel[%i]: offset=%"PRIu64"\n",
711 i, rtex->surface.level[i].dcc_offset);
712 }
713
714 for (i = 0; i <= rtex->surface.last_level; i++)
715 fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
716 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
717 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
718 i, rtex->surface.level[i].offset,
719 rtex->surface.level[i].slice_size,
720 u_minify(rtex->resource.b.b.width0, i),
721 u_minify(rtex->resource.b.b.height0, i),
722 u_minify(rtex->resource.b.b.depth0, i),
723 rtex->surface.level[i].nblk_x,
724 rtex->surface.level[i].nblk_y,
725 rtex->surface.level[i].nblk_z,
726 rtex->surface.level[i].pitch_bytes,
727 rtex->surface.level[i].mode);
728
729 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
730 for (i = 0; i <= rtex->surface.last_level; i++) {
731 fprintf(f, " StencilLayout: tilesplit=%u\n",
732 rtex->surface.stencil_tile_split);
733 fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
734 "slice_size=%"PRIu64", npix_x=%u, "
735 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
736 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
737 i, rtex->surface.stencil_level[i].offset,
738 rtex->surface.stencil_level[i].slice_size,
739 u_minify(rtex->resource.b.b.width0, i),
740 u_minify(rtex->resource.b.b.height0, i),
741 u_minify(rtex->resource.b.b.depth0, i),
742 rtex->surface.stencil_level[i].nblk_x,
743 rtex->surface.stencil_level[i].nblk_y,
744 rtex->surface.stencil_level[i].nblk_z,
745 rtex->surface.stencil_level[i].pitch_bytes,
746 rtex->surface.stencil_level[i].mode);
747 }
748 }
749 }
750
751 /* Common processing for r600_texture_create and r600_texture_from_handle */
752 static struct r600_texture *
753 r600_texture_create_object(struct pipe_screen *screen,
754 const struct pipe_resource *base,
755 unsigned pitch_in_bytes_override,
756 struct pb_buffer *buf,
757 struct radeon_surf *surface)
758 {
759 struct r600_texture *rtex;
760 struct r600_resource *resource;
761 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
762
763 rtex = CALLOC_STRUCT(r600_texture);
764 if (!rtex)
765 return NULL;
766
767 resource = &rtex->resource;
768 resource->b.b = *base;
769 resource->b.vtbl = &r600_texture_vtbl;
770 pipe_reference_init(&resource->b.b.reference, 1);
771 resource->b.b.screen = screen;
772
773 /* don't include stencil-only formats which we don't support for rendering */
774 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
775
776 rtex->surface = *surface;
777 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override)) {
778 FREE(rtex);
779 return NULL;
780 }
781
782 /* Tiled depth textures utilize the non-displayable tile order.
783 * This must be done after r600_setup_surface.
784 * Applies to R600-Cayman. */
785 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
786
787 if (rtex->is_depth) {
788 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
789 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
790 !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
791
792 r600_texture_allocate_htile(rscreen, rtex);
793 }
794 } else {
795 if (base->nr_samples > 1) {
796 if (!buf) {
797 r600_texture_allocate_fmask(rscreen, rtex);
798 r600_texture_allocate_cmask(rscreen, rtex);
799 rtex->cmask_buffer = &rtex->resource;
800 }
801 if (!rtex->fmask.size || !rtex->cmask.size) {
802 FREE(rtex);
803 return NULL;
804 }
805 }
806
807 if (!buf && rtex->surface.dcc_size &&
808 !(rscreen->debug_flags & DBG_NO_DCC)) {
809 /* Reserve space for the DCC buffer. */
810 rtex->dcc_offset = align(rtex->size, rtex->surface.dcc_alignment);
811 rtex->size = rtex->dcc_offset + rtex->surface.dcc_size;
812 rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
813 }
814 }
815
816 /* Now create the backing buffer. */
817 if (!buf) {
818 if (!r600_init_resource(rscreen, resource, rtex->size,
819 rtex->surface.bo_alignment, TRUE)) {
820 FREE(rtex);
821 return NULL;
822 }
823 } else {
824 resource->buf = buf;
825 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
826 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
827 }
828
829 if (rtex->cmask.size) {
830 /* Initialize the cmask to 0xCC (= compressed state). */
831 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
832 rtex->cmask.offset, rtex->cmask.size,
833 0xCCCCCCCC, true);
834 }
835 if (rtex->dcc_offset) {
836 r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
837 rtex->dcc_offset,
838 rtex->surface.dcc_size,
839 0xFFFFFFFF, true);
840 }
841
842 /* Initialize the CMASK base register value. */
843 rtex->cmask.base_address_reg =
844 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
845
846 if (rscreen->debug_flags & DBG_VM) {
847 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
848 rtex->resource.gpu_address,
849 rtex->resource.gpu_address + rtex->resource.buf->size,
850 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
851 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
852 }
853
854 if (rscreen->debug_flags & DBG_TEX) {
855 puts("Texture:");
856 r600_print_texture_info(rtex, stdout);
857 }
858
859 return rtex;
860 }
861
862 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
863 const struct pipe_resource *templ)
864 {
865 const struct util_format_description *desc = util_format_description(templ->format);
866 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
867
868 /* MSAA resources must be 2D tiled. */
869 if (templ->nr_samples > 1)
870 return RADEON_SURF_MODE_2D;
871
872 /* Transfer resources should be linear. */
873 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
874 return RADEON_SURF_MODE_LINEAR_ALIGNED;
875
876 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
877 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
878 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
879 (templ->target == PIPE_TEXTURE_2D ||
880 templ->target == PIPE_TEXTURE_3D))
881 force_tiling = true;
882
883 /* Handle common candidates for the linear mode.
884 * Compressed textures must always be tiled. */
885 if (!force_tiling && !util_format_is_compressed(templ->format)) {
886 /* Not everything can be linear, so we cannot enforce it
887 * for all textures. */
888 if ((rscreen->debug_flags & DBG_NO_TILING) &&
889 (!util_format_is_depth_or_stencil(templ->format) ||
890 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH)))
891 return RADEON_SURF_MODE_LINEAR_ALIGNED;
892
893 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
894 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
895 return RADEON_SURF_MODE_LINEAR_ALIGNED;
896
897 /* Cursors are linear on SI.
898 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
899 if (rscreen->chip_class >= SI &&
900 (templ->bind & PIPE_BIND_CURSOR))
901 return RADEON_SURF_MODE_LINEAR_ALIGNED;
902
903 if (templ->bind & PIPE_BIND_LINEAR)
904 return RADEON_SURF_MODE_LINEAR_ALIGNED;
905
906 /* Textures with a very small height are recommended to be linear. */
907 if (templ->target == PIPE_TEXTURE_1D ||
908 templ->target == PIPE_TEXTURE_1D_ARRAY ||
909 templ->height0 <= 4)
910 return RADEON_SURF_MODE_LINEAR_ALIGNED;
911
912 /* Textures likely to be mapped often. */
913 if (templ->usage == PIPE_USAGE_STAGING ||
914 templ->usage == PIPE_USAGE_STREAM)
915 return RADEON_SURF_MODE_LINEAR_ALIGNED;
916 }
917
918 /* Make small textures 1D tiled. */
919 if (templ->width0 <= 16 || templ->height0 <= 16 ||
920 (rscreen->debug_flags & DBG_NO_2D_TILING))
921 return RADEON_SURF_MODE_1D;
922
923 /* The allocator will switch to 1D if needed. */
924 return RADEON_SURF_MODE_2D;
925 }
926
927 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
928 const struct pipe_resource *templ)
929 {
930 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
931 struct radeon_surf surface = {0};
932 int r;
933
934 r = r600_init_surface(rscreen, &surface, templ,
935 r600_choose_tiling(rscreen, templ),
936 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
937 if (r) {
938 return NULL;
939 }
940 r = rscreen->ws->surface_best(rscreen->ws, &surface);
941 if (r) {
942 return NULL;
943 }
944 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
945 0, NULL, &surface);
946 }
947
948 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
949 const struct pipe_resource *templ,
950 struct winsys_handle *whandle,
951 unsigned usage)
952 {
953 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
954 struct pb_buffer *buf = NULL;
955 unsigned stride = 0;
956 unsigned array_mode;
957 struct radeon_surf surface;
958 int r;
959 struct radeon_bo_metadata metadata = {};
960 struct r600_texture *rtex;
961
962 /* Support only 2D textures without mipmaps */
963 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
964 templ->depth0 != 1 || templ->last_level != 0)
965 return NULL;
966
967 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
968 if (!buf)
969 return NULL;
970
971 rscreen->ws->buffer_get_metadata(buf, &metadata);
972
973 surface.bankw = metadata.bankw;
974 surface.bankh = metadata.bankh;
975 surface.tile_split = metadata.tile_split;
976 surface.stencil_tile_split = metadata.stencil_tile_split;
977 surface.mtilea = metadata.mtilea;
978
979 if (metadata.macrotile == RADEON_LAYOUT_TILED)
980 array_mode = RADEON_SURF_MODE_2D;
981 else if (metadata.microtile == RADEON_LAYOUT_TILED)
982 array_mode = RADEON_SURF_MODE_1D;
983 else
984 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
985
986 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
987 if (r) {
988 return NULL;
989 }
990
991 if (metadata.scanout)
992 surface.flags |= RADEON_SURF_SCANOUT;
993
994 rtex = r600_texture_create_object(screen, templ,
995 stride, buf, &surface);
996 if (!rtex)
997 return NULL;
998
999 rtex->resource.is_shared = true;
1000 rtex->resource.external_usage = usage;
1001 return &rtex->resource.b.b;
1002 }
1003
1004 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
1005 struct pipe_resource *texture,
1006 struct r600_texture **staging)
1007 {
1008 struct r600_texture *rtex = (struct r600_texture*)texture;
1009 struct pipe_resource resource;
1010 struct r600_texture **flushed_depth_texture = staging ?
1011 staging : &rtex->flushed_depth_texture;
1012
1013 if (!staging && rtex->flushed_depth_texture)
1014 return true; /* it's ready */
1015
1016 resource.target = texture->target;
1017 resource.format = texture->format;
1018 resource.width0 = texture->width0;
1019 resource.height0 = texture->height0;
1020 resource.depth0 = texture->depth0;
1021 resource.array_size = texture->array_size;
1022 resource.last_level = texture->last_level;
1023 resource.nr_samples = texture->nr_samples;
1024 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1025 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
1026 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1027
1028 if (staging)
1029 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
1030
1031 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
1032 if (*flushed_depth_texture == NULL) {
1033 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1034 return false;
1035 }
1036
1037 (*flushed_depth_texture)->is_flushing_texture = TRUE;
1038 (*flushed_depth_texture)->non_disp_tiling = false;
1039 return true;
1040 }
1041
1042 /**
1043 * Initialize the pipe_resource descriptor to be of the same size as the box,
1044 * which is supposed to hold a subregion of the texture "orig" at the given
1045 * mipmap level.
1046 */
1047 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
1048 struct pipe_resource *orig,
1049 const struct pipe_box *box,
1050 unsigned level, unsigned flags)
1051 {
1052 memset(res, 0, sizeof(*res));
1053 res->format = orig->format;
1054 res->width0 = box->width;
1055 res->height0 = box->height;
1056 res->depth0 = 1;
1057 res->array_size = 1;
1058 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1059 res->flags = flags;
1060
1061 /* We must set the correct texture target and dimensions for a 3D box. */
1062 if (box->depth > 1 && util_max_layer(orig, level) > 0)
1063 res->target = orig->target;
1064 else
1065 res->target = PIPE_TEXTURE_2D;
1066
1067 switch (res->target) {
1068 case PIPE_TEXTURE_1D_ARRAY:
1069 case PIPE_TEXTURE_2D_ARRAY:
1070 case PIPE_TEXTURE_CUBE_ARRAY:
1071 res->array_size = box->depth;
1072 break;
1073 case PIPE_TEXTURE_3D:
1074 res->depth0 = box->depth;
1075 break;
1076 default:;
1077 }
1078 }
1079
1080 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1081 struct pipe_resource *texture,
1082 unsigned level,
1083 unsigned usage,
1084 const struct pipe_box *box,
1085 struct pipe_transfer **ptransfer)
1086 {
1087 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1088 struct r600_texture *rtex = (struct r600_texture*)texture;
1089 struct r600_transfer *trans;
1090 boolean use_staging_texture = FALSE;
1091 struct r600_resource *buf;
1092 unsigned offset = 0;
1093 char *map;
1094
1095 /* We cannot map a tiled texture directly because the data is
1096 * in a different order, therefore we do detiling using a blit.
1097 *
1098 * Also, use a temporary in GTT memory for read transfers, as
1099 * the CPU is much happier reading out of cached system memory
1100 * than uncached VRAM.
1101 */
1102 if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
1103 use_staging_texture = TRUE;
1104 } else if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
1105 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
1106 /* Untiled buffers in VRAM, which is slow for CPU reads */
1107 use_staging_texture = TRUE;
1108 } else if (!(usage & PIPE_TRANSFER_READ) &&
1109 (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf, RADEON_USAGE_READWRITE) ||
1110 !rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) {
1111 /* Use a staging texture for uploads if the underlying BO is busy. */
1112 use_staging_texture = TRUE;
1113 }
1114
1115 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
1116 use_staging_texture = FALSE;
1117 }
1118
1119 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
1120 return NULL;
1121 }
1122
1123 trans = CALLOC_STRUCT(r600_transfer);
1124 if (!trans)
1125 return NULL;
1126 trans->transfer.resource = texture;
1127 trans->transfer.level = level;
1128 trans->transfer.usage = usage;
1129 trans->transfer.box = *box;
1130
1131 if (rtex->is_depth) {
1132 struct r600_texture *staging_depth;
1133
1134 if (rtex->resource.b.b.nr_samples > 1) {
1135 /* MSAA depth buffers need to be converted to single sample buffers.
1136 *
1137 * Mapping MSAA depth buffers can occur if ReadPixels is called
1138 * with a multisample GLX visual.
1139 *
1140 * First downsample the depth buffer to a temporary texture,
1141 * then decompress the temporary one to staging.
1142 *
1143 * Only the region being mapped is transfered.
1144 */
1145 struct pipe_resource resource;
1146
1147 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1148
1149 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1150 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1151 FREE(trans);
1152 return NULL;
1153 }
1154
1155 if (usage & PIPE_TRANSFER_READ) {
1156 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1157 if (!temp) {
1158 R600_ERR("failed to create a temporary depth texture\n");
1159 FREE(trans);
1160 return NULL;
1161 }
1162
1163 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1164 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1165 0, 0, 0, box->depth, 0, 0);
1166 pipe_resource_reference(&temp, NULL);
1167 }
1168 }
1169 else {
1170 /* XXX: only readback the rectangle which is being mapped? */
1171 /* XXX: when discard is true, no need to read back from depth texture */
1172 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1173 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1174 FREE(trans);
1175 return NULL;
1176 }
1177
1178 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1179 level, level,
1180 box->z, box->z + box->depth - 1,
1181 0, 0);
1182
1183 offset = r600_texture_get_offset(staging_depth, level, box);
1184 }
1185
1186 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
1187 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1188 trans->staging = (struct r600_resource*)staging_depth;
1189 } else if (use_staging_texture) {
1190 struct pipe_resource resource;
1191 struct r600_texture *staging;
1192
1193 r600_init_temp_resource_from_box(&resource, texture, box, level,
1194 R600_RESOURCE_FLAG_TRANSFER);
1195 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1196 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1197
1198 /* Create the temporary texture. */
1199 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1200 if (!staging) {
1201 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1202 FREE(trans);
1203 return NULL;
1204 }
1205 trans->staging = &staging->resource;
1206 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1207 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1208 if (usage & PIPE_TRANSFER_READ) {
1209 r600_copy_to_staging_texture(ctx, trans);
1210 }
1211 } else {
1212 /* the resource is mapped directly */
1213 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1214 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1215 offset = r600_texture_get_offset(rtex, level, box);
1216 }
1217
1218 if (trans->staging) {
1219 buf = trans->staging;
1220 if (!rtex->is_depth && !(usage & PIPE_TRANSFER_READ))
1221 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1222 } else {
1223 buf = &rtex->resource;
1224 }
1225
1226 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1227 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1228 FREE(trans);
1229 return NULL;
1230 }
1231
1232 *ptransfer = &trans->transfer;
1233 return map + offset;
1234 }
1235
1236 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1237 struct pipe_transfer* transfer)
1238 {
1239 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1240 struct pipe_resource *texture = transfer->resource;
1241 struct r600_texture *rtex = (struct r600_texture*)texture;
1242
1243 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1244 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1245 ctx->resource_copy_region(ctx, texture, transfer->level,
1246 transfer->box.x, transfer->box.y, transfer->box.z,
1247 &rtransfer->staging->b.b, transfer->level,
1248 &transfer->box);
1249 } else {
1250 r600_copy_from_staging_texture(ctx, rtransfer);
1251 }
1252 }
1253
1254 if (rtransfer->staging)
1255 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1256
1257 FREE(transfer);
1258 }
1259
1260 static const struct u_resource_vtbl r600_texture_vtbl =
1261 {
1262 NULL, /* get_handle */
1263 r600_texture_destroy, /* resource_destroy */
1264 r600_texture_transfer_map, /* transfer_map */
1265 u_default_transfer_flush_region, /* transfer_flush_region */
1266 r600_texture_transfer_unmap, /* transfer_unmap */
1267 NULL /* transfer_inline_write */
1268 };
1269
1270 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1271 struct pipe_resource *texture,
1272 const struct pipe_surface *templ,
1273 unsigned width, unsigned height)
1274 {
1275 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1276
1277 if (!surface)
1278 return NULL;
1279
1280 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1281 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1282
1283 pipe_reference_init(&surface->base.reference, 1);
1284 pipe_resource_reference(&surface->base.texture, texture);
1285 surface->base.context = pipe;
1286 surface->base.format = templ->format;
1287 surface->base.width = width;
1288 surface->base.height = height;
1289 surface->base.u = templ->u;
1290 return &surface->base;
1291 }
1292
1293 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1294 struct pipe_resource *tex,
1295 const struct pipe_surface *templ)
1296 {
1297 unsigned level = templ->u.tex.level;
1298 unsigned width = u_minify(tex->width0, level);
1299 unsigned height = u_minify(tex->height0, level);
1300
1301 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1302 const struct util_format_description *tex_desc
1303 = util_format_description(tex->format);
1304 const struct util_format_description *templ_desc
1305 = util_format_description(templ->format);
1306
1307 assert(tex_desc->block.bits == templ_desc->block.bits);
1308
1309 /* Adjust size of surface if and only if the block width or
1310 * height is changed. */
1311 if (tex_desc->block.width != templ_desc->block.width ||
1312 tex_desc->block.height != templ_desc->block.height) {
1313 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1314 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1315
1316 width = nblks_x * templ_desc->block.width;
1317 height = nblks_y * templ_desc->block.height;
1318 }
1319 }
1320
1321 return r600_create_surface_custom(pipe, tex, templ, width, height);
1322 }
1323
1324 static void r600_surface_destroy(struct pipe_context *pipe,
1325 struct pipe_surface *surface)
1326 {
1327 struct r600_surface *surf = (struct r600_surface*)surface;
1328 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1329 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1330 pipe_resource_reference(&surface->texture, NULL);
1331 FREE(surface);
1332 }
1333
1334 unsigned r600_translate_colorswap(enum pipe_format format)
1335 {
1336 const struct util_format_description *desc = util_format_description(format);
1337
1338 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1339
1340 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1341 return V_0280A0_SWAP_STD;
1342
1343 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1344 return ~0U;
1345
1346 switch (desc->nr_channels) {
1347 case 1:
1348 if (HAS_SWIZZLE(0,X))
1349 return V_0280A0_SWAP_STD; /* X___ */
1350 else if (HAS_SWIZZLE(3,X))
1351 return V_0280A0_SWAP_ALT_REV; /* ___X */
1352 break;
1353 case 2:
1354 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1355 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1356 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1357 return V_0280A0_SWAP_STD; /* XY__ */
1358 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1359 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1360 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1361 return V_0280A0_SWAP_STD_REV; /* YX__ */
1362 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1363 return V_0280A0_SWAP_ALT; /* X__Y */
1364 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1365 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1366 break;
1367 case 3:
1368 if (HAS_SWIZZLE(0,X))
1369 return V_0280A0_SWAP_STD; /* XYZ */
1370 else if (HAS_SWIZZLE(0,Z))
1371 return V_0280A0_SWAP_STD_REV; /* ZYX */
1372 break;
1373 case 4:
1374 /* check the middle channels, the 1st and 4th channel can be NONE */
1375 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
1376 return V_0280A0_SWAP_STD; /* XYZW */
1377 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
1378 return V_0280A0_SWAP_STD_REV; /* WZYX */
1379 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
1380 return V_0280A0_SWAP_ALT; /* ZYXW */
1381 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W))
1382 return V_0280A0_SWAP_ALT_REV; /* YZWX */
1383 break;
1384 }
1385 return ~0U;
1386 }
1387
1388 static void evergreen_set_clear_color(struct r600_texture *rtex,
1389 enum pipe_format surface_format,
1390 const union pipe_color_union *color)
1391 {
1392 union util_color uc;
1393
1394 memset(&uc, 0, sizeof(uc));
1395
1396 if (util_format_is_pure_uint(surface_format)) {
1397 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1398 } else if (util_format_is_pure_sint(surface_format)) {
1399 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1400 } else {
1401 util_pack_color(color->f, surface_format, &uc);
1402 }
1403
1404 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1405 }
1406
1407 static void vi_get_fast_clear_parameters(enum pipe_format surface_format,
1408 const union pipe_color_union *color,
1409 uint32_t* reset_value,
1410 bool* clear_words_needed)
1411 {
1412 bool values[4] = {};
1413 int i;
1414 bool main_value = false;
1415 bool extra_value = false;
1416 int extra_channel;
1417 const struct util_format_description *desc = util_format_description(surface_format);
1418
1419 *clear_words_needed = true;
1420 *reset_value = 0x20202020U;
1421
1422 /* If we want to clear without needing a fast clear eliminate step, we
1423 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1424 * have two sets of flags, one for the last or first channel(extra) and
1425 * one for the other channels(main).
1426 */
1427
1428 if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
1429 surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
1430 surface_format == PIPE_FORMAT_B5G6R5_SRGB) {
1431 extra_channel = -1;
1432 } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
1433 if(r600_translate_colorswap(surface_format) <= 1)
1434 extra_channel = desc->nr_channels - 1;
1435 else
1436 extra_channel = 0;
1437 } else
1438 return;
1439
1440 for (i = 0; i < 4; ++i) {
1441 int index = desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X;
1442
1443 if (desc->swizzle[i] < UTIL_FORMAT_SWIZZLE_X ||
1444 desc->swizzle[i] > UTIL_FORMAT_SWIZZLE_W)
1445 continue;
1446
1447 if (util_format_is_pure_sint(surface_format)) {
1448 values[i] = color->i[i] != 0;
1449 if (color->i[i] != 0 && color->i[i] != INT32_MAX)
1450 return;
1451 } else if (util_format_is_pure_uint(surface_format)) {
1452 values[i] = color->ui[i] != 0U;
1453 if (color->ui[i] != 0U && color->ui[i] != UINT32_MAX)
1454 return;
1455 } else {
1456 values[i] = color->f[i] != 0.0F;
1457 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
1458 return;
1459 }
1460
1461 if (index == extra_channel)
1462 extra_value = values[i];
1463 else
1464 main_value = values[i];
1465 }
1466
1467 for (int i = 0; i < 4; ++i)
1468 if (values[i] != main_value &&
1469 desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X != extra_channel &&
1470 desc->swizzle[i] >= UTIL_FORMAT_SWIZZLE_X &&
1471 desc->swizzle[i] <= UTIL_FORMAT_SWIZZLE_W)
1472 return;
1473
1474 *clear_words_needed = false;
1475 if (main_value)
1476 *reset_value |= 0x80808080U;
1477
1478 if (extra_value)
1479 *reset_value |= 0x40404040U;
1480 }
1481
1482 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1483 struct pipe_framebuffer_state *fb,
1484 struct r600_atom *fb_state,
1485 unsigned *buffers, unsigned *dirty_cbufs,
1486 const union pipe_color_union *color)
1487 {
1488 int i;
1489
1490 /* This function is broken in BE, so just disable this path for now */
1491 #ifdef PIPE_ARCH_BIG_ENDIAN
1492 return;
1493 #endif
1494
1495 if (rctx->render_cond)
1496 return;
1497
1498 for (i = 0; i < fb->nr_cbufs; i++) {
1499 struct r600_texture *tex;
1500 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1501
1502 if (!fb->cbufs[i])
1503 continue;
1504
1505 /* if this colorbuffer is not being cleared */
1506 if (!(*buffers & clear_bit))
1507 continue;
1508
1509 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1510
1511 /* 128-bit formats are unusupported */
1512 if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
1513 continue;
1514 }
1515
1516 /* the clear is allowed if all layers are bound */
1517 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1518 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1519 continue;
1520 }
1521
1522 /* cannot clear mipmapped textures */
1523 if (fb->cbufs[i]->texture->last_level != 0) {
1524 continue;
1525 }
1526
1527 /* only supported on tiled surfaces */
1528 if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
1529 continue;
1530 }
1531
1532 /* shared textures can't use fast clear without an explicit flush,
1533 * because there is no way to communicate the clear color among
1534 * all clients
1535 */
1536 if (tex->resource.is_shared &&
1537 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
1538 continue;
1539
1540 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1541 if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
1542 rctx->chip_class >= CIK &&
1543 rctx->screen->info.drm_major == 2 &&
1544 rctx->screen->info.drm_minor < 38) {
1545 continue;
1546 }
1547
1548 if (tex->dcc_offset) {
1549 uint32_t reset_value;
1550 bool clear_words_needed;
1551
1552 if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
1553 continue;
1554
1555 vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed);
1556
1557 rctx->clear_buffer(&rctx->b, &tex->resource.b.b,
1558 tex->dcc_offset, tex->surface.dcc_size,
1559 reset_value, true);
1560
1561 if (clear_words_needed)
1562 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1563 } else {
1564 /* Stoney/RB+ doesn't work with CMASK fast clear. */
1565 if (rctx->family == CHIP_STONEY)
1566 continue;
1567
1568 /* ensure CMASK is enabled */
1569 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1570 if (tex->cmask.size == 0) {
1571 continue;
1572 }
1573
1574 /* Do the fast clear. */
1575 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1576 tex->cmask.offset, tex->cmask.size, 0, true);
1577
1578 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1579 }
1580
1581 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1582
1583 if (dirty_cbufs)
1584 *dirty_cbufs |= 1 << i;
1585 rctx->set_atom_dirty(rctx, fb_state, true);
1586 *buffers &= ~clear_bit;
1587 }
1588 }
1589
1590 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1591 {
1592 rscreen->b.resource_from_handle = r600_texture_from_handle;
1593 rscreen->b.resource_get_handle = r600_texture_get_handle;
1594 }
1595
1596 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1597 {
1598 rctx->b.create_surface = r600_create_surface;
1599 rctx->b.surface_destroy = r600_surface_destroy;
1600 }