2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_pipe_common.h"
25 #include "r600_query.h"
26 #include "util/u_format.h"
27 #include "util/u_log.h"
28 #include "util/u_memory.h"
29 #include "util/u_pack_color.h"
30 #include "util/u_surface.h"
31 #include "util/os_time.h"
34 #include "state_tracker/drm_driver.h"
35 #include "amd/common/sid.h"
37 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
38 struct r600_texture
*rtex
);
39 static enum radeon_surf_mode
40 r600_choose_tiling(struct r600_common_screen
*rscreen
,
41 const struct pipe_resource
*templ
);
44 bool si_prepare_for_dma_blit(struct r600_common_context
*rctx
,
45 struct r600_texture
*rdst
,
46 unsigned dst_level
, unsigned dstx
,
47 unsigned dsty
, unsigned dstz
,
48 struct r600_texture
*rsrc
,
50 const struct pipe_box
*src_box
)
55 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
58 /* MSAA: Blits don't exist in the real world. */
59 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
60 rdst
->resource
.b
.b
.nr_samples
> 1)
63 /* Depth-stencil surfaces:
64 * When dst is linear, the DB->CB copy preserves HTILE.
65 * When dst is tiled, the 3D path must be used to update HTILE.
67 if (rsrc
->is_depth
|| rdst
->is_depth
)
71 * src: Use the 3D path. DCC decompression is expensive.
72 * dst: Use the 3D path to compress the pixels with DCC.
74 if (vi_dcc_enabled(rsrc
, src_level
) ||
75 vi_dcc_enabled(rdst
, dst_level
))
79 * src: Both texture and SDMA paths need decompression. Use SDMA.
80 * dst: If overwriting the whole texture, discard CMASK and use
81 * SDMA. Otherwise, use the 3D path.
83 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
84 /* The CMASK clear is only enabled for the first level. */
85 assert(dst_level
== 0);
86 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
87 dstx
, dsty
, dstz
, src_box
->width
,
88 src_box
->height
, src_box
->depth
))
91 r600_texture_discard_cmask(rctx
->screen
, rdst
);
94 /* All requirements are met. Prepare textures for SDMA. */
95 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
96 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
98 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
99 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
104 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
105 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
106 struct pipe_resource
*dst
,
108 unsigned dstx
, unsigned dsty
, unsigned dstz
,
109 struct pipe_resource
*src
,
111 const struct pipe_box
*src_box
)
113 struct pipe_blit_info blit
;
115 memset(&blit
, 0, sizeof(blit
));
116 blit
.src
.resource
= src
;
117 blit
.src
.format
= src
->format
;
118 blit
.src
.level
= src_level
;
119 blit
.src
.box
= *src_box
;
120 blit
.dst
.resource
= dst
;
121 blit
.dst
.format
= dst
->format
;
122 blit
.dst
.level
= dst_level
;
123 blit
.dst
.box
.x
= dstx
;
124 blit
.dst
.box
.y
= dsty
;
125 blit
.dst
.box
.z
= dstz
;
126 blit
.dst
.box
.width
= src_box
->width
;
127 blit
.dst
.box
.height
= src_box
->height
;
128 blit
.dst
.box
.depth
= src_box
->depth
;
129 blit
.mask
= util_format_get_mask(src
->format
) &
130 util_format_get_mask(dst
->format
);
131 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
134 pipe
->blit(pipe
, &blit
);
138 /* Copy from a full GPU texture to a transfer's staging one. */
139 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
141 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
142 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
143 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
144 struct pipe_resource
*src
= transfer
->resource
;
146 if (src
->nr_samples
> 1) {
147 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
148 src
, transfer
->level
, &transfer
->box
);
152 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
156 /* Copy from a transfer's staging texture to a full GPU one. */
157 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
159 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
160 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
161 struct pipe_resource
*dst
= transfer
->resource
;
162 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
163 struct pipe_box sbox
;
165 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
167 if (dst
->nr_samples
> 1) {
168 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
169 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
174 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
175 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
179 static unsigned r600_texture_get_offset(struct r600_common_screen
*rscreen
,
180 struct r600_texture
*rtex
, unsigned level
,
181 const struct pipe_box
*box
,
183 unsigned *layer_stride
)
185 if (rscreen
->chip_class
>= GFX9
) {
186 *stride
= rtex
->surface
.u
.gfx9
.surf_pitch
* rtex
->surface
.bpe
;
187 *layer_stride
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
192 /* Each texture is an array of slices. Each slice is an array
193 * of mipmap levels. */
194 return box
->z
* rtex
->surface
.u
.gfx9
.surf_slice_size
+
195 rtex
->surface
.u
.gfx9
.offset
[level
] +
196 (box
->y
/ rtex
->surface
.blk_h
*
197 rtex
->surface
.u
.gfx9
.surf_pitch
+
198 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
200 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
202 *layer_stride
= rtex
->surface
.u
.legacy
.level
[level
].slice_size
;
205 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
207 /* Each texture is an array of mipmap levels. Each level is
208 * an array of slices. */
209 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
210 box
->z
* rtex
->surface
.u
.legacy
.level
[level
].slice_size
+
211 (box
->y
/ rtex
->surface
.blk_h
*
212 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
213 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
217 static int r600_init_surface(struct r600_common_screen
*rscreen
,
218 struct radeon_surf
*surface
,
219 const struct pipe_resource
*ptex
,
220 enum radeon_surf_mode array_mode
,
221 unsigned pitch_in_bytes_override
,
225 bool is_flushed_depth
,
226 bool tc_compatible_htile
)
228 const struct util_format_description
*desc
=
229 util_format_description(ptex
->format
);
230 bool is_depth
, is_stencil
;
232 unsigned i
, bpe
, flags
= 0;
234 is_depth
= util_format_has_depth(desc
);
235 is_stencil
= util_format_has_stencil(desc
);
237 if (!is_flushed_depth
&&
238 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
239 bpe
= 4; /* stencil is allocated separately on evergreen */
241 bpe
= util_format_get_blocksize(ptex
->format
);
242 assert(util_is_power_of_two(bpe
));
245 if (!is_flushed_depth
&& is_depth
) {
246 flags
|= RADEON_SURF_ZBUFFER
;
248 if (tc_compatible_htile
&&
249 (rscreen
->chip_class
>= GFX9
||
250 array_mode
== RADEON_SURF_MODE_2D
)) {
251 /* TC-compatible HTILE only supports Z32_FLOAT.
252 * GFX9 also supports Z16_UNORM.
253 * On VI, promote Z16 to Z32. DB->CB copies will convert
254 * the format for transfers.
256 if (rscreen
->chip_class
== VI
)
259 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
263 flags
|= RADEON_SURF_SBUFFER
;
266 if (rscreen
->chip_class
>= VI
&&
267 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
268 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
269 flags
|= RADEON_SURF_DISABLE_DCC
;
271 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
272 /* This should catch bugs in gallium users setting incorrect flags. */
273 assert(ptex
->nr_samples
<= 1 &&
274 ptex
->array_size
== 1 &&
276 ptex
->last_level
== 0 &&
277 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
279 flags
|= RADEON_SURF_SCANOUT
;
282 if (ptex
->bind
& PIPE_BIND_SHARED
)
283 flags
|= RADEON_SURF_SHAREABLE
;
285 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
286 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
287 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
289 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
290 array_mode
, surface
);
295 if (rscreen
->chip_class
>= GFX9
) {
296 assert(!pitch_in_bytes_override
||
297 pitch_in_bytes_override
== surface
->u
.gfx9
.surf_pitch
* bpe
);
298 surface
->u
.gfx9
.surf_offset
= offset
;
300 if (pitch_in_bytes_override
&&
301 pitch_in_bytes_override
!= surface
->u
.legacy
.level
[0].nblk_x
* bpe
) {
302 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
305 surface
->u
.legacy
.level
[0].nblk_x
= pitch_in_bytes_override
/ bpe
;
306 surface
->u
.legacy
.level
[0].slice_size
= pitch_in_bytes_override
*
307 surface
->u
.legacy
.level
[0].nblk_y
;
311 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
312 surface
->u
.legacy
.level
[i
].offset
+= offset
;
318 static void r600_texture_init_metadata(struct r600_common_screen
*rscreen
,
319 struct r600_texture
*rtex
,
320 struct radeon_bo_metadata
*metadata
)
322 struct radeon_surf
*surface
= &rtex
->surface
;
324 memset(metadata
, 0, sizeof(*metadata
));
326 if (rscreen
->chip_class
>= GFX9
) {
327 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
329 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
330 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
331 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
332 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
333 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
334 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
335 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
336 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
337 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
338 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
339 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
340 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
344 static void r600_surface_import_metadata(struct r600_common_screen
*rscreen
,
345 struct radeon_surf
*surf
,
346 struct radeon_bo_metadata
*metadata
,
347 enum radeon_surf_mode
*array_mode
,
350 if (rscreen
->chip_class
>= GFX9
) {
351 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
352 *array_mode
= RADEON_SURF_MODE_2D
;
354 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
356 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
357 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
359 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
361 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
362 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
363 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
364 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
365 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
366 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
368 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
369 *array_mode
= RADEON_SURF_MODE_2D
;
370 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
371 *array_mode
= RADEON_SURF_MODE_1D
;
373 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
375 *is_scanout
= metadata
->u
.legacy
.scanout
;
379 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
380 struct r600_texture
*rtex
)
382 struct r600_common_screen
*rscreen
= rctx
->screen
;
383 struct pipe_context
*ctx
= &rctx
->b
;
385 if (ctx
== rscreen
->aux_context
)
386 mtx_lock(&rscreen
->aux_context_lock
);
388 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
389 ctx
->flush(ctx
, NULL
, 0);
391 if (ctx
== rscreen
->aux_context
)
392 mtx_unlock(&rscreen
->aux_context_lock
);
395 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
396 struct r600_texture
*rtex
)
398 if (!rtex
->cmask
.size
)
401 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
404 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
405 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
406 rtex
->dirty_level_mask
= 0;
408 rtex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
410 if (rtex
->cmask_buffer
!= &rtex
->resource
)
411 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
413 /* Notify all contexts about the change. */
414 p_atomic_inc(&rscreen
->dirty_tex_counter
);
415 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
418 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
420 /* We can't disable DCC if it can be written by another process. */
421 return rtex
->dcc_offset
&&
422 (!rtex
->resource
.b
.is_shared
||
423 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
426 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
427 struct r600_texture
*rtex
)
429 if (!r600_can_disable_dcc(rtex
))
432 assert(rtex
->dcc_separate_buffer
== NULL
);
435 rtex
->dcc_offset
= 0;
437 /* Notify all contexts about the change. */
438 p_atomic_inc(&rscreen
->dirty_tex_counter
);
443 * Disable DCC for the texture. (first decompress, then discard metadata).
445 * There is unresolved multi-context synchronization issue between
446 * screen::aux_context and the current context. If applications do this with
447 * multiple contexts, it's already undefined behavior for them and we don't
448 * have to worry about that. The scenario is:
450 * If context 1 disables DCC and context 2 has queued commands that write
451 * to the texture via CB with DCC enabled, and the order of operations is
453 * context 2 queues draw calls rendering to the texture, but doesn't flush
454 * context 1 disables DCC and flushes
455 * context 1 & 2 reset descriptors and FB state
456 * context 2 flushes (new compressed tiles written by the draw calls)
457 * context 1 & 2 read garbage, because DCC is disabled, yet there are
460 * \param rctx the current context if you have one, or rscreen->aux_context
463 bool si_texture_disable_dcc(struct r600_common_context
*rctx
,
464 struct r600_texture
*rtex
)
466 struct r600_common_screen
*rscreen
= rctx
->screen
;
468 if (!r600_can_disable_dcc(rtex
))
471 if (&rctx
->b
== rscreen
->aux_context
)
472 mtx_lock(&rscreen
->aux_context_lock
);
474 /* Decompress DCC. */
475 rctx
->decompress_dcc(&rctx
->b
, rtex
);
476 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
478 if (&rctx
->b
== rscreen
->aux_context
)
479 mtx_unlock(&rscreen
->aux_context_lock
);
481 return r600_texture_discard_dcc(rscreen
, rtex
);
484 static void r600_reallocate_texture_inplace(struct r600_common_context
*rctx
,
485 struct r600_texture
*rtex
,
486 unsigned new_bind_flag
,
487 bool invalidate_storage
)
489 struct pipe_screen
*screen
= rctx
->b
.screen
;
490 struct r600_texture
*new_tex
;
491 struct pipe_resource templ
= rtex
->resource
.b
.b
;
494 templ
.bind
|= new_bind_flag
;
496 if (rtex
->resource
.b
.is_shared
)
499 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
500 if (rtex
->surface
.is_linear
)
503 /* This fails with MSAA, depth, and compressed textures. */
504 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
505 RADEON_SURF_MODE_LINEAR_ALIGNED
)
509 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
513 /* Copy the pixels to the new texture. */
514 if (!invalidate_storage
) {
515 for (i
= 0; i
<= templ
.last_level
; i
++) {
519 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
520 util_max_layer(&templ
, i
) + 1, &box
);
522 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
523 &rtex
->resource
.b
.b
, i
, &box
);
527 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
528 r600_texture_discard_cmask(rctx
->screen
, rtex
);
529 r600_texture_discard_dcc(rctx
->screen
, rtex
);
532 /* Replace the structure fields of rtex. */
533 rtex
->resource
.b
.b
.bind
= templ
.bind
;
534 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
535 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
536 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
537 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
538 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
539 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
540 rtex
->resource
.domains
= new_tex
->resource
.domains
;
541 rtex
->resource
.flags
= new_tex
->resource
.flags
;
542 rtex
->size
= new_tex
->size
;
543 rtex
->db_render_format
= new_tex
->db_render_format
;
544 rtex
->db_compatible
= new_tex
->db_compatible
;
545 rtex
->can_sample_z
= new_tex
->can_sample_z
;
546 rtex
->can_sample_s
= new_tex
->can_sample_s
;
547 rtex
->surface
= new_tex
->surface
;
548 rtex
->fmask
= new_tex
->fmask
;
549 rtex
->cmask
= new_tex
->cmask
;
550 rtex
->cb_color_info
= new_tex
->cb_color_info
;
551 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
552 rtex
->htile_offset
= new_tex
->htile_offset
;
553 rtex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
554 rtex
->depth_cleared
= new_tex
->depth_cleared
;
555 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
556 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
557 rtex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
558 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
560 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
561 assert(!rtex
->htile_offset
);
562 assert(!rtex
->cmask
.size
);
563 assert(!rtex
->fmask
.size
);
564 assert(!rtex
->dcc_offset
);
565 assert(!rtex
->is_depth
);
568 r600_texture_reference(&new_tex
, NULL
);
570 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
573 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
574 struct pipe_context
*ctx
,
575 struct pipe_resource
*resource
,
576 struct winsys_handle
*whandle
,
579 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
580 struct r600_common_context
*rctx
;
581 struct r600_resource
*res
= (struct r600_resource
*)resource
;
582 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
583 struct radeon_bo_metadata metadata
;
584 bool update_metadata
= false;
585 unsigned stride
, offset
, slice_size
;
587 ctx
= threaded_context_unwrap_sync(ctx
);
588 rctx
= (struct r600_common_context
*)(ctx
? ctx
: rscreen
->aux_context
);
590 if (resource
->target
!= PIPE_BUFFER
) {
591 /* This is not supported now, but it might be required for OpenCL
592 * interop in the future.
594 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
597 /* Move a suballocated texture into a non-suballocated allocation. */
598 if (rscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
599 rtex
->surface
.tile_swizzle
||
600 (rtex
->resource
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
601 whandle
->type
!= DRM_API_HANDLE_TYPE_KMS
)) {
602 assert(!res
->b
.is_shared
);
603 r600_reallocate_texture_inplace(rctx
, rtex
,
604 PIPE_BIND_SHARED
, false);
605 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
606 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
607 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
608 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
609 assert(rtex
->surface
.tile_swizzle
== 0);
612 /* Since shader image stores don't support DCC on VI,
613 * disable it for external clients that want write
616 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
617 if (si_texture_disable_dcc(rctx
, rtex
))
618 update_metadata
= true;
621 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
622 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
623 /* Eliminate fast clear (both CMASK and DCC) */
624 r600_eliminate_fast_color_clear(rctx
, rtex
);
626 /* Disable CMASK if flush_resource isn't going
629 if (rtex
->cmask
.size
)
630 r600_texture_discard_cmask(rscreen
, rtex
);
634 if (!res
->b
.is_shared
|| update_metadata
) {
635 r600_texture_init_metadata(rscreen
, rtex
, &metadata
);
636 if (rscreen
->query_opaque_metadata
)
637 rscreen
->query_opaque_metadata(rscreen
, rtex
,
640 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
643 if (rscreen
->chip_class
>= GFX9
) {
644 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
645 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
647 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
649 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
650 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
652 slice_size
= rtex
->surface
.u
.legacy
.level
[0].slice_size
;
655 /* Move a suballocated buffer into a non-suballocated allocation. */
656 if (rscreen
->ws
->buffer_is_suballocated(res
->buf
)) {
657 assert(!res
->b
.is_shared
);
659 /* Allocate a new buffer with PIPE_BIND_SHARED. */
660 struct pipe_resource templ
= res
->b
.b
;
661 templ
.bind
|= PIPE_BIND_SHARED
;
663 struct pipe_resource
*newb
=
664 screen
->resource_create(screen
, &templ
);
668 /* Copy the old buffer contents to the new one. */
670 u_box_1d(0, newb
->width0
, &box
);
671 rctx
->b
.resource_copy_region(&rctx
->b
, newb
, 0, 0, 0, 0,
673 /* Move the new buffer storage to the old pipe_resource. */
674 si_replace_buffer_storage(&rctx
->b
, &res
->b
.b
, newb
);
675 pipe_resource_reference(&newb
, NULL
);
677 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
678 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
687 if (res
->b
.is_shared
) {
688 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
691 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
692 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
693 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
695 res
->b
.is_shared
= true;
696 res
->external_usage
= usage
;
699 return rscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
700 slice_size
, whandle
);
703 static void r600_texture_destroy(struct pipe_screen
*screen
,
704 struct pipe_resource
*ptex
)
706 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
707 struct r600_resource
*resource
= &rtex
->resource
;
709 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
711 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
712 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
714 pb_reference(&resource
->buf
, NULL
);
715 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
716 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
720 static const struct u_resource_vtbl r600_texture_vtbl
;
722 /* The number of samples can be specified independently of the texture. */
723 void si_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
724 struct r600_texture
*rtex
,
726 struct r600_fmask_info
*out
)
728 /* FMASK is allocated like an ordinary texture. */
729 struct pipe_resource templ
= rtex
->resource
.b
.b
;
730 struct radeon_surf fmask
= {};
733 memset(out
, 0, sizeof(*out
));
735 if (rscreen
->chip_class
>= GFX9
) {
736 out
->alignment
= rtex
->surface
.u
.gfx9
.fmask_alignment
;
737 out
->size
= rtex
->surface
.u
.gfx9
.fmask_size
;
741 templ
.nr_samples
= 1;
742 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
744 switch (nr_samples
) {
753 R600_ERR("Invalid sample count for FMASK allocation.\n");
757 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
758 RADEON_SURF_MODE_2D
, &fmask
)) {
759 R600_ERR("Got error in surface_init while allocating FMASK.\n");
763 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
765 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
766 if (out
->slice_tile_max
)
767 out
->slice_tile_max
-= 1;
769 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
770 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
771 out
->bank_height
= fmask
.u
.legacy
.bankh
;
772 out
->tile_swizzle
= fmask
.tile_swizzle
;
773 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
774 out
->size
= fmask
.surf_size
;
777 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
778 struct r600_texture
*rtex
)
780 si_texture_get_fmask_info(rscreen
, rtex
,
781 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
783 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
784 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
787 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
788 struct r600_texture
*rtex
,
789 struct r600_cmask_info
*out
)
791 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
792 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
793 unsigned cl_width
, cl_height
;
795 if (rscreen
->chip_class
>= GFX9
) {
796 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
797 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
814 case 16: /* Hawaii */
823 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
825 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
826 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
827 unsigned slice_elements
= (width
* height
) / (8*8);
829 /* Each element of CMASK is a nibble. */
830 unsigned slice_bytes
= slice_elements
/ 2;
832 out
->slice_tile_max
= (width
* height
) / (128*128);
833 if (out
->slice_tile_max
)
834 out
->slice_tile_max
-= 1;
836 out
->alignment
= MAX2(256, base_align
);
837 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
838 align(slice_bytes
, base_align
);
841 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
842 struct r600_texture
*rtex
)
844 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
846 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
847 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
849 rtex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
852 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
853 struct r600_texture
*rtex
)
855 if (rtex
->cmask_buffer
)
858 assert(rtex
->cmask
.size
== 0);
860 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
862 rtex
->cmask_buffer
= (struct r600_resource
*)
863 si_aligned_buffer_create(&rscreen
->b
,
864 R600_RESOURCE_FLAG_UNMAPPABLE
,
867 rtex
->cmask
.alignment
);
868 if (rtex
->cmask_buffer
== NULL
) {
869 rtex
->cmask
.size
= 0;
873 /* update colorbuffer state bits */
874 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
876 rtex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
878 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
881 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
882 struct r600_texture
*rtex
)
884 unsigned cl_width
, cl_height
, width
, height
;
885 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
886 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
888 assert(rscreen
->chip_class
<= VI
);
890 rtex
->surface
.htile_size
= 0;
892 /* HTILE is broken with 1D tiling on old kernels and CIK. */
893 if (rscreen
->chip_class
>= CIK
&&
894 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
895 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
898 /* Overalign HTILE on P2 configs to work around GPU hangs in
899 * piglit/depthstencil-render-miplevels 585.
901 * This has been confirmed to help Kabini & Stoney, where the hangs
902 * are always reproducible. I think I have seen the test hang
903 * on Carrizo too, though it was very rare there.
905 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
934 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
935 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
937 slice_elements
= (width
* height
) / (8 * 8);
938 slice_bytes
= slice_elements
* 4;
940 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
941 base_align
= num_pipes
* pipe_interleave_bytes
;
943 rtex
->surface
.htile_alignment
= base_align
;
944 rtex
->surface
.htile_size
=
945 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
946 align(slice_bytes
, base_align
);
949 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
950 struct r600_texture
*rtex
)
952 if (rscreen
->chip_class
<= VI
&& !rtex
->tc_compatible_htile
)
953 r600_texture_get_htile_size(rscreen
, rtex
);
955 if (!rtex
->surface
.htile_size
)
958 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
959 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
962 void si_print_texture_info(struct r600_common_screen
*rscreen
,
963 struct r600_texture
*rtex
, struct u_log_context
*log
)
967 /* Common parameters. */
968 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
969 "blk_h=%u, array_size=%u, last_level=%u, "
970 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
971 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
972 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
974 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
975 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
976 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
978 if (rscreen
->chip_class
>= GFX9
) {
979 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
980 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
981 rtex
->surface
.surf_size
,
982 rtex
->surface
.u
.gfx9
.surf_slice_size
,
983 rtex
->surface
.surf_alignment
,
984 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
985 rtex
->surface
.u
.gfx9
.surf
.epitch
,
986 rtex
->surface
.u
.gfx9
.surf_pitch
);
988 if (rtex
->fmask
.size
) {
989 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
990 "alignment=%u, swmode=%u, epitch=%u\n",
992 rtex
->surface
.u
.gfx9
.fmask_size
,
993 rtex
->surface
.u
.gfx9
.fmask_alignment
,
994 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
995 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
998 if (rtex
->cmask
.size
) {
999 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
1000 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1002 rtex
->surface
.u
.gfx9
.cmask_size
,
1003 rtex
->surface
.u
.gfx9
.cmask_alignment
,
1004 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1005 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1008 if (rtex
->htile_offset
) {
1009 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1010 "rb_aligned=%u, pipe_aligned=%u\n",
1012 rtex
->surface
.htile_size
,
1013 rtex
->surface
.htile_alignment
,
1014 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1015 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1018 if (rtex
->dcc_offset
) {
1019 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", "
1020 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1021 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1022 rtex
->surface
.dcc_alignment
,
1023 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
1024 rtex
->surface
.num_dcc_levels
);
1027 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
1028 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1029 rtex
->surface
.u
.gfx9
.stencil_offset
,
1030 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1031 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1036 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1037 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1038 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1039 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1040 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1041 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1043 if (rtex
->fmask
.size
)
1044 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1045 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1046 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
1047 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
1048 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
1050 if (rtex
->cmask
.size
)
1051 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1052 "slice_tile_max=%u\n",
1053 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1054 rtex
->cmask
.slice_tile_max
);
1056 if (rtex
->htile_offset
)
1057 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%"PRIu64
", "
1058 "alignment=%u, TC_compatible = %u\n",
1059 rtex
->htile_offset
, rtex
->surface
.htile_size
,
1060 rtex
->surface
.htile_alignment
,
1061 rtex
->tc_compatible_htile
);
1063 if (rtex
->dcc_offset
) {
1064 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u\n",
1065 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1066 rtex
->surface
.dcc_alignment
);
1067 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1068 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
1069 "fast_clear_size=%"PRIu64
"\n",
1070 i
, i
< rtex
->surface
.num_dcc_levels
,
1071 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1072 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1075 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1076 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1077 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1078 "mode=%u, tiling_index = %u\n",
1079 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1080 rtex
->surface
.u
.legacy
.level
[i
].slice_size
,
1081 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1082 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1083 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1084 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1085 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1086 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1087 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1089 if (rtex
->surface
.has_stencil
) {
1090 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1091 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1092 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
1093 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1094 "slice_size=%"PRIu64
", npix_x=%u, "
1095 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1096 "mode=%u, tiling_index = %u\n",
1097 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1098 rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size
,
1099 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1100 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1101 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1102 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1103 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1104 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1105 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1110 /* Common processing for r600_texture_create and r600_texture_from_handle */
1111 static struct r600_texture
*
1112 r600_texture_create_object(struct pipe_screen
*screen
,
1113 const struct pipe_resource
*base
,
1114 struct pb_buffer
*buf
,
1115 struct radeon_surf
*surface
)
1117 struct r600_texture
*rtex
;
1118 struct r600_resource
*resource
;
1119 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1121 rtex
= CALLOC_STRUCT(r600_texture
);
1125 resource
= &rtex
->resource
;
1126 resource
->b
.b
= *base
;
1127 resource
->b
.b
.next
= NULL
;
1128 resource
->b
.vtbl
= &r600_texture_vtbl
;
1129 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1130 resource
->b
.b
.screen
= screen
;
1132 /* don't include stencil-only formats which we don't support for rendering */
1133 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1135 rtex
->surface
= *surface
;
1136 rtex
->size
= rtex
->surface
.surf_size
;
1138 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1139 (rtex
->surface
.flags
&
1140 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1142 /* TC-compatible HTILE:
1143 * - VI only supports Z32_FLOAT.
1144 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1145 if (rtex
->tc_compatible_htile
) {
1146 if (rscreen
->chip_class
>= GFX9
&&
1147 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1148 rtex
->db_render_format
= base
->format
;
1150 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1151 rtex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1152 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1155 rtex
->db_render_format
= base
->format
;
1158 /* Tiled depth textures utilize the non-displayable tile order.
1159 * This must be done after r600_setup_surface.
1160 * Applies to R600-Cayman. */
1161 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1162 /* Applies to GCN. */
1163 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1165 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1166 * between frames, so the only thing that can enable separate DCC
1167 * with DRI2 is multiple slow clears within a frame.
1169 rtex
->ps_draw_ratio
= 0;
1171 if (rtex
->is_depth
) {
1172 if (rscreen
->chip_class
>= GFX9
) {
1173 rtex
->can_sample_z
= true;
1174 rtex
->can_sample_s
= true;
1176 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1177 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1180 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1181 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1182 rtex
->db_compatible
= true;
1184 if (!(rscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1185 r600_texture_allocate_htile(rscreen
, rtex
);
1188 if (base
->nr_samples
> 1) {
1190 r600_texture_allocate_fmask(rscreen
, rtex
);
1191 r600_texture_allocate_cmask(rscreen
, rtex
);
1192 rtex
->cmask_buffer
= &rtex
->resource
;
1194 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1200 /* Shared textures must always set up DCC here.
1201 * If it's not present, it will be disabled by
1202 * apply_opaque_metadata later.
1204 if (rtex
->surface
.dcc_size
&&
1205 (buf
|| !(rscreen
->debug_flags
& DBG(NO_DCC
))) &&
1206 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1207 /* Reserve space for the DCC buffer. */
1208 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1209 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1213 /* Now create the backing buffer. */
1215 si_init_resource_fields(rscreen
, resource
, rtex
->size
,
1216 rtex
->surface
.surf_alignment
);
1218 if (!si_alloc_resource(rscreen
, resource
)) {
1223 resource
->buf
= buf
;
1224 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1225 resource
->bo_size
= buf
->size
;
1226 resource
->bo_alignment
= buf
->alignment
;
1227 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1228 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1229 resource
->vram_usage
= buf
->size
;
1230 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1231 resource
->gart_usage
= buf
->size
;
1234 if (rtex
->cmask
.size
) {
1235 /* Initialize the cmask to 0xCC (= compressed state). */
1236 si_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1237 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1240 if (rtex
->htile_offset
) {
1241 uint32_t clear_value
= 0;
1243 if (rscreen
->chip_class
>= GFX9
|| rtex
->tc_compatible_htile
)
1244 clear_value
= 0x0000030F;
1246 si_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1248 rtex
->surface
.htile_size
,
1252 /* Initialize DCC only if the texture is not being imported. */
1253 if (!buf
&& rtex
->dcc_offset
) {
1254 si_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1256 rtex
->surface
.dcc_size
,
1260 /* Initialize the CMASK base register value. */
1261 rtex
->cmask
.base_address_reg
=
1262 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1264 if (rscreen
->debug_flags
& DBG(VM
)) {
1265 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1266 rtex
->resource
.gpu_address
,
1267 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1268 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1269 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1272 if (rscreen
->debug_flags
& DBG(TEX
)) {
1274 struct u_log_context log
;
1275 u_log_context_init(&log
);
1276 si_print_texture_info(rscreen
, rtex
, &log
);
1277 u_log_new_page_print(&log
, stdout
);
1279 u_log_context_destroy(&log
);
1285 static enum radeon_surf_mode
1286 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1287 const struct pipe_resource
*templ
)
1289 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1290 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1291 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1292 !(templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1294 /* MSAA resources must be 2D tiled. */
1295 if (templ
->nr_samples
> 1)
1296 return RADEON_SURF_MODE_2D
;
1298 /* Transfer resources should be linear. */
1299 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1300 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1302 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1303 * which requires 2D tiling.
1305 if (rscreen
->chip_class
== VI
&&
1307 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
))
1308 return RADEON_SURF_MODE_2D
;
1310 /* Handle common candidates for the linear mode.
1311 * Compressed textures and DB surfaces must always be tiled.
1313 if (!force_tiling
&&
1314 !is_depth_stencil
&&
1315 !util_format_is_compressed(templ
->format
)) {
1316 if (rscreen
->debug_flags
& DBG(NO_TILING
))
1317 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1319 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1320 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1321 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1323 /* Cursors are linear on SI.
1324 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1325 if (templ
->bind
& PIPE_BIND_CURSOR
)
1326 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1328 if (templ
->bind
& PIPE_BIND_LINEAR
)
1329 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1331 /* Textures with a very small height are recommended to be linear. */
1332 if (templ
->target
== PIPE_TEXTURE_1D
||
1333 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1334 /* Only very thin and long 2D textures should benefit from
1335 * linear_aligned. */
1336 (templ
->width0
> 8 && templ
->height0
<= 2))
1337 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1339 /* Textures likely to be mapped often. */
1340 if (templ
->usage
== PIPE_USAGE_STAGING
||
1341 templ
->usage
== PIPE_USAGE_STREAM
)
1342 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1345 /* Make small textures 1D tiled. */
1346 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1347 (rscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1348 return RADEON_SURF_MODE_1D
;
1350 /* The allocator will switch to 1D if needed. */
1351 return RADEON_SURF_MODE_2D
;
1354 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1355 const struct pipe_resource
*templ
)
1357 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1358 struct radeon_surf surface
= {0};
1359 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1360 bool tc_compatible_htile
=
1361 rscreen
->chip_class
>= VI
&&
1362 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1363 !(rscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1364 !is_flushed_depth
&&
1365 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1366 util_format_is_depth_or_stencil(templ
->format
);
1370 r
= r600_init_surface(rscreen
, &surface
, templ
,
1371 r600_choose_tiling(rscreen
, templ
), 0, 0,
1372 false, false, is_flushed_depth
,
1373 tc_compatible_htile
);
1378 return (struct pipe_resource
*)
1379 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1382 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1383 const struct pipe_resource
*templ
,
1384 struct winsys_handle
*whandle
,
1387 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1388 struct pb_buffer
*buf
= NULL
;
1389 unsigned stride
= 0, offset
= 0;
1390 enum radeon_surf_mode array_mode
;
1391 struct radeon_surf surface
= {};
1393 struct radeon_bo_metadata metadata
= {};
1394 struct r600_texture
*rtex
;
1397 /* Support only 2D textures without mipmaps */
1398 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1399 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1402 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1406 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1407 r600_surface_import_metadata(rscreen
, &surface
, &metadata
,
1408 &array_mode
, &is_scanout
);
1410 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1411 offset
, true, is_scanout
, false, false);
1416 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1420 rtex
->resource
.b
.is_shared
= true;
1421 rtex
->resource
.external_usage
= usage
;
1423 if (rscreen
->apply_opaque_metadata
)
1424 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1426 assert(rtex
->surface
.tile_swizzle
== 0);
1427 return &rtex
->resource
.b
.b
;
1430 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1431 struct pipe_resource
*texture
,
1432 struct r600_texture
**staging
)
1434 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1435 struct pipe_resource resource
;
1436 struct r600_texture
**flushed_depth_texture
= staging
?
1437 staging
: &rtex
->flushed_depth_texture
;
1438 enum pipe_format pipe_format
= texture
->format
;
1441 if (rtex
->flushed_depth_texture
)
1442 return true; /* it's ready */
1444 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1445 switch (pipe_format
) {
1446 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1447 /* Save memory by not allocating the S plane. */
1448 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1450 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1451 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1452 /* Save memory bandwidth by not copying the
1453 * stencil part during flush.
1455 * This potentially increases memory bandwidth
1456 * if an application uses both Z and S texturing
1457 * simultaneously (a flushed Z24S8 texture
1458 * would be stored compactly), but how often
1459 * does that really happen?
1461 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1465 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1466 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1468 /* DB->CB copies to an 8bpp surface don't work. */
1469 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1473 memset(&resource
, 0, sizeof(resource
));
1474 resource
.target
= texture
->target
;
1475 resource
.format
= pipe_format
;
1476 resource
.width0
= texture
->width0
;
1477 resource
.height0
= texture
->height0
;
1478 resource
.depth0
= texture
->depth0
;
1479 resource
.array_size
= texture
->array_size
;
1480 resource
.last_level
= texture
->last_level
;
1481 resource
.nr_samples
= texture
->nr_samples
;
1482 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1483 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1484 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1487 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1489 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1490 if (*flushed_depth_texture
== NULL
) {
1491 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1495 (*flushed_depth_texture
)->non_disp_tiling
= false;
1500 * Initialize the pipe_resource descriptor to be of the same size as the box,
1501 * which is supposed to hold a subregion of the texture "orig" at the given
1504 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1505 struct pipe_resource
*orig
,
1506 const struct pipe_box
*box
,
1507 unsigned level
, unsigned flags
)
1509 memset(res
, 0, sizeof(*res
));
1510 res
->format
= orig
->format
;
1511 res
->width0
= box
->width
;
1512 res
->height0
= box
->height
;
1514 res
->array_size
= 1;
1515 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1518 /* We must set the correct texture target and dimensions for a 3D box. */
1519 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1520 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1521 res
->array_size
= box
->depth
;
1523 res
->target
= PIPE_TEXTURE_2D
;
1527 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1528 struct r600_texture
*rtex
,
1529 unsigned transfer_usage
,
1530 const struct pipe_box
*box
)
1532 return !rtex
->resource
.b
.is_shared
&&
1533 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1534 rtex
->resource
.b
.b
.last_level
== 0 &&
1535 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1536 box
->x
, box
->y
, box
->z
,
1537 box
->width
, box
->height
,
1541 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1542 struct r600_texture
*rtex
)
1544 struct r600_common_screen
*rscreen
= rctx
->screen
;
1546 /* There is no point in discarding depth and tiled buffers. */
1547 assert(!rtex
->is_depth
);
1548 assert(rtex
->surface
.is_linear
);
1550 /* Reallocate the buffer in the same pipe_resource. */
1551 si_alloc_resource(rscreen
, &rtex
->resource
);
1553 /* Initialize the CMASK base address (needed even without CMASK). */
1554 rtex
->cmask
.base_address_reg
=
1555 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1557 p_atomic_inc(&rscreen
->dirty_tex_counter
);
1559 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1562 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1563 struct pipe_resource
*texture
,
1566 const struct pipe_box
*box
,
1567 struct pipe_transfer
**ptransfer
)
1569 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1570 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1571 struct r600_transfer
*trans
;
1572 struct r600_resource
*buf
;
1573 unsigned offset
= 0;
1575 bool use_staging_texture
= false;
1577 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1578 assert(box
->width
&& box
->height
&& box
->depth
);
1580 /* Depth textures use staging unconditionally. */
1581 if (!rtex
->is_depth
) {
1582 /* Degrade the tile mode if we get too many transfers on APUs.
1583 * On dGPUs, the staging texture is always faster.
1584 * Only count uploads that are at least 4x4 pixels large.
1586 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1588 box
->width
>= 4 && box
->height
>= 4 &&
1589 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1590 bool can_invalidate
=
1591 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1594 r600_reallocate_texture_inplace(rctx
, rtex
,
1599 /* Tiled textures need to be converted into a linear texture for CPU
1600 * access. The staging texture is always linear and is placed in GART.
1602 * Reading from VRAM or GTT WC is slow, always use the staging
1603 * texture in this case.
1605 * Use the staging texture for uploads if the underlying BO
1608 if (!rtex
->surface
.is_linear
)
1609 use_staging_texture
= true;
1610 else if (usage
& PIPE_TRANSFER_READ
)
1611 use_staging_texture
=
1612 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1613 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1614 /* Write & linear only: */
1615 else if (si_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1616 RADEON_USAGE_READWRITE
) ||
1617 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1618 RADEON_USAGE_READWRITE
)) {
1620 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1622 r600_texture_invalidate_storage(rctx
, rtex
);
1624 use_staging_texture
= true;
1628 trans
= CALLOC_STRUCT(r600_transfer
);
1631 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1632 trans
->b
.b
.level
= level
;
1633 trans
->b
.b
.usage
= usage
;
1634 trans
->b
.b
.box
= *box
;
1636 if (rtex
->is_depth
) {
1637 struct r600_texture
*staging_depth
;
1639 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1640 /* MSAA depth buffers need to be converted to single sample buffers.
1642 * Mapping MSAA depth buffers can occur if ReadPixels is called
1643 * with a multisample GLX visual.
1645 * First downsample the depth buffer to a temporary texture,
1646 * then decompress the temporary one to staging.
1648 * Only the region being mapped is transfered.
1650 struct pipe_resource resource
;
1652 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1654 if (!si_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1655 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1660 if (usage
& PIPE_TRANSFER_READ
) {
1661 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1663 R600_ERR("failed to create a temporary depth texture\n");
1668 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1669 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1670 0, 0, 0, box
->depth
, 0, 0);
1671 pipe_resource_reference(&temp
, NULL
);
1674 /* Just get the strides. */
1675 r600_texture_get_offset(rctx
->screen
, staging_depth
, level
, NULL
,
1677 &trans
->b
.b
.layer_stride
);
1679 /* XXX: only readback the rectangle which is being mapped? */
1680 /* XXX: when discard is true, no need to read back from depth texture */
1681 if (!si_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1682 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1687 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1689 box
->z
, box
->z
+ box
->depth
- 1,
1692 offset
= r600_texture_get_offset(rctx
->screen
, staging_depth
,
1695 &trans
->b
.b
.layer_stride
);
1698 trans
->staging
= (struct r600_resource
*)staging_depth
;
1699 buf
= trans
->staging
;
1700 } else if (use_staging_texture
) {
1701 struct pipe_resource resource
;
1702 struct r600_texture
*staging
;
1704 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1705 R600_RESOURCE_FLAG_TRANSFER
);
1706 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1707 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1709 /* Create the temporary texture. */
1710 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1712 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1716 trans
->staging
= &staging
->resource
;
1718 /* Just get the strides. */
1719 r600_texture_get_offset(rctx
->screen
, staging
, 0, NULL
,
1721 &trans
->b
.b
.layer_stride
);
1723 if (usage
& PIPE_TRANSFER_READ
)
1724 r600_copy_to_staging_texture(ctx
, trans
);
1726 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1728 buf
= trans
->staging
;
1730 /* the resource is mapped directly */
1731 offset
= r600_texture_get_offset(rctx
->screen
, rtex
, level
, box
,
1733 &trans
->b
.b
.layer_stride
);
1734 buf
= &rtex
->resource
;
1737 if (!(map
= si_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1738 r600_resource_reference(&trans
->staging
, NULL
);
1743 *ptransfer
= &trans
->b
.b
;
1744 return map
+ offset
;
1747 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1748 struct pipe_transfer
* transfer
)
1750 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1751 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1752 struct pipe_resource
*texture
= transfer
->resource
;
1753 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1755 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1756 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1757 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1758 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1759 &rtransfer
->staging
->b
.b
, transfer
->level
,
1762 r600_copy_from_staging_texture(ctx
, rtransfer
);
1766 if (rtransfer
->staging
) {
1767 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1768 r600_resource_reference(&rtransfer
->staging
, NULL
);
1771 /* Heuristic for {upload, draw, upload, draw, ..}:
1773 * Flush the gfx IB if we've allocated too much texture storage.
1775 * The idea is that we don't want to build IBs that use too much
1776 * memory and put pressure on the kernel memory manager and we also
1777 * want to make temporary and invalidated buffers go idle ASAP to
1778 * decrease the total memory usage or make them reusable. The memory
1779 * usage will be slightly higher than given here because of the buffer
1780 * cache in the winsys.
1782 * The result is that the kernel memory manager is never a bottleneck.
1784 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1785 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1786 rctx
->num_alloc_tex_transfer_bytes
= 0;
1789 pipe_resource_reference(&transfer
->resource
, NULL
);
1793 static const struct u_resource_vtbl r600_texture_vtbl
=
1795 NULL
, /* get_handle */
1796 r600_texture_destroy
, /* resource_destroy */
1797 r600_texture_transfer_map
, /* transfer_map */
1798 u_default_transfer_flush_region
, /* transfer_flush_region */
1799 r600_texture_transfer_unmap
, /* transfer_unmap */
1802 /* DCC channel type categories within which formats can be reinterpreted
1803 * while keeping the same DCC encoding. The swizzle must also match. */
1804 enum dcc_channel_type
{
1805 dcc_channel_float32
,
1808 dcc_channel_float16
,
1811 dcc_channel_uint_10_10_10_2
,
1814 dcc_channel_incompatible
,
1817 /* Return the type of DCC encoding. */
1818 static enum dcc_channel_type
1819 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1823 /* Find the first non-void channel. */
1824 for (i
= 0; i
< desc
->nr_channels
; i
++)
1825 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1827 if (i
== desc
->nr_channels
)
1828 return dcc_channel_incompatible
;
1830 switch (desc
->channel
[i
].size
) {
1832 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1833 return dcc_channel_float32
;
1834 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1835 return dcc_channel_uint32
;
1836 return dcc_channel_sint32
;
1838 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1839 return dcc_channel_float16
;
1840 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1841 return dcc_channel_uint16
;
1842 return dcc_channel_sint16
;
1844 return dcc_channel_uint_10_10_10_2
;
1846 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1847 return dcc_channel_uint8
;
1848 return dcc_channel_sint8
;
1850 return dcc_channel_incompatible
;
1854 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1855 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1856 enum pipe_format format2
)
1858 const struct util_format_description
*desc1
, *desc2
;
1859 enum dcc_channel_type type1
, type2
;
1862 if (format1
== format2
)
1865 desc1
= util_format_description(format1
);
1866 desc2
= util_format_description(format2
);
1868 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1871 /* Swizzles must be the same. */
1872 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1873 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1874 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1875 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1878 type1
= vi_get_dcc_channel_type(desc1
);
1879 type2
= vi_get_dcc_channel_type(desc2
);
1881 return type1
!= dcc_channel_incompatible
&&
1882 type2
!= dcc_channel_incompatible
&&
1886 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1888 enum pipe_format view_format
)
1890 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1892 return vi_dcc_enabled(rtex
, level
) &&
1893 !vi_dcc_formats_compatible(tex
->format
, view_format
);
1896 /* This can't be merged with the above function, because
1897 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1898 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
1899 struct pipe_resource
*tex
,
1901 enum pipe_format view_format
)
1903 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1905 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
1906 if (!si_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1907 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1910 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1911 struct pipe_resource
*texture
,
1912 const struct pipe_surface
*templ
,
1913 unsigned width0
, unsigned height0
,
1914 unsigned width
, unsigned height
)
1916 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1921 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1922 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1924 pipe_reference_init(&surface
->base
.reference
, 1);
1925 pipe_resource_reference(&surface
->base
.texture
, texture
);
1926 surface
->base
.context
= pipe
;
1927 surface
->base
.format
= templ
->format
;
1928 surface
->base
.width
= width
;
1929 surface
->base
.height
= height
;
1930 surface
->base
.u
= templ
->u
;
1932 surface
->width0
= width0
;
1933 surface
->height0
= height0
;
1935 surface
->dcc_incompatible
=
1936 texture
->target
!= PIPE_BUFFER
&&
1937 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
1939 return &surface
->base
;
1942 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1943 struct pipe_resource
*tex
,
1944 const struct pipe_surface
*templ
)
1946 unsigned level
= templ
->u
.tex
.level
;
1947 unsigned width
= u_minify(tex
->width0
, level
);
1948 unsigned height
= u_minify(tex
->height0
, level
);
1949 unsigned width0
= tex
->width0
;
1950 unsigned height0
= tex
->height0
;
1952 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1953 const struct util_format_description
*tex_desc
1954 = util_format_description(tex
->format
);
1955 const struct util_format_description
*templ_desc
1956 = util_format_description(templ
->format
);
1958 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1960 /* Adjust size of surface if and only if the block width or
1961 * height is changed. */
1962 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1963 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1964 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1965 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1967 width
= nblks_x
* templ_desc
->block
.width
;
1968 height
= nblks_y
* templ_desc
->block
.height
;
1970 width0
= util_format_get_nblocksx(tex
->format
, width0
);
1971 height0
= util_format_get_nblocksy(tex
->format
, height0
);
1975 return si_create_surface_custom(pipe
, tex
, templ
,
1980 static void r600_surface_destroy(struct pipe_context
*pipe
,
1981 struct pipe_surface
*surface
)
1983 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1984 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1985 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1986 pipe_resource_reference(&surface
->texture
, NULL
);
1990 static void r600_clear_texture(struct pipe_context
*pipe
,
1991 struct pipe_resource
*tex
,
1993 const struct pipe_box
*box
,
1996 struct pipe_screen
*screen
= pipe
->screen
;
1997 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1998 struct pipe_surface tmpl
= {{0}};
1999 struct pipe_surface
*sf
;
2000 const struct util_format_description
*desc
=
2001 util_format_description(tex
->format
);
2003 tmpl
.format
= tex
->format
;
2004 tmpl
.u
.tex
.first_layer
= box
->z
;
2005 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
2006 tmpl
.u
.tex
.level
= level
;
2007 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
2011 if (rtex
->is_depth
) {
2014 uint8_t stencil
= 0;
2016 /* Depth is always present. */
2017 clear
= PIPE_CLEAR_DEPTH
;
2018 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
2020 if (rtex
->surface
.has_stencil
) {
2021 clear
|= PIPE_CLEAR_STENCIL
;
2022 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
2025 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
2027 box
->width
, box
->height
, false);
2029 union pipe_color_union color
;
2031 /* pipe_color_union requires the full vec4 representation. */
2032 if (util_format_is_pure_uint(tex
->format
))
2033 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
2034 else if (util_format_is_pure_sint(tex
->format
))
2035 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
2037 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
2039 if (screen
->is_format_supported(screen
, tex
->format
,
2041 PIPE_BIND_RENDER_TARGET
)) {
2042 pipe
->clear_render_target(pipe
, sf
, &color
,
2044 box
->width
, box
->height
, false);
2046 /* Software fallback - just for R9G9B9E5_FLOAT */
2047 util_clear_render_target(pipe
, sf
, &color
,
2049 box
->width
, box
->height
);
2052 pipe_surface_reference(&sf
, NULL
);
2055 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2057 const struct util_format_description
*desc
= util_format_description(format
);
2059 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2061 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2062 return V_028C70_SWAP_STD
;
2064 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2067 switch (desc
->nr_channels
) {
2069 if (HAS_SWIZZLE(0,X
))
2070 return V_028C70_SWAP_STD
; /* X___ */
2071 else if (HAS_SWIZZLE(3,X
))
2072 return V_028C70_SWAP_ALT_REV
; /* ___X */
2075 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2076 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2077 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2078 return V_028C70_SWAP_STD
; /* XY__ */
2079 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2080 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2081 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2083 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2084 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2085 return V_028C70_SWAP_ALT
; /* X__Y */
2086 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2087 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2090 if (HAS_SWIZZLE(0,X
))
2091 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2092 else if (HAS_SWIZZLE(0,Z
))
2093 return V_028C70_SWAP_STD_REV
; /* ZYX */
2096 /* check the middle channels, the 1st and 4th channel can be NONE */
2097 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2098 return V_028C70_SWAP_STD
; /* XYZW */
2099 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2100 return V_028C70_SWAP_STD_REV
; /* WZYX */
2101 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2102 return V_028C70_SWAP_ALT
; /* ZYXW */
2103 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2106 return V_028C70_SWAP_ALT_REV
;
2108 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2115 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2117 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
2122 if (rctx
->dcc_stats
[slot
].query_active
)
2123 vi_separate_dcc_stop_query(&rctx
->b
,
2124 rctx
->dcc_stats
[slot
].tex
);
2126 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
2127 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2128 rctx
->b
.destroy_query(&rctx
->b
,
2129 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
2130 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2133 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2137 * Return the per-context slot where DCC statistics queries for the texture live.
2139 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2140 struct r600_texture
*tex
)
2142 int i
, empty_slot
= -1;
2144 /* Remove zombie textures (textures kept alive by this array only). */
2145 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2146 if (rctx
->dcc_stats
[i
].tex
&&
2147 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2148 vi_dcc_clean_up_context_slot(rctx
, i
);
2150 /* Find the texture. */
2151 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2152 /* Return if found. */
2153 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2154 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2158 /* Record the first seen empty slot. */
2159 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2163 /* Not found. Remove the oldest member to make space in the array. */
2164 if (empty_slot
== -1) {
2165 int oldest_slot
= 0;
2167 /* Find the oldest slot. */
2168 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2169 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2170 rctx
->dcc_stats
[i
].last_use_timestamp
)
2173 /* Clean up the oldest slot. */
2174 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2175 empty_slot
= oldest_slot
;
2178 /* Add the texture to the new slot. */
2179 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2180 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2184 static struct pipe_query
*
2185 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2187 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2188 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2190 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2191 return (struct pipe_query
*)query
;
2195 * Called when binding a color buffer.
2197 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2198 struct r600_texture
*tex
)
2200 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2201 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2203 assert(!rctx
->dcc_stats
[i
].query_active
);
2205 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2206 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2208 /* begin or resume the query */
2209 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2210 rctx
->dcc_stats
[i
].query_active
= true;
2214 * Called when unbinding a color buffer.
2216 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2217 struct r600_texture
*tex
)
2219 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2220 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2222 assert(rctx
->dcc_stats
[i
].query_active
);
2223 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2225 /* pause or end the query */
2226 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2227 rctx
->dcc_stats
[i
].query_active
= false;
2230 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2232 /* The minimum number of fullscreen draws per frame that is required
2234 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2237 /* Called by fast clear. */
2238 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2239 struct r600_texture
*tex
)
2241 /* The intent is to use this with shared displayable back buffers,
2242 * but it's not strictly limited only to them.
2244 if (!tex
->resource
.b
.is_shared
||
2245 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2246 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2247 tex
->resource
.b
.b
.last_level
> 0 ||
2248 !tex
->surface
.dcc_size
)
2251 if (tex
->dcc_offset
)
2252 return; /* already enabled */
2254 /* Enable the DCC stat gathering. */
2255 if (!tex
->dcc_gather_statistics
) {
2256 tex
->dcc_gather_statistics
= true;
2257 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2260 if (!vi_should_enable_separate_dcc(tex
))
2261 return; /* stats show that DCC decompression is too expensive */
2263 assert(tex
->surface
.num_dcc_levels
);
2264 assert(!tex
->dcc_separate_buffer
);
2266 r600_texture_discard_cmask(rctx
->screen
, tex
);
2268 /* Get a DCC buffer. */
2269 if (tex
->last_dcc_separate_buffer
) {
2270 assert(tex
->dcc_gather_statistics
);
2271 assert(!tex
->dcc_separate_buffer
);
2272 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2273 tex
->last_dcc_separate_buffer
= NULL
;
2275 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2276 si_aligned_buffer_create(rctx
->b
.screen
,
2277 R600_RESOURCE_FLAG_UNMAPPABLE
,
2279 tex
->surface
.dcc_size
,
2280 tex
->surface
.dcc_alignment
);
2281 if (!tex
->dcc_separate_buffer
)
2285 /* dcc_offset is the absolute GPUVM address. */
2286 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2288 /* no need to flag anything since this is called by fast clear that
2289 * flags framebuffer state
2294 * Called by pipe_context::flush_resource, the place where DCC decompression
2297 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2298 struct r600_texture
*tex
)
2300 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2301 struct pipe_query
*tmp
;
2302 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2303 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2304 bool disable
= false;
2306 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2307 union pipe_query_result result
;
2309 /* Read the results. */
2310 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2312 si_query_hw_reset_buffers(rctx
,
2313 (struct r600_query_hw
*)
2314 rctx
->dcc_stats
[i
].ps_stats
[2]);
2316 /* Compute the approximate number of fullscreen draws. */
2317 tex
->ps_draw_ratio
=
2318 result
.pipeline_statistics
.ps_invocations
/
2319 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2320 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2322 disable
= tex
->dcc_separate_buffer
&&
2323 !vi_should_enable_separate_dcc(tex
);
2326 tex
->num_slow_clears
= 0;
2328 /* stop the statistics query for ps_stats[0] */
2330 vi_separate_dcc_stop_query(ctx
, tex
);
2332 /* Move the queries in the queue by one. */
2333 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2334 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2335 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2336 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2338 /* create and start a new query as ps_stats[0] */
2340 vi_separate_dcc_start_query(ctx
, tex
);
2343 assert(!tex
->last_dcc_separate_buffer
);
2344 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2345 tex
->dcc_separate_buffer
= NULL
;
2346 tex
->dcc_offset
= 0;
2347 /* no need to flag anything since this is called after
2348 * decompression that re-sets framebuffer state
2353 /* FAST COLOR CLEAR */
2355 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2356 enum pipe_format surface_format
,
2357 const union pipe_color_union
*color
)
2359 union util_color uc
;
2361 memset(&uc
, 0, sizeof(uc
));
2363 if (rtex
->surface
.bpe
== 16) {
2364 /* DCC fast clear only:
2365 * CLEAR_WORD0 = R = G = B
2368 assert(color
->ui
[0] == color
->ui
[1] &&
2369 color
->ui
[0] == color
->ui
[2]);
2370 uc
.ui
[0] = color
->ui
[0];
2371 uc
.ui
[1] = color
->ui
[3];
2372 } else if (util_format_is_pure_uint(surface_format
)) {
2373 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2374 } else if (util_format_is_pure_sint(surface_format
)) {
2375 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2377 util_pack_color(color
->f
, surface_format
, &uc
);
2380 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2383 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2384 const union pipe_color_union
*color
,
2385 uint32_t* reset_value
,
2386 bool* clear_words_needed
)
2388 bool values
[4] = {};
2390 bool main_value
= false;
2391 bool extra_value
= false;
2394 /* This is needed to get the correct DCC clear value for luminance formats.
2395 * 1) Get the linear format (because the next step can't handle L8_SRGB).
2396 * 2) Convert luminance to red. (the real hw format for luminance)
2398 surface_format
= util_format_linear(surface_format
);
2399 surface_format
= util_format_luminance_to_red(surface_format
);
2401 const struct util_format_description
*desc
= util_format_description(surface_format
);
2403 if (desc
->block
.bits
== 128 &&
2404 (color
->ui
[0] != color
->ui
[1] ||
2405 color
->ui
[0] != color
->ui
[2]))
2408 *clear_words_needed
= true;
2409 *reset_value
= 0x20202020U
;
2411 /* If we want to clear without needing a fast clear eliminate step, we
2412 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2413 * have two sets of flags, one for the last or first channel(extra) and
2414 * one for the other channels(main).
2417 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2418 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2419 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
||
2420 util_format_is_alpha(surface_format
)) {
2422 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2423 if(si_translate_colorswap(surface_format
, false) <= 1)
2424 extra_channel
= desc
->nr_channels
- 1;
2430 for (i
= 0; i
< 4; ++i
) {
2431 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2433 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2434 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2437 if (desc
->channel
[i
].pure_integer
&&
2438 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2439 /* Use the maximum value for clamping the clear color. */
2440 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2442 values
[i
] = color
->i
[i
] != 0;
2443 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2445 } else if (desc
->channel
[i
].pure_integer
&&
2446 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2447 /* Use the maximum value for clamping the clear color. */
2448 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2450 values
[i
] = color
->ui
[i
] != 0U;
2451 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2454 values
[i
] = color
->f
[i
] != 0.0F
;
2455 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2459 if (index
== extra_channel
)
2460 extra_value
= values
[i
];
2462 main_value
= values
[i
];
2465 for (int i
= 0; i
< 4; ++i
)
2466 if (values
[i
] != main_value
&&
2467 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2468 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2469 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2472 *clear_words_needed
= false;
2474 *reset_value
|= 0x80808080U
;
2477 *reset_value
|= 0x40404040U
;
2481 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2482 struct r600_texture
*rtex
,
2483 unsigned level
, unsigned clear_value
)
2485 struct pipe_resource
*dcc_buffer
;
2486 uint64_t dcc_offset
, clear_size
;
2488 assert(vi_dcc_enabled(rtex
, level
));
2490 if (rtex
->dcc_separate_buffer
) {
2491 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2494 dcc_buffer
= &rtex
->resource
.b
.b
;
2495 dcc_offset
= rtex
->dcc_offset
;
2498 if (rctx
->chip_class
>= GFX9
) {
2499 /* Mipmap level clears aren't implemented. */
2500 assert(rtex
->resource
.b
.b
.last_level
== 0);
2501 /* MSAA needs a different clear size. */
2502 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
2503 clear_size
= rtex
->surface
.dcc_size
;
2505 dcc_offset
+= rtex
->surface
.u
.legacy
.level
[level
].dcc_offset
;
2506 clear_size
= rtex
->surface
.u
.legacy
.level
[level
].dcc_fast_clear_size
;
2509 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
, clear_size
,
2510 clear_value
, R600_COHERENCY_CB_META
);
2513 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2514 * This allows hitting the MSAA resolve fast path, which requires that both
2515 * src and dst micro tile modes match.
2517 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2518 struct r600_texture
*rtex
)
2520 if (rtex
->resource
.b
.is_shared
||
2521 rtex
->resource
.b
.b
.nr_samples
<= 1 ||
2522 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2525 assert(rscreen
->chip_class
>= GFX9
||
2526 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2527 assert(rtex
->resource
.b
.b
.last_level
== 0);
2529 if (rscreen
->chip_class
>= GFX9
) {
2530 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
2531 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
>= 4);
2533 /* If you do swizzle_mode % 4, you'll get:
2539 * Depth-sample order isn't allowed:
2541 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
% 4 != 0);
2543 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2544 case RADEON_MICRO_MODE_DISPLAY
:
2545 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2546 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 2; /* D */
2548 case RADEON_MICRO_MODE_THIN
:
2549 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2550 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 1; /* S */
2552 case RADEON_MICRO_MODE_ROTATED
:
2553 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2554 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 3; /* R */
2556 default: /* depth */
2557 assert(!"unexpected micro mode");
2560 } else if (rscreen
->chip_class
>= CIK
) {
2561 /* These magic numbers were copied from addrlib. It doesn't use
2562 * any definitions for them either. They are all 2D_TILED_THIN1
2563 * modes with different bpp and micro tile mode.
2565 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2566 case RADEON_MICRO_MODE_DISPLAY
:
2567 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2569 case RADEON_MICRO_MODE_THIN
:
2570 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2572 case RADEON_MICRO_MODE_ROTATED
:
2573 rtex
->surface
.u
.legacy
.tiling_index
[0] = 28;
2575 default: /* depth, thick */
2576 assert(!"unexpected micro mode");
2580 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2581 case RADEON_MICRO_MODE_DISPLAY
:
2582 switch (rtex
->surface
.bpe
) {
2584 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2587 rtex
->surface
.u
.legacy
.tiling_index
[0] = 11;
2590 rtex
->surface
.u
.legacy
.tiling_index
[0] = 12;
2594 case RADEON_MICRO_MODE_THIN
:
2595 switch (rtex
->surface
.bpe
) {
2597 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2600 rtex
->surface
.u
.legacy
.tiling_index
[0] = 15;
2603 rtex
->surface
.u
.legacy
.tiling_index
[0] = 16;
2605 default: /* 8, 16 */
2606 rtex
->surface
.u
.legacy
.tiling_index
[0] = 17;
2610 default: /* depth, thick */
2611 assert(!"unexpected micro mode");
2616 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2618 p_atomic_inc(&rscreen
->dirty_tex_counter
);
2621 void si_do_fast_color_clear(struct r600_common_context
*rctx
,
2622 struct pipe_framebuffer_state
*fb
,
2623 struct r600_atom
*fb_state
,
2624 unsigned *buffers
, ubyte
*dirty_cbufs
,
2625 const union pipe_color_union
*color
)
2629 /* This function is broken in BE, so just disable this path for now */
2630 #ifdef PIPE_ARCH_BIG_ENDIAN
2634 if (rctx
->render_cond
)
2637 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2638 struct r600_texture
*tex
;
2639 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2644 /* if this colorbuffer is not being cleared */
2645 if (!(*buffers
& clear_bit
))
2648 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2650 /* the clear is allowed if all layers are bound */
2651 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2652 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2656 /* cannot clear mipmapped textures */
2657 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2661 /* only supported on tiled surfaces */
2662 if (tex
->surface
.is_linear
) {
2666 /* shared textures can't use fast clear without an explicit flush,
2667 * because there is no way to communicate the clear color among
2670 if (tex
->resource
.b
.is_shared
&&
2671 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2674 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2675 if (rctx
->chip_class
== CIK
&&
2676 tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2677 rctx
->screen
->info
.drm_major
== 2 &&
2678 rctx
->screen
->info
.drm_minor
< 38) {
2682 /* Fast clear is the most appropriate place to enable DCC for
2683 * displayable surfaces.
2685 if (rctx
->chip_class
>= VI
&&
2686 !(rctx
->screen
->debug_flags
& DBG(NO_DCC_FB
))) {
2687 vi_separate_dcc_try_enable(rctx
, tex
);
2689 /* RB+ isn't supported with a CMASK clear only on Stoney,
2690 * so all clears are considered to be hypothetically slow
2691 * clears, which is weighed when determining whether to
2692 * enable separate DCC.
2694 if (tex
->dcc_gather_statistics
&&
2695 rctx
->family
== CHIP_STONEY
)
2696 tex
->num_slow_clears
++;
2699 /* Try to clear DCC first, otherwise try CMASK. */
2700 if (vi_dcc_enabled(tex
, 0)) {
2701 uint32_t reset_value
;
2702 bool clear_words_needed
;
2704 if (rctx
->screen
->debug_flags
& DBG(NO_DCC_CLEAR
))
2707 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2708 color
, &reset_value
,
2709 &clear_words_needed
))
2712 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2714 unsigned level_bit
= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2715 if (clear_words_needed
) {
2716 bool need_compressed_update
= !tex
->dirty_level_mask
;
2718 tex
->dirty_level_mask
|= level_bit
;
2720 if (need_compressed_update
)
2721 p_atomic_inc(&rctx
->screen
->compressed_colortex_counter
);
2723 tex
->separate_dcc_dirty
= true;
2725 /* 128-bit formats are unusupported */
2726 if (tex
->surface
.bpe
> 8) {
2730 /* RB+ doesn't work with CMASK fast clear on Stoney. */
2731 if (rctx
->family
== CHIP_STONEY
)
2734 /* ensure CMASK is enabled */
2735 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2736 if (tex
->cmask
.size
== 0) {
2740 /* Do the fast clear. */
2741 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2742 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2743 R600_COHERENCY_CB_META
);
2745 bool need_compressed_update
= !tex
->dirty_level_mask
;
2747 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2749 if (need_compressed_update
)
2750 p_atomic_inc(&rctx
->screen
->compressed_colortex_counter
);
2753 /* We can change the micro tile mode before a full clear. */
2754 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2756 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2759 *dirty_cbufs
|= 1 << i
;
2760 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2761 *buffers
&= ~clear_bit
;
2765 static struct pipe_memory_object
*
2766 r600_memobj_from_handle(struct pipe_screen
*screen
,
2767 struct winsys_handle
*whandle
,
2770 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
2771 struct r600_memory_object
*memobj
= CALLOC_STRUCT(r600_memory_object
);
2772 struct pb_buffer
*buf
= NULL
;
2773 uint32_t stride
, offset
;
2778 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
,
2785 memobj
->b
.dedicated
= dedicated
;
2787 memobj
->stride
= stride
;
2788 memobj
->offset
= offset
;
2790 return (struct pipe_memory_object
*)memobj
;
2795 r600_memobj_destroy(struct pipe_screen
*screen
,
2796 struct pipe_memory_object
*_memobj
)
2798 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2800 pb_reference(&memobj
->buf
, NULL
);
2804 static struct pipe_resource
*
2805 r600_texture_from_memobj(struct pipe_screen
*screen
,
2806 const struct pipe_resource
*templ
,
2807 struct pipe_memory_object
*_memobj
,
2811 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
2812 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2813 struct r600_texture
*rtex
;
2814 struct radeon_surf surface
= {};
2815 struct radeon_bo_metadata metadata
= {};
2816 enum radeon_surf_mode array_mode
;
2818 struct pb_buffer
*buf
= NULL
;
2820 if (memobj
->b
.dedicated
) {
2821 rscreen
->ws
->buffer_get_metadata(memobj
->buf
, &metadata
);
2822 r600_surface_import_metadata(rscreen
, &surface
, &metadata
,
2823 &array_mode
, &is_scanout
);
2826 * The bo metadata is unset for un-dedicated images. So we fall
2827 * back to linear. See answer to question 5 of the
2828 * VK_KHX_external_memory spec for some details.
2830 * It is possible that this case isn't going to work if the
2831 * surface pitch isn't correctly aligned by default.
2833 * In order to support it correctly we require multi-image
2834 * metadata to be syncrhonized between radv and radeonsi. The
2835 * semantics of associating multiple image metadata to a memory
2836 * object on the vulkan export side are not concretely defined
2839 * All the use cases we are aware of at the moment for memory
2840 * objects use dedicated allocations. So lets keep the initial
2841 * implementation simple.
2843 * A possible alternative is to attempt to reconstruct the
2844 * tiling information when the TexParameter TEXTURE_TILING_EXT
2847 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
2852 r
= r600_init_surface(rscreen
, &surface
, templ
,
2853 array_mode
, memobj
->stride
,
2854 offset
, true, is_scanout
,
2859 rtex
= r600_texture_create_object(screen
, templ
, memobj
->buf
, &surface
);
2863 /* r600_texture_create_object doesn't increment refcount of
2864 * memobj->buf, so increment it here.
2866 pb_reference(&buf
, memobj
->buf
);
2868 rtex
->resource
.b
.is_shared
= true;
2869 rtex
->resource
.external_usage
= PIPE_HANDLE_USAGE_READ_WRITE
;
2871 if (rscreen
->apply_opaque_metadata
)
2872 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
2874 return &rtex
->resource
.b
.b
;
2877 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2878 struct pipe_resource
*resource
,
2881 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
2883 /* Buffers only support the linear flag. */
2884 if (resource
->target
== PIPE_BUFFER
)
2885 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2887 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2890 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2893 /* TODO: PIPE_BIND_CURSOR - do we care? */
2897 void si_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2899 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2900 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2901 rscreen
->b
.resource_from_memobj
= r600_texture_from_memobj
;
2902 rscreen
->b
.memobj_create_from_handle
= r600_memobj_from_handle
;
2903 rscreen
->b
.memobj_destroy
= r600_memobj_destroy
;
2904 rscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2907 void si_init_context_texture_functions(struct r600_common_context
*rctx
)
2909 rctx
->b
.create_surface
= r600_create_surface
;
2910 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2911 rctx
->b
.clear_texture
= r600_clear_texture
;