2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static enum radeon_surf_mode
41 r600_choose_tiling(struct r600_common_screen
*rscreen
,
42 const struct pipe_resource
*templ
);
45 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
46 struct r600_texture
*rdst
,
47 unsigned dst_level
, unsigned dstx
,
48 unsigned dsty
, unsigned dstz
,
49 struct r600_texture
*rsrc
,
51 const struct pipe_box
*src_box
)
56 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
59 /* MSAA: Blits don't exist in the real world. */
60 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
61 rdst
->resource
.b
.b
.nr_samples
> 1)
64 /* Depth-stencil surfaces:
65 * When dst is linear, the DB->CB copy preserves HTILE.
66 * When dst is tiled, the 3D path must be used to update HTILE.
68 if (rsrc
->is_depth
|| rdst
->is_depth
)
72 * src: Use the 3D path. DCC decompression is expensive.
73 * dst: Use the 3D path to compress the pixels with DCC.
75 if (vi_dcc_enabled(rsrc
, src_level
) ||
76 vi_dcc_enabled(rdst
, dst_level
))
80 * src: Both texture and SDMA paths need decompression. Use SDMA.
81 * dst: If overwriting the whole texture, discard CMASK and use
82 * SDMA. Otherwise, use the 3D path.
84 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
85 /* The CMASK clear is only enabled for the first level. */
86 assert(dst_level
== 0);
87 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
88 dstx
, dsty
, dstz
, src_box
->width
,
89 src_box
->height
, src_box
->depth
))
92 r600_texture_discard_cmask(rctx
->screen
, rdst
);
95 /* All requirements are met. Prepare textures for SDMA. */
96 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
97 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
99 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
100 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
105 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
106 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
107 struct pipe_resource
*dst
,
109 unsigned dstx
, unsigned dsty
, unsigned dstz
,
110 struct pipe_resource
*src
,
112 const struct pipe_box
*src_box
)
114 struct pipe_blit_info blit
;
116 memset(&blit
, 0, sizeof(blit
));
117 blit
.src
.resource
= src
;
118 blit
.src
.format
= src
->format
;
119 blit
.src
.level
= src_level
;
120 blit
.src
.box
= *src_box
;
121 blit
.dst
.resource
= dst
;
122 blit
.dst
.format
= dst
->format
;
123 blit
.dst
.level
= dst_level
;
124 blit
.dst
.box
.x
= dstx
;
125 blit
.dst
.box
.y
= dsty
;
126 blit
.dst
.box
.z
= dstz
;
127 blit
.dst
.box
.width
= src_box
->width
;
128 blit
.dst
.box
.height
= src_box
->height
;
129 blit
.dst
.box
.depth
= src_box
->depth
;
130 blit
.mask
= util_format_get_mask(src
->format
) &
131 util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
142 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
144 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1) {
148 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
160 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1) {
169 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
176 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
180 static unsigned r600_texture_get_offset(struct r600_common_screen
*rscreen
,
181 struct r600_texture
*rtex
, unsigned level
,
182 const struct pipe_box
*box
,
184 unsigned *layer_stride
)
186 if (rscreen
->chip_class
>= GFX9
) {
187 *stride
= rtex
->surface
.u
.gfx9
.surf_pitch
* rtex
->surface
.bpe
;
188 *layer_stride
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
193 /* Each texture is an array of slices. Each slice is an array
194 * of mipmap levels. */
195 return box
->z
* rtex
->surface
.u
.gfx9
.surf_slice_size
+
196 rtex
->surface
.u
.gfx9
.offset
[level
] +
197 (box
->y
/ rtex
->surface
.blk_h
*
198 rtex
->surface
.u
.gfx9
.surf_pitch
+
199 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
201 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
203 *layer_stride
= rtex
->surface
.u
.legacy
.level
[level
].slice_size
;
206 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
208 /* Each texture is an array of mipmap levels. Each level is
209 * an array of slices. */
210 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
211 box
->z
* rtex
->surface
.u
.legacy
.level
[level
].slice_size
+
212 (box
->y
/ rtex
->surface
.blk_h
*
213 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
214 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
218 static int r600_init_surface(struct r600_common_screen
*rscreen
,
219 struct radeon_surf
*surface
,
220 const struct pipe_resource
*ptex
,
221 enum radeon_surf_mode array_mode
,
222 unsigned pitch_in_bytes_override
,
226 bool is_flushed_depth
,
227 bool tc_compatible_htile
)
229 const struct util_format_description
*desc
=
230 util_format_description(ptex
->format
);
231 bool is_depth
, is_stencil
;
233 unsigned i
, bpe
, flags
= 0;
235 is_depth
= util_format_has_depth(desc
);
236 is_stencil
= util_format_has_stencil(desc
);
238 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
239 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
240 bpe
= 4; /* stencil is allocated separately on evergreen */
242 bpe
= util_format_get_blocksize(ptex
->format
);
243 assert(util_is_power_of_two(bpe
));
246 if (!is_flushed_depth
&& is_depth
) {
247 flags
|= RADEON_SURF_ZBUFFER
;
249 if (tc_compatible_htile
&&
250 (rscreen
->chip_class
>= GFX9
||
251 array_mode
== RADEON_SURF_MODE_2D
)) {
252 /* TC-compatible HTILE only supports Z32_FLOAT.
253 * GFX9 also supports Z16_UNORM.
254 * On VI, promote Z16 to Z32. DB->CB copies will convert
255 * the format for transfers.
257 if (rscreen
->chip_class
== VI
)
260 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
264 flags
|= RADEON_SURF_SBUFFER
;
267 if (rscreen
->chip_class
>= VI
&&
268 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
269 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
270 flags
|= RADEON_SURF_DISABLE_DCC
;
272 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
273 /* This should catch bugs in gallium users setting incorrect flags. */
274 assert(ptex
->nr_samples
<= 1 &&
275 ptex
->array_size
== 1 &&
277 ptex
->last_level
== 0 &&
278 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
280 flags
|= RADEON_SURF_SCANOUT
;
284 flags
|= RADEON_SURF_IMPORTED
;
285 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
286 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
288 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
289 array_mode
, surface
);
294 if (rscreen
->chip_class
>= GFX9
) {
295 assert(!pitch_in_bytes_override
||
296 pitch_in_bytes_override
== surface
->u
.gfx9
.surf_pitch
* bpe
);
297 surface
->u
.gfx9
.surf_offset
= offset
;
299 if (pitch_in_bytes_override
&&
300 pitch_in_bytes_override
!= surface
->u
.legacy
.level
[0].nblk_x
* bpe
) {
301 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
304 surface
->u
.legacy
.level
[0].nblk_x
= pitch_in_bytes_override
/ bpe
;
305 surface
->u
.legacy
.level
[0].slice_size
= pitch_in_bytes_override
*
306 surface
->u
.legacy
.level
[0].nblk_y
;
310 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
311 surface
->u
.legacy
.level
[i
].offset
+= offset
;
317 static void r600_texture_init_metadata(struct r600_common_screen
*rscreen
,
318 struct r600_texture
*rtex
,
319 struct radeon_bo_metadata
*metadata
)
321 struct radeon_surf
*surface
= &rtex
->surface
;
323 memset(metadata
, 0, sizeof(*metadata
));
325 if (rscreen
->chip_class
>= GFX9
) {
326 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
328 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
329 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
330 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
331 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
332 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
333 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
334 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
335 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
336 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
337 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
338 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
339 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
343 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
344 struct r600_texture
*rtex
)
346 struct r600_common_screen
*rscreen
= rctx
->screen
;
347 struct pipe_context
*ctx
= &rctx
->b
;
349 if (ctx
== rscreen
->aux_context
)
350 mtx_lock(&rscreen
->aux_context_lock
);
352 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
353 ctx
->flush(ctx
, NULL
, 0);
355 if (ctx
== rscreen
->aux_context
)
356 mtx_unlock(&rscreen
->aux_context_lock
);
359 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
360 struct r600_texture
*rtex
)
362 if (!rtex
->cmask
.size
)
365 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
368 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
369 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
370 rtex
->dirty_level_mask
= 0;
372 if (rscreen
->chip_class
>= SI
)
373 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
375 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
377 if (rtex
->cmask_buffer
!= &rtex
->resource
)
378 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
380 /* Notify all contexts about the change. */
381 p_atomic_inc(&rscreen
->dirty_tex_counter
);
382 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
385 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
387 /* We can't disable DCC if it can be written by another process. */
388 return rtex
->dcc_offset
&&
389 (!rtex
->resource
.b
.is_shared
||
390 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
393 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
394 struct r600_texture
*rtex
)
396 if (!r600_can_disable_dcc(rtex
))
399 assert(rtex
->dcc_separate_buffer
== NULL
);
402 rtex
->dcc_offset
= 0;
404 /* Notify all contexts about the change. */
405 p_atomic_inc(&rscreen
->dirty_tex_counter
);
410 * Disable DCC for the texture. (first decompress, then discard metadata).
412 * There is unresolved multi-context synchronization issue between
413 * screen::aux_context and the current context. If applications do this with
414 * multiple contexts, it's already undefined behavior for them and we don't
415 * have to worry about that. The scenario is:
417 * If context 1 disables DCC and context 2 has queued commands that write
418 * to the texture via CB with DCC enabled, and the order of operations is
420 * context 2 queues draw calls rendering to the texture, but doesn't flush
421 * context 1 disables DCC and flushes
422 * context 1 & 2 reset descriptors and FB state
423 * context 2 flushes (new compressed tiles written by the draw calls)
424 * context 1 & 2 read garbage, because DCC is disabled, yet there are
427 * \param rctx the current context if you have one, or rscreen->aux_context
430 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
431 struct r600_texture
*rtex
)
433 struct r600_common_screen
*rscreen
= rctx
->screen
;
435 if (!r600_can_disable_dcc(rtex
))
438 if (&rctx
->b
== rscreen
->aux_context
)
439 mtx_lock(&rscreen
->aux_context_lock
);
441 /* Decompress DCC. */
442 rctx
->decompress_dcc(&rctx
->b
, rtex
);
443 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
445 if (&rctx
->b
== rscreen
->aux_context
)
446 mtx_unlock(&rscreen
->aux_context_lock
);
448 return r600_texture_discard_dcc(rscreen
, rtex
);
451 static void r600_reallocate_texture_inplace(struct r600_common_context
*rctx
,
452 struct r600_texture
*rtex
,
453 unsigned new_bind_flag
,
454 bool invalidate_storage
)
456 struct pipe_screen
*screen
= rctx
->b
.screen
;
457 struct r600_texture
*new_tex
;
458 struct pipe_resource templ
= rtex
->resource
.b
.b
;
461 templ
.bind
|= new_bind_flag
;
463 /* r600g doesn't react to dirty_tex_descriptor_counter */
464 if (rctx
->chip_class
< SI
)
467 if (rtex
->resource
.b
.is_shared
)
470 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
471 if (rtex
->surface
.is_linear
)
474 /* This fails with MSAA, depth, and compressed textures. */
475 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
476 RADEON_SURF_MODE_LINEAR_ALIGNED
)
480 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
484 /* Copy the pixels to the new texture. */
485 if (!invalidate_storage
) {
486 for (i
= 0; i
<= templ
.last_level
; i
++) {
490 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
491 util_max_layer(&templ
, i
) + 1, &box
);
493 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
494 &rtex
->resource
.b
.b
, i
, &box
);
498 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
499 r600_texture_discard_cmask(rctx
->screen
, rtex
);
500 r600_texture_discard_dcc(rctx
->screen
, rtex
);
503 /* Replace the structure fields of rtex. */
504 rtex
->resource
.b
.b
.bind
= templ
.bind
;
505 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
506 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
507 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
508 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
509 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
510 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
511 rtex
->resource
.domains
= new_tex
->resource
.domains
;
512 rtex
->resource
.flags
= new_tex
->resource
.flags
;
513 rtex
->size
= new_tex
->size
;
514 rtex
->db_render_format
= new_tex
->db_render_format
;
515 rtex
->db_compatible
= new_tex
->db_compatible
;
516 rtex
->can_sample_z
= new_tex
->can_sample_z
;
517 rtex
->can_sample_s
= new_tex
->can_sample_s
;
518 rtex
->surface
= new_tex
->surface
;
519 rtex
->fmask
= new_tex
->fmask
;
520 rtex
->cmask
= new_tex
->cmask
;
521 rtex
->cb_color_info
= new_tex
->cb_color_info
;
522 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
523 rtex
->htile_offset
= new_tex
->htile_offset
;
524 rtex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
525 rtex
->depth_cleared
= new_tex
->depth_cleared
;
526 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
527 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
528 rtex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
529 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
531 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
532 assert(!rtex
->htile_offset
);
533 assert(!rtex
->cmask
.size
);
534 assert(!rtex
->fmask
.size
);
535 assert(!rtex
->dcc_offset
);
536 assert(!rtex
->is_depth
);
539 r600_texture_reference(&new_tex
, NULL
);
541 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
544 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
545 struct pipe_context
*ctx
,
546 struct pipe_resource
*resource
,
547 struct winsys_handle
*whandle
,
550 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
551 struct r600_common_context
*rctx
;
552 struct r600_resource
*res
= (struct r600_resource
*)resource
;
553 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
554 struct radeon_bo_metadata metadata
;
555 bool update_metadata
= false;
556 unsigned stride
, offset
, slice_size
;
558 ctx
= threaded_context_unwrap_sync(ctx
);
559 rctx
= (struct r600_common_context
*)(ctx
? ctx
: rscreen
->aux_context
);
561 if (resource
->target
!= PIPE_BUFFER
) {
562 /* This is not supported now, but it might be required for OpenCL
563 * interop in the future.
565 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
568 /* Move a suballocated texture into a non-suballocated allocation. */
569 if (rscreen
->ws
->buffer_is_suballocated(res
->buf
)) {
570 assert(!res
->b
.is_shared
);
571 r600_reallocate_texture_inplace(rctx
, rtex
,
572 PIPE_BIND_SHARED
, false);
573 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
574 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
577 /* Since shader image stores don't support DCC on VI,
578 * disable it for external clients that want write
581 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
582 if (r600_texture_disable_dcc(rctx
, rtex
))
583 update_metadata
= true;
586 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
587 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
588 /* Eliminate fast clear (both CMASK and DCC) */
589 r600_eliminate_fast_color_clear(rctx
, rtex
);
591 /* Disable CMASK if flush_resource isn't going
594 if (rtex
->cmask
.size
)
595 r600_texture_discard_cmask(rscreen
, rtex
);
599 if (!res
->b
.is_shared
|| update_metadata
) {
600 r600_texture_init_metadata(rscreen
, rtex
, &metadata
);
601 if (rscreen
->query_opaque_metadata
)
602 rscreen
->query_opaque_metadata(rscreen
, rtex
,
605 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
608 if (rscreen
->chip_class
>= GFX9
) {
609 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
610 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
612 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
614 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
615 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
617 slice_size
= rtex
->surface
.u
.legacy
.level
[0].slice_size
;
626 if (res
->b
.is_shared
) {
627 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
630 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
631 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
632 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
634 res
->b
.is_shared
= true;
635 res
->external_usage
= usage
;
638 return rscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
639 slice_size
, whandle
);
642 static void r600_texture_destroy(struct pipe_screen
*screen
,
643 struct pipe_resource
*ptex
)
645 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
646 struct r600_resource
*resource
= &rtex
->resource
;
648 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
650 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
651 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
653 pb_reference(&resource
->buf
, NULL
);
654 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
655 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
659 static const struct u_resource_vtbl r600_texture_vtbl
;
661 /* The number of samples can be specified independently of the texture. */
662 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
663 struct r600_texture
*rtex
,
665 struct r600_fmask_info
*out
)
667 /* FMASK is allocated like an ordinary texture. */
668 struct pipe_resource templ
= rtex
->resource
.b
.b
;
669 struct radeon_surf fmask
= {};
672 memset(out
, 0, sizeof(*out
));
674 if (rscreen
->chip_class
>= GFX9
) {
675 out
->alignment
= rtex
->surface
.u
.gfx9
.fmask_alignment
;
676 out
->size
= rtex
->surface
.u
.gfx9
.fmask_size
;
680 templ
.nr_samples
= 1;
681 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
683 if (rscreen
->chip_class
<= CAYMAN
) {
684 /* Use the same parameters and tile mode. */
685 fmask
.u
.legacy
.bankw
= rtex
->surface
.u
.legacy
.bankw
;
686 fmask
.u
.legacy
.bankh
= rtex
->surface
.u
.legacy
.bankh
;
687 fmask
.u
.legacy
.mtilea
= rtex
->surface
.u
.legacy
.mtilea
;
688 fmask
.u
.legacy
.tile_split
= rtex
->surface
.u
.legacy
.tile_split
;
691 fmask
.u
.legacy
.bankh
= 4;
694 switch (nr_samples
) {
703 R600_ERR("Invalid sample count for FMASK allocation.\n");
707 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
708 * This can be fixed by writing a separate FMASK allocator specifically
709 * for R600-R700 asics. */
710 if (rscreen
->chip_class
<= R700
) {
714 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
715 RADEON_SURF_MODE_2D
, &fmask
)) {
716 R600_ERR("Got error in surface_init while allocating FMASK.\n");
720 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
722 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
723 if (out
->slice_tile_max
)
724 out
->slice_tile_max
-= 1;
726 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
727 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
728 out
->bank_height
= fmask
.u
.legacy
.bankh
;
729 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
730 out
->size
= fmask
.surf_size
;
733 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
734 struct r600_texture
*rtex
)
736 r600_texture_get_fmask_info(rscreen
, rtex
,
737 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
739 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
740 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
743 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
744 struct r600_texture
*rtex
,
745 struct r600_cmask_info
*out
)
747 unsigned cmask_tile_width
= 8;
748 unsigned cmask_tile_height
= 8;
749 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
750 unsigned element_bits
= 4;
751 unsigned cmask_cache_bits
= 1024;
752 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
753 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
755 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
756 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
757 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
758 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
759 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
761 unsigned pitch_elements
= align(rtex
->resource
.b
.b
.width0
, macro_tile_width
);
762 unsigned height
= align(rtex
->resource
.b
.b
.height0
, macro_tile_height
);
764 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
765 unsigned slice_bytes
=
766 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
768 assert(macro_tile_width
% 128 == 0);
769 assert(macro_tile_height
% 128 == 0);
771 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
772 out
->alignment
= MAX2(256, base_align
);
773 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
774 align(slice_bytes
, base_align
);
777 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
778 struct r600_texture
*rtex
,
779 struct r600_cmask_info
*out
)
781 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
782 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
783 unsigned cl_width
, cl_height
;
785 if (rscreen
->chip_class
>= GFX9
) {
786 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
787 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
804 case 16: /* Hawaii */
813 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
815 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
816 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
817 unsigned slice_elements
= (width
* height
) / (8*8);
819 /* Each element of CMASK is a nibble. */
820 unsigned slice_bytes
= slice_elements
/ 2;
822 out
->slice_tile_max
= (width
* height
) / (128*128);
823 if (out
->slice_tile_max
)
824 out
->slice_tile_max
-= 1;
826 out
->alignment
= MAX2(256, base_align
);
827 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
828 align(slice_bytes
, base_align
);
831 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
832 struct r600_texture
*rtex
)
834 if (rscreen
->chip_class
>= SI
) {
835 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
837 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
840 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
841 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
843 if (rscreen
->chip_class
>= SI
)
844 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
846 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
849 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
850 struct r600_texture
*rtex
)
852 if (rtex
->cmask_buffer
)
855 assert(rtex
->cmask
.size
== 0);
857 if (rscreen
->chip_class
>= SI
) {
858 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
860 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
863 rtex
->cmask_buffer
= (struct r600_resource
*)
864 r600_aligned_buffer_create(&rscreen
->b
,
865 R600_RESOURCE_FLAG_UNMAPPABLE
,
868 rtex
->cmask
.alignment
);
869 if (rtex
->cmask_buffer
== NULL
) {
870 rtex
->cmask
.size
= 0;
874 /* update colorbuffer state bits */
875 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
877 if (rscreen
->chip_class
>= SI
)
878 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
880 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
882 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
885 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
886 struct r600_texture
*rtex
)
888 unsigned cl_width
, cl_height
, width
, height
;
889 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
890 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
892 assert(rscreen
->chip_class
<= VI
);
894 rtex
->surface
.htile_size
= 0;
896 if (rscreen
->chip_class
<= EVERGREEN
&&
897 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
900 /* HW bug on R6xx. */
901 if (rscreen
->chip_class
== R600
&&
902 (rtex
->resource
.b
.b
.width0
> 7680 ||
903 rtex
->resource
.b
.b
.height0
> 7680))
906 /* HTILE is broken with 1D tiling on old kernels and CIK. */
907 if (rscreen
->chip_class
>= CIK
&&
908 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
909 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
912 /* Overalign HTILE on P2 configs to work around GPU hangs in
913 * piglit/depthstencil-render-miplevels 585.
915 * This has been confirmed to help Kabini & Stoney, where the hangs
916 * are always reproducible. I think I have seen the test hang
917 * on Carrizo too, though it was very rare there.
919 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
948 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
949 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
951 slice_elements
= (width
* height
) / (8 * 8);
952 slice_bytes
= slice_elements
* 4;
954 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
955 base_align
= num_pipes
* pipe_interleave_bytes
;
957 rtex
->surface
.htile_alignment
= base_align
;
958 rtex
->surface
.htile_size
=
959 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
960 align(slice_bytes
, base_align
);
963 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
964 struct r600_texture
*rtex
)
966 if (rscreen
->chip_class
<= VI
&& !rtex
->tc_compatible_htile
)
967 r600_texture_get_htile_size(rscreen
, rtex
);
969 if (!rtex
->surface
.htile_size
)
972 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
973 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
976 void r600_print_texture_info(struct r600_common_screen
*rscreen
,
977 struct r600_texture
*rtex
, FILE *f
)
981 /* Common parameters. */
982 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
983 "blk_h=%u, array_size=%u, last_level=%u, "
984 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
985 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
986 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
988 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
989 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
990 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
992 if (rscreen
->chip_class
>= GFX9
) {
993 fprintf(f
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
994 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
995 rtex
->surface
.surf_size
,
996 rtex
->surface
.u
.gfx9
.surf_slice_size
,
997 rtex
->surface
.surf_alignment
,
998 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
999 rtex
->surface
.u
.gfx9
.surf
.epitch
,
1000 rtex
->surface
.u
.gfx9
.surf_pitch
);
1002 if (rtex
->fmask
.size
) {
1003 fprintf(f
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1004 "alignment=%u, swmode=%u, epitch=%u\n",
1006 rtex
->surface
.u
.gfx9
.fmask_size
,
1007 rtex
->surface
.u
.gfx9
.fmask_alignment
,
1008 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1009 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
1012 if (rtex
->cmask
.size
) {
1013 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
1014 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1016 rtex
->surface
.u
.gfx9
.cmask_size
,
1017 rtex
->surface
.u
.gfx9
.cmask_alignment
,
1018 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1019 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1022 if (rtex
->htile_offset
) {
1023 fprintf(f
, " HTile: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1024 "rb_aligned=%u, pipe_aligned=%u\n",
1026 rtex
->surface
.htile_size
,
1027 rtex
->surface
.htile_alignment
,
1028 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1029 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1032 if (rtex
->dcc_offset
) {
1033 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", "
1034 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1035 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1036 rtex
->surface
.dcc_alignment
,
1037 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
1038 rtex
->surface
.num_dcc_levels
);
1041 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
1042 fprintf(f
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1043 rtex
->surface
.u
.gfx9
.stencil_offset
,
1044 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1045 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1050 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1051 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1052 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1053 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1054 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1055 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1057 if (rtex
->fmask
.size
)
1058 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1059 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1060 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
1061 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
1062 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
1064 if (rtex
->cmask
.size
)
1065 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1066 "slice_tile_max=%u\n",
1067 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1068 rtex
->cmask
.slice_tile_max
);
1070 if (rtex
->htile_offset
)
1071 fprintf(f
, " HTile: offset=%"PRIu64
", size=%"PRIu64
", "
1072 "alignment=%u, TC_compatible = %u\n",
1073 rtex
->htile_offset
, rtex
->surface
.htile_size
,
1074 rtex
->surface
.htile_alignment
,
1075 rtex
->tc_compatible_htile
);
1077 if (rtex
->dcc_offset
) {
1078 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u\n",
1079 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1080 rtex
->surface
.dcc_alignment
);
1081 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1082 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
1083 "fast_clear_size=%"PRIu64
"\n",
1084 i
, i
< rtex
->surface
.num_dcc_levels
,
1085 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1086 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1089 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1090 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1091 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1092 "mode=%u, tiling_index = %u\n",
1093 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1094 rtex
->surface
.u
.legacy
.level
[i
].slice_size
,
1095 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1096 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1097 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1098 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1099 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1100 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1101 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1103 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1104 fprintf(f
, " StencilLayout: tilesplit=%u\n",
1105 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1106 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
1107 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
1108 "slice_size=%"PRIu64
", npix_x=%u, "
1109 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1110 "mode=%u, tiling_index = %u\n",
1111 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1112 rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size
,
1113 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1114 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1115 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1116 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1117 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1118 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1119 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1124 /* Common processing for r600_texture_create and r600_texture_from_handle */
1125 static struct r600_texture
*
1126 r600_texture_create_object(struct pipe_screen
*screen
,
1127 const struct pipe_resource
*base
,
1128 struct pb_buffer
*buf
,
1129 struct radeon_surf
*surface
)
1131 struct r600_texture
*rtex
;
1132 struct r600_resource
*resource
;
1133 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1135 rtex
= CALLOC_STRUCT(r600_texture
);
1139 resource
= &rtex
->resource
;
1140 resource
->b
.b
= *base
;
1141 resource
->b
.b
.next
= NULL
;
1142 resource
->b
.vtbl
= &r600_texture_vtbl
;
1143 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1144 resource
->b
.b
.screen
= screen
;
1146 /* don't include stencil-only formats which we don't support for rendering */
1147 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1149 rtex
->surface
= *surface
;
1150 rtex
->size
= rtex
->surface
.surf_size
;
1152 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1153 (rtex
->surface
.flags
&
1154 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1156 /* TC-compatible HTILE:
1157 * - VI only supports Z32_FLOAT.
1158 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1159 if (rtex
->tc_compatible_htile
) {
1160 if (rscreen
->chip_class
>= GFX9
&&
1161 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1162 rtex
->db_render_format
= base
->format
;
1164 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1166 rtex
->db_render_format
= base
->format
;
1169 /* Tiled depth textures utilize the non-displayable tile order.
1170 * This must be done after r600_setup_surface.
1171 * Applies to R600-Cayman. */
1172 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1173 /* Applies to GCN. */
1174 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1176 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1177 * between frames, so the only thing that can enable separate DCC
1178 * with DRI2 is multiple slow clears within a frame.
1180 rtex
->ps_draw_ratio
= 0;
1182 if (rtex
->is_depth
) {
1183 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1184 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1185 rscreen
->chip_class
>= EVERGREEN
) {
1186 if (rscreen
->chip_class
>= GFX9
) {
1187 rtex
->can_sample_z
= true;
1188 rtex
->can_sample_s
= true;
1190 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1191 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1194 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1195 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1196 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1197 rtex
->can_sample_z
= true;
1200 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1201 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1202 rtex
->db_compatible
= true;
1204 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1205 r600_texture_allocate_htile(rscreen
, rtex
);
1208 if (base
->nr_samples
> 1) {
1210 r600_texture_allocate_fmask(rscreen
, rtex
);
1211 r600_texture_allocate_cmask(rscreen
, rtex
);
1212 rtex
->cmask_buffer
= &rtex
->resource
;
1214 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1220 /* Shared textures must always set up DCC here.
1221 * If it's not present, it will be disabled by
1222 * apply_opaque_metadata later.
1224 if (rtex
->surface
.dcc_size
&&
1225 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1226 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1227 /* Reserve space for the DCC buffer. */
1228 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1229 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1233 /* Now create the backing buffer. */
1235 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
1236 rtex
->surface
.surf_alignment
);
1238 /* Displayable surfaces are not suballocated. */
1239 if (resource
->b
.b
.bind
& PIPE_BIND_SCANOUT
)
1240 resource
->flags
|= RADEON_FLAG_NO_SUBALLOC
;
1242 if (!r600_alloc_resource(rscreen
, resource
)) {
1247 resource
->buf
= buf
;
1248 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1249 resource
->bo_size
= buf
->size
;
1250 resource
->bo_alignment
= buf
->alignment
;
1251 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1252 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1253 resource
->vram_usage
= buf
->size
;
1254 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1255 resource
->gart_usage
= buf
->size
;
1258 if (rtex
->cmask
.size
) {
1259 /* Initialize the cmask to 0xCC (= compressed state). */
1260 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1261 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1264 if (rtex
->htile_offset
) {
1265 uint32_t clear_value
= 0;
1267 if (rscreen
->chip_class
>= GFX9
|| rtex
->tc_compatible_htile
)
1268 clear_value
= 0x0000030F;
1270 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1272 rtex
->surface
.htile_size
,
1276 /* Initialize DCC only if the texture is not being imported. */
1277 if (!buf
&& rtex
->dcc_offset
) {
1278 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1280 rtex
->surface
.dcc_size
,
1284 /* Initialize the CMASK base register value. */
1285 rtex
->cmask
.base_address_reg
=
1286 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1288 if (rscreen
->debug_flags
& DBG_VM
) {
1289 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1290 rtex
->resource
.gpu_address
,
1291 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1292 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1293 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1296 if (rscreen
->debug_flags
& DBG_TEX
) {
1298 r600_print_texture_info(rscreen
, rtex
, stdout
);
1305 static enum radeon_surf_mode
1306 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1307 const struct pipe_resource
*templ
)
1309 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1310 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1311 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1312 !(templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1314 /* MSAA resources must be 2D tiled. */
1315 if (templ
->nr_samples
> 1)
1316 return RADEON_SURF_MODE_2D
;
1318 /* Transfer resources should be linear. */
1319 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1320 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1322 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1323 * which requires 2D tiling.
1325 if (rscreen
->chip_class
== VI
&&
1327 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
))
1328 return RADEON_SURF_MODE_2D
;
1330 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1331 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1332 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1333 (templ
->target
== PIPE_TEXTURE_2D
||
1334 templ
->target
== PIPE_TEXTURE_3D
))
1335 force_tiling
= true;
1337 /* Handle common candidates for the linear mode.
1338 * Compressed textures and DB surfaces must always be tiled.
1340 if (!force_tiling
&&
1341 !is_depth_stencil
&&
1342 !util_format_is_compressed(templ
->format
)) {
1343 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1344 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1346 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1347 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1348 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1350 /* Cursors are linear on SI.
1351 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1352 if (rscreen
->chip_class
>= SI
&&
1353 (templ
->bind
& PIPE_BIND_CURSOR
))
1354 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1356 if (templ
->bind
& PIPE_BIND_LINEAR
)
1357 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1359 /* Textures with a very small height are recommended to be linear. */
1360 if (templ
->target
== PIPE_TEXTURE_1D
||
1361 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1362 /* Only very thin and long 2D textures should benefit from
1363 * linear_aligned. */
1364 (templ
->width0
> 8 && templ
->height0
<= 2))
1365 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1367 /* Textures likely to be mapped often. */
1368 if (templ
->usage
== PIPE_USAGE_STAGING
||
1369 templ
->usage
== PIPE_USAGE_STREAM
)
1370 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1373 /* Make small textures 1D tiled. */
1374 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1375 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1376 return RADEON_SURF_MODE_1D
;
1378 /* The allocator will switch to 1D if needed. */
1379 return RADEON_SURF_MODE_2D
;
1382 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1383 const struct pipe_resource
*templ
)
1385 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1386 struct radeon_surf surface
= {0};
1387 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1388 bool tc_compatible_htile
=
1389 rscreen
->chip_class
>= VI
&&
1390 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1391 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
) &&
1392 !is_flushed_depth
&&
1393 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1394 util_format_is_depth_or_stencil(templ
->format
);
1398 r
= r600_init_surface(rscreen
, &surface
, templ
,
1399 r600_choose_tiling(rscreen
, templ
), 0, 0,
1400 false, false, is_flushed_depth
,
1401 tc_compatible_htile
);
1406 return (struct pipe_resource
*)
1407 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1410 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1411 const struct pipe_resource
*templ
,
1412 struct winsys_handle
*whandle
,
1415 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1416 struct pb_buffer
*buf
= NULL
;
1417 unsigned stride
= 0, offset
= 0;
1418 unsigned array_mode
;
1419 struct radeon_surf surface
;
1421 struct radeon_bo_metadata metadata
= {};
1422 struct r600_texture
*rtex
;
1425 /* Support only 2D textures without mipmaps */
1426 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1427 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1430 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1434 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1436 if (rscreen
->chip_class
>= GFX9
) {
1437 if (metadata
.u
.gfx9
.swizzle_mode
> 0)
1438 array_mode
= RADEON_SURF_MODE_2D
;
1440 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1442 is_scanout
= metadata
.u
.gfx9
.swizzle_mode
== 0 ||
1443 metadata
.u
.gfx9
.swizzle_mode
% 4 == 2;
1445 surface
.u
.legacy
.pipe_config
= metadata
.u
.legacy
.pipe_config
;
1446 surface
.u
.legacy
.bankw
= metadata
.u
.legacy
.bankw
;
1447 surface
.u
.legacy
.bankh
= metadata
.u
.legacy
.bankh
;
1448 surface
.u
.legacy
.tile_split
= metadata
.u
.legacy
.tile_split
;
1449 surface
.u
.legacy
.mtilea
= metadata
.u
.legacy
.mtilea
;
1450 surface
.u
.legacy
.num_banks
= metadata
.u
.legacy
.num_banks
;
1452 if (metadata
.u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
1453 array_mode
= RADEON_SURF_MODE_2D
;
1454 else if (metadata
.u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
1455 array_mode
= RADEON_SURF_MODE_1D
;
1457 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1459 is_scanout
= metadata
.u
.legacy
.scanout
;
1462 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1463 offset
, true, is_scanout
, false, false);
1468 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1472 rtex
->resource
.b
.is_shared
= true;
1473 rtex
->resource
.external_usage
= usage
;
1475 if (rscreen
->apply_opaque_metadata
)
1476 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1478 /* Validate that addrlib arrived at the same surface parameters. */
1479 if (rscreen
->chip_class
>= GFX9
) {
1480 assert(metadata
.u
.gfx9
.swizzle_mode
== surface
.u
.gfx9
.surf
.swizzle_mode
);
1483 return &rtex
->resource
.b
.b
;
1486 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1487 struct pipe_resource
*texture
,
1488 struct r600_texture
**staging
)
1490 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1491 struct pipe_resource resource
;
1492 struct r600_texture
**flushed_depth_texture
= staging
?
1493 staging
: &rtex
->flushed_depth_texture
;
1494 enum pipe_format pipe_format
= texture
->format
;
1497 if (rtex
->flushed_depth_texture
)
1498 return true; /* it's ready */
1500 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1501 switch (pipe_format
) {
1502 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1503 /* Save memory by not allocating the S plane. */
1504 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1506 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1507 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1508 /* Save memory bandwidth by not copying the
1509 * stencil part during flush.
1511 * This potentially increases memory bandwidth
1512 * if an application uses both Z and S texturing
1513 * simultaneously (a flushed Z24S8 texture
1514 * would be stored compactly), but how often
1515 * does that really happen?
1517 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1521 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1522 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1524 /* DB->CB copies to an 8bpp surface don't work. */
1525 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1529 memset(&resource
, 0, sizeof(resource
));
1530 resource
.target
= texture
->target
;
1531 resource
.format
= pipe_format
;
1532 resource
.width0
= texture
->width0
;
1533 resource
.height0
= texture
->height0
;
1534 resource
.depth0
= texture
->depth0
;
1535 resource
.array_size
= texture
->array_size
;
1536 resource
.last_level
= texture
->last_level
;
1537 resource
.nr_samples
= texture
->nr_samples
;
1538 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1539 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1540 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1543 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1545 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1546 if (*flushed_depth_texture
== NULL
) {
1547 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1551 (*flushed_depth_texture
)->non_disp_tiling
= false;
1556 * Initialize the pipe_resource descriptor to be of the same size as the box,
1557 * which is supposed to hold a subregion of the texture "orig" at the given
1560 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1561 struct pipe_resource
*orig
,
1562 const struct pipe_box
*box
,
1563 unsigned level
, unsigned flags
)
1565 memset(res
, 0, sizeof(*res
));
1566 res
->format
= orig
->format
;
1567 res
->width0
= box
->width
;
1568 res
->height0
= box
->height
;
1570 res
->array_size
= 1;
1571 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1574 /* We must set the correct texture target and dimensions for a 3D box. */
1575 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1576 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1577 res
->array_size
= box
->depth
;
1579 res
->target
= PIPE_TEXTURE_2D
;
1583 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1584 struct r600_texture
*rtex
,
1585 unsigned transfer_usage
,
1586 const struct pipe_box
*box
)
1588 /* r600g doesn't react to dirty_tex_descriptor_counter */
1589 return rscreen
->chip_class
>= SI
&&
1590 !rtex
->resource
.b
.is_shared
&&
1591 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1592 rtex
->resource
.b
.b
.last_level
== 0 &&
1593 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1594 box
->x
, box
->y
, box
->z
,
1595 box
->width
, box
->height
,
1599 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1600 struct r600_texture
*rtex
)
1602 struct r600_common_screen
*rscreen
= rctx
->screen
;
1604 /* There is no point in discarding depth and tiled buffers. */
1605 assert(!rtex
->is_depth
);
1606 assert(rtex
->surface
.is_linear
);
1608 /* Reallocate the buffer in the same pipe_resource. */
1609 r600_alloc_resource(rscreen
, &rtex
->resource
);
1611 /* Initialize the CMASK base address (needed even without CMASK). */
1612 rtex
->cmask
.base_address_reg
=
1613 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1615 p_atomic_inc(&rscreen
->dirty_tex_counter
);
1617 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1620 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1621 struct pipe_resource
*texture
,
1624 const struct pipe_box
*box
,
1625 struct pipe_transfer
**ptransfer
)
1627 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1628 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1629 struct r600_transfer
*trans
;
1630 struct r600_resource
*buf
;
1631 unsigned offset
= 0;
1633 bool use_staging_texture
= false;
1635 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1636 assert(box
->width
&& box
->height
&& box
->depth
);
1638 /* Depth textures use staging unconditionally. */
1639 if (!rtex
->is_depth
) {
1640 /* Degrade the tile mode if we get too many transfers on APUs.
1641 * On dGPUs, the staging texture is always faster.
1642 * Only count uploads that are at least 4x4 pixels large.
1644 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1646 box
->width
>= 4 && box
->height
>= 4 &&
1647 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1648 bool can_invalidate
=
1649 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1652 r600_reallocate_texture_inplace(rctx
, rtex
,
1657 /* Tiled textures need to be converted into a linear texture for CPU
1658 * access. The staging texture is always linear and is placed in GART.
1660 * Reading from VRAM or GTT WC is slow, always use the staging
1661 * texture in this case.
1663 * Use the staging texture for uploads if the underlying BO
1666 if (!rtex
->surface
.is_linear
)
1667 use_staging_texture
= true;
1668 else if (usage
& PIPE_TRANSFER_READ
)
1669 use_staging_texture
=
1670 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1671 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1672 /* Write & linear only: */
1673 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1674 RADEON_USAGE_READWRITE
) ||
1675 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1676 RADEON_USAGE_READWRITE
)) {
1678 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1680 r600_texture_invalidate_storage(rctx
, rtex
);
1682 use_staging_texture
= true;
1686 trans
= CALLOC_STRUCT(r600_transfer
);
1689 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1690 trans
->b
.b
.level
= level
;
1691 trans
->b
.b
.usage
= usage
;
1692 trans
->b
.b
.box
= *box
;
1694 if (rtex
->is_depth
) {
1695 struct r600_texture
*staging_depth
;
1697 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1698 /* MSAA depth buffers need to be converted to single sample buffers.
1700 * Mapping MSAA depth buffers can occur if ReadPixels is called
1701 * with a multisample GLX visual.
1703 * First downsample the depth buffer to a temporary texture,
1704 * then decompress the temporary one to staging.
1706 * Only the region being mapped is transfered.
1708 struct pipe_resource resource
;
1710 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1712 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1713 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1718 if (usage
& PIPE_TRANSFER_READ
) {
1719 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1721 R600_ERR("failed to create a temporary depth texture\n");
1726 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1727 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1728 0, 0, 0, box
->depth
, 0, 0);
1729 pipe_resource_reference(&temp
, NULL
);
1732 /* Just get the strides. */
1733 r600_texture_get_offset(rctx
->screen
, staging_depth
, level
, NULL
,
1735 &trans
->b
.b
.layer_stride
);
1737 /* XXX: only readback the rectangle which is being mapped? */
1738 /* XXX: when discard is true, no need to read back from depth texture */
1739 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1740 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1745 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1747 box
->z
, box
->z
+ box
->depth
- 1,
1750 offset
= r600_texture_get_offset(rctx
->screen
, staging_depth
,
1753 &trans
->b
.b
.layer_stride
);
1756 trans
->staging
= (struct r600_resource
*)staging_depth
;
1757 buf
= trans
->staging
;
1758 } else if (use_staging_texture
) {
1759 struct pipe_resource resource
;
1760 struct r600_texture
*staging
;
1762 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1763 R600_RESOURCE_FLAG_TRANSFER
);
1764 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1765 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1767 /* Create the temporary texture. */
1768 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1770 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1774 trans
->staging
= &staging
->resource
;
1776 /* Just get the strides. */
1777 r600_texture_get_offset(rctx
->screen
, staging
, 0, NULL
,
1779 &trans
->b
.b
.layer_stride
);
1781 if (usage
& PIPE_TRANSFER_READ
)
1782 r600_copy_to_staging_texture(ctx
, trans
);
1784 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1786 buf
= trans
->staging
;
1788 /* the resource is mapped directly */
1789 offset
= r600_texture_get_offset(rctx
->screen
, rtex
, level
, box
,
1791 &trans
->b
.b
.layer_stride
);
1792 buf
= &rtex
->resource
;
1795 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1796 r600_resource_reference(&trans
->staging
, NULL
);
1801 *ptransfer
= &trans
->b
.b
;
1802 return map
+ offset
;
1805 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1806 struct pipe_transfer
* transfer
)
1808 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1809 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1810 struct pipe_resource
*texture
= transfer
->resource
;
1811 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1813 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1814 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1815 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1816 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1817 &rtransfer
->staging
->b
.b
, transfer
->level
,
1820 r600_copy_from_staging_texture(ctx
, rtransfer
);
1824 if (rtransfer
->staging
) {
1825 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1826 r600_resource_reference(&rtransfer
->staging
, NULL
);
1829 /* Heuristic for {upload, draw, upload, draw, ..}:
1831 * Flush the gfx IB if we've allocated too much texture storage.
1833 * The idea is that we don't want to build IBs that use too much
1834 * memory and put pressure on the kernel memory manager and we also
1835 * want to make temporary and invalidated buffers go idle ASAP to
1836 * decrease the total memory usage or make them reusable. The memory
1837 * usage will be slightly higher than given here because of the buffer
1838 * cache in the winsys.
1840 * The result is that the kernel memory manager is never a bottleneck.
1842 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1843 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1844 rctx
->num_alloc_tex_transfer_bytes
= 0;
1847 pipe_resource_reference(&transfer
->resource
, NULL
);
1851 static const struct u_resource_vtbl r600_texture_vtbl
=
1853 NULL
, /* get_handle */
1854 r600_texture_destroy
, /* resource_destroy */
1855 r600_texture_transfer_map
, /* transfer_map */
1856 u_default_transfer_flush_region
, /* transfer_flush_region */
1857 r600_texture_transfer_unmap
, /* transfer_unmap */
1860 /* DCC channel type categories within which formats can be reinterpreted
1861 * while keeping the same DCC encoding. The swizzle must also match. */
1862 enum dcc_channel_type
{
1863 dcc_channel_float32
,
1866 dcc_channel_float16
,
1869 dcc_channel_uint_10_10_10_2
,
1872 dcc_channel_incompatible
,
1875 /* Return the type of DCC encoding. */
1876 static enum dcc_channel_type
1877 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1881 /* Find the first non-void channel. */
1882 for (i
= 0; i
< desc
->nr_channels
; i
++)
1883 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1885 if (i
== desc
->nr_channels
)
1886 return dcc_channel_incompatible
;
1888 switch (desc
->channel
[i
].size
) {
1890 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1891 return dcc_channel_float32
;
1892 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1893 return dcc_channel_uint32
;
1894 return dcc_channel_sint32
;
1896 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1897 return dcc_channel_float16
;
1898 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1899 return dcc_channel_uint16
;
1900 return dcc_channel_sint16
;
1902 return dcc_channel_uint_10_10_10_2
;
1904 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1905 return dcc_channel_uint8
;
1906 return dcc_channel_sint8
;
1908 return dcc_channel_incompatible
;
1912 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1913 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1914 enum pipe_format format2
)
1916 const struct util_format_description
*desc1
, *desc2
;
1917 enum dcc_channel_type type1
, type2
;
1920 if (format1
== format2
)
1923 desc1
= util_format_description(format1
);
1924 desc2
= util_format_description(format2
);
1926 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1929 /* Swizzles must be the same. */
1930 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1931 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1932 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1933 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1936 type1
= vi_get_dcc_channel_type(desc1
);
1937 type2
= vi_get_dcc_channel_type(desc2
);
1939 return type1
!= dcc_channel_incompatible
&&
1940 type2
!= dcc_channel_incompatible
&&
1944 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1946 enum pipe_format view_format
)
1948 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1950 return vi_dcc_enabled(rtex
, level
) &&
1951 !vi_dcc_formats_compatible(tex
->format
, view_format
);
1954 /* This can't be merged with the above function, because
1955 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1956 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
1957 struct pipe_resource
*tex
,
1959 enum pipe_format view_format
)
1961 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1963 if (vi_dcc_enabled(rtex
, level
) &&
1964 !vi_dcc_formats_compatible(tex
->format
, view_format
))
1965 if (!r600_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1966 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1969 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1970 struct pipe_resource
*texture
,
1971 const struct pipe_surface
*templ
,
1972 unsigned width0
, unsigned height0
,
1973 unsigned width
, unsigned height
)
1975 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1980 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1981 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1983 pipe_reference_init(&surface
->base
.reference
, 1);
1984 pipe_resource_reference(&surface
->base
.texture
, texture
);
1985 surface
->base
.context
= pipe
;
1986 surface
->base
.format
= templ
->format
;
1987 surface
->base
.width
= width
;
1988 surface
->base
.height
= height
;
1989 surface
->base
.u
= templ
->u
;
1991 surface
->width0
= width0
;
1992 surface
->height0
= height0
;
1994 surface
->dcc_incompatible
=
1995 texture
->target
!= PIPE_BUFFER
&&
1996 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
1998 return &surface
->base
;
2001 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
2002 struct pipe_resource
*tex
,
2003 const struct pipe_surface
*templ
)
2005 unsigned level
= templ
->u
.tex
.level
;
2006 unsigned width
= u_minify(tex
->width0
, level
);
2007 unsigned height
= u_minify(tex
->height0
, level
);
2008 unsigned width0
= tex
->width0
;
2009 unsigned height0
= tex
->height0
;
2011 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2012 const struct util_format_description
*tex_desc
2013 = util_format_description(tex
->format
);
2014 const struct util_format_description
*templ_desc
2015 = util_format_description(templ
->format
);
2017 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2019 /* Adjust size of surface if and only if the block width or
2020 * height is changed. */
2021 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2022 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2023 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2024 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2026 width
= nblks_x
* templ_desc
->block
.width
;
2027 height
= nblks_y
* templ_desc
->block
.height
;
2029 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2030 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2034 return r600_create_surface_custom(pipe
, tex
, templ
,
2039 static void r600_surface_destroy(struct pipe_context
*pipe
,
2040 struct pipe_surface
*surface
)
2042 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
2043 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
2044 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
2045 pipe_resource_reference(&surface
->texture
, NULL
);
2049 static void r600_clear_texture(struct pipe_context
*pipe
,
2050 struct pipe_resource
*tex
,
2052 const struct pipe_box
*box
,
2055 struct pipe_screen
*screen
= pipe
->screen
;
2056 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
2057 struct pipe_surface tmpl
= {{0}};
2058 struct pipe_surface
*sf
;
2059 const struct util_format_description
*desc
=
2060 util_format_description(tex
->format
);
2062 tmpl
.format
= tex
->format
;
2063 tmpl
.u
.tex
.first_layer
= box
->z
;
2064 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
2065 tmpl
.u
.tex
.level
= level
;
2066 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
2070 if (rtex
->is_depth
) {
2073 uint8_t stencil
= 0;
2075 /* Depth is always present. */
2076 clear
= PIPE_CLEAR_DEPTH
;
2077 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
2079 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
2080 clear
|= PIPE_CLEAR_STENCIL
;
2081 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
2084 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
2086 box
->width
, box
->height
, false);
2088 union pipe_color_union color
;
2090 /* pipe_color_union requires the full vec4 representation. */
2091 if (util_format_is_pure_uint(tex
->format
))
2092 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
2093 else if (util_format_is_pure_sint(tex
->format
))
2094 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
2096 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
2098 if (screen
->is_format_supported(screen
, tex
->format
,
2100 PIPE_BIND_RENDER_TARGET
)) {
2101 pipe
->clear_render_target(pipe
, sf
, &color
,
2103 box
->width
, box
->height
, false);
2105 /* Software fallback - just for R9G9B9E5_FLOAT */
2106 util_clear_render_target(pipe
, sf
, &color
,
2108 box
->width
, box
->height
);
2111 pipe_surface_reference(&sf
, NULL
);
2114 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2116 const struct util_format_description
*desc
= util_format_description(format
);
2118 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2120 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2121 return V_0280A0_SWAP_STD
;
2123 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2126 switch (desc
->nr_channels
) {
2128 if (HAS_SWIZZLE(0,X
))
2129 return V_0280A0_SWAP_STD
; /* X___ */
2130 else if (HAS_SWIZZLE(3,X
))
2131 return V_0280A0_SWAP_ALT_REV
; /* ___X */
2134 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2135 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2136 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2137 return V_0280A0_SWAP_STD
; /* XY__ */
2138 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2139 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2140 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2142 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
2143 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2144 return V_0280A0_SWAP_ALT
; /* X__Y */
2145 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2146 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
2149 if (HAS_SWIZZLE(0,X
))
2150 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
2151 else if (HAS_SWIZZLE(0,Z
))
2152 return V_0280A0_SWAP_STD_REV
; /* ZYX */
2155 /* check the middle channels, the 1st and 4th channel can be NONE */
2156 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2157 return V_0280A0_SWAP_STD
; /* XYZW */
2158 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2159 return V_0280A0_SWAP_STD_REV
; /* WZYX */
2160 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2161 return V_0280A0_SWAP_ALT
; /* ZYXW */
2162 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2165 return V_0280A0_SWAP_ALT_REV
;
2167 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
2174 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2176 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
2181 if (rctx
->dcc_stats
[slot
].query_active
)
2182 vi_separate_dcc_stop_query(&rctx
->b
,
2183 rctx
->dcc_stats
[slot
].tex
);
2185 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
2186 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2187 rctx
->b
.destroy_query(&rctx
->b
,
2188 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
2189 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2192 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2196 * Return the per-context slot where DCC statistics queries for the texture live.
2198 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2199 struct r600_texture
*tex
)
2201 int i
, empty_slot
= -1;
2203 /* Remove zombie textures (textures kept alive by this array only). */
2204 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2205 if (rctx
->dcc_stats
[i
].tex
&&
2206 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2207 vi_dcc_clean_up_context_slot(rctx
, i
);
2209 /* Find the texture. */
2210 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2211 /* Return if found. */
2212 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2213 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2217 /* Record the first seen empty slot. */
2218 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2222 /* Not found. Remove the oldest member to make space in the array. */
2223 if (empty_slot
== -1) {
2224 int oldest_slot
= 0;
2226 /* Find the oldest slot. */
2227 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2228 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2229 rctx
->dcc_stats
[i
].last_use_timestamp
)
2232 /* Clean up the oldest slot. */
2233 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2234 empty_slot
= oldest_slot
;
2237 /* Add the texture to the new slot. */
2238 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2239 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2243 static struct pipe_query
*
2244 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2246 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2247 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2249 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2250 return (struct pipe_query
*)query
;
2254 * Called when binding a color buffer.
2256 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2257 struct r600_texture
*tex
)
2259 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2260 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2262 assert(!rctx
->dcc_stats
[i
].query_active
);
2264 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2265 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2267 /* begin or resume the query */
2268 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2269 rctx
->dcc_stats
[i
].query_active
= true;
2273 * Called when unbinding a color buffer.
2275 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2276 struct r600_texture
*tex
)
2278 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2279 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2281 assert(rctx
->dcc_stats
[i
].query_active
);
2282 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2284 /* pause or end the query */
2285 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2286 rctx
->dcc_stats
[i
].query_active
= false;
2289 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2291 /* The minimum number of fullscreen draws per frame that is required
2293 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2296 /* Called by fast clear. */
2297 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2298 struct r600_texture
*tex
)
2300 /* The intent is to use this with shared displayable back buffers,
2301 * but it's not strictly limited only to them.
2303 if (!tex
->resource
.b
.is_shared
||
2304 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2305 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2306 tex
->resource
.b
.b
.last_level
> 0 ||
2307 !tex
->surface
.dcc_size
)
2310 if (tex
->dcc_offset
)
2311 return; /* already enabled */
2313 /* Enable the DCC stat gathering. */
2314 if (!tex
->dcc_gather_statistics
) {
2315 tex
->dcc_gather_statistics
= true;
2316 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2319 if (!vi_should_enable_separate_dcc(tex
))
2320 return; /* stats show that DCC decompression is too expensive */
2322 assert(tex
->surface
.num_dcc_levels
);
2323 assert(!tex
->dcc_separate_buffer
);
2325 r600_texture_discard_cmask(rctx
->screen
, tex
);
2327 /* Get a DCC buffer. */
2328 if (tex
->last_dcc_separate_buffer
) {
2329 assert(tex
->dcc_gather_statistics
);
2330 assert(!tex
->dcc_separate_buffer
);
2331 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2332 tex
->last_dcc_separate_buffer
= NULL
;
2334 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2335 r600_aligned_buffer_create(rctx
->b
.screen
,
2336 R600_RESOURCE_FLAG_UNMAPPABLE
,
2338 tex
->surface
.dcc_size
,
2339 tex
->surface
.dcc_alignment
);
2340 if (!tex
->dcc_separate_buffer
)
2344 /* dcc_offset is the absolute GPUVM address. */
2345 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2347 /* no need to flag anything since this is called by fast clear that
2348 * flags framebuffer state
2353 * Called by pipe_context::flush_resource, the place where DCC decompression
2356 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2357 struct r600_texture
*tex
)
2359 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2360 struct pipe_query
*tmp
;
2361 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2362 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2363 bool disable
= false;
2365 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2366 union pipe_query_result result
;
2368 /* Read the results. */
2369 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2371 r600_query_hw_reset_buffers(rctx
,
2372 (struct r600_query_hw
*)
2373 rctx
->dcc_stats
[i
].ps_stats
[2]);
2375 /* Compute the approximate number of fullscreen draws. */
2376 tex
->ps_draw_ratio
=
2377 result
.pipeline_statistics
.ps_invocations
/
2378 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2379 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2381 disable
= tex
->dcc_separate_buffer
&&
2382 !vi_should_enable_separate_dcc(tex
);
2385 tex
->num_slow_clears
= 0;
2387 /* stop the statistics query for ps_stats[0] */
2389 vi_separate_dcc_stop_query(ctx
, tex
);
2391 /* Move the queries in the queue by one. */
2392 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2393 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2394 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2395 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2397 /* create and start a new query as ps_stats[0] */
2399 vi_separate_dcc_start_query(ctx
, tex
);
2402 assert(!tex
->last_dcc_separate_buffer
);
2403 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2404 tex
->dcc_separate_buffer
= NULL
;
2405 tex
->dcc_offset
= 0;
2406 /* no need to flag anything since this is called after
2407 * decompression that re-sets framebuffer state
2412 /* FAST COLOR CLEAR */
2414 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2415 enum pipe_format surface_format
,
2416 const union pipe_color_union
*color
)
2418 union util_color uc
;
2420 memset(&uc
, 0, sizeof(uc
));
2422 if (rtex
->surface
.bpe
== 16) {
2423 /* DCC fast clear only:
2424 * CLEAR_WORD0 = R = G = B
2427 assert(color
->ui
[0] == color
->ui
[1] &&
2428 color
->ui
[0] == color
->ui
[2]);
2429 uc
.ui
[0] = color
->ui
[0];
2430 uc
.ui
[1] = color
->ui
[3];
2431 } else if (util_format_is_pure_uint(surface_format
)) {
2432 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2433 } else if (util_format_is_pure_sint(surface_format
)) {
2434 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2436 util_pack_color(color
->f
, surface_format
, &uc
);
2439 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2442 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2443 const union pipe_color_union
*color
,
2444 uint32_t* reset_value
,
2445 bool* clear_words_needed
)
2447 bool values
[4] = {};
2449 bool main_value
= false;
2450 bool extra_value
= false;
2453 /* This is needed to get the correct DCC clear value for luminance formats.
2454 * 1) Get the linear format (because the next step can't handle L8_SRGB).
2455 * 2) Convert luminance to red. (the real hw format for luminance)
2457 surface_format
= util_format_linear(surface_format
);
2458 surface_format
= util_format_luminance_to_red(surface_format
);
2460 const struct util_format_description
*desc
= util_format_description(surface_format
);
2462 if (desc
->block
.bits
== 128 &&
2463 (color
->ui
[0] != color
->ui
[1] ||
2464 color
->ui
[0] != color
->ui
[2]))
2467 *clear_words_needed
= true;
2468 *reset_value
= 0x20202020U
;
2470 /* If we want to clear without needing a fast clear eliminate step, we
2471 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2472 * have two sets of flags, one for the last or first channel(extra) and
2473 * one for the other channels(main).
2476 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2477 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2478 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
||
2479 util_format_is_alpha(surface_format
)) {
2481 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2482 if(r600_translate_colorswap(surface_format
, false) <= 1)
2483 extra_channel
= desc
->nr_channels
- 1;
2489 for (i
= 0; i
< 4; ++i
) {
2490 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2492 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2493 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2496 if (desc
->channel
[i
].pure_integer
&&
2497 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2498 /* Use the maximum value for clamping the clear color. */
2499 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2501 values
[i
] = color
->i
[i
] != 0;
2502 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2504 } else if (desc
->channel
[i
].pure_integer
&&
2505 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2506 /* Use the maximum value for clamping the clear color. */
2507 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2509 values
[i
] = color
->ui
[i
] != 0U;
2510 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2513 values
[i
] = color
->f
[i
] != 0.0F
;
2514 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2518 if (index
== extra_channel
)
2519 extra_value
= values
[i
];
2521 main_value
= values
[i
];
2524 for (int i
= 0; i
< 4; ++i
)
2525 if (values
[i
] != main_value
&&
2526 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2527 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2528 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2531 *clear_words_needed
= false;
2533 *reset_value
|= 0x80808080U
;
2536 *reset_value
|= 0x40404040U
;
2540 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2541 struct r600_texture
*rtex
,
2542 unsigned level
, unsigned clear_value
)
2544 struct pipe_resource
*dcc_buffer
;
2545 uint64_t dcc_offset
, clear_size
;
2547 assert(vi_dcc_enabled(rtex
, level
));
2549 if (rtex
->dcc_separate_buffer
) {
2550 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2553 dcc_buffer
= &rtex
->resource
.b
.b
;
2554 dcc_offset
= rtex
->dcc_offset
;
2557 if (rctx
->chip_class
>= GFX9
) {
2558 /* Mipmap level clears aren't implemented. */
2559 assert(rtex
->resource
.b
.b
.last_level
== 0);
2560 /* MSAA needs a different clear size. */
2561 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
2562 clear_size
= rtex
->surface
.dcc_size
;
2564 dcc_offset
+= rtex
->surface
.u
.legacy
.level
[level
].dcc_offset
;
2565 clear_size
= rtex
->surface
.u
.legacy
.level
[level
].dcc_fast_clear_size
;
2568 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
, clear_size
,
2569 clear_value
, R600_COHERENCY_CB_META
);
2572 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2573 * This allows hitting the MSAA resolve fast path, which requires that both
2574 * src and dst micro tile modes match.
2576 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2577 struct r600_texture
*rtex
)
2579 if (rtex
->resource
.b
.is_shared
||
2580 rtex
->resource
.b
.b
.nr_samples
<= 1 ||
2581 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2584 assert(rscreen
->chip_class
>= GFX9
||
2585 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2586 assert(rtex
->resource
.b
.b
.last_level
== 0);
2588 if (rscreen
->chip_class
>= GFX9
) {
2589 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
2590 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
>= 4);
2592 /* If you do swizzle_mode % 4, you'll get:
2598 * Depth-sample order isn't allowed:
2600 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
% 4 != 0);
2602 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2603 case RADEON_MICRO_MODE_DISPLAY
:
2604 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2605 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 2; /* D */
2607 case RADEON_MICRO_MODE_THIN
:
2608 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2609 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 1; /* S */
2611 case RADEON_MICRO_MODE_ROTATED
:
2612 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2613 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 3; /* R */
2615 default: /* depth */
2616 assert(!"unexpected micro mode");
2619 } else if (rscreen
->chip_class
>= CIK
) {
2620 /* These magic numbers were copied from addrlib. It doesn't use
2621 * any definitions for them either. They are all 2D_TILED_THIN1
2622 * modes with different bpp and micro tile mode.
2624 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2625 case RADEON_MICRO_MODE_DISPLAY
:
2626 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2628 case RADEON_MICRO_MODE_THIN
:
2629 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2631 case RADEON_MICRO_MODE_ROTATED
:
2632 rtex
->surface
.u
.legacy
.tiling_index
[0] = 28;
2634 default: /* depth, thick */
2635 assert(!"unexpected micro mode");
2639 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2640 case RADEON_MICRO_MODE_DISPLAY
:
2641 switch (rtex
->surface
.bpe
) {
2643 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2646 rtex
->surface
.u
.legacy
.tiling_index
[0] = 11;
2649 rtex
->surface
.u
.legacy
.tiling_index
[0] = 12;
2653 case RADEON_MICRO_MODE_THIN
:
2654 switch (rtex
->surface
.bpe
) {
2656 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2659 rtex
->surface
.u
.legacy
.tiling_index
[0] = 15;
2662 rtex
->surface
.u
.legacy
.tiling_index
[0] = 16;
2664 default: /* 8, 16 */
2665 rtex
->surface
.u
.legacy
.tiling_index
[0] = 17;
2669 default: /* depth, thick */
2670 assert(!"unexpected micro mode");
2675 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2677 p_atomic_inc(&rscreen
->dirty_tex_counter
);
2680 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2681 struct pipe_framebuffer_state
*fb
,
2682 struct r600_atom
*fb_state
,
2683 unsigned *buffers
, ubyte
*dirty_cbufs
,
2684 const union pipe_color_union
*color
)
2688 /* This function is broken in BE, so just disable this path for now */
2689 #ifdef PIPE_ARCH_BIG_ENDIAN
2693 if (rctx
->render_cond
)
2696 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2697 struct r600_texture
*tex
;
2698 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2703 /* if this colorbuffer is not being cleared */
2704 if (!(*buffers
& clear_bit
))
2707 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2709 /* the clear is allowed if all layers are bound */
2710 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2711 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2715 /* cannot clear mipmapped textures */
2716 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2720 /* only supported on tiled surfaces */
2721 if (tex
->surface
.is_linear
) {
2725 /* shared textures can't use fast clear without an explicit flush,
2726 * because there is no way to communicate the clear color among
2729 if (tex
->resource
.b
.is_shared
&&
2730 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2733 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2734 if (rctx
->chip_class
== CIK
&&
2735 tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2736 rctx
->screen
->info
.drm_major
== 2 &&
2737 rctx
->screen
->info
.drm_minor
< 38) {
2741 /* Fast clear is the most appropriate place to enable DCC for
2742 * displayable surfaces.
2744 if (rctx
->chip_class
>= VI
&&
2745 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2746 vi_separate_dcc_try_enable(rctx
, tex
);
2748 /* RB+ isn't supported with a CMASK clear only on Stoney,
2749 * so all clears are considered to be hypothetically slow
2750 * clears, which is weighed when determining whether to
2751 * enable separate DCC.
2753 if (tex
->dcc_gather_statistics
&&
2754 rctx
->family
== CHIP_STONEY
)
2755 tex
->num_slow_clears
++;
2758 /* Try to clear DCC first, otherwise try CMASK. */
2759 if (vi_dcc_enabled(tex
, 0)) {
2760 uint32_t reset_value
;
2761 bool clear_words_needed
;
2763 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2766 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2767 color
, &reset_value
,
2768 &clear_words_needed
))
2771 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2773 unsigned level_bit
= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2774 if (clear_words_needed
) {
2775 bool need_compressed_update
= !tex
->dirty_level_mask
;
2777 tex
->dirty_level_mask
|= level_bit
;
2779 if (need_compressed_update
)
2780 p_atomic_inc(&rctx
->screen
->compressed_colortex_counter
);
2782 tex
->separate_dcc_dirty
= true;
2784 /* 128-bit formats are unusupported */
2785 if (tex
->surface
.bpe
> 8) {
2789 /* RB+ doesn't work with CMASK fast clear on Stoney. */
2790 if (rctx
->family
== CHIP_STONEY
)
2793 /* ensure CMASK is enabled */
2794 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2795 if (tex
->cmask
.size
== 0) {
2799 /* Do the fast clear. */
2800 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2801 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2802 R600_COHERENCY_CB_META
);
2804 bool need_compressed_update
= !tex
->dirty_level_mask
;
2806 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2808 if (need_compressed_update
)
2809 p_atomic_inc(&rctx
->screen
->compressed_colortex_counter
);
2812 /* We can change the micro tile mode before a full clear. */
2813 if (rctx
->screen
->chip_class
>= SI
)
2814 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2816 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2819 *dirty_cbufs
|= 1 << i
;
2820 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2821 *buffers
&= ~clear_bit
;
2825 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2827 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2828 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2831 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2833 rctx
->b
.create_surface
= r600_create_surface
;
2834 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2835 rctx
->b
.clear_texture
= r600_clear_texture
;