2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static enum radeon_surf_mode
41 r600_choose_tiling(struct r600_common_screen
*rscreen
,
42 const struct pipe_resource
*templ
);
45 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
46 struct r600_texture
*rdst
,
47 unsigned dst_level
, unsigned dstx
,
48 unsigned dsty
, unsigned dstz
,
49 struct r600_texture
*rsrc
,
51 const struct pipe_box
*src_box
)
56 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
59 /* MSAA: Blits don't exist in the real world. */
60 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
61 rdst
->resource
.b
.b
.nr_samples
> 1)
64 /* Depth-stencil surfaces:
65 * When dst is linear, the DB->CB copy preserves HTILE.
66 * When dst is tiled, the 3D path must be used to update HTILE.
68 if (rsrc
->is_depth
|| rdst
->is_depth
)
72 * src: Use the 3D path. DCC decompression is expensive.
73 * dst: Use the 3D path to compress the pixels with DCC.
75 if ((rsrc
->dcc_offset
&& src_level
< rsrc
->surface
.num_dcc_levels
) ||
76 (rdst
->dcc_offset
&& dst_level
< rdst
->surface
.num_dcc_levels
))
80 * src: Both texture and SDMA paths need decompression. Use SDMA.
81 * dst: If overwriting the whole texture, discard CMASK and use
82 * SDMA. Otherwise, use the 3D path.
84 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
85 /* The CMASK clear is only enabled for the first level. */
86 assert(dst_level
== 0);
87 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
88 dstx
, dsty
, dstz
, src_box
->width
,
89 src_box
->height
, src_box
->depth
))
92 r600_texture_discard_cmask(rctx
->screen
, rdst
);
95 /* All requirements are met. Prepare textures for SDMA. */
96 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
97 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
99 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
100 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
105 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
106 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
107 struct pipe_resource
*dst
,
109 unsigned dstx
, unsigned dsty
, unsigned dstz
,
110 struct pipe_resource
*src
,
112 const struct pipe_box
*src_box
)
114 struct pipe_blit_info blit
;
116 memset(&blit
, 0, sizeof(blit
));
117 blit
.src
.resource
= src
;
118 blit
.src
.format
= src
->format
;
119 blit
.src
.level
= src_level
;
120 blit
.src
.box
= *src_box
;
121 blit
.dst
.resource
= dst
;
122 blit
.dst
.format
= dst
->format
;
123 blit
.dst
.level
= dst_level
;
124 blit
.dst
.box
.x
= dstx
;
125 blit
.dst
.box
.y
= dsty
;
126 blit
.dst
.box
.z
= dstz
;
127 blit
.dst
.box
.width
= src_box
->width
;
128 blit
.dst
.box
.height
= src_box
->height
;
129 blit
.dst
.box
.depth
= src_box
->depth
;
130 blit
.mask
= util_format_get_mask(src
->format
) &
131 util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
142 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
144 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1) {
148 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
160 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1) {
169 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
176 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
180 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
181 const struct pipe_box
*box
)
183 return rtex
->surface
.level
[level
].offset
+
184 box
->z
* rtex
->surface
.level
[level
].slice_size
+
185 box
->y
/ rtex
->surface
.blk_h
* rtex
->surface
.level
[level
].pitch_bytes
+
186 box
->x
/ rtex
->surface
.blk_w
* rtex
->surface
.bpe
;
189 static int r600_init_surface(struct r600_common_screen
*rscreen
,
190 struct radeon_surf
*surface
,
191 const struct pipe_resource
*ptex
,
192 enum radeon_surf_mode array_mode
,
193 unsigned pitch_in_bytes_override
,
197 bool is_flushed_depth
,
198 bool tc_compatible_htile
)
200 const struct util_format_description
*desc
=
201 util_format_description(ptex
->format
);
202 bool is_depth
, is_stencil
;
204 unsigned i
, bpe
, flags
= 0;
206 is_depth
= util_format_has_depth(desc
);
207 is_stencil
= util_format_has_stencil(desc
);
209 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
210 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
211 bpe
= 4; /* stencil is allocated separately on evergreen */
213 bpe
= util_format_get_blocksize(ptex
->format
);
214 /* align byte per element on dword */
220 if (!is_flushed_depth
&& is_depth
) {
221 flags
|= RADEON_SURF_ZBUFFER
;
223 if (tc_compatible_htile
&&
224 array_mode
== RADEON_SURF_MODE_2D
) {
225 /* TC-compatible HTILE only supports Z32_FLOAT.
226 * Promote Z16 to Z32. DB->CB copies will convert
227 * the format for transfers.
230 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
234 flags
|= RADEON_SURF_SBUFFER
;
237 if (rscreen
->chip_class
>= VI
&&
238 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
239 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
240 flags
|= RADEON_SURF_DISABLE_DCC
;
242 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
243 /* This should catch bugs in gallium users setting incorrect flags. */
244 assert(ptex
->nr_samples
<= 1 &&
245 ptex
->array_size
== 1 &&
247 ptex
->last_level
== 0 &&
248 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
250 flags
|= RADEON_SURF_SCANOUT
;
254 flags
|= RADEON_SURF_IMPORTED
;
256 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
257 array_mode
, surface
);
262 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= surface
->level
[0].pitch_bytes
) {
263 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
266 surface
->level
[0].nblk_x
= pitch_in_bytes_override
/ bpe
;
267 surface
->level
[0].pitch_bytes
= pitch_in_bytes_override
;
268 surface
->level
[0].slice_size
= pitch_in_bytes_override
* surface
->level
[0].nblk_y
;
272 for (i
= 0; i
< ARRAY_SIZE(surface
->level
); ++i
)
273 surface
->level
[i
].offset
+= offset
;
278 static void r600_texture_init_metadata(struct r600_texture
*rtex
,
279 struct radeon_bo_metadata
*metadata
)
281 struct radeon_surf
*surface
= &rtex
->surface
;
283 memset(metadata
, 0, sizeof(*metadata
));
284 metadata
->microtile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
285 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
286 metadata
->macrotile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
287 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
288 metadata
->pipe_config
= surface
->pipe_config
;
289 metadata
->bankw
= surface
->bankw
;
290 metadata
->bankh
= surface
->bankh
;
291 metadata
->tile_split
= surface
->tile_split
;
292 metadata
->mtilea
= surface
->mtilea
;
293 metadata
->num_banks
= surface
->num_banks
;
294 metadata
->stride
= surface
->level
[0].pitch_bytes
;
295 metadata
->scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
298 static void r600_dirty_all_framebuffer_states(struct r600_common_screen
*rscreen
)
300 p_atomic_inc(&rscreen
->dirty_fb_counter
);
303 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
304 struct r600_texture
*rtex
)
306 struct r600_common_screen
*rscreen
= rctx
->screen
;
307 struct pipe_context
*ctx
= &rctx
->b
;
309 if (ctx
== rscreen
->aux_context
)
310 pipe_mutex_lock(rscreen
->aux_context_lock
);
312 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
313 ctx
->flush(ctx
, NULL
, 0);
315 if (ctx
== rscreen
->aux_context
)
316 pipe_mutex_unlock(rscreen
->aux_context_lock
);
319 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
320 struct r600_texture
*rtex
)
322 if (!rtex
->cmask
.size
)
325 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
328 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
329 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
330 rtex
->dirty_level_mask
= 0;
332 if (rscreen
->chip_class
>= SI
)
333 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
335 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
337 if (rtex
->cmask_buffer
!= &rtex
->resource
)
338 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
340 /* Notify all contexts about the change. */
341 r600_dirty_all_framebuffer_states(rscreen
);
342 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
345 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
347 /* We can't disable DCC if it can be written by another process. */
348 return rtex
->dcc_offset
&&
349 (!rtex
->resource
.is_shared
||
350 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
353 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
354 struct r600_texture
*rtex
)
356 if (!r600_can_disable_dcc(rtex
))
359 assert(rtex
->dcc_separate_buffer
== NULL
);
362 rtex
->dcc_offset
= 0;
364 /* Notify all contexts about the change. */
365 r600_dirty_all_framebuffer_states(rscreen
);
370 * Disable DCC for the texture. (first decompress, then discard metadata).
372 * There is unresolved multi-context synchronization issue between
373 * screen::aux_context and the current context. If applications do this with
374 * multiple contexts, it's already undefined behavior for them and we don't
375 * have to worry about that. The scenario is:
377 * If context 1 disables DCC and context 2 has queued commands that write
378 * to the texture via CB with DCC enabled, and the order of operations is
380 * context 2 queues draw calls rendering to the texture, but doesn't flush
381 * context 1 disables DCC and flushes
382 * context 1 & 2 reset descriptors and FB state
383 * context 2 flushes (new compressed tiles written by the draw calls)
384 * context 1 & 2 read garbage, because DCC is disabled, yet there are
387 * \param rctx the current context if you have one, or rscreen->aux_context
390 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
391 struct r600_texture
*rtex
)
393 struct r600_common_screen
*rscreen
= rctx
->screen
;
395 if (!r600_can_disable_dcc(rtex
))
398 if (&rctx
->b
== rscreen
->aux_context
)
399 pipe_mutex_lock(rscreen
->aux_context_lock
);
401 /* Decompress DCC. */
402 rctx
->decompress_dcc(&rctx
->b
, rtex
);
403 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
405 if (&rctx
->b
== rscreen
->aux_context
)
406 pipe_mutex_unlock(rscreen
->aux_context_lock
);
408 return r600_texture_discard_dcc(rscreen
, rtex
);
411 static void r600_degrade_tile_mode_to_linear(struct r600_common_context
*rctx
,
412 struct r600_texture
*rtex
,
413 bool invalidate_storage
)
415 struct pipe_screen
*screen
= rctx
->b
.screen
;
416 struct r600_texture
*new_tex
;
417 struct pipe_resource templ
= rtex
->resource
.b
.b
;
420 templ
.bind
|= PIPE_BIND_LINEAR
;
422 /* r600g doesn't react to dirty_tex_descriptor_counter */
423 if (rctx
->chip_class
< SI
)
426 if (rtex
->resource
.is_shared
||
427 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
)
430 /* This fails with MSAA, depth, and compressed textures. */
431 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
432 RADEON_SURF_MODE_LINEAR_ALIGNED
)
435 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
439 /* Copy the pixels to the new texture. */
440 if (!invalidate_storage
) {
441 for (i
= 0; i
<= templ
.last_level
; i
++) {
445 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
446 util_max_layer(&templ
, i
) + 1, &box
);
448 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
449 &rtex
->resource
.b
.b
, i
, &box
);
453 r600_texture_discard_cmask(rctx
->screen
, rtex
);
454 r600_texture_discard_dcc(rctx
->screen
, rtex
);
456 /* Replace the structure fields of rtex. */
457 rtex
->resource
.b
.b
.bind
= templ
.bind
;
458 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
459 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
460 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
461 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
462 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
463 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
464 rtex
->resource
.domains
= new_tex
->resource
.domains
;
465 rtex
->resource
.flags
= new_tex
->resource
.flags
;
466 rtex
->size
= new_tex
->size
;
467 rtex
->surface
= new_tex
->surface
;
468 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
469 rtex
->cb_color_info
= new_tex
->cb_color_info
;
470 rtex
->cmask
= new_tex
->cmask
; /* needed even without CMASK */
472 assert(!rtex
->htile_buffer
);
473 assert(!rtex
->cmask
.size
);
474 assert(!rtex
->fmask
.size
);
475 assert(!rtex
->dcc_offset
);
476 assert(!rtex
->is_depth
);
478 r600_texture_reference(&new_tex
, NULL
);
480 r600_dirty_all_framebuffer_states(rctx
->screen
);
481 p_atomic_inc(&rctx
->screen
->dirty_tex_descriptor_counter
);
484 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
485 struct pipe_context
*ctx
,
486 struct pipe_resource
*resource
,
487 struct winsys_handle
*whandle
,
490 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
491 struct r600_common_context
*rctx
= (struct r600_common_context
*)
492 (ctx
? ctx
: rscreen
->aux_context
);
493 struct r600_resource
*res
= (struct r600_resource
*)resource
;
494 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
495 struct radeon_bo_metadata metadata
;
496 bool update_metadata
= false;
498 /* This is not supported now, but it might be required for OpenCL
499 * interop in the future.
501 if (resource
->target
!= PIPE_BUFFER
&&
502 (resource
->nr_samples
> 1 || rtex
->is_depth
))
505 if (resource
->target
!= PIPE_BUFFER
) {
506 /* Since shader image stores don't support DCC on VI,
507 * disable it for external clients that want write
510 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
511 if (r600_texture_disable_dcc(rctx
, rtex
))
512 update_metadata
= true;
515 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
516 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
517 /* Eliminate fast clear (both CMASK and DCC) */
518 r600_eliminate_fast_color_clear(rctx
, rtex
);
520 /* Disable CMASK if flush_resource isn't going
523 if (rtex
->cmask
.size
)
524 r600_texture_discard_cmask(rscreen
, rtex
);
528 if (!res
->is_shared
|| update_metadata
) {
529 r600_texture_init_metadata(rtex
, &metadata
);
530 if (rscreen
->query_opaque_metadata
)
531 rscreen
->query_opaque_metadata(rscreen
, rtex
,
534 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
538 if (res
->is_shared
) {
539 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
542 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
543 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
544 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
546 res
->is_shared
= true;
547 res
->external_usage
= usage
;
550 return rscreen
->ws
->buffer_get_handle(res
->buf
,
551 rtex
->surface
.level
[0].pitch_bytes
,
552 rtex
->surface
.level
[0].offset
,
553 rtex
->surface
.level
[0].slice_size
,
557 static void r600_texture_destroy(struct pipe_screen
*screen
,
558 struct pipe_resource
*ptex
)
560 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
561 struct r600_resource
*resource
= &rtex
->resource
;
563 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
565 r600_resource_reference(&rtex
->htile_buffer
, NULL
);
566 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
567 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
569 pb_reference(&resource
->buf
, NULL
);
570 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
571 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
575 static const struct u_resource_vtbl r600_texture_vtbl
;
577 /* The number of samples can be specified independently of the texture. */
578 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
579 struct r600_texture
*rtex
,
581 struct r600_fmask_info
*out
)
583 /* FMASK is allocated like an ordinary texture. */
584 struct pipe_resource templ
= rtex
->resource
.b
.b
;
585 struct radeon_surf fmask
= {};
588 memset(out
, 0, sizeof(*out
));
590 templ
.nr_samples
= 1;
591 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
593 if (rscreen
->chip_class
<= CAYMAN
) {
594 /* Use the same parameters and tile mode. */
595 fmask
.bankw
= rtex
->surface
.bankw
;
596 fmask
.bankh
= rtex
->surface
.bankh
;
597 fmask
.mtilea
= rtex
->surface
.mtilea
;
598 fmask
.tile_split
= rtex
->surface
.tile_split
;
604 switch (nr_samples
) {
613 R600_ERR("Invalid sample count for FMASK allocation.\n");
617 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
618 * This can be fixed by writing a separate FMASK allocator specifically
619 * for R600-R700 asics. */
620 if (rscreen
->chip_class
<= R700
) {
624 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
625 RADEON_SURF_MODE_2D
, &fmask
)) {
626 R600_ERR("Got error in surface_init while allocating FMASK.\n");
630 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
632 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
633 if (out
->slice_tile_max
)
634 out
->slice_tile_max
-= 1;
636 out
->tile_mode_index
= fmask
.tiling_index
[0];
637 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
638 out
->bank_height
= fmask
.bankh
;
639 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
640 out
->size
= fmask
.surf_size
;
643 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
644 struct r600_texture
*rtex
)
646 r600_texture_get_fmask_info(rscreen
, rtex
,
647 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
649 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
650 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
653 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
654 struct r600_texture
*rtex
,
655 struct r600_cmask_info
*out
)
657 unsigned cmask_tile_width
= 8;
658 unsigned cmask_tile_height
= 8;
659 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
660 unsigned element_bits
= 4;
661 unsigned cmask_cache_bits
= 1024;
662 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
663 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
665 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
666 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
667 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
668 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
669 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
671 unsigned pitch_elements
= align(rtex
->resource
.b
.b
.width0
, macro_tile_width
);
672 unsigned height
= align(rtex
->resource
.b
.b
.height0
, macro_tile_height
);
674 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
675 unsigned slice_bytes
=
676 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
678 assert(macro_tile_width
% 128 == 0);
679 assert(macro_tile_height
% 128 == 0);
681 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
682 out
->alignment
= MAX2(256, base_align
);
683 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
684 align(slice_bytes
, base_align
);
687 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
688 struct r600_texture
*rtex
,
689 struct r600_cmask_info
*out
)
691 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
692 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
693 unsigned cl_width
, cl_height
;
708 case 16: /* Hawaii */
717 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
719 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
720 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
721 unsigned slice_elements
= (width
* height
) / (8*8);
723 /* Each element of CMASK is a nibble. */
724 unsigned slice_bytes
= slice_elements
/ 2;
726 out
->slice_tile_max
= (width
* height
) / (128*128);
727 if (out
->slice_tile_max
)
728 out
->slice_tile_max
-= 1;
730 out
->alignment
= MAX2(256, base_align
);
731 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
732 align(slice_bytes
, base_align
);
735 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
736 struct r600_texture
*rtex
)
738 if (rscreen
->chip_class
>= SI
) {
739 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
741 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
744 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
745 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
747 if (rscreen
->chip_class
>= SI
)
748 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
750 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
753 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
754 struct r600_texture
*rtex
)
756 if (rtex
->cmask_buffer
)
759 assert(rtex
->cmask
.size
== 0);
761 if (rscreen
->chip_class
>= SI
) {
762 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
764 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
767 rtex
->cmask_buffer
= (struct r600_resource
*)
768 r600_aligned_buffer_create(&rscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
770 rtex
->cmask
.alignment
);
771 if (rtex
->cmask_buffer
== NULL
) {
772 rtex
->cmask
.size
= 0;
776 /* update colorbuffer state bits */
777 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
779 if (rscreen
->chip_class
>= SI
)
780 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
782 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
784 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
787 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
788 struct r600_texture
*rtex
)
790 unsigned cl_width
, cl_height
, width
, height
;
791 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
792 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
794 rtex
->surface
.htile_size
= 0;
796 if (rscreen
->chip_class
<= EVERGREEN
&&
797 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
800 /* HW bug on R6xx. */
801 if (rscreen
->chip_class
== R600
&&
802 (rtex
->resource
.b
.b
.width0
> 7680 ||
803 rtex
->resource
.b
.b
.height0
> 7680))
806 /* HTILE is broken with 1D tiling on old kernels and CIK. */
807 if (rscreen
->chip_class
>= CIK
&&
808 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
809 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
812 /* Overalign HTILE on P2 configs to work around GPU hangs in
813 * piglit/depthstencil-render-miplevels 585.
815 * This has been confirmed to help Kabini & Stoney, where the hangs
816 * are always reproducible. I think I have seen the test hang
817 * on Carrizo too, though it was very rare there.
819 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
848 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
849 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
851 slice_elements
= (width
* height
) / (8 * 8);
852 slice_bytes
= slice_elements
* 4;
854 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
855 base_align
= num_pipes
* pipe_interleave_bytes
;
857 rtex
->surface
.htile_alignment
= base_align
;
858 rtex
->surface
.htile_size
=
859 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
860 align(slice_bytes
, base_align
);
863 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
864 struct r600_texture
*rtex
)
866 uint32_t clear_value
;
868 if (rtex
->tc_compatible_htile
) {
869 clear_value
= 0x0000030F;
871 r600_texture_get_htile_size(rscreen
, rtex
);
875 if (!rtex
->surface
.htile_size
)
878 rtex
->htile_buffer
= (struct r600_resource
*)
879 r600_aligned_buffer_create(&rscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
880 rtex
->surface
.htile_size
,
881 rtex
->surface
.htile_alignment
);
882 if (rtex
->htile_buffer
== NULL
) {
883 /* this is not a fatal error as we can still keep rendering
884 * without htile buffer */
885 R600_ERR("Failed to create buffer object for htile buffer.\n");
887 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
,
888 0, rtex
->surface
.htile_size
,
889 clear_value
, R600_COHERENCY_NONE
);
893 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
)
897 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
898 "blk_h=%u, array_size=%u, last_level=%u, "
899 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
900 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
901 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
903 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
904 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
905 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
907 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
908 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
909 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.bankw
,
910 rtex
->surface
.bankh
, rtex
->surface
.num_banks
, rtex
->surface
.mtilea
,
911 rtex
->surface
.tile_split
, rtex
->surface
.pipe_config
,
912 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
914 if (rtex
->fmask
.size
)
915 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
916 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
917 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
918 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
919 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
921 if (rtex
->cmask
.size
)
922 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
923 "slice_tile_max=%u\n",
924 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
925 rtex
->cmask
.slice_tile_max
);
927 if (rtex
->htile_buffer
)
928 fprintf(f
, " HTile: size=%u, alignment=%u, TC_compatible = %u\n",
929 rtex
->htile_buffer
->b
.b
.width0
,
930 rtex
->htile_buffer
->buf
->alignment
,
931 rtex
->tc_compatible_htile
);
933 if (rtex
->dcc_offset
) {
934 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u\n",
935 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
936 rtex
->surface
.dcc_alignment
);
937 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
938 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
939 "fast_clear_size=%"PRIu64
"\n",
940 i
, i
< rtex
->surface
.num_dcc_levels
,
941 rtex
->surface
.level
[i
].dcc_offset
,
942 rtex
->surface
.level
[i
].dcc_fast_clear_size
);
945 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
946 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
947 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
948 "pitch_bytes=%u, mode=%u, tiling_index = %u\n",
949 i
, rtex
->surface
.level
[i
].offset
,
950 rtex
->surface
.level
[i
].slice_size
,
951 u_minify(rtex
->resource
.b
.b
.width0
, i
),
952 u_minify(rtex
->resource
.b
.b
.height0
, i
),
953 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
954 rtex
->surface
.level
[i
].nblk_x
,
955 rtex
->surface
.level
[i
].nblk_y
,
956 rtex
->surface
.level
[i
].pitch_bytes
,
957 rtex
->surface
.level
[i
].mode
,
958 rtex
->surface
.tiling_index
[i
]);
960 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
961 fprintf(f
, " StencilLayout: tilesplit=%u\n",
962 rtex
->surface
.stencil_tile_split
);
963 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
964 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
965 "slice_size=%"PRIu64
", npix_x=%u, "
966 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
967 "pitch_bytes=%u, mode=%u, tiling_index = %u\n",
968 i
, rtex
->surface
.stencil_level
[i
].offset
,
969 rtex
->surface
.stencil_level
[i
].slice_size
,
970 u_minify(rtex
->resource
.b
.b
.width0
, i
),
971 u_minify(rtex
->resource
.b
.b
.height0
, i
),
972 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
973 rtex
->surface
.stencil_level
[i
].nblk_x
,
974 rtex
->surface
.stencil_level
[i
].nblk_y
,
975 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
976 rtex
->surface
.stencil_level
[i
].mode
,
977 rtex
->surface
.stencil_tiling_index
[i
]);
982 /* Common processing for r600_texture_create and r600_texture_from_handle */
983 static struct r600_texture
*
984 r600_texture_create_object(struct pipe_screen
*screen
,
985 const struct pipe_resource
*base
,
986 struct pb_buffer
*buf
,
987 struct radeon_surf
*surface
)
989 struct r600_texture
*rtex
;
990 struct r600_resource
*resource
;
991 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
993 rtex
= CALLOC_STRUCT(r600_texture
);
997 resource
= &rtex
->resource
;
998 resource
->b
.b
= *base
;
999 resource
->b
.b
.next
= NULL
;
1000 resource
->b
.vtbl
= &r600_texture_vtbl
;
1001 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1002 resource
->b
.b
.screen
= screen
;
1004 /* don't include stencil-only formats which we don't support for rendering */
1005 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1007 rtex
->surface
= *surface
;
1008 rtex
->size
= rtex
->surface
.surf_size
;
1010 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0;
1011 assert(!!(rtex
->surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
) ==
1012 rtex
->tc_compatible_htile
);
1014 /* TC-compatible HTILE only supports Z32_FLOAT. */
1015 if (rtex
->tc_compatible_htile
)
1016 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1018 rtex
->db_render_format
= base
->format
;
1020 /* Tiled depth textures utilize the non-displayable tile order.
1021 * This must be done after r600_setup_surface.
1022 * Applies to R600-Cayman. */
1023 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1024 /* Applies to GCN. */
1025 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1027 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1028 * between frames, so the only thing that can enable separate DCC
1029 * with DRI2 is multiple slow clears within a frame.
1031 rtex
->ps_draw_ratio
= 0;
1033 if (rtex
->is_depth
) {
1034 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1035 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1036 rscreen
->chip_class
>= EVERGREEN
) {
1037 rtex
->can_sample_z
= !rtex
->surface
.depth_adjusted
;
1038 rtex
->can_sample_s
= !rtex
->surface
.stencil_adjusted
;
1040 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1041 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1042 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1043 rtex
->can_sample_z
= true;
1046 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1047 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1048 rtex
->db_compatible
= true;
1050 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1051 r600_texture_allocate_htile(rscreen
, rtex
);
1054 if (base
->nr_samples
> 1) {
1056 r600_texture_allocate_fmask(rscreen
, rtex
);
1057 r600_texture_allocate_cmask(rscreen
, rtex
);
1058 rtex
->cmask_buffer
= &rtex
->resource
;
1060 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1066 /* Shared textures must always set up DCC here.
1067 * If it's not present, it will be disabled by
1068 * apply_opaque_metadata later.
1070 if (rtex
->surface
.dcc_size
&&
1071 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1072 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1073 /* Reserve space for the DCC buffer. */
1074 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1075 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1079 /* Now create the backing buffer. */
1081 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
1082 rtex
->surface
.surf_alignment
);
1084 resource
->flags
|= RADEON_FLAG_HANDLE
;
1086 if (!r600_alloc_resource(rscreen
, resource
)) {
1091 resource
->buf
= buf
;
1092 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1093 resource
->bo_size
= buf
->size
;
1094 resource
->bo_alignment
= buf
->alignment
;
1095 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1096 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1097 resource
->vram_usage
= buf
->size
;
1098 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1099 resource
->gart_usage
= buf
->size
;
1102 if (rtex
->cmask
.size
) {
1103 /* Initialize the cmask to 0xCC (= compressed state). */
1104 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1105 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1106 0xCCCCCCCC, R600_COHERENCY_NONE
);
1109 /* Initialize DCC only if the texture is not being imported. */
1110 if (!buf
&& rtex
->dcc_offset
) {
1111 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1113 rtex
->surface
.dcc_size
,
1114 0xFFFFFFFF, R600_COHERENCY_NONE
);
1117 /* Initialize the CMASK base register value. */
1118 rtex
->cmask
.base_address_reg
=
1119 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1121 if (rscreen
->debug_flags
& DBG_VM
) {
1122 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1123 rtex
->resource
.gpu_address
,
1124 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1125 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1126 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1129 if (rscreen
->debug_flags
& DBG_TEX
) {
1131 r600_print_texture_info(rtex
, stdout
);
1138 static enum radeon_surf_mode
1139 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1140 const struct pipe_resource
*templ
)
1142 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1143 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1145 /* MSAA resources must be 2D tiled. */
1146 if (templ
->nr_samples
> 1)
1147 return RADEON_SURF_MODE_2D
;
1149 /* Transfer resources should be linear. */
1150 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1151 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1153 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1154 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1155 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1156 (templ
->target
== PIPE_TEXTURE_2D
||
1157 templ
->target
== PIPE_TEXTURE_3D
))
1158 force_tiling
= true;
1160 /* Handle common candidates for the linear mode.
1161 * Compressed textures and DB surfaces must always be tiled.
1163 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
1164 (!util_format_is_depth_or_stencil(templ
->format
) ||
1165 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
1166 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1167 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1169 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1170 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1171 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1173 /* Cursors are linear on SI.
1174 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1175 if (rscreen
->chip_class
>= SI
&&
1176 (templ
->bind
& PIPE_BIND_CURSOR
))
1177 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1179 if (templ
->bind
& PIPE_BIND_LINEAR
)
1180 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1182 /* Textures with a very small height are recommended to be linear. */
1183 if (templ
->target
== PIPE_TEXTURE_1D
||
1184 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1185 templ
->height0
<= 4)
1186 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1188 /* Textures likely to be mapped often. */
1189 if (templ
->usage
== PIPE_USAGE_STAGING
||
1190 templ
->usage
== PIPE_USAGE_STREAM
)
1191 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1194 /* Make small textures 1D tiled. */
1195 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1196 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1197 return RADEON_SURF_MODE_1D
;
1199 /* The allocator will switch to 1D if needed. */
1200 return RADEON_SURF_MODE_2D
;
1203 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1204 const struct pipe_resource
*templ
)
1206 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1207 struct radeon_surf surface
= {0};
1208 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1209 bool tc_compatible_htile
=
1210 rscreen
->chip_class
>= VI
&&
1211 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1212 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
) &&
1213 !is_flushed_depth
&&
1214 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1215 util_format_is_depth_or_stencil(templ
->format
);
1219 r
= r600_init_surface(rscreen
, &surface
, templ
,
1220 r600_choose_tiling(rscreen
, templ
), 0, 0,
1221 false, false, is_flushed_depth
,
1222 tc_compatible_htile
);
1227 return (struct pipe_resource
*)
1228 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1231 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1232 const struct pipe_resource
*templ
,
1233 struct winsys_handle
*whandle
,
1236 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1237 struct pb_buffer
*buf
= NULL
;
1238 unsigned stride
= 0, offset
= 0;
1239 unsigned array_mode
;
1240 struct radeon_surf surface
;
1242 struct radeon_bo_metadata metadata
= {};
1243 struct r600_texture
*rtex
;
1245 /* Support only 2D textures without mipmaps */
1246 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1247 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1250 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1254 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1256 surface
.pipe_config
= metadata
.pipe_config
;
1257 surface
.bankw
= metadata
.bankw
;
1258 surface
.bankh
= metadata
.bankh
;
1259 surface
.tile_split
= metadata
.tile_split
;
1260 surface
.mtilea
= metadata
.mtilea
;
1261 surface
.num_banks
= metadata
.num_banks
;
1263 if (metadata
.macrotile
== RADEON_LAYOUT_TILED
)
1264 array_mode
= RADEON_SURF_MODE_2D
;
1265 else if (metadata
.microtile
== RADEON_LAYOUT_TILED
)
1266 array_mode
= RADEON_SURF_MODE_1D
;
1268 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1270 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1271 offset
, true, metadata
.scanout
, false, false);
1276 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1280 rtex
->resource
.is_shared
= true;
1281 rtex
->resource
.external_usage
= usage
;
1283 if (rscreen
->apply_opaque_metadata
)
1284 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1286 return &rtex
->resource
.b
.b
;
1289 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1290 struct pipe_resource
*texture
,
1291 struct r600_texture
**staging
)
1293 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1294 struct pipe_resource resource
;
1295 struct r600_texture
**flushed_depth_texture
= staging
?
1296 staging
: &rtex
->flushed_depth_texture
;
1297 enum pipe_format pipe_format
= texture
->format
;
1300 if (rtex
->flushed_depth_texture
)
1301 return true; /* it's ready */
1303 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1304 switch (pipe_format
) {
1305 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1306 /* Save memory by not allocating the S plane. */
1307 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1309 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1310 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1311 /* Save memory bandwidth by not copying the
1312 * stencil part during flush.
1314 * This potentially increases memory bandwidth
1315 * if an application uses both Z and S texturing
1316 * simultaneously (a flushed Z24S8 texture
1317 * would be stored compactly), but how often
1318 * does that really happen?
1320 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1324 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1325 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1327 /* DB->CB copies to an 8bpp surface don't work. */
1328 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1332 memset(&resource
, 0, sizeof(resource
));
1333 resource
.target
= texture
->target
;
1334 resource
.format
= pipe_format
;
1335 resource
.width0
= texture
->width0
;
1336 resource
.height0
= texture
->height0
;
1337 resource
.depth0
= texture
->depth0
;
1338 resource
.array_size
= texture
->array_size
;
1339 resource
.last_level
= texture
->last_level
;
1340 resource
.nr_samples
= texture
->nr_samples
;
1341 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1342 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1343 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1346 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1348 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1349 if (*flushed_depth_texture
== NULL
) {
1350 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1354 (*flushed_depth_texture
)->non_disp_tiling
= false;
1359 * Initialize the pipe_resource descriptor to be of the same size as the box,
1360 * which is supposed to hold a subregion of the texture "orig" at the given
1363 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1364 struct pipe_resource
*orig
,
1365 const struct pipe_box
*box
,
1366 unsigned level
, unsigned flags
)
1368 memset(res
, 0, sizeof(*res
));
1369 res
->format
= orig
->format
;
1370 res
->width0
= box
->width
;
1371 res
->height0
= box
->height
;
1373 res
->array_size
= 1;
1374 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1377 /* We must set the correct texture target and dimensions for a 3D box. */
1378 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1379 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1380 res
->array_size
= box
->depth
;
1382 res
->target
= PIPE_TEXTURE_2D
;
1386 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1387 struct r600_texture
*rtex
,
1388 unsigned transfer_usage
,
1389 const struct pipe_box
*box
)
1391 /* r600g doesn't react to dirty_tex_descriptor_counter */
1392 return rscreen
->chip_class
>= SI
&&
1393 !rtex
->resource
.is_shared
&&
1394 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1395 rtex
->resource
.b
.b
.last_level
== 0 &&
1396 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1397 box
->x
, box
->y
, box
->z
,
1398 box
->width
, box
->height
,
1402 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1403 struct r600_texture
*rtex
)
1405 struct r600_common_screen
*rscreen
= rctx
->screen
;
1407 /* There is no point in discarding depth and tiled buffers. */
1408 assert(!rtex
->is_depth
);
1409 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
);
1411 /* Reallocate the buffer in the same pipe_resource. */
1412 r600_alloc_resource(rscreen
, &rtex
->resource
);
1414 /* Initialize the CMASK base address (needed even without CMASK). */
1415 rtex
->cmask
.base_address_reg
=
1416 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1418 r600_dirty_all_framebuffer_states(rscreen
);
1419 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
1421 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1424 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1425 struct pipe_resource
*texture
,
1428 const struct pipe_box
*box
,
1429 struct pipe_transfer
**ptransfer
)
1431 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1432 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1433 struct r600_transfer
*trans
;
1434 struct r600_resource
*buf
;
1435 unsigned offset
= 0;
1437 bool use_staging_texture
= false;
1439 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1441 /* Depth textures use staging unconditionally. */
1442 if (!rtex
->is_depth
) {
1443 /* Degrade the tile mode if we get too many transfers on APUs.
1444 * On dGPUs, the staging texture is always faster.
1445 * Only count uploads that are at least 4x4 pixels large.
1447 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1449 box
->width
>= 4 && box
->height
>= 4 &&
1450 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1451 bool can_invalidate
=
1452 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1455 r600_degrade_tile_mode_to_linear(rctx
, rtex
,
1459 /* Tiled textures need to be converted into a linear texture for CPU
1460 * access. The staging texture is always linear and is placed in GART.
1462 * Reading from VRAM is slow, always use the staging texture in
1465 * Use the staging texture for uploads if the underlying BO
1468 if (rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
)
1469 use_staging_texture
= true;
1470 else if (usage
& PIPE_TRANSFER_READ
)
1471 use_staging_texture
= (rtex
->resource
.domains
&
1472 RADEON_DOMAIN_VRAM
) != 0;
1473 /* Write & linear only: */
1474 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1475 RADEON_USAGE_READWRITE
) ||
1476 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1477 RADEON_USAGE_READWRITE
)) {
1479 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1481 r600_texture_invalidate_storage(rctx
, rtex
);
1483 use_staging_texture
= true;
1487 trans
= CALLOC_STRUCT(r600_transfer
);
1490 trans
->transfer
.resource
= texture
;
1491 trans
->transfer
.level
= level
;
1492 trans
->transfer
.usage
= usage
;
1493 trans
->transfer
.box
= *box
;
1495 if (rtex
->is_depth
) {
1496 struct r600_texture
*staging_depth
;
1498 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1499 /* MSAA depth buffers need to be converted to single sample buffers.
1501 * Mapping MSAA depth buffers can occur if ReadPixels is called
1502 * with a multisample GLX visual.
1504 * First downsample the depth buffer to a temporary texture,
1505 * then decompress the temporary one to staging.
1507 * Only the region being mapped is transfered.
1509 struct pipe_resource resource
;
1511 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1513 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1514 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1519 if (usage
& PIPE_TRANSFER_READ
) {
1520 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1522 R600_ERR("failed to create a temporary depth texture\n");
1527 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1528 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1529 0, 0, 0, box
->depth
, 0, 0);
1530 pipe_resource_reference(&temp
, NULL
);
1534 /* XXX: only readback the rectangle which is being mapped? */
1535 /* XXX: when discard is true, no need to read back from depth texture */
1536 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1537 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1542 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1544 box
->z
, box
->z
+ box
->depth
- 1,
1547 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1550 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
1551 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
1552 trans
->staging
= (struct r600_resource
*)staging_depth
;
1553 buf
= trans
->staging
;
1554 } else if (use_staging_texture
) {
1555 struct pipe_resource resource
;
1556 struct r600_texture
*staging
;
1558 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1559 R600_RESOURCE_FLAG_TRANSFER
);
1560 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1561 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1563 /* Create the temporary texture. */
1564 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1566 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1570 trans
->staging
= &staging
->resource
;
1571 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
1572 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1574 if (usage
& PIPE_TRANSFER_READ
)
1575 r600_copy_to_staging_texture(ctx
, trans
);
1577 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1579 buf
= trans
->staging
;
1581 /* the resource is mapped directly */
1582 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
1583 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1584 offset
= r600_texture_get_offset(rtex
, level
, box
);
1585 buf
= &rtex
->resource
;
1588 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1589 r600_resource_reference(&trans
->staging
, NULL
);
1594 *ptransfer
= &trans
->transfer
;
1595 return map
+ offset
;
1598 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1599 struct pipe_transfer
* transfer
)
1601 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1602 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1603 struct pipe_resource
*texture
= transfer
->resource
;
1604 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1606 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1607 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1608 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1609 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1610 &rtransfer
->staging
->b
.b
, transfer
->level
,
1613 r600_copy_from_staging_texture(ctx
, rtransfer
);
1617 if (rtransfer
->staging
) {
1618 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1619 r600_resource_reference(&rtransfer
->staging
, NULL
);
1622 /* Heuristic for {upload, draw, upload, draw, ..}:
1624 * Flush the gfx IB if we've allocated too much texture storage.
1626 * The idea is that we don't want to build IBs that use too much
1627 * memory and put pressure on the kernel memory manager and we also
1628 * want to make temporary and invalidated buffers go idle ASAP to
1629 * decrease the total memory usage or make them reusable. The memory
1630 * usage will be slightly higher than given here because of the buffer
1631 * cache in the winsys.
1633 * The result is that the kernel memory manager is never a bottleneck.
1635 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1636 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1637 rctx
->num_alloc_tex_transfer_bytes
= 0;
1643 static const struct u_resource_vtbl r600_texture_vtbl
=
1645 NULL
, /* get_handle */
1646 r600_texture_destroy
, /* resource_destroy */
1647 r600_texture_transfer_map
, /* transfer_map */
1648 u_default_transfer_flush_region
, /* transfer_flush_region */
1649 r600_texture_transfer_unmap
, /* transfer_unmap */
1652 /* DCC channel type categories within which formats can be reinterpreted
1653 * while keeping the same DCC encoding. The swizzle must also match. */
1654 enum dcc_channel_type
{
1655 dcc_channel_float32
,
1658 dcc_channel_float16
,
1661 dcc_channel_uint_10_10_10_2
,
1664 dcc_channel_incompatible
,
1667 /* Return the type of DCC encoding. */
1668 static enum dcc_channel_type
1669 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1673 /* Find the first non-void channel. */
1674 for (i
= 0; i
< desc
->nr_channels
; i
++)
1675 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1677 if (i
== desc
->nr_channels
)
1678 return dcc_channel_incompatible
;
1680 switch (desc
->channel
[i
].size
) {
1682 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1683 return dcc_channel_float32
;
1684 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1685 return dcc_channel_uint32
;
1686 return dcc_channel_sint32
;
1688 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1689 return dcc_channel_float16
;
1690 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1691 return dcc_channel_uint16
;
1692 return dcc_channel_sint16
;
1694 return dcc_channel_uint_10_10_10_2
;
1696 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1697 return dcc_channel_uint8
;
1698 return dcc_channel_sint8
;
1700 return dcc_channel_incompatible
;
1704 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1705 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1706 enum pipe_format format2
)
1708 const struct util_format_description
*desc1
, *desc2
;
1709 enum dcc_channel_type type1
, type2
;
1712 if (format1
== format2
)
1715 desc1
= util_format_description(format1
);
1716 desc2
= util_format_description(format2
);
1718 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1721 /* Swizzles must be the same. */
1722 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1723 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1724 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1725 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1728 type1
= vi_get_dcc_channel_type(desc1
);
1729 type2
= vi_get_dcc_channel_type(desc2
);
1731 return type1
!= dcc_channel_incompatible
&&
1732 type2
!= dcc_channel_incompatible
&&
1736 void vi_dcc_disable_if_incompatible_format(struct r600_common_context
*rctx
,
1737 struct pipe_resource
*tex
,
1739 enum pipe_format view_format
)
1741 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1743 if (rtex
->dcc_offset
&&
1744 level
< rtex
->surface
.num_dcc_levels
&&
1745 !vi_dcc_formats_compatible(tex
->format
, view_format
))
1746 if (!r600_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1747 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1750 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1751 struct pipe_resource
*texture
,
1752 const struct pipe_surface
*templ
,
1753 unsigned width
, unsigned height
)
1755 struct r600_common_context
*rctx
= (struct r600_common_context
*)pipe
;
1756 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1757 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1762 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1763 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1765 pipe_reference_init(&surface
->base
.reference
, 1);
1766 pipe_resource_reference(&surface
->base
.texture
, texture
);
1767 surface
->base
.context
= pipe
;
1768 surface
->base
.format
= templ
->format
;
1769 surface
->base
.width
= width
;
1770 surface
->base
.height
= height
;
1771 surface
->base
.u
= templ
->u
;
1772 surface
->level_info
= &rtex
->surface
.level
[templ
->u
.tex
.level
];
1774 if (texture
->target
!= PIPE_BUFFER
)
1775 vi_dcc_disable_if_incompatible_format(rctx
, texture
,
1779 return &surface
->base
;
1782 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1783 struct pipe_resource
*tex
,
1784 const struct pipe_surface
*templ
)
1786 unsigned level
= templ
->u
.tex
.level
;
1787 unsigned width
= u_minify(tex
->width0
, level
);
1788 unsigned height
= u_minify(tex
->height0
, level
);
1790 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1791 const struct util_format_description
*tex_desc
1792 = util_format_description(tex
->format
);
1793 const struct util_format_description
*templ_desc
1794 = util_format_description(templ
->format
);
1796 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1798 /* Adjust size of surface if and only if the block width or
1799 * height is changed. */
1800 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1801 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1802 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1803 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1805 width
= nblks_x
* templ_desc
->block
.width
;
1806 height
= nblks_y
* templ_desc
->block
.height
;
1810 return r600_create_surface_custom(pipe
, tex
, templ
, width
, height
);
1813 static void r600_surface_destroy(struct pipe_context
*pipe
,
1814 struct pipe_surface
*surface
)
1816 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1817 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1818 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1819 pipe_resource_reference(&surface
->texture
, NULL
);
1823 static void r600_clear_texture(struct pipe_context
*pipe
,
1824 struct pipe_resource
*tex
,
1826 const struct pipe_box
*box
,
1829 struct pipe_screen
*screen
= pipe
->screen
;
1830 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1831 struct pipe_surface tmpl
= {{0}};
1832 struct pipe_surface
*sf
;
1833 const struct util_format_description
*desc
=
1834 util_format_description(tex
->format
);
1836 tmpl
.format
= tex
->format
;
1837 tmpl
.u
.tex
.first_layer
= box
->z
;
1838 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
1839 tmpl
.u
.tex
.level
= level
;
1840 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
1844 if (rtex
->is_depth
) {
1847 uint8_t stencil
= 0;
1849 /* Depth is always present. */
1850 clear
= PIPE_CLEAR_DEPTH
;
1851 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
1853 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1854 clear
|= PIPE_CLEAR_STENCIL
;
1855 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
1858 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
1860 box
->width
, box
->height
, false);
1862 union pipe_color_union color
;
1864 /* pipe_color_union requires the full vec4 representation. */
1865 if (util_format_is_pure_uint(tex
->format
))
1866 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
1867 else if (util_format_is_pure_sint(tex
->format
))
1868 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
1870 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
1872 if (screen
->is_format_supported(screen
, tex
->format
,
1874 PIPE_BIND_RENDER_TARGET
)) {
1875 pipe
->clear_render_target(pipe
, sf
, &color
,
1877 box
->width
, box
->height
, false);
1879 /* Software fallback - just for R9G9B9E5_FLOAT */
1880 util_clear_render_target(pipe
, sf
, &color
,
1882 box
->width
, box
->height
);
1885 pipe_surface_reference(&sf
, NULL
);
1888 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1890 const struct util_format_description
*desc
= util_format_description(format
);
1892 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1894 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1895 return V_0280A0_SWAP_STD
;
1897 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1900 switch (desc
->nr_channels
) {
1902 if (HAS_SWIZZLE(0,X
))
1903 return V_0280A0_SWAP_STD
; /* X___ */
1904 else if (HAS_SWIZZLE(3,X
))
1905 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1908 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1909 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1910 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1911 return V_0280A0_SWAP_STD
; /* XY__ */
1912 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1913 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1914 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1916 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
1917 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1918 return V_0280A0_SWAP_ALT
; /* X__Y */
1919 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1920 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1923 if (HAS_SWIZZLE(0,X
))
1924 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
1925 else if (HAS_SWIZZLE(0,Z
))
1926 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1929 /* check the middle channels, the 1st and 4th channel can be NONE */
1930 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
1931 return V_0280A0_SWAP_STD
; /* XYZW */
1932 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
1933 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1934 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
1935 return V_0280A0_SWAP_ALT
; /* ZYXW */
1936 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
1939 return V_0280A0_SWAP_ALT_REV
;
1941 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
1948 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
1950 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
1955 if (rctx
->dcc_stats
[slot
].query_active
)
1956 vi_separate_dcc_stop_query(&rctx
->b
,
1957 rctx
->dcc_stats
[slot
].tex
);
1959 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
1960 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
1961 rctx
->b
.destroy_query(&rctx
->b
,
1962 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
1963 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
1966 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
1970 * Return the per-context slot where DCC statistics queries for the texture live.
1972 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
1973 struct r600_texture
*tex
)
1975 int i
, empty_slot
= -1;
1977 /* Remove zombie textures (textures kept alive by this array only). */
1978 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
1979 if (rctx
->dcc_stats
[i
].tex
&&
1980 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
1981 vi_dcc_clean_up_context_slot(rctx
, i
);
1983 /* Find the texture. */
1984 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
1985 /* Return if found. */
1986 if (rctx
->dcc_stats
[i
].tex
== tex
) {
1987 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
1991 /* Record the first seen empty slot. */
1992 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
1996 /* Not found. Remove the oldest member to make space in the array. */
1997 if (empty_slot
== -1) {
1998 int oldest_slot
= 0;
2000 /* Find the oldest slot. */
2001 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2002 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2003 rctx
->dcc_stats
[i
].last_use_timestamp
)
2006 /* Clean up the oldest slot. */
2007 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2008 empty_slot
= oldest_slot
;
2011 /* Add the texture to the new slot. */
2012 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2013 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2017 static struct pipe_query
*
2018 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2020 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2021 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2023 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2024 return (struct pipe_query
*)query
;
2028 * Called when binding a color buffer.
2030 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2031 struct r600_texture
*tex
)
2033 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2034 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2036 assert(!rctx
->dcc_stats
[i
].query_active
);
2038 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2039 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2041 /* begin or resume the query */
2042 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2043 rctx
->dcc_stats
[i
].query_active
= true;
2047 * Called when unbinding a color buffer.
2049 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2050 struct r600_texture
*tex
)
2052 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2053 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2055 assert(rctx
->dcc_stats
[i
].query_active
);
2056 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2058 /* pause or end the query */
2059 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2060 rctx
->dcc_stats
[i
].query_active
= false;
2063 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2065 /* The minimum number of fullscreen draws per frame that is required
2067 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2070 /* Called by fast clear. */
2071 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2072 struct r600_texture
*tex
)
2074 /* The intent is to use this with shared displayable back buffers,
2075 * but it's not strictly limited only to them.
2077 if (!tex
->resource
.is_shared
||
2078 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2079 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2080 tex
->resource
.b
.b
.last_level
> 0 ||
2081 !tex
->surface
.dcc_size
)
2084 if (tex
->dcc_offset
)
2085 return; /* already enabled */
2087 /* Enable the DCC stat gathering. */
2088 if (!tex
->dcc_gather_statistics
) {
2089 tex
->dcc_gather_statistics
= true;
2090 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2093 if (!vi_should_enable_separate_dcc(tex
))
2094 return; /* stats show that DCC decompression is too expensive */
2096 assert(tex
->surface
.num_dcc_levels
);
2097 assert(!tex
->dcc_separate_buffer
);
2099 r600_texture_discard_cmask(rctx
->screen
, tex
);
2101 /* Get a DCC buffer. */
2102 if (tex
->last_dcc_separate_buffer
) {
2103 assert(tex
->dcc_gather_statistics
);
2104 assert(!tex
->dcc_separate_buffer
);
2105 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2106 tex
->last_dcc_separate_buffer
= NULL
;
2108 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2109 r600_aligned_buffer_create(rctx
->b
.screen
, 0,
2111 tex
->surface
.dcc_size
,
2112 tex
->surface
.dcc_alignment
);
2113 if (!tex
->dcc_separate_buffer
)
2117 /* dcc_offset is the absolute GPUVM address. */
2118 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2120 /* no need to flag anything since this is called by fast clear that
2121 * flags framebuffer state
2126 * Called by pipe_context::flush_resource, the place where DCC decompression
2129 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2130 struct r600_texture
*tex
)
2132 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2133 struct pipe_query
*tmp
;
2134 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2135 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2136 bool disable
= false;
2138 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2139 union pipe_query_result result
;
2141 /* Read the results. */
2142 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2144 r600_query_hw_reset_buffers(rctx
,
2145 (struct r600_query_hw
*)
2146 rctx
->dcc_stats
[i
].ps_stats
[2]);
2148 /* Compute the approximate number of fullscreen draws. */
2149 tex
->ps_draw_ratio
=
2150 result
.pipeline_statistics
.ps_invocations
/
2151 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2152 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2154 disable
= tex
->dcc_separate_buffer
&&
2155 !vi_should_enable_separate_dcc(tex
);
2158 tex
->num_slow_clears
= 0;
2160 /* stop the statistics query for ps_stats[0] */
2162 vi_separate_dcc_stop_query(ctx
, tex
);
2164 /* Move the queries in the queue by one. */
2165 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2166 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2167 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2168 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2170 /* create and start a new query as ps_stats[0] */
2172 vi_separate_dcc_start_query(ctx
, tex
);
2175 assert(!tex
->last_dcc_separate_buffer
);
2176 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2177 tex
->dcc_separate_buffer
= NULL
;
2178 tex
->dcc_offset
= 0;
2179 /* no need to flag anything since this is called after
2180 * decompression that re-sets framebuffer state
2185 /* FAST COLOR CLEAR */
2187 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2188 enum pipe_format surface_format
,
2189 const union pipe_color_union
*color
)
2191 union util_color uc
;
2193 memset(&uc
, 0, sizeof(uc
));
2195 if (rtex
->surface
.bpe
== 16) {
2196 /* DCC fast clear only:
2197 * CLEAR_WORD0 = R = G = B
2200 assert(color
->ui
[0] == color
->ui
[1] &&
2201 color
->ui
[0] == color
->ui
[2]);
2202 uc
.ui
[0] = color
->ui
[0];
2203 uc
.ui
[1] = color
->ui
[3];
2204 } else if (util_format_is_pure_uint(surface_format
)) {
2205 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2206 } else if (util_format_is_pure_sint(surface_format
)) {
2207 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2209 util_pack_color(color
->f
, surface_format
, &uc
);
2212 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2215 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2216 const union pipe_color_union
*color
,
2217 uint32_t* reset_value
,
2218 bool* clear_words_needed
)
2220 bool values
[4] = {};
2222 bool main_value
= false;
2223 bool extra_value
= false;
2225 const struct util_format_description
*desc
= util_format_description(surface_format
);
2227 if (desc
->block
.bits
== 128 &&
2228 (color
->ui
[0] != color
->ui
[1] ||
2229 color
->ui
[0] != color
->ui
[2]))
2232 *clear_words_needed
= true;
2233 *reset_value
= 0x20202020U
;
2235 /* If we want to clear without needing a fast clear eliminate step, we
2236 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2237 * have two sets of flags, one for the last or first channel(extra) and
2238 * one for the other channels(main).
2241 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2242 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2243 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
2245 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2246 if(r600_translate_colorswap(surface_format
, false) <= 1)
2247 extra_channel
= desc
->nr_channels
- 1;
2253 for (i
= 0; i
< 4; ++i
) {
2254 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2256 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2257 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2260 if (desc
->channel
[i
].pure_integer
&&
2261 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2262 /* Use the maximum value for clamping the clear color. */
2263 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2265 values
[i
] = color
->i
[i
] != 0;
2266 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2268 } else if (desc
->channel
[i
].pure_integer
&&
2269 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2270 /* Use the maximum value for clamping the clear color. */
2271 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2273 values
[i
] = color
->ui
[i
] != 0U;
2274 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2277 values
[i
] = color
->f
[i
] != 0.0F
;
2278 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2282 if (index
== extra_channel
)
2283 extra_value
= values
[i
];
2285 main_value
= values
[i
];
2288 for (int i
= 0; i
< 4; ++i
)
2289 if (values
[i
] != main_value
&&
2290 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2291 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2292 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2295 *clear_words_needed
= false;
2297 *reset_value
|= 0x80808080U
;
2300 *reset_value
|= 0x40404040U
;
2304 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2305 struct r600_texture
*rtex
,
2306 unsigned level
, unsigned clear_value
)
2308 struct pipe_resource
*dcc_buffer
;
2309 uint64_t dcc_offset
;
2311 assert(rtex
->dcc_offset
&& level
< rtex
->surface
.num_dcc_levels
);
2313 if (rtex
->dcc_separate_buffer
) {
2314 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2317 dcc_buffer
= &rtex
->resource
.b
.b
;
2318 dcc_offset
= rtex
->dcc_offset
;
2321 dcc_offset
+= rtex
->surface
.level
[level
].dcc_offset
;
2323 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
,
2324 rtex
->surface
.level
[level
].dcc_fast_clear_size
,
2325 clear_value
, R600_COHERENCY_CB_META
);
2328 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2329 * This allows hitting the MSAA resolve fast path, which requires that both
2330 * src and dst micro tile modes match.
2332 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2333 struct r600_texture
*rtex
)
2335 if (rtex
->resource
.is_shared
||
2336 rtex
->resource
.b
.b
.nr_samples
<= 1 ||
2337 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2340 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2341 assert(rtex
->resource
.b
.b
.last_level
== 0);
2343 /* These magic numbers were copied from addrlib. It doesn't use any
2344 * definitions for them either. They are all 2D_TILED_THIN1 modes with
2345 * different bpp and micro tile mode.
2347 if (rscreen
->chip_class
>= CIK
) {
2348 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2349 case 0: /* displayable */
2350 rtex
->surface
.tiling_index
[0] = 10;
2353 rtex
->surface
.tiling_index
[0] = 14;
2355 case 3: /* rotated */
2356 rtex
->surface
.tiling_index
[0] = 28;
2358 default: /* depth, thick */
2359 assert(!"unexpected micro mode");
2363 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2364 case 0: /* displayable */
2365 switch (rtex
->surface
.bpe
) {
2367 rtex
->surface
.tiling_index
[0] = 10;
2370 rtex
->surface
.tiling_index
[0] = 11;
2373 rtex
->surface
.tiling_index
[0] = 12;
2378 switch (rtex
->surface
.bpe
) {
2380 rtex
->surface
.tiling_index
[0] = 14;
2383 rtex
->surface
.tiling_index
[0] = 15;
2386 rtex
->surface
.tiling_index
[0] = 16;
2388 default: /* 8, 16 */
2389 rtex
->surface
.tiling_index
[0] = 17;
2393 default: /* depth, thick */
2394 assert(!"unexpected micro mode");
2399 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2401 p_atomic_inc(&rscreen
->dirty_fb_counter
);
2402 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
2405 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2406 struct pipe_framebuffer_state
*fb
,
2407 struct r600_atom
*fb_state
,
2408 unsigned *buffers
, unsigned *dirty_cbufs
,
2409 const union pipe_color_union
*color
)
2413 /* This function is broken in BE, so just disable this path for now */
2414 #ifdef PIPE_ARCH_BIG_ENDIAN
2418 if (rctx
->render_cond
)
2421 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2422 struct r600_texture
*tex
;
2423 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2428 /* if this colorbuffer is not being cleared */
2429 if (!(*buffers
& clear_bit
))
2432 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2434 /* the clear is allowed if all layers are bound */
2435 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2436 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2440 /* cannot clear mipmapped textures */
2441 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2445 /* only supported on tiled surfaces */
2446 if (tex
->surface
.level
[0].mode
< RADEON_SURF_MODE_1D
) {
2450 /* shared textures can't use fast clear without an explicit flush,
2451 * because there is no way to communicate the clear color among
2454 if (tex
->resource
.is_shared
&&
2455 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2458 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2459 if (tex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2460 rctx
->chip_class
>= CIK
&&
2461 rctx
->screen
->info
.drm_major
== 2 &&
2462 rctx
->screen
->info
.drm_minor
< 38) {
2466 /* Fast clear is the most appropriate place to enable DCC for
2467 * displayable surfaces.
2469 if (rctx
->chip_class
>= VI
&&
2470 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2471 vi_separate_dcc_try_enable(rctx
, tex
);
2473 /* Stoney can't do a CMASK-based clear, so all clears are
2474 * considered to be hypothetically slow clears, which
2475 * is weighed when determining to enable separate DCC.
2477 if (tex
->dcc_gather_statistics
&&
2478 rctx
->family
== CHIP_STONEY
)
2479 tex
->num_slow_clears
++;
2482 /* Try to clear DCC first, otherwise try CMASK. */
2483 if (tex
->dcc_offset
&& tex
->surface
.num_dcc_levels
) {
2484 uint32_t reset_value
;
2485 bool clear_words_needed
;
2487 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2490 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2491 color
, &reset_value
,
2492 &clear_words_needed
))
2495 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2497 if (clear_words_needed
)
2498 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2499 tex
->separate_dcc_dirty
= true;
2501 /* 128-bit formats are unusupported */
2502 if (tex
->surface
.bpe
> 8) {
2506 /* Stoney/RB+ doesn't work with CMASK fast clear. */
2507 if (rctx
->family
== CHIP_STONEY
)
2510 /* ensure CMASK is enabled */
2511 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2512 if (tex
->cmask
.size
== 0) {
2516 /* Do the fast clear. */
2517 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2518 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2519 R600_COHERENCY_CB_META
);
2521 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2524 /* We can change the micro tile mode before a full clear. */
2525 if (rctx
->screen
->chip_class
>= SI
)
2526 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2528 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2531 *dirty_cbufs
|= 1 << i
;
2532 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2533 *buffers
&= ~clear_bit
;
2537 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2539 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2540 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2543 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2545 rctx
->b
.create_surface
= r600_create_surface
;
2546 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2547 rctx
->b
.clear_texture
= r600_clear_texture
;