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37cac91f76fd8081c926a4cbd084665045864860
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include <errno.h>
33 #include <inttypes.h>
34
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context *pipe,
37 struct pipe_resource *dst,
38 unsigned dst_level,
39 unsigned dstx, unsigned dsty, unsigned dstz,
40 struct pipe_resource *src,
41 unsigned src_level,
42 const struct pipe_box *src_box)
43 {
44 struct pipe_blit_info blit;
45
46 memset(&blit, 0, sizeof(blit));
47 blit.src.resource = src;
48 blit.src.format = src->format;
49 blit.src.level = src_level;
50 blit.src.box = *src_box;
51 blit.dst.resource = dst;
52 blit.dst.format = dst->format;
53 blit.dst.level = dst_level;
54 blit.dst.box.x = dstx;
55 blit.dst.box.y = dsty;
56 blit.dst.box.z = dstz;
57 blit.dst.box.width = src_box->width;
58 blit.dst.box.height = src_box->height;
59 blit.dst.box.depth = src_box->depth;
60 blit.mask = util_format_get_mask(src->format) &
61 util_format_get_mask(dst->format);
62 blit.filter = PIPE_TEX_FILTER_NEAREST;
63
64 if (blit.mask) {
65 pipe->blit(pipe, &blit);
66 }
67 }
68
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
71 {
72 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
73 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
74 struct pipe_resource *dst = &rtransfer->staging->b.b;
75 struct pipe_resource *src = transfer->resource;
76
77 if (src->nr_samples > 1) {
78 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
79 src, transfer->level, &transfer->box);
80 return;
81 }
82
83 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
84 &transfer->box);
85 }
86
87 /* Copy from a transfer's staging texture to a full GPU one. */
88 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
89 {
90 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
91 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
92 struct pipe_resource *dst = transfer->resource;
93 struct pipe_resource *src = &rtransfer->staging->b.b;
94 struct pipe_box sbox;
95
96 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
97
98 if (dst->nr_samples > 1) {
99 r600_copy_region_with_blit(ctx, dst, transfer->level,
100 transfer->box.x, transfer->box.y, transfer->box.z,
101 src, 0, &sbox);
102 return;
103 }
104
105 rctx->dma_copy(ctx, dst, transfer->level,
106 transfer->box.x, transfer->box.y, transfer->box.z,
107 src, 0, &sbox);
108 }
109
110 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
111 const struct pipe_box *box)
112 {
113 enum pipe_format format = rtex->resource.b.b.format;
114
115 return rtex->surface.level[level].offset +
116 box->z * rtex->surface.level[level].slice_size +
117 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
118 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
119 }
120
121 static int r600_init_surface(struct r600_common_screen *rscreen,
122 struct radeon_surf *surface,
123 const struct pipe_resource *ptex,
124 unsigned array_mode,
125 bool is_flushed_depth)
126 {
127 const struct util_format_description *desc =
128 util_format_description(ptex->format);
129 bool is_depth, is_stencil;
130
131 is_depth = util_format_has_depth(desc);
132 is_stencil = util_format_has_stencil(desc);
133
134 surface->npix_x = ptex->width0;
135 surface->npix_y = ptex->height0;
136 surface->npix_z = ptex->depth0;
137 surface->blk_w = util_format_get_blockwidth(ptex->format);
138 surface->blk_h = util_format_get_blockheight(ptex->format);
139 surface->blk_d = 1;
140 surface->array_size = 1;
141 surface->last_level = ptex->last_level;
142
143 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
144 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
145 surface->bpe = 4; /* stencil is allocated separately on evergreen */
146 } else {
147 surface->bpe = util_format_get_blocksize(ptex->format);
148 /* align byte per element on dword */
149 if (surface->bpe == 3) {
150 surface->bpe = 4;
151 }
152 }
153
154 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
155 surface->flags = RADEON_SURF_SET(array_mode, MODE);
156
157 switch (ptex->target) {
158 case PIPE_TEXTURE_1D:
159 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
160 break;
161 case PIPE_TEXTURE_RECT:
162 case PIPE_TEXTURE_2D:
163 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
164 break;
165 case PIPE_TEXTURE_3D:
166 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
167 break;
168 case PIPE_TEXTURE_1D_ARRAY:
169 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
170 surface->array_size = ptex->array_size;
171 break;
172 case PIPE_TEXTURE_2D_ARRAY:
173 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
175 surface->array_size = ptex->array_size;
176 break;
177 case PIPE_TEXTURE_CUBE:
178 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
179 break;
180 case PIPE_BUFFER:
181 default:
182 return -EINVAL;
183 }
184 if (ptex->bind & PIPE_BIND_SCANOUT) {
185 surface->flags |= RADEON_SURF_SCANOUT;
186 }
187
188 if (!is_flushed_depth && is_depth) {
189 surface->flags |= RADEON_SURF_ZBUFFER;
190
191 if (is_stencil) {
192 surface->flags |= RADEON_SURF_SBUFFER |
193 RADEON_SURF_HAS_SBUFFER_MIPTREE;
194 }
195 }
196 if (rscreen->chip_class >= SI) {
197 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
198 }
199 return 0;
200 }
201
202 static int r600_setup_surface(struct pipe_screen *screen,
203 struct r600_texture *rtex,
204 unsigned pitch_in_bytes_override)
205 {
206 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
207 int r;
208
209 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
210 if (r) {
211 return r;
212 }
213
214 rtex->size = rtex->surface.bo_size;
215
216 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
217 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
218 * for those
219 */
220 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
221 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
222 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
223 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
224 rtex->surface.stencil_offset =
225 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
226 }
227 }
228 return 0;
229 }
230
231 static boolean r600_texture_get_handle(struct pipe_screen* screen,
232 struct pipe_resource *ptex,
233 struct winsys_handle *whandle)
234 {
235 struct r600_texture *rtex = (struct r600_texture*)ptex;
236 struct r600_resource *resource = &rtex->resource;
237 struct radeon_surf *surface = &rtex->surface;
238 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
239
240 rscreen->ws->buffer_set_tiling(resource->buf,
241 NULL,
242 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
243 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
244 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
245 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
246 surface->pipe_config,
247 surface->bankw, surface->bankh,
248 surface->tile_split,
249 surface->stencil_tile_split,
250 surface->mtilea, surface->num_banks,
251 surface->level[0].pitch_bytes,
252 (surface->flags & RADEON_SURF_SCANOUT) != 0);
253
254 return rscreen->ws->buffer_get_handle(resource->buf,
255 surface->level[0].pitch_bytes, whandle);
256 }
257
258 static void r600_texture_destroy(struct pipe_screen *screen,
259 struct pipe_resource *ptex)
260 {
261 struct r600_texture *rtex = (struct r600_texture*)ptex;
262 struct r600_resource *resource = &rtex->resource;
263
264 if (rtex->flushed_depth_texture)
265 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
266
267 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
268 if (rtex->cmask_buffer != &rtex->resource) {
269 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
270 }
271 pipe_resource_reference((struct pipe_resource**)&rtex->dcc_buffer, NULL);
272 pb_reference(&resource->buf, NULL);
273 FREE(rtex);
274 }
275
276 static const struct u_resource_vtbl r600_texture_vtbl;
277
278 /* The number of samples can be specified independently of the texture. */
279 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
280 struct r600_texture *rtex,
281 unsigned nr_samples,
282 struct r600_fmask_info *out)
283 {
284 /* FMASK is allocated like an ordinary texture. */
285 struct radeon_surf fmask = rtex->surface;
286
287 memset(out, 0, sizeof(*out));
288
289 fmask.bo_alignment = 0;
290 fmask.bo_size = 0;
291 fmask.nsamples = 1;
292 fmask.flags |= RADEON_SURF_FMASK;
293
294 /* Force 2D tiling if it wasn't set. This may occur when creating
295 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
296 * destination buffer must have an FMASK too. */
297 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
298 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
299
300 if (rscreen->chip_class >= SI) {
301 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
302 }
303
304 switch (nr_samples) {
305 case 2:
306 case 4:
307 fmask.bpe = 1;
308 if (rscreen->chip_class <= CAYMAN) {
309 fmask.bankh = 4;
310 }
311 break;
312 case 8:
313 fmask.bpe = 4;
314 break;
315 default:
316 R600_ERR("Invalid sample count for FMASK allocation.\n");
317 return;
318 }
319
320 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
321 * This can be fixed by writing a separate FMASK allocator specifically
322 * for R600-R700 asics. */
323 if (rscreen->chip_class <= R700) {
324 fmask.bpe *= 2;
325 }
326
327 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
328 R600_ERR("Got error in surface_init while allocating FMASK.\n");
329 return;
330 }
331
332 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
333
334 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
335 if (out->slice_tile_max)
336 out->slice_tile_max -= 1;
337
338 out->tile_mode_index = fmask.tiling_index[0];
339 out->pitch_in_pixels = fmask.level[0].nblk_x;
340 out->bank_height = fmask.bankh;
341 out->alignment = MAX2(256, fmask.bo_alignment);
342 out->size = fmask.bo_size;
343 }
344
345 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
346 struct r600_texture *rtex)
347 {
348 r600_texture_get_fmask_info(rscreen, rtex,
349 rtex->resource.b.b.nr_samples, &rtex->fmask);
350
351 rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
352 rtex->size = rtex->fmask.offset + rtex->fmask.size;
353 }
354
355 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
356 struct r600_texture *rtex,
357 struct r600_cmask_info *out)
358 {
359 unsigned cmask_tile_width = 8;
360 unsigned cmask_tile_height = 8;
361 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
362 unsigned element_bits = 4;
363 unsigned cmask_cache_bits = 1024;
364 unsigned num_pipes = rscreen->tiling_info.num_channels;
365 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
366
367 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
368 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
369 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
370 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
371 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
372
373 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
374 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
375
376 unsigned base_align = num_pipes * pipe_interleave_bytes;
377 unsigned slice_bytes =
378 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
379
380 assert(macro_tile_width % 128 == 0);
381 assert(macro_tile_height % 128 == 0);
382
383 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
384 out->alignment = MAX2(256, base_align);
385 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
386 align(slice_bytes, base_align);
387 }
388
389 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
390 struct r600_texture *rtex,
391 struct r600_cmask_info *out)
392 {
393 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
394 unsigned num_pipes = rscreen->tiling_info.num_channels;
395 unsigned cl_width, cl_height;
396
397 switch (num_pipes) {
398 case 2:
399 cl_width = 32;
400 cl_height = 16;
401 break;
402 case 4:
403 cl_width = 32;
404 cl_height = 32;
405 break;
406 case 8:
407 cl_width = 64;
408 cl_height = 32;
409 break;
410 case 16: /* Hawaii */
411 cl_width = 64;
412 cl_height = 64;
413 break;
414 default:
415 assert(0);
416 return;
417 }
418
419 unsigned base_align = num_pipes * pipe_interleave_bytes;
420
421 unsigned width = align(rtex->surface.npix_x, cl_width*8);
422 unsigned height = align(rtex->surface.npix_y, cl_height*8);
423 unsigned slice_elements = (width * height) / (8*8);
424
425 /* Each element of CMASK is a nibble. */
426 unsigned slice_bytes = slice_elements / 2;
427
428 out->slice_tile_max = (width * height) / (128*128);
429 if (out->slice_tile_max)
430 out->slice_tile_max -= 1;
431
432 out->alignment = MAX2(256, base_align);
433 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
434 align(slice_bytes, base_align);
435 }
436
437 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
438 struct r600_texture *rtex)
439 {
440 if (rscreen->chip_class >= SI) {
441 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
442 } else {
443 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
444 }
445
446 rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
447 rtex->size = rtex->cmask.offset + rtex->cmask.size;
448
449 if (rscreen->chip_class >= SI)
450 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
451 else
452 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
453 }
454
455 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
456 struct r600_texture *rtex)
457 {
458 if (rtex->cmask_buffer)
459 return;
460
461 assert(rtex->cmask.size == 0);
462
463 if (rscreen->chip_class >= SI) {
464 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
465 } else {
466 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
467 }
468
469 rtex->cmask_buffer = (struct r600_resource *)
470 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
471 PIPE_USAGE_DEFAULT, rtex->cmask.size);
472 if (rtex->cmask_buffer == NULL) {
473 rtex->cmask.size = 0;
474 return;
475 }
476
477 /* update colorbuffer state bits */
478 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
479
480 if (rscreen->chip_class >= SI)
481 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
482 else
483 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
484 }
485
486 static void vi_texture_alloc_dcc_separate(struct r600_common_screen *rscreen,
487 struct r600_texture *rtex)
488 {
489 if (rscreen->debug_flags & DBG_NO_DCC)
490 return;
491
492 rtex->dcc_buffer = (struct r600_resource *)
493 r600_aligned_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
494 PIPE_USAGE_DEFAULT, rtex->surface.dcc_size, rtex->surface.dcc_alignment);
495 if (rtex->dcc_buffer == NULL) {
496 return;
497 }
498
499 r600_screen_clear_buffer(rscreen, &rtex->dcc_buffer->b.b, 0, rtex->surface.dcc_size,
500 0xFFFFFFFF, true);
501
502 rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
503 }
504
505 static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
506 struct r600_texture *rtex)
507 {
508 unsigned cl_width, cl_height, width, height;
509 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
510 unsigned num_pipes = rscreen->tiling_info.num_channels;
511
512 if (rscreen->chip_class <= EVERGREEN &&
513 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
514 return 0;
515
516 /* HW bug on R6xx. */
517 if (rscreen->chip_class == R600 &&
518 (rtex->surface.level[0].npix_x > 7680 ||
519 rtex->surface.level[0].npix_y > 7680))
520 return 0;
521
522 /* HTILE is broken with 1D tiling on old kernels and CIK. */
523 if (rscreen->chip_class >= CIK &&
524 rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
525 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
526 return 0;
527
528 switch (num_pipes) {
529 case 1:
530 cl_width = 32;
531 cl_height = 16;
532 break;
533 case 2:
534 cl_width = 32;
535 cl_height = 32;
536 break;
537 case 4:
538 cl_width = 64;
539 cl_height = 32;
540 break;
541 case 8:
542 cl_width = 64;
543 cl_height = 64;
544 break;
545 case 16:
546 cl_width = 128;
547 cl_height = 64;
548 break;
549 default:
550 assert(0);
551 return 0;
552 }
553
554 width = align(rtex->surface.npix_x, cl_width * 8);
555 height = align(rtex->surface.npix_y, cl_height * 8);
556
557 slice_elements = (width * height) / (8 * 8);
558 slice_bytes = slice_elements * 4;
559
560 pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
561 base_align = num_pipes * pipe_interleave_bytes;
562
563 return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
564 align(slice_bytes, base_align);
565 }
566
567 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
568 struct r600_texture *rtex)
569 {
570 unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex);
571
572 if (!htile_size)
573 return;
574
575 rtex->htile_buffer = (struct r600_resource*)
576 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
577 PIPE_USAGE_DEFAULT, htile_size);
578 if (rtex->htile_buffer == NULL) {
579 /* this is not a fatal error as we can still keep rendering
580 * without htile buffer */
581 R600_ERR("Failed to create buffer object for htile buffer.\n");
582 } else {
583 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0,
584 htile_size, 0, true);
585 }
586 }
587
588 static void
589 r600_print_texture_info(struct r600_texture *rtex, FILE *f)
590 {
591 int i;
592
593 fprintf(f, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
594 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
595 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
596 rtex->surface.npix_x, rtex->surface.npix_y,
597 rtex->surface.npix_z, rtex->surface.blk_w,
598 rtex->surface.blk_h, rtex->surface.blk_d,
599 rtex->surface.array_size, rtex->surface.last_level,
600 rtex->surface.bpe, rtex->surface.nsamples,
601 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
602
603 fprintf(f, " Layout: size=%"PRIu64", alignment=%"PRIu64", bankw=%u, "
604 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
605 rtex->surface.bo_size, rtex->surface.bo_alignment, rtex->surface.bankw,
606 rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
607 rtex->surface.tile_split, rtex->surface.pipe_config,
608 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
609
610 if (rtex->fmask.size)
611 fprintf(f, " FMask: offset=%u, size=%u, alignment=%u, pitch_in_pixels=%u, "
612 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
613 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
614 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
615 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
616
617 if (rtex->cmask.size)
618 fprintf(f, " CMask: offset=%u, size=%u, alignment=%u, "
619 "slice_tile_max=%u\n",
620 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
621 rtex->cmask.slice_tile_max);
622
623 if (rtex->htile_buffer)
624 fprintf(f, " HTile: size=%u, alignment=%u\n",
625 rtex->htile_buffer->b.b.width0,
626 rtex->htile_buffer->buf->alignment);
627
628 if (rtex->dcc_buffer) {
629 fprintf(f, " DCC: size=%u, alignment=%u\n",
630 rtex->dcc_buffer->b.b.width0,
631 rtex->dcc_buffer->buf->alignment);
632 for (i = 0; i <= rtex->surface.last_level; i++)
633 fprintf(f, " DCCLevel[%i]: offset=%"PRIu64"\n",
634 i, rtex->surface.level[i].dcc_offset);
635 }
636
637 for (i = 0; i <= rtex->surface.last_level; i++)
638 fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
639 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
640 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
641 i, rtex->surface.level[i].offset,
642 rtex->surface.level[i].slice_size,
643 u_minify(rtex->resource.b.b.width0, i),
644 u_minify(rtex->resource.b.b.height0, i),
645 u_minify(rtex->resource.b.b.depth0, i),
646 rtex->surface.level[i].nblk_x,
647 rtex->surface.level[i].nblk_y,
648 rtex->surface.level[i].nblk_z,
649 rtex->surface.level[i].pitch_bytes,
650 rtex->surface.level[i].mode);
651
652 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
653 for (i = 0; i <= rtex->surface.last_level; i++) {
654 fprintf(f, " StencilLayout: tilesplit=%u\n",
655 rtex->surface.stencil_tile_split);
656 fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
657 "slice_size=%"PRIu64", npix_x=%u, "
658 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
659 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
660 i, rtex->surface.stencil_level[i].offset,
661 rtex->surface.stencil_level[i].slice_size,
662 u_minify(rtex->resource.b.b.width0, i),
663 u_minify(rtex->resource.b.b.height0, i),
664 u_minify(rtex->resource.b.b.depth0, i),
665 rtex->surface.stencil_level[i].nblk_x,
666 rtex->surface.stencil_level[i].nblk_y,
667 rtex->surface.stencil_level[i].nblk_z,
668 rtex->surface.stencil_level[i].pitch_bytes,
669 rtex->surface.stencil_level[i].mode);
670 }
671 }
672 }
673
674 /* Common processing for r600_texture_create and r600_texture_from_handle */
675 static struct r600_texture *
676 r600_texture_create_object(struct pipe_screen *screen,
677 const struct pipe_resource *base,
678 unsigned pitch_in_bytes_override,
679 struct pb_buffer *buf,
680 struct radeon_surf *surface)
681 {
682 struct r600_texture *rtex;
683 struct r600_resource *resource;
684 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
685
686 rtex = CALLOC_STRUCT(r600_texture);
687 if (rtex == NULL)
688 return NULL;
689
690 resource = &rtex->resource;
691 resource->b.b = *base;
692 resource->b.vtbl = &r600_texture_vtbl;
693 pipe_reference_init(&resource->b.b.reference, 1);
694 resource->b.b.screen = screen;
695
696 /* don't include stencil-only formats which we don't support for rendering */
697 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
698
699 rtex->surface = *surface;
700 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override)) {
701 FREE(rtex);
702 return NULL;
703 }
704
705 /* Tiled depth textures utilize the non-displayable tile order.
706 * This must be done after r600_setup_surface.
707 * Applies to R600-Cayman. */
708 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
709
710 if (rtex->is_depth) {
711 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
712 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
713 !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
714
715 r600_texture_allocate_htile(rscreen, rtex);
716 }
717 } else {
718 if (base->nr_samples > 1) {
719 if (!buf) {
720 r600_texture_allocate_fmask(rscreen, rtex);
721 r600_texture_allocate_cmask(rscreen, rtex);
722 rtex->cmask_buffer = &rtex->resource;
723 }
724 if (!rtex->fmask.size || !rtex->cmask.size) {
725 FREE(rtex);
726 return NULL;
727 }
728 }
729 if (rtex->surface.dcc_size)
730 vi_texture_alloc_dcc_separate(rscreen, rtex);
731 }
732
733 /* Now create the backing buffer. */
734 if (!buf) {
735 if (!r600_init_resource(rscreen, resource, rtex->size,
736 rtex->surface.bo_alignment, TRUE)) {
737 FREE(rtex);
738 return NULL;
739 }
740 } else {
741 resource->buf = buf;
742 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
743 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->cs_buf);
744 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->cs_buf);
745 }
746
747 if (rtex->cmask.size) {
748 /* Initialize the cmask to 0xCC (= compressed state). */
749 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
750 rtex->cmask.offset, rtex->cmask.size,
751 0xCCCCCCCC, true);
752 }
753
754 /* Initialize the CMASK base register value. */
755 rtex->cmask.base_address_reg =
756 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
757
758 if (rscreen->debug_flags & DBG_VM) {
759 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
760 rtex->resource.gpu_address,
761 rtex->resource.gpu_address + rtex->resource.buf->size,
762 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
763 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
764 }
765
766 if (rscreen->debug_flags & DBG_TEX) {
767 puts("Texture:");
768 r600_print_texture_info(rtex, stdout);
769 }
770
771 return rtex;
772 }
773
774 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
775 const struct pipe_resource *templ)
776 {
777 const struct util_format_description *desc = util_format_description(templ->format);
778 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
779
780 /* MSAA resources must be 2D tiled. */
781 if (templ->nr_samples > 1)
782 return RADEON_SURF_MODE_2D;
783
784 /* Transfer resources should be linear. */
785 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
786 return RADEON_SURF_MODE_LINEAR_ALIGNED;
787
788 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
789 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
790 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
791 (templ->target == PIPE_TEXTURE_2D ||
792 templ->target == PIPE_TEXTURE_3D))
793 force_tiling = true;
794
795 /* Handle common candidates for the linear mode.
796 * Compressed textures must always be tiled. */
797 if (!force_tiling && !util_format_is_compressed(templ->format)) {
798 /* Not everything can be linear, so we cannot enforce it
799 * for all textures. */
800 if ((rscreen->debug_flags & DBG_NO_TILING) &&
801 (!util_format_is_depth_or_stencil(templ->format) ||
802 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH)))
803 return RADEON_SURF_MODE_LINEAR_ALIGNED;
804
805 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
806 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
807 return RADEON_SURF_MODE_LINEAR_ALIGNED;
808
809 /* Cursors are linear on SI.
810 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
811 if (rscreen->chip_class >= SI &&
812 (templ->bind & PIPE_BIND_CURSOR))
813 return RADEON_SURF_MODE_LINEAR_ALIGNED;
814
815 if (templ->bind & PIPE_BIND_LINEAR)
816 return RADEON_SURF_MODE_LINEAR_ALIGNED;
817
818 /* Textures with a very small height are recommended to be linear. */
819 if (templ->target == PIPE_TEXTURE_1D ||
820 templ->target == PIPE_TEXTURE_1D_ARRAY ||
821 templ->height0 <= 4)
822 return RADEON_SURF_MODE_LINEAR_ALIGNED;
823
824 /* Textures likely to be mapped often. */
825 if (templ->usage == PIPE_USAGE_STAGING ||
826 templ->usage == PIPE_USAGE_STREAM)
827 return RADEON_SURF_MODE_LINEAR_ALIGNED;
828 }
829
830 /* Make small textures 1D tiled. */
831 if (templ->width0 <= 16 || templ->height0 <= 16 ||
832 (rscreen->debug_flags & DBG_NO_2D_TILING))
833 return RADEON_SURF_MODE_1D;
834
835 /* The allocator will switch to 1D if needed. */
836 return RADEON_SURF_MODE_2D;
837 }
838
839 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
840 const struct pipe_resource *templ)
841 {
842 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
843 struct radeon_surf surface = {0};
844 int r;
845
846 r = r600_init_surface(rscreen, &surface, templ,
847 r600_choose_tiling(rscreen, templ),
848 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
849 if (r) {
850 return NULL;
851 }
852 r = rscreen->ws->surface_best(rscreen->ws, &surface);
853 if (r) {
854 return NULL;
855 }
856 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
857 0, NULL, &surface);
858 }
859
860 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
861 const struct pipe_resource *templ,
862 struct winsys_handle *whandle)
863 {
864 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
865 struct pb_buffer *buf = NULL;
866 unsigned stride = 0;
867 unsigned array_mode;
868 enum radeon_bo_layout micro, macro;
869 struct radeon_surf surface;
870 bool scanout;
871 int r;
872
873 /* Support only 2D textures without mipmaps */
874 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
875 templ->depth0 != 1 || templ->last_level != 0)
876 return NULL;
877
878 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
879 if (!buf)
880 return NULL;
881
882 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
883 &surface.bankw, &surface.bankh,
884 &surface.tile_split,
885 &surface.stencil_tile_split,
886 &surface.mtilea, &scanout);
887
888 if (macro == RADEON_LAYOUT_TILED)
889 array_mode = RADEON_SURF_MODE_2D;
890 else if (micro == RADEON_LAYOUT_TILED)
891 array_mode = RADEON_SURF_MODE_1D;
892 else
893 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
894
895 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
896 if (r) {
897 return NULL;
898 }
899
900 if (scanout)
901 surface.flags |= RADEON_SURF_SCANOUT;
902
903 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
904 stride, buf, &surface);
905 }
906
907 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
908 struct pipe_resource *texture,
909 struct r600_texture **staging)
910 {
911 struct r600_texture *rtex = (struct r600_texture*)texture;
912 struct pipe_resource resource;
913 struct r600_texture **flushed_depth_texture = staging ?
914 staging : &rtex->flushed_depth_texture;
915
916 if (!staging && rtex->flushed_depth_texture)
917 return true; /* it's ready */
918
919 resource.target = texture->target;
920 resource.format = texture->format;
921 resource.width0 = texture->width0;
922 resource.height0 = texture->height0;
923 resource.depth0 = texture->depth0;
924 resource.array_size = texture->array_size;
925 resource.last_level = texture->last_level;
926 resource.nr_samples = texture->nr_samples;
927 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
928 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
929 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
930
931 if (staging)
932 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
933
934 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
935 if (*flushed_depth_texture == NULL) {
936 R600_ERR("failed to create temporary texture to hold flushed depth\n");
937 return false;
938 }
939
940 (*flushed_depth_texture)->is_flushing_texture = TRUE;
941 (*flushed_depth_texture)->non_disp_tiling = false;
942 return true;
943 }
944
945 /**
946 * Initialize the pipe_resource descriptor to be of the same size as the box,
947 * which is supposed to hold a subregion of the texture "orig" at the given
948 * mipmap level.
949 */
950 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
951 struct pipe_resource *orig,
952 const struct pipe_box *box,
953 unsigned level, unsigned flags)
954 {
955 memset(res, 0, sizeof(*res));
956 res->format = orig->format;
957 res->width0 = box->width;
958 res->height0 = box->height;
959 res->depth0 = 1;
960 res->array_size = 1;
961 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
962 res->flags = flags;
963
964 /* We must set the correct texture target and dimensions for a 3D box. */
965 if (box->depth > 1 && util_max_layer(orig, level) > 0)
966 res->target = orig->target;
967 else
968 res->target = PIPE_TEXTURE_2D;
969
970 switch (res->target) {
971 case PIPE_TEXTURE_1D_ARRAY:
972 case PIPE_TEXTURE_2D_ARRAY:
973 case PIPE_TEXTURE_CUBE_ARRAY:
974 res->array_size = box->depth;
975 break;
976 case PIPE_TEXTURE_3D:
977 res->depth0 = box->depth;
978 break;
979 default:;
980 }
981 }
982
983 static void *r600_texture_transfer_map(struct pipe_context *ctx,
984 struct pipe_resource *texture,
985 unsigned level,
986 unsigned usage,
987 const struct pipe_box *box,
988 struct pipe_transfer **ptransfer)
989 {
990 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
991 struct r600_texture *rtex = (struct r600_texture*)texture;
992 struct r600_transfer *trans;
993 boolean use_staging_texture = FALSE;
994 struct r600_resource *buf;
995 unsigned offset = 0;
996 char *map;
997
998 /* We cannot map a tiled texture directly because the data is
999 * in a different order, therefore we do detiling using a blit.
1000 *
1001 * Also, use a temporary in GTT memory for read transfers, as
1002 * the CPU is much happier reading out of cached system memory
1003 * than uncached VRAM.
1004 */
1005 if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
1006 use_staging_texture = TRUE;
1007 } else if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
1008 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
1009 /* Untiled buffers in VRAM, which is slow for CPU reads */
1010 use_staging_texture = TRUE;
1011 } else if (!(usage & PIPE_TRANSFER_READ) &&
1012 (r600_rings_is_buffer_referenced(rctx, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
1013 !rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) {
1014 /* Use a staging texture for uploads if the underlying BO is busy. */
1015 use_staging_texture = TRUE;
1016 }
1017
1018 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
1019 use_staging_texture = FALSE;
1020 }
1021
1022 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
1023 return NULL;
1024 }
1025
1026 trans = CALLOC_STRUCT(r600_transfer);
1027 if (trans == NULL)
1028 return NULL;
1029 trans->transfer.resource = texture;
1030 trans->transfer.level = level;
1031 trans->transfer.usage = usage;
1032 trans->transfer.box = *box;
1033
1034 if (rtex->is_depth) {
1035 struct r600_texture *staging_depth;
1036
1037 if (rtex->resource.b.b.nr_samples > 1) {
1038 /* MSAA depth buffers need to be converted to single sample buffers.
1039 *
1040 * Mapping MSAA depth buffers can occur if ReadPixels is called
1041 * with a multisample GLX visual.
1042 *
1043 * First downsample the depth buffer to a temporary texture,
1044 * then decompress the temporary one to staging.
1045 *
1046 * Only the region being mapped is transfered.
1047 */
1048 struct pipe_resource resource;
1049
1050 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1051
1052 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1053 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1054 FREE(trans);
1055 return NULL;
1056 }
1057
1058 if (usage & PIPE_TRANSFER_READ) {
1059 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1060 if (!temp) {
1061 R600_ERR("failed to create a temporary depth texture\n");
1062 FREE(trans);
1063 return NULL;
1064 }
1065
1066 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1067 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1068 0, 0, 0, box->depth, 0, 0);
1069 pipe_resource_reference((struct pipe_resource**)&temp, NULL);
1070 }
1071 }
1072 else {
1073 /* XXX: only readback the rectangle which is being mapped? */
1074 /* XXX: when discard is true, no need to read back from depth texture */
1075 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1076 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1077 FREE(trans);
1078 return NULL;
1079 }
1080
1081 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1082 level, level,
1083 box->z, box->z + box->depth - 1,
1084 0, 0);
1085
1086 offset = r600_texture_get_offset(staging_depth, level, box);
1087 }
1088
1089 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
1090 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1091 trans->staging = (struct r600_resource*)staging_depth;
1092 } else if (use_staging_texture) {
1093 struct pipe_resource resource;
1094 struct r600_texture *staging;
1095
1096 r600_init_temp_resource_from_box(&resource, texture, box, level,
1097 R600_RESOURCE_FLAG_TRANSFER);
1098 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1099 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1100
1101 /* Create the temporary texture. */
1102 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1103 if (staging == NULL) {
1104 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1105 FREE(trans);
1106 return NULL;
1107 }
1108 trans->staging = &staging->resource;
1109 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1110 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1111 if (usage & PIPE_TRANSFER_READ) {
1112 r600_copy_to_staging_texture(ctx, trans);
1113 }
1114 } else {
1115 /* the resource is mapped directly */
1116 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1117 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1118 offset = r600_texture_get_offset(rtex, level, box);
1119 }
1120
1121 if (trans->staging) {
1122 buf = trans->staging;
1123 if (!rtex->is_depth && !(usage & PIPE_TRANSFER_READ))
1124 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1125 } else {
1126 buf = &rtex->resource;
1127 }
1128
1129 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1130 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1131 FREE(trans);
1132 return NULL;
1133 }
1134
1135 *ptransfer = &trans->transfer;
1136 return map + offset;
1137 }
1138
1139 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1140 struct pipe_transfer* transfer)
1141 {
1142 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1143 struct pipe_resource *texture = transfer->resource;
1144 struct r600_texture *rtex = (struct r600_texture*)texture;
1145
1146 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1147 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1148 ctx->resource_copy_region(ctx, texture, transfer->level,
1149 transfer->box.x, transfer->box.y, transfer->box.z,
1150 &rtransfer->staging->b.b, transfer->level,
1151 &transfer->box);
1152 } else {
1153 r600_copy_from_staging_texture(ctx, rtransfer);
1154 }
1155 }
1156
1157 if (rtransfer->staging)
1158 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1159
1160 FREE(transfer);
1161 }
1162
1163 static const struct u_resource_vtbl r600_texture_vtbl =
1164 {
1165 NULL, /* get_handle */
1166 r600_texture_destroy, /* resource_destroy */
1167 r600_texture_transfer_map, /* transfer_map */
1168 u_default_transfer_flush_region, /* transfer_flush_region */
1169 r600_texture_transfer_unmap, /* transfer_unmap */
1170 NULL /* transfer_inline_write */
1171 };
1172
1173 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1174 struct pipe_resource *texture,
1175 const struct pipe_surface *templ,
1176 unsigned width, unsigned height)
1177 {
1178 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1179
1180 if (surface == NULL)
1181 return NULL;
1182
1183 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1184 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1185
1186 pipe_reference_init(&surface->base.reference, 1);
1187 pipe_resource_reference(&surface->base.texture, texture);
1188 surface->base.context = pipe;
1189 surface->base.format = templ->format;
1190 surface->base.width = width;
1191 surface->base.height = height;
1192 surface->base.u = templ->u;
1193 return &surface->base;
1194 }
1195
1196 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1197 struct pipe_resource *tex,
1198 const struct pipe_surface *templ)
1199 {
1200 unsigned level = templ->u.tex.level;
1201
1202 return r600_create_surface_custom(pipe, tex, templ,
1203 u_minify(tex->width0, level),
1204 u_minify(tex->height0, level));
1205 }
1206
1207 static void r600_surface_destroy(struct pipe_context *pipe,
1208 struct pipe_surface *surface)
1209 {
1210 struct r600_surface *surf = (struct r600_surface*)surface;
1211 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1212 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1213 pipe_resource_reference(&surface->texture, NULL);
1214 FREE(surface);
1215 }
1216
1217 unsigned r600_translate_colorswap(enum pipe_format format)
1218 {
1219 const struct util_format_description *desc = util_format_description(format);
1220
1221 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1222
1223 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1224 return V_0280A0_SWAP_STD;
1225
1226 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1227 return ~0U;
1228
1229 switch (desc->nr_channels) {
1230 case 1:
1231 if (HAS_SWIZZLE(0,X))
1232 return V_0280A0_SWAP_STD; /* X___ */
1233 else if (HAS_SWIZZLE(3,X))
1234 return V_0280A0_SWAP_ALT_REV; /* ___X */
1235 break;
1236 case 2:
1237 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1238 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1239 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1240 return V_0280A0_SWAP_STD; /* XY__ */
1241 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1242 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1243 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1244 return V_0280A0_SWAP_STD_REV; /* YX__ */
1245 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1246 return V_0280A0_SWAP_ALT; /* X__Y */
1247 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1248 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1249 break;
1250 case 3:
1251 if (HAS_SWIZZLE(0,X))
1252 return V_0280A0_SWAP_STD; /* XYZ */
1253 else if (HAS_SWIZZLE(0,Z))
1254 return V_0280A0_SWAP_STD_REV; /* ZYX */
1255 break;
1256 case 4:
1257 /* check the middle channels, the 1st and 4th channel can be NONE */
1258 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
1259 return V_0280A0_SWAP_STD; /* XYZW */
1260 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
1261 return V_0280A0_SWAP_STD_REV; /* WZYX */
1262 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
1263 return V_0280A0_SWAP_ALT; /* ZYXW */
1264 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
1265 return V_0280A0_SWAP_ALT_REV; /* WXYZ */
1266 break;
1267 }
1268 return ~0U;
1269 }
1270
1271 static void evergreen_set_clear_color(struct r600_texture *rtex,
1272 enum pipe_format surface_format,
1273 const union pipe_color_union *color)
1274 {
1275 union util_color uc;
1276
1277 memset(&uc, 0, sizeof(uc));
1278
1279 if (util_format_is_pure_uint(surface_format)) {
1280 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1281 } else if (util_format_is_pure_sint(surface_format)) {
1282 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1283 } else {
1284 util_pack_color(color->f, surface_format, &uc);
1285 }
1286
1287 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1288 }
1289
1290 static void vi_get_fast_clear_parameters(enum pipe_format surface_format,
1291 const union pipe_color_union *color,
1292 uint32_t* reset_value,
1293 bool* clear_words_needed)
1294 {
1295 bool values[4] = {};
1296 int i;
1297 bool main_value = false;
1298 bool extra_value = false;
1299 int extra_channel;
1300 const struct util_format_description *desc = util_format_description(surface_format);
1301
1302 *clear_words_needed = true;
1303 *reset_value = 0x20202020U;
1304
1305 /* If we want to clear without needing a fast clear eliminate step, we
1306 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1307 * have two sets of flags, one for the last or first channel(extra) and
1308 * one for the other channels(main).
1309 */
1310
1311 if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
1312 surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
1313 surface_format == PIPE_FORMAT_B5G6R5_SRGB) {
1314 extra_channel = -1;
1315 } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
1316 if(r600_translate_colorswap(surface_format) <= 1)
1317 extra_channel = desc->nr_channels - 1;
1318 else
1319 extra_channel = 0;
1320 } else
1321 return;
1322
1323 for (i = 0; i < 4; ++i) {
1324 int index = desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X;
1325
1326 if (desc->swizzle[i] < UTIL_FORMAT_SWIZZLE_X ||
1327 desc->swizzle[i] > UTIL_FORMAT_SWIZZLE_W)
1328 continue;
1329
1330 if (util_format_is_pure_sint(surface_format)) {
1331 values[i] = color->i[i] != 0;
1332 if (color->i[i] != 0 && color->i[i] != INT32_MAX)
1333 return;
1334 } else if (util_format_is_pure_uint(surface_format)) {
1335 values[i] = color->ui[i] != 0U;
1336 if (color->ui[i] != 0U && color->ui[i] != UINT32_MAX)
1337 return;
1338 } else {
1339 values[i] = color->f[i] != 0.0F;
1340 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
1341 return;
1342 }
1343
1344 if (index == extra_channel)
1345 extra_value = values[i];
1346 else
1347 main_value = values[i];
1348 }
1349
1350 for (int i = 0; i < 4; ++i)
1351 if (values[i] != main_value &&
1352 desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X != extra_channel &&
1353 desc->swizzle[i] >= UTIL_FORMAT_SWIZZLE_X &&
1354 desc->swizzle[i] <= UTIL_FORMAT_SWIZZLE_W)
1355 return;
1356
1357 *clear_words_needed = false;
1358 if (main_value)
1359 *reset_value |= 0x80808080U;
1360
1361 if (extra_value)
1362 *reset_value |= 0x40404040U;
1363 }
1364
1365 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1366 struct pipe_framebuffer_state *fb,
1367 struct r600_atom *fb_state,
1368 unsigned *buffers, unsigned *dirty_cbufs,
1369 const union pipe_color_union *color)
1370 {
1371 int i;
1372
1373 if (rctx->render_cond)
1374 return;
1375
1376 for (i = 0; i < fb->nr_cbufs; i++) {
1377 struct r600_texture *tex;
1378 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1379
1380 if (!fb->cbufs[i])
1381 continue;
1382
1383 /* if this colorbuffer is not being cleared */
1384 if (!(*buffers & clear_bit))
1385 continue;
1386
1387 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1388
1389 /* 128-bit formats are unusupported */
1390 if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
1391 continue;
1392 }
1393
1394 /* the clear is allowed if all layers are bound */
1395 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1396 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1397 continue;
1398 }
1399
1400 /* cannot clear mipmapped textures */
1401 if (fb->cbufs[i]->texture->last_level != 0) {
1402 continue;
1403 }
1404
1405 /* only supported on tiled surfaces */
1406 if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
1407 continue;
1408 }
1409
1410 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1411 if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
1412 rctx->chip_class >= CIK &&
1413 rctx->screen->info.drm_major == 2 &&
1414 rctx->screen->info.drm_minor < 38) {
1415 continue;
1416 }
1417
1418 if (tex->dcc_buffer) {
1419 uint32_t reset_value;
1420 bool clear_words_needed;
1421
1422 if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
1423 continue;
1424
1425 vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed);
1426
1427 rctx->clear_buffer(&rctx->b, &tex->dcc_buffer->b.b,
1428 0, tex->surface.dcc_size, reset_value, true);
1429
1430 if (clear_words_needed)
1431 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1432 } else {
1433 /* ensure CMASK is enabled */
1434 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1435 if (tex->cmask.size == 0) {
1436 continue;
1437 }
1438
1439 /* Do the fast clear. */
1440 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1441 tex->cmask.offset, tex->cmask.size, 0, true);
1442
1443 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1444 }
1445
1446 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1447
1448 if (dirty_cbufs)
1449 *dirty_cbufs |= 1 << i;
1450 rctx->set_atom_dirty(rctx, fb_state, true);
1451 *buffers &= ~clear_bit;
1452 }
1453 }
1454
1455 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1456 {
1457 rscreen->b.resource_from_handle = r600_texture_from_handle;
1458 rscreen->b.resource_get_handle = r600_texture_get_handle;
1459 }
1460
1461 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1462 {
1463 rctx->b.create_surface = r600_create_surface;
1464 rctx->b.surface_destroy = r600_surface_destroy;
1465 }