2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static enum radeon_surf_mode
41 r600_choose_tiling(struct r600_common_screen
*rscreen
,
42 const struct pipe_resource
*templ
);
45 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
46 struct r600_texture
*rdst
,
47 unsigned dst_level
, unsigned dstx
,
48 unsigned dsty
, unsigned dstz
,
49 struct r600_texture
*rsrc
,
51 const struct pipe_box
*src_box
)
56 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
59 /* MSAA: Blits don't exist in the real world. */
60 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
61 rdst
->resource
.b
.b
.nr_samples
> 1)
64 /* Depth-stencil surfaces:
65 * When dst is linear, the DB->CB copy preserves HTILE.
66 * When dst is tiled, the 3D path must be used to update HTILE.
68 if (rsrc
->is_depth
|| rdst
->is_depth
)
72 * src: Use the 3D path. DCC decompression is expensive.
73 * dst: Use the 3D path to compress the pixels with DCC.
75 if (vi_dcc_enabled(rsrc
, src_level
) ||
76 vi_dcc_enabled(rdst
, dst_level
))
80 * src: Both texture and SDMA paths need decompression. Use SDMA.
81 * dst: If overwriting the whole texture, discard CMASK and use
82 * SDMA. Otherwise, use the 3D path.
84 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
85 /* The CMASK clear is only enabled for the first level. */
86 assert(dst_level
== 0);
87 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
88 dstx
, dsty
, dstz
, src_box
->width
,
89 src_box
->height
, src_box
->depth
))
92 r600_texture_discard_cmask(rctx
->screen
, rdst
);
95 /* All requirements are met. Prepare textures for SDMA. */
96 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
97 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
99 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
100 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
105 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
106 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
107 struct pipe_resource
*dst
,
109 unsigned dstx
, unsigned dsty
, unsigned dstz
,
110 struct pipe_resource
*src
,
112 const struct pipe_box
*src_box
)
114 struct pipe_blit_info blit
;
116 memset(&blit
, 0, sizeof(blit
));
117 blit
.src
.resource
= src
;
118 blit
.src
.format
= src
->format
;
119 blit
.src
.level
= src_level
;
120 blit
.src
.box
= *src_box
;
121 blit
.dst
.resource
= dst
;
122 blit
.dst
.format
= dst
->format
;
123 blit
.dst
.level
= dst_level
;
124 blit
.dst
.box
.x
= dstx
;
125 blit
.dst
.box
.y
= dsty
;
126 blit
.dst
.box
.z
= dstz
;
127 blit
.dst
.box
.width
= src_box
->width
;
128 blit
.dst
.box
.height
= src_box
->height
;
129 blit
.dst
.box
.depth
= src_box
->depth
;
130 blit
.mask
= util_format_get_mask(src
->format
) &
131 util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
142 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
144 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1) {
148 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
160 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1) {
169 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
176 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
180 static unsigned r600_texture_get_offset(struct r600_common_screen
*rscreen
,
181 struct r600_texture
*rtex
, unsigned level
,
182 const struct pipe_box
*box
,
184 unsigned *layer_stride
)
186 if (rscreen
->chip_class
>= GFX9
) {
187 *stride
= rtex
->surface
.u
.gfx9
.surf_pitch
* rtex
->surface
.bpe
;
188 *layer_stride
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
193 /* Each texture is an array of slices. Each slice is an array
194 * of mipmap levels. */
195 return box
->z
* rtex
->surface
.u
.gfx9
.surf_slice_size
+
196 rtex
->surface
.u
.gfx9
.offset
[level
] +
197 (box
->y
/ rtex
->surface
.blk_h
*
198 rtex
->surface
.u
.gfx9
.surf_pitch
+
199 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
201 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
203 *layer_stride
= rtex
->surface
.u
.legacy
.level
[level
].slice_size
;
206 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
208 /* Each texture is an array of mipmap levels. Each level is
209 * an array of slices. */
210 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
211 box
->z
* rtex
->surface
.u
.legacy
.level
[level
].slice_size
+
212 (box
->y
/ rtex
->surface
.blk_h
*
213 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
214 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
218 static int r600_init_surface(struct r600_common_screen
*rscreen
,
219 struct radeon_surf
*surface
,
220 const struct pipe_resource
*ptex
,
221 enum radeon_surf_mode array_mode
,
222 unsigned pitch_in_bytes_override
,
226 bool is_flushed_depth
,
227 bool tc_compatible_htile
)
229 const struct util_format_description
*desc
=
230 util_format_description(ptex
->format
);
231 bool is_depth
, is_stencil
;
233 unsigned i
, bpe
, flags
= 0;
235 is_depth
= util_format_has_depth(desc
);
236 is_stencil
= util_format_has_stencil(desc
);
238 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
239 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
240 bpe
= 4; /* stencil is allocated separately on evergreen */
242 bpe
= util_format_get_blocksize(ptex
->format
);
243 assert(util_is_power_of_two(bpe
));
246 if (!is_flushed_depth
&& is_depth
) {
247 flags
|= RADEON_SURF_ZBUFFER
;
249 if (tc_compatible_htile
&&
250 (rscreen
->chip_class
>= GFX9
||
251 array_mode
== RADEON_SURF_MODE_2D
)) {
252 /* TC-compatible HTILE only supports Z32_FLOAT.
253 * GFX9 also supports Z16_UNORM.
254 * On VI, promote Z16 to Z32. DB->CB copies will convert
255 * the format for transfers.
257 if (rscreen
->chip_class
== VI
)
260 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
264 flags
|= RADEON_SURF_SBUFFER
;
267 if (rscreen
->chip_class
>= VI
&&
268 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
269 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
270 flags
|= RADEON_SURF_DISABLE_DCC
;
272 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
273 /* This should catch bugs in gallium users setting incorrect flags. */
274 assert(ptex
->nr_samples
<= 1 &&
275 ptex
->array_size
== 1 &&
277 ptex
->last_level
== 0 &&
278 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
280 flags
|= RADEON_SURF_SCANOUT
;
284 flags
|= RADEON_SURF_IMPORTED
;
285 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
286 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
288 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
289 array_mode
, surface
);
294 if (rscreen
->chip_class
>= GFX9
) {
295 assert(!pitch_in_bytes_override
||
296 pitch_in_bytes_override
== surface
->u
.gfx9
.surf_pitch
* bpe
);
297 surface
->u
.gfx9
.surf_offset
= offset
;
299 if (pitch_in_bytes_override
&&
300 pitch_in_bytes_override
!= surface
->u
.legacy
.level
[0].nblk_x
* bpe
) {
301 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
304 surface
->u
.legacy
.level
[0].nblk_x
= pitch_in_bytes_override
/ bpe
;
305 surface
->u
.legacy
.level
[0].slice_size
= pitch_in_bytes_override
*
306 surface
->u
.legacy
.level
[0].nblk_y
;
310 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
311 surface
->u
.legacy
.level
[i
].offset
+= offset
;
317 static void r600_texture_init_metadata(struct r600_common_screen
*rscreen
,
318 struct r600_texture
*rtex
,
319 struct radeon_bo_metadata
*metadata
)
321 struct radeon_surf
*surface
= &rtex
->surface
;
323 memset(metadata
, 0, sizeof(*metadata
));
325 if (rscreen
->chip_class
>= GFX9
) {
326 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
328 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
329 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
330 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
331 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
332 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
333 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
334 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
335 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
336 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
337 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
338 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
339 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
343 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
344 struct r600_texture
*rtex
)
346 struct r600_common_screen
*rscreen
= rctx
->screen
;
347 struct pipe_context
*ctx
= &rctx
->b
;
349 if (ctx
== rscreen
->aux_context
)
350 mtx_lock(&rscreen
->aux_context_lock
);
352 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
353 ctx
->flush(ctx
, NULL
, 0);
355 if (ctx
== rscreen
->aux_context
)
356 mtx_unlock(&rscreen
->aux_context_lock
);
359 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
360 struct r600_texture
*rtex
)
362 if (!rtex
->cmask
.size
)
365 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
368 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
369 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
370 rtex
->dirty_level_mask
= 0;
372 if (rscreen
->chip_class
>= SI
)
373 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
375 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
377 if (rtex
->cmask_buffer
!= &rtex
->resource
)
378 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
380 /* Notify all contexts about the change. */
381 p_atomic_inc(&rscreen
->dirty_tex_counter
);
382 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
385 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
387 /* We can't disable DCC if it can be written by another process. */
388 return rtex
->dcc_offset
&&
389 (!rtex
->resource
.b
.is_shared
||
390 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
393 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
394 struct r600_texture
*rtex
)
396 if (!r600_can_disable_dcc(rtex
))
399 assert(rtex
->dcc_separate_buffer
== NULL
);
402 rtex
->dcc_offset
= 0;
404 /* Notify all contexts about the change. */
405 p_atomic_inc(&rscreen
->dirty_tex_counter
);
410 * Disable DCC for the texture. (first decompress, then discard metadata).
412 * There is unresolved multi-context synchronization issue between
413 * screen::aux_context and the current context. If applications do this with
414 * multiple contexts, it's already undefined behavior for them and we don't
415 * have to worry about that. The scenario is:
417 * If context 1 disables DCC and context 2 has queued commands that write
418 * to the texture via CB with DCC enabled, and the order of operations is
420 * context 2 queues draw calls rendering to the texture, but doesn't flush
421 * context 1 disables DCC and flushes
422 * context 1 & 2 reset descriptors and FB state
423 * context 2 flushes (new compressed tiles written by the draw calls)
424 * context 1 & 2 read garbage, because DCC is disabled, yet there are
427 * \param rctx the current context if you have one, or rscreen->aux_context
430 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
431 struct r600_texture
*rtex
)
433 struct r600_common_screen
*rscreen
= rctx
->screen
;
435 if (!r600_can_disable_dcc(rtex
))
438 if (&rctx
->b
== rscreen
->aux_context
)
439 mtx_lock(&rscreen
->aux_context_lock
);
441 /* Decompress DCC. */
442 rctx
->decompress_dcc(&rctx
->b
, rtex
);
443 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
445 if (&rctx
->b
== rscreen
->aux_context
)
446 mtx_unlock(&rscreen
->aux_context_lock
);
448 return r600_texture_discard_dcc(rscreen
, rtex
);
451 static void r600_reallocate_texture_inplace(struct r600_common_context
*rctx
,
452 struct r600_texture
*rtex
,
453 unsigned new_bind_flag
,
454 bool invalidate_storage
)
456 struct pipe_screen
*screen
= rctx
->b
.screen
;
457 struct r600_texture
*new_tex
;
458 struct pipe_resource templ
= rtex
->resource
.b
.b
;
461 templ
.bind
|= new_bind_flag
;
463 /* r600g doesn't react to dirty_tex_descriptor_counter */
464 if (rctx
->chip_class
< SI
)
467 if (rtex
->resource
.b
.is_shared
)
470 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
471 if (rtex
->surface
.is_linear
)
474 /* This fails with MSAA, depth, and compressed textures. */
475 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
476 RADEON_SURF_MODE_LINEAR_ALIGNED
)
480 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
484 /* Copy the pixels to the new texture. */
485 if (!invalidate_storage
) {
486 for (i
= 0; i
<= templ
.last_level
; i
++) {
490 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
491 util_max_layer(&templ
, i
) + 1, &box
);
493 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
494 &rtex
->resource
.b
.b
, i
, &box
);
498 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
499 r600_texture_discard_cmask(rctx
->screen
, rtex
);
500 r600_texture_discard_dcc(rctx
->screen
, rtex
);
503 /* Replace the structure fields of rtex. */
504 rtex
->resource
.b
.b
.bind
= templ
.bind
;
505 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
506 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
507 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
508 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
509 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
510 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
511 rtex
->resource
.domains
= new_tex
->resource
.domains
;
512 rtex
->resource
.flags
= new_tex
->resource
.flags
;
513 rtex
->size
= new_tex
->size
;
514 rtex
->db_render_format
= new_tex
->db_render_format
;
515 rtex
->db_compatible
= new_tex
->db_compatible
;
516 rtex
->can_sample_z
= new_tex
->can_sample_z
;
517 rtex
->can_sample_s
= new_tex
->can_sample_s
;
518 rtex
->surface
= new_tex
->surface
;
519 rtex
->fmask
= new_tex
->fmask
;
520 rtex
->cmask
= new_tex
->cmask
;
521 rtex
->cb_color_info
= new_tex
->cb_color_info
;
522 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
523 rtex
->htile_offset
= new_tex
->htile_offset
;
524 rtex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
525 rtex
->depth_cleared
= new_tex
->depth_cleared
;
526 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
527 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
528 rtex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
529 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
531 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
532 assert(!rtex
->htile_offset
);
533 assert(!rtex
->cmask
.size
);
534 assert(!rtex
->fmask
.size
);
535 assert(!rtex
->dcc_offset
);
536 assert(!rtex
->is_depth
);
539 r600_texture_reference(&new_tex
, NULL
);
541 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
544 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
545 struct pipe_context
*ctx
,
546 struct pipe_resource
*resource
,
547 struct winsys_handle
*whandle
,
550 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
551 struct r600_common_context
*rctx
;
552 struct r600_resource
*res
= (struct r600_resource
*)resource
;
553 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
554 struct radeon_bo_metadata metadata
;
555 bool update_metadata
= false;
556 unsigned stride
, offset
, slice_size
;
558 ctx
= threaded_context_unwrap_sync(ctx
);
559 rctx
= (struct r600_common_context
*)(ctx
? ctx
: rscreen
->aux_context
);
561 if (resource
->target
!= PIPE_BUFFER
) {
562 /* This is not supported now, but it might be required for OpenCL
563 * interop in the future.
565 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
568 /* Since shader image stores don't support DCC on VI,
569 * disable it for external clients that want write
572 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
573 if (r600_texture_disable_dcc(rctx
, rtex
))
574 update_metadata
= true;
577 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
578 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
579 /* Eliminate fast clear (both CMASK and DCC) */
580 r600_eliminate_fast_color_clear(rctx
, rtex
);
582 /* Disable CMASK if flush_resource isn't going
585 if (rtex
->cmask
.size
)
586 r600_texture_discard_cmask(rscreen
, rtex
);
590 if (!res
->b
.is_shared
|| update_metadata
) {
591 r600_texture_init_metadata(rscreen
, rtex
, &metadata
);
592 if (rscreen
->query_opaque_metadata
)
593 rscreen
->query_opaque_metadata(rscreen
, rtex
,
596 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
599 if (rscreen
->chip_class
>= GFX9
) {
600 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
601 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
603 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
605 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
606 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
608 slice_size
= rtex
->surface
.u
.legacy
.level
[0].slice_size
;
617 if (res
->b
.is_shared
) {
618 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
621 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
622 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
623 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
625 res
->b
.is_shared
= true;
626 res
->external_usage
= usage
;
629 return rscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
630 slice_size
, whandle
);
633 static void r600_texture_destroy(struct pipe_screen
*screen
,
634 struct pipe_resource
*ptex
)
636 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
637 struct r600_resource
*resource
= &rtex
->resource
;
639 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
641 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
642 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
644 pb_reference(&resource
->buf
, NULL
);
645 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
646 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
650 static const struct u_resource_vtbl r600_texture_vtbl
;
652 /* The number of samples can be specified independently of the texture. */
653 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
654 struct r600_texture
*rtex
,
656 struct r600_fmask_info
*out
)
658 /* FMASK is allocated like an ordinary texture. */
659 struct pipe_resource templ
= rtex
->resource
.b
.b
;
660 struct radeon_surf fmask
= {};
663 memset(out
, 0, sizeof(*out
));
665 if (rscreen
->chip_class
>= GFX9
) {
666 out
->alignment
= rtex
->surface
.u
.gfx9
.fmask_alignment
;
667 out
->size
= rtex
->surface
.u
.gfx9
.fmask_size
;
671 templ
.nr_samples
= 1;
672 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
674 if (rscreen
->chip_class
<= CAYMAN
) {
675 /* Use the same parameters and tile mode. */
676 fmask
.u
.legacy
.bankw
= rtex
->surface
.u
.legacy
.bankw
;
677 fmask
.u
.legacy
.bankh
= rtex
->surface
.u
.legacy
.bankh
;
678 fmask
.u
.legacy
.mtilea
= rtex
->surface
.u
.legacy
.mtilea
;
679 fmask
.u
.legacy
.tile_split
= rtex
->surface
.u
.legacy
.tile_split
;
682 fmask
.u
.legacy
.bankh
= 4;
685 switch (nr_samples
) {
694 R600_ERR("Invalid sample count for FMASK allocation.\n");
698 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
699 * This can be fixed by writing a separate FMASK allocator specifically
700 * for R600-R700 asics. */
701 if (rscreen
->chip_class
<= R700
) {
705 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
706 RADEON_SURF_MODE_2D
, &fmask
)) {
707 R600_ERR("Got error in surface_init while allocating FMASK.\n");
711 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
713 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
714 if (out
->slice_tile_max
)
715 out
->slice_tile_max
-= 1;
717 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
718 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
719 out
->bank_height
= fmask
.u
.legacy
.bankh
;
720 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
721 out
->size
= fmask
.surf_size
;
724 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
725 struct r600_texture
*rtex
)
727 r600_texture_get_fmask_info(rscreen
, rtex
,
728 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
730 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
731 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
734 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
735 struct r600_texture
*rtex
,
736 struct r600_cmask_info
*out
)
738 unsigned cmask_tile_width
= 8;
739 unsigned cmask_tile_height
= 8;
740 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
741 unsigned element_bits
= 4;
742 unsigned cmask_cache_bits
= 1024;
743 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
744 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
746 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
747 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
748 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
749 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
750 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
752 unsigned pitch_elements
= align(rtex
->resource
.b
.b
.width0
, macro_tile_width
);
753 unsigned height
= align(rtex
->resource
.b
.b
.height0
, macro_tile_height
);
755 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
756 unsigned slice_bytes
=
757 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
759 assert(macro_tile_width
% 128 == 0);
760 assert(macro_tile_height
% 128 == 0);
762 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
763 out
->alignment
= MAX2(256, base_align
);
764 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
765 align(slice_bytes
, base_align
);
768 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
769 struct r600_texture
*rtex
,
770 struct r600_cmask_info
*out
)
772 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
773 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
774 unsigned cl_width
, cl_height
;
776 if (rscreen
->chip_class
>= GFX9
) {
777 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
778 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
795 case 16: /* Hawaii */
804 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
806 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
807 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
808 unsigned slice_elements
= (width
* height
) / (8*8);
810 /* Each element of CMASK is a nibble. */
811 unsigned slice_bytes
= slice_elements
/ 2;
813 out
->slice_tile_max
= (width
* height
) / (128*128);
814 if (out
->slice_tile_max
)
815 out
->slice_tile_max
-= 1;
817 out
->alignment
= MAX2(256, base_align
);
818 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
819 align(slice_bytes
, base_align
);
822 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
823 struct r600_texture
*rtex
)
825 if (rscreen
->chip_class
>= SI
) {
826 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
828 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
831 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
832 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
834 if (rscreen
->chip_class
>= SI
)
835 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
837 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
840 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
841 struct r600_texture
*rtex
)
843 if (rtex
->cmask_buffer
)
846 assert(rtex
->cmask
.size
== 0);
848 if (rscreen
->chip_class
>= SI
) {
849 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
851 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
854 rtex
->cmask_buffer
= (struct r600_resource
*)
855 r600_aligned_buffer_create(&rscreen
->b
,
856 R600_RESOURCE_FLAG_UNMAPPABLE
,
859 rtex
->cmask
.alignment
);
860 if (rtex
->cmask_buffer
== NULL
) {
861 rtex
->cmask
.size
= 0;
865 /* update colorbuffer state bits */
866 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
868 if (rscreen
->chip_class
>= SI
)
869 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
871 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
873 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
876 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
877 struct r600_texture
*rtex
)
879 unsigned cl_width
, cl_height
, width
, height
;
880 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
881 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
883 assert(rscreen
->chip_class
<= VI
);
885 rtex
->surface
.htile_size
= 0;
887 if (rscreen
->chip_class
<= EVERGREEN
&&
888 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
891 /* HW bug on R6xx. */
892 if (rscreen
->chip_class
== R600
&&
893 (rtex
->resource
.b
.b
.width0
> 7680 ||
894 rtex
->resource
.b
.b
.height0
> 7680))
897 /* HTILE is broken with 1D tiling on old kernels and CIK. */
898 if (rscreen
->chip_class
>= CIK
&&
899 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
900 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
903 /* Overalign HTILE on P2 configs to work around GPU hangs in
904 * piglit/depthstencil-render-miplevels 585.
906 * This has been confirmed to help Kabini & Stoney, where the hangs
907 * are always reproducible. I think I have seen the test hang
908 * on Carrizo too, though it was very rare there.
910 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
939 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
940 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
942 slice_elements
= (width
* height
) / (8 * 8);
943 slice_bytes
= slice_elements
* 4;
945 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
946 base_align
= num_pipes
* pipe_interleave_bytes
;
948 rtex
->surface
.htile_alignment
= base_align
;
949 rtex
->surface
.htile_size
=
950 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
951 align(slice_bytes
, base_align
);
954 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
955 struct r600_texture
*rtex
)
957 if (rscreen
->chip_class
<= VI
&& !rtex
->tc_compatible_htile
)
958 r600_texture_get_htile_size(rscreen
, rtex
);
960 if (!rtex
->surface
.htile_size
)
963 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
964 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
967 void r600_print_texture_info(struct r600_common_screen
*rscreen
,
968 struct r600_texture
*rtex
, FILE *f
)
972 /* Common parameters. */
973 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
974 "blk_h=%u, array_size=%u, last_level=%u, "
975 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
976 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
977 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
979 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
980 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
981 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
983 if (rscreen
->chip_class
>= GFX9
) {
984 fprintf(f
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
985 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
986 rtex
->surface
.surf_size
,
987 rtex
->surface
.u
.gfx9
.surf_slice_size
,
988 rtex
->surface
.surf_alignment
,
989 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
990 rtex
->surface
.u
.gfx9
.surf
.epitch
,
991 rtex
->surface
.u
.gfx9
.surf_pitch
);
993 if (rtex
->fmask
.size
) {
994 fprintf(f
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
995 "alignment=%u, swmode=%u, epitch=%u\n",
997 rtex
->surface
.u
.gfx9
.fmask_size
,
998 rtex
->surface
.u
.gfx9
.fmask_alignment
,
999 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1000 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
1003 if (rtex
->cmask
.size
) {
1004 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
1005 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1007 rtex
->surface
.u
.gfx9
.cmask_size
,
1008 rtex
->surface
.u
.gfx9
.cmask_alignment
,
1009 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1010 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1013 if (rtex
->htile_offset
) {
1014 fprintf(f
, " HTile: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1015 "rb_aligned=%u, pipe_aligned=%u\n",
1017 rtex
->surface
.htile_size
,
1018 rtex
->surface
.htile_alignment
,
1019 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1020 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1023 if (rtex
->dcc_offset
) {
1024 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", "
1025 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1026 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1027 rtex
->surface
.dcc_alignment
,
1028 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
1029 rtex
->surface
.num_dcc_levels
);
1032 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
1033 fprintf(f
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1034 rtex
->surface
.u
.gfx9
.stencil_offset
,
1035 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1036 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1041 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1042 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1043 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1044 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1045 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1046 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1048 if (rtex
->fmask
.size
)
1049 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1050 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1051 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
1052 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
1053 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
1055 if (rtex
->cmask
.size
)
1056 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1057 "slice_tile_max=%u\n",
1058 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1059 rtex
->cmask
.slice_tile_max
);
1061 if (rtex
->htile_offset
)
1062 fprintf(f
, " HTile: offset=%"PRIu64
", size=%"PRIu64
", "
1063 "alignment=%u, TC_compatible = %u\n",
1064 rtex
->htile_offset
, rtex
->surface
.htile_size
,
1065 rtex
->surface
.htile_alignment
,
1066 rtex
->tc_compatible_htile
);
1068 if (rtex
->dcc_offset
) {
1069 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u\n",
1070 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1071 rtex
->surface
.dcc_alignment
);
1072 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1073 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
1074 "fast_clear_size=%"PRIu64
"\n",
1075 i
, i
< rtex
->surface
.num_dcc_levels
,
1076 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1077 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1080 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1081 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1082 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1083 "mode=%u, tiling_index = %u\n",
1084 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1085 rtex
->surface
.u
.legacy
.level
[i
].slice_size
,
1086 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1087 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1088 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1089 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1090 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1091 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1092 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1094 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1095 fprintf(f
, " StencilLayout: tilesplit=%u\n",
1096 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1097 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
1098 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
1099 "slice_size=%"PRIu64
", npix_x=%u, "
1100 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1101 "mode=%u, tiling_index = %u\n",
1102 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1103 rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size
,
1104 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1105 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1106 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1107 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1108 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1109 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1110 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1115 /* Common processing for r600_texture_create and r600_texture_from_handle */
1116 static struct r600_texture
*
1117 r600_texture_create_object(struct pipe_screen
*screen
,
1118 const struct pipe_resource
*base
,
1119 struct pb_buffer
*buf
,
1120 struct radeon_surf
*surface
)
1122 struct r600_texture
*rtex
;
1123 struct r600_resource
*resource
;
1124 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1126 rtex
= CALLOC_STRUCT(r600_texture
);
1130 resource
= &rtex
->resource
;
1131 resource
->b
.b
= *base
;
1132 resource
->b
.b
.next
= NULL
;
1133 resource
->b
.vtbl
= &r600_texture_vtbl
;
1134 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1135 resource
->b
.b
.screen
= screen
;
1137 /* don't include stencil-only formats which we don't support for rendering */
1138 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1140 rtex
->surface
= *surface
;
1141 rtex
->size
= rtex
->surface
.surf_size
;
1143 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1144 (rtex
->surface
.flags
&
1145 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1147 /* TC-compatible HTILE:
1148 * - VI only supports Z32_FLOAT.
1149 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1150 if (rtex
->tc_compatible_htile
) {
1151 if (rscreen
->chip_class
>= GFX9
&&
1152 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1153 rtex
->db_render_format
= base
->format
;
1155 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1157 rtex
->db_render_format
= base
->format
;
1160 /* Tiled depth textures utilize the non-displayable tile order.
1161 * This must be done after r600_setup_surface.
1162 * Applies to R600-Cayman. */
1163 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1164 /* Applies to GCN. */
1165 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1167 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1168 * between frames, so the only thing that can enable separate DCC
1169 * with DRI2 is multiple slow clears within a frame.
1171 rtex
->ps_draw_ratio
= 0;
1173 if (rtex
->is_depth
) {
1174 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1175 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1176 rscreen
->chip_class
>= EVERGREEN
) {
1177 if (rscreen
->chip_class
>= GFX9
) {
1178 rtex
->can_sample_z
= true;
1179 rtex
->can_sample_s
= true;
1181 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1182 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1185 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1186 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1187 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1188 rtex
->can_sample_z
= true;
1191 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1192 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1193 rtex
->db_compatible
= true;
1195 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1196 r600_texture_allocate_htile(rscreen
, rtex
);
1199 if (base
->nr_samples
> 1) {
1201 r600_texture_allocate_fmask(rscreen
, rtex
);
1202 r600_texture_allocate_cmask(rscreen
, rtex
);
1203 rtex
->cmask_buffer
= &rtex
->resource
;
1205 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1211 /* Shared textures must always set up DCC here.
1212 * If it's not present, it will be disabled by
1213 * apply_opaque_metadata later.
1215 if (rtex
->surface
.dcc_size
&&
1216 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1217 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1218 /* Reserve space for the DCC buffer. */
1219 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1220 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1224 /* Now create the backing buffer. */
1226 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
1227 rtex
->surface
.surf_alignment
);
1229 resource
->flags
|= RADEON_FLAG_NO_SUBALLOC
;
1231 if (!r600_alloc_resource(rscreen
, resource
)) {
1236 resource
->buf
= buf
;
1237 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1238 resource
->bo_size
= buf
->size
;
1239 resource
->bo_alignment
= buf
->alignment
;
1240 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1241 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1242 resource
->vram_usage
= buf
->size
;
1243 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1244 resource
->gart_usage
= buf
->size
;
1247 if (rtex
->cmask
.size
) {
1248 /* Initialize the cmask to 0xCC (= compressed state). */
1249 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1250 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1253 if (rtex
->htile_offset
) {
1254 uint32_t clear_value
= 0;
1256 if (rscreen
->chip_class
>= GFX9
|| rtex
->tc_compatible_htile
)
1257 clear_value
= 0x0000030F;
1259 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1261 rtex
->surface
.htile_size
,
1265 /* Initialize DCC only if the texture is not being imported. */
1266 if (!buf
&& rtex
->dcc_offset
) {
1267 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1269 rtex
->surface
.dcc_size
,
1273 /* Initialize the CMASK base register value. */
1274 rtex
->cmask
.base_address_reg
=
1275 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1277 if (rscreen
->debug_flags
& DBG_VM
) {
1278 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1279 rtex
->resource
.gpu_address
,
1280 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1281 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1282 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1285 if (rscreen
->debug_flags
& DBG_TEX
) {
1287 r600_print_texture_info(rscreen
, rtex
, stdout
);
1294 static enum radeon_surf_mode
1295 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1296 const struct pipe_resource
*templ
)
1298 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1299 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1300 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1301 !(templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1303 /* MSAA resources must be 2D tiled. */
1304 if (templ
->nr_samples
> 1)
1305 return RADEON_SURF_MODE_2D
;
1307 /* Transfer resources should be linear. */
1308 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1309 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1311 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1312 * which requires 2D tiling.
1314 if (rscreen
->chip_class
== VI
&&
1316 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
))
1317 return RADEON_SURF_MODE_2D
;
1319 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1320 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1321 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1322 (templ
->target
== PIPE_TEXTURE_2D
||
1323 templ
->target
== PIPE_TEXTURE_3D
))
1324 force_tiling
= true;
1326 /* Handle common candidates for the linear mode.
1327 * Compressed textures and DB surfaces must always be tiled.
1329 if (!force_tiling
&&
1330 !is_depth_stencil
&&
1331 !util_format_is_compressed(templ
->format
)) {
1332 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1333 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1335 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1336 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1337 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1339 /* Cursors are linear on SI.
1340 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1341 if (rscreen
->chip_class
>= SI
&&
1342 (templ
->bind
& PIPE_BIND_CURSOR
))
1343 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1345 if (templ
->bind
& PIPE_BIND_LINEAR
)
1346 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1348 /* Textures with a very small height are recommended to be linear. */
1349 if (templ
->target
== PIPE_TEXTURE_1D
||
1350 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1351 /* Only very thin and long 2D textures should benefit from
1352 * linear_aligned. */
1353 (templ
->width0
> 8 && templ
->height0
<= 2))
1354 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1356 /* Textures likely to be mapped often. */
1357 if (templ
->usage
== PIPE_USAGE_STAGING
||
1358 templ
->usage
== PIPE_USAGE_STREAM
)
1359 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1362 /* Make small textures 1D tiled. */
1363 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1364 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1365 return RADEON_SURF_MODE_1D
;
1367 /* The allocator will switch to 1D if needed. */
1368 return RADEON_SURF_MODE_2D
;
1371 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1372 const struct pipe_resource
*templ
)
1374 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1375 struct radeon_surf surface
= {0};
1376 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1377 bool tc_compatible_htile
=
1378 rscreen
->chip_class
>= VI
&&
1379 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1380 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
) &&
1381 !is_flushed_depth
&&
1382 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1383 util_format_is_depth_or_stencil(templ
->format
);
1387 r
= r600_init_surface(rscreen
, &surface
, templ
,
1388 r600_choose_tiling(rscreen
, templ
), 0, 0,
1389 false, false, is_flushed_depth
,
1390 tc_compatible_htile
);
1395 return (struct pipe_resource
*)
1396 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1399 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1400 const struct pipe_resource
*templ
,
1401 struct winsys_handle
*whandle
,
1404 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1405 struct pb_buffer
*buf
= NULL
;
1406 unsigned stride
= 0, offset
= 0;
1407 unsigned array_mode
;
1408 struct radeon_surf surface
;
1410 struct radeon_bo_metadata metadata
= {};
1411 struct r600_texture
*rtex
;
1414 /* Support only 2D textures without mipmaps */
1415 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1416 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1419 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1423 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1425 if (rscreen
->chip_class
>= GFX9
) {
1426 if (metadata
.u
.gfx9
.swizzle_mode
> 0)
1427 array_mode
= RADEON_SURF_MODE_2D
;
1429 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1431 is_scanout
= metadata
.u
.gfx9
.swizzle_mode
== 0 ||
1432 metadata
.u
.gfx9
.swizzle_mode
% 4 == 2;
1434 surface
.u
.legacy
.pipe_config
= metadata
.u
.legacy
.pipe_config
;
1435 surface
.u
.legacy
.bankw
= metadata
.u
.legacy
.bankw
;
1436 surface
.u
.legacy
.bankh
= metadata
.u
.legacy
.bankh
;
1437 surface
.u
.legacy
.tile_split
= metadata
.u
.legacy
.tile_split
;
1438 surface
.u
.legacy
.mtilea
= metadata
.u
.legacy
.mtilea
;
1439 surface
.u
.legacy
.num_banks
= metadata
.u
.legacy
.num_banks
;
1441 if (metadata
.u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
1442 array_mode
= RADEON_SURF_MODE_2D
;
1443 else if (metadata
.u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
1444 array_mode
= RADEON_SURF_MODE_1D
;
1446 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1448 is_scanout
= metadata
.u
.legacy
.scanout
;
1451 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1452 offset
, true, is_scanout
, false, false);
1457 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1461 rtex
->resource
.b
.is_shared
= true;
1462 rtex
->resource
.external_usage
= usage
;
1464 if (rscreen
->apply_opaque_metadata
)
1465 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1467 /* Validate that addrlib arrived at the same surface parameters. */
1468 if (rscreen
->chip_class
>= GFX9
) {
1469 assert(metadata
.u
.gfx9
.swizzle_mode
== surface
.u
.gfx9
.surf
.swizzle_mode
);
1472 return &rtex
->resource
.b
.b
;
1475 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1476 struct pipe_resource
*texture
,
1477 struct r600_texture
**staging
)
1479 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1480 struct pipe_resource resource
;
1481 struct r600_texture
**flushed_depth_texture
= staging
?
1482 staging
: &rtex
->flushed_depth_texture
;
1483 enum pipe_format pipe_format
= texture
->format
;
1486 if (rtex
->flushed_depth_texture
)
1487 return true; /* it's ready */
1489 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1490 switch (pipe_format
) {
1491 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1492 /* Save memory by not allocating the S plane. */
1493 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1495 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1496 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1497 /* Save memory bandwidth by not copying the
1498 * stencil part during flush.
1500 * This potentially increases memory bandwidth
1501 * if an application uses both Z and S texturing
1502 * simultaneously (a flushed Z24S8 texture
1503 * would be stored compactly), but how often
1504 * does that really happen?
1506 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1510 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1511 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1513 /* DB->CB copies to an 8bpp surface don't work. */
1514 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1518 memset(&resource
, 0, sizeof(resource
));
1519 resource
.target
= texture
->target
;
1520 resource
.format
= pipe_format
;
1521 resource
.width0
= texture
->width0
;
1522 resource
.height0
= texture
->height0
;
1523 resource
.depth0
= texture
->depth0
;
1524 resource
.array_size
= texture
->array_size
;
1525 resource
.last_level
= texture
->last_level
;
1526 resource
.nr_samples
= texture
->nr_samples
;
1527 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1528 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1529 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1532 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1534 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1535 if (*flushed_depth_texture
== NULL
) {
1536 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1540 (*flushed_depth_texture
)->non_disp_tiling
= false;
1545 * Initialize the pipe_resource descriptor to be of the same size as the box,
1546 * which is supposed to hold a subregion of the texture "orig" at the given
1549 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1550 struct pipe_resource
*orig
,
1551 const struct pipe_box
*box
,
1552 unsigned level
, unsigned flags
)
1554 memset(res
, 0, sizeof(*res
));
1555 res
->format
= orig
->format
;
1556 res
->width0
= box
->width
;
1557 res
->height0
= box
->height
;
1559 res
->array_size
= 1;
1560 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1563 /* We must set the correct texture target and dimensions for a 3D box. */
1564 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1565 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1566 res
->array_size
= box
->depth
;
1568 res
->target
= PIPE_TEXTURE_2D
;
1572 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1573 struct r600_texture
*rtex
,
1574 unsigned transfer_usage
,
1575 const struct pipe_box
*box
)
1577 /* r600g doesn't react to dirty_tex_descriptor_counter */
1578 return rscreen
->chip_class
>= SI
&&
1579 !rtex
->resource
.b
.is_shared
&&
1580 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1581 rtex
->resource
.b
.b
.last_level
== 0 &&
1582 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1583 box
->x
, box
->y
, box
->z
,
1584 box
->width
, box
->height
,
1588 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1589 struct r600_texture
*rtex
)
1591 struct r600_common_screen
*rscreen
= rctx
->screen
;
1593 /* There is no point in discarding depth and tiled buffers. */
1594 assert(!rtex
->is_depth
);
1595 assert(rtex
->surface
.is_linear
);
1597 /* Reallocate the buffer in the same pipe_resource. */
1598 r600_alloc_resource(rscreen
, &rtex
->resource
);
1600 /* Initialize the CMASK base address (needed even without CMASK). */
1601 rtex
->cmask
.base_address_reg
=
1602 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1604 p_atomic_inc(&rscreen
->dirty_tex_counter
);
1606 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1609 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1610 struct pipe_resource
*texture
,
1613 const struct pipe_box
*box
,
1614 struct pipe_transfer
**ptransfer
)
1616 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1617 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1618 struct r600_transfer
*trans
;
1619 struct r600_resource
*buf
;
1620 unsigned offset
= 0;
1622 bool use_staging_texture
= false;
1624 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1625 assert(box
->width
&& box
->height
&& box
->depth
);
1627 /* Depth textures use staging unconditionally. */
1628 if (!rtex
->is_depth
) {
1629 /* Degrade the tile mode if we get too many transfers on APUs.
1630 * On dGPUs, the staging texture is always faster.
1631 * Only count uploads that are at least 4x4 pixels large.
1633 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1635 box
->width
>= 4 && box
->height
>= 4 &&
1636 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1637 bool can_invalidate
=
1638 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1641 r600_reallocate_texture_inplace(rctx
, rtex
,
1646 /* Tiled textures need to be converted into a linear texture for CPU
1647 * access. The staging texture is always linear and is placed in GART.
1649 * Reading from VRAM or GTT WC is slow, always use the staging
1650 * texture in this case.
1652 * Use the staging texture for uploads if the underlying BO
1655 if (!rtex
->surface
.is_linear
)
1656 use_staging_texture
= true;
1657 else if (usage
& PIPE_TRANSFER_READ
)
1658 use_staging_texture
=
1659 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1660 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1661 /* Write & linear only: */
1662 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1663 RADEON_USAGE_READWRITE
) ||
1664 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1665 RADEON_USAGE_READWRITE
)) {
1667 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1669 r600_texture_invalidate_storage(rctx
, rtex
);
1671 use_staging_texture
= true;
1675 trans
= CALLOC_STRUCT(r600_transfer
);
1678 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1679 trans
->b
.b
.level
= level
;
1680 trans
->b
.b
.usage
= usage
;
1681 trans
->b
.b
.box
= *box
;
1683 if (rtex
->is_depth
) {
1684 struct r600_texture
*staging_depth
;
1686 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1687 /* MSAA depth buffers need to be converted to single sample buffers.
1689 * Mapping MSAA depth buffers can occur if ReadPixels is called
1690 * with a multisample GLX visual.
1692 * First downsample the depth buffer to a temporary texture,
1693 * then decompress the temporary one to staging.
1695 * Only the region being mapped is transfered.
1697 struct pipe_resource resource
;
1699 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1701 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1702 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1707 if (usage
& PIPE_TRANSFER_READ
) {
1708 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1710 R600_ERR("failed to create a temporary depth texture\n");
1715 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1716 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1717 0, 0, 0, box
->depth
, 0, 0);
1718 pipe_resource_reference(&temp
, NULL
);
1721 /* Just get the strides. */
1722 r600_texture_get_offset(rctx
->screen
, staging_depth
, level
, NULL
,
1724 &trans
->b
.b
.layer_stride
);
1726 /* XXX: only readback the rectangle which is being mapped? */
1727 /* XXX: when discard is true, no need to read back from depth texture */
1728 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1729 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1734 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1736 box
->z
, box
->z
+ box
->depth
- 1,
1739 offset
= r600_texture_get_offset(rctx
->screen
, staging_depth
,
1742 &trans
->b
.b
.layer_stride
);
1745 trans
->staging
= (struct r600_resource
*)staging_depth
;
1746 buf
= trans
->staging
;
1747 } else if (use_staging_texture
) {
1748 struct pipe_resource resource
;
1749 struct r600_texture
*staging
;
1751 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1752 R600_RESOURCE_FLAG_TRANSFER
);
1753 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1754 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1756 /* Create the temporary texture. */
1757 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1759 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1763 trans
->staging
= &staging
->resource
;
1765 /* Just get the strides. */
1766 r600_texture_get_offset(rctx
->screen
, staging
, 0, NULL
,
1768 &trans
->b
.b
.layer_stride
);
1770 if (usage
& PIPE_TRANSFER_READ
)
1771 r600_copy_to_staging_texture(ctx
, trans
);
1773 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1775 buf
= trans
->staging
;
1777 /* the resource is mapped directly */
1778 offset
= r600_texture_get_offset(rctx
->screen
, rtex
, level
, box
,
1780 &trans
->b
.b
.layer_stride
);
1781 buf
= &rtex
->resource
;
1784 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1785 r600_resource_reference(&trans
->staging
, NULL
);
1790 *ptransfer
= &trans
->b
.b
;
1791 return map
+ offset
;
1794 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1795 struct pipe_transfer
* transfer
)
1797 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1798 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1799 struct pipe_resource
*texture
= transfer
->resource
;
1800 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1802 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1803 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1804 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1805 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1806 &rtransfer
->staging
->b
.b
, transfer
->level
,
1809 r600_copy_from_staging_texture(ctx
, rtransfer
);
1813 if (rtransfer
->staging
) {
1814 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1815 r600_resource_reference(&rtransfer
->staging
, NULL
);
1818 /* Heuristic for {upload, draw, upload, draw, ..}:
1820 * Flush the gfx IB if we've allocated too much texture storage.
1822 * The idea is that we don't want to build IBs that use too much
1823 * memory and put pressure on the kernel memory manager and we also
1824 * want to make temporary and invalidated buffers go idle ASAP to
1825 * decrease the total memory usage or make them reusable. The memory
1826 * usage will be slightly higher than given here because of the buffer
1827 * cache in the winsys.
1829 * The result is that the kernel memory manager is never a bottleneck.
1831 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1832 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1833 rctx
->num_alloc_tex_transfer_bytes
= 0;
1836 pipe_resource_reference(&transfer
->resource
, NULL
);
1840 static const struct u_resource_vtbl r600_texture_vtbl
=
1842 NULL
, /* get_handle */
1843 r600_texture_destroy
, /* resource_destroy */
1844 r600_texture_transfer_map
, /* transfer_map */
1845 u_default_transfer_flush_region
, /* transfer_flush_region */
1846 r600_texture_transfer_unmap
, /* transfer_unmap */
1849 /* DCC channel type categories within which formats can be reinterpreted
1850 * while keeping the same DCC encoding. The swizzle must also match. */
1851 enum dcc_channel_type
{
1852 dcc_channel_float32
,
1855 dcc_channel_float16
,
1858 dcc_channel_uint_10_10_10_2
,
1861 dcc_channel_incompatible
,
1864 /* Return the type of DCC encoding. */
1865 static enum dcc_channel_type
1866 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1870 /* Find the first non-void channel. */
1871 for (i
= 0; i
< desc
->nr_channels
; i
++)
1872 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1874 if (i
== desc
->nr_channels
)
1875 return dcc_channel_incompatible
;
1877 switch (desc
->channel
[i
].size
) {
1879 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1880 return dcc_channel_float32
;
1881 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1882 return dcc_channel_uint32
;
1883 return dcc_channel_sint32
;
1885 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1886 return dcc_channel_float16
;
1887 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1888 return dcc_channel_uint16
;
1889 return dcc_channel_sint16
;
1891 return dcc_channel_uint_10_10_10_2
;
1893 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1894 return dcc_channel_uint8
;
1895 return dcc_channel_sint8
;
1897 return dcc_channel_incompatible
;
1901 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1902 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1903 enum pipe_format format2
)
1905 const struct util_format_description
*desc1
, *desc2
;
1906 enum dcc_channel_type type1
, type2
;
1909 if (format1
== format2
)
1912 desc1
= util_format_description(format1
);
1913 desc2
= util_format_description(format2
);
1915 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1918 /* Swizzles must be the same. */
1919 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1920 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1921 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1922 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1925 type1
= vi_get_dcc_channel_type(desc1
);
1926 type2
= vi_get_dcc_channel_type(desc2
);
1928 return type1
!= dcc_channel_incompatible
&&
1929 type2
!= dcc_channel_incompatible
&&
1933 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1935 enum pipe_format view_format
)
1937 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1939 return vi_dcc_enabled(rtex
, level
) &&
1940 !vi_dcc_formats_compatible(tex
->format
, view_format
);
1943 /* This can't be merged with the above function, because
1944 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1945 void vi_disable_dcc_if_incompatible_format(struct r600_common_context
*rctx
,
1946 struct pipe_resource
*tex
,
1948 enum pipe_format view_format
)
1950 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1952 if (vi_dcc_enabled(rtex
, level
) &&
1953 !vi_dcc_formats_compatible(tex
->format
, view_format
))
1954 if (!r600_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1955 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1958 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1959 struct pipe_resource
*texture
,
1960 const struct pipe_surface
*templ
,
1961 unsigned width0
, unsigned height0
,
1962 unsigned width
, unsigned height
)
1964 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1969 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1970 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1972 pipe_reference_init(&surface
->base
.reference
, 1);
1973 pipe_resource_reference(&surface
->base
.texture
, texture
);
1974 surface
->base
.context
= pipe
;
1975 surface
->base
.format
= templ
->format
;
1976 surface
->base
.width
= width
;
1977 surface
->base
.height
= height
;
1978 surface
->base
.u
= templ
->u
;
1980 surface
->width0
= width0
;
1981 surface
->height0
= height0
;
1983 surface
->dcc_incompatible
=
1984 texture
->target
!= PIPE_BUFFER
&&
1985 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
1987 return &surface
->base
;
1990 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1991 struct pipe_resource
*tex
,
1992 const struct pipe_surface
*templ
)
1994 unsigned level
= templ
->u
.tex
.level
;
1995 unsigned width
= u_minify(tex
->width0
, level
);
1996 unsigned height
= u_minify(tex
->height0
, level
);
1997 unsigned width0
= tex
->width0
;
1998 unsigned height0
= tex
->height0
;
2000 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2001 const struct util_format_description
*tex_desc
2002 = util_format_description(tex
->format
);
2003 const struct util_format_description
*templ_desc
2004 = util_format_description(templ
->format
);
2006 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2008 /* Adjust size of surface if and only if the block width or
2009 * height is changed. */
2010 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2011 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2012 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2013 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2015 width
= nblks_x
* templ_desc
->block
.width
;
2016 height
= nblks_y
* templ_desc
->block
.height
;
2018 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2019 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2023 return r600_create_surface_custom(pipe
, tex
, templ
,
2028 static void r600_surface_destroy(struct pipe_context
*pipe
,
2029 struct pipe_surface
*surface
)
2031 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
2032 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
2033 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
2034 pipe_resource_reference(&surface
->texture
, NULL
);
2038 static void r600_clear_texture(struct pipe_context
*pipe
,
2039 struct pipe_resource
*tex
,
2041 const struct pipe_box
*box
,
2044 struct pipe_screen
*screen
= pipe
->screen
;
2045 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
2046 struct pipe_surface tmpl
= {{0}};
2047 struct pipe_surface
*sf
;
2048 const struct util_format_description
*desc
=
2049 util_format_description(tex
->format
);
2051 tmpl
.format
= tex
->format
;
2052 tmpl
.u
.tex
.first_layer
= box
->z
;
2053 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
2054 tmpl
.u
.tex
.level
= level
;
2055 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
2059 if (rtex
->is_depth
) {
2062 uint8_t stencil
= 0;
2064 /* Depth is always present. */
2065 clear
= PIPE_CLEAR_DEPTH
;
2066 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
2068 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
2069 clear
|= PIPE_CLEAR_STENCIL
;
2070 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
2073 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
2075 box
->width
, box
->height
, false);
2077 union pipe_color_union color
;
2079 /* pipe_color_union requires the full vec4 representation. */
2080 if (util_format_is_pure_uint(tex
->format
))
2081 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
2082 else if (util_format_is_pure_sint(tex
->format
))
2083 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
2085 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
2087 if (screen
->is_format_supported(screen
, tex
->format
,
2089 PIPE_BIND_RENDER_TARGET
)) {
2090 pipe
->clear_render_target(pipe
, sf
, &color
,
2092 box
->width
, box
->height
, false);
2094 /* Software fallback - just for R9G9B9E5_FLOAT */
2095 util_clear_render_target(pipe
, sf
, &color
,
2097 box
->width
, box
->height
);
2100 pipe_surface_reference(&sf
, NULL
);
2103 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2105 const struct util_format_description
*desc
= util_format_description(format
);
2107 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2109 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2110 return V_0280A0_SWAP_STD
;
2112 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2115 switch (desc
->nr_channels
) {
2117 if (HAS_SWIZZLE(0,X
))
2118 return V_0280A0_SWAP_STD
; /* X___ */
2119 else if (HAS_SWIZZLE(3,X
))
2120 return V_0280A0_SWAP_ALT_REV
; /* ___X */
2123 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2124 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2125 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2126 return V_0280A0_SWAP_STD
; /* XY__ */
2127 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2128 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2129 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2131 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
2132 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2133 return V_0280A0_SWAP_ALT
; /* X__Y */
2134 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2135 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
2138 if (HAS_SWIZZLE(0,X
))
2139 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
2140 else if (HAS_SWIZZLE(0,Z
))
2141 return V_0280A0_SWAP_STD_REV
; /* ZYX */
2144 /* check the middle channels, the 1st and 4th channel can be NONE */
2145 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2146 return V_0280A0_SWAP_STD
; /* XYZW */
2147 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2148 return V_0280A0_SWAP_STD_REV
; /* WZYX */
2149 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2150 return V_0280A0_SWAP_ALT
; /* ZYXW */
2151 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2154 return V_0280A0_SWAP_ALT_REV
;
2156 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
2163 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2165 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
2170 if (rctx
->dcc_stats
[slot
].query_active
)
2171 vi_separate_dcc_stop_query(&rctx
->b
,
2172 rctx
->dcc_stats
[slot
].tex
);
2174 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
2175 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2176 rctx
->b
.destroy_query(&rctx
->b
,
2177 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
2178 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2181 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2185 * Return the per-context slot where DCC statistics queries for the texture live.
2187 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2188 struct r600_texture
*tex
)
2190 int i
, empty_slot
= -1;
2192 /* Remove zombie textures (textures kept alive by this array only). */
2193 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2194 if (rctx
->dcc_stats
[i
].tex
&&
2195 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2196 vi_dcc_clean_up_context_slot(rctx
, i
);
2198 /* Find the texture. */
2199 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2200 /* Return if found. */
2201 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2202 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2206 /* Record the first seen empty slot. */
2207 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2211 /* Not found. Remove the oldest member to make space in the array. */
2212 if (empty_slot
== -1) {
2213 int oldest_slot
= 0;
2215 /* Find the oldest slot. */
2216 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2217 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2218 rctx
->dcc_stats
[i
].last_use_timestamp
)
2221 /* Clean up the oldest slot. */
2222 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2223 empty_slot
= oldest_slot
;
2226 /* Add the texture to the new slot. */
2227 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2228 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2232 static struct pipe_query
*
2233 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2235 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2236 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2238 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2239 return (struct pipe_query
*)query
;
2243 * Called when binding a color buffer.
2245 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2246 struct r600_texture
*tex
)
2248 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2249 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2251 assert(!rctx
->dcc_stats
[i
].query_active
);
2253 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2254 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2256 /* begin or resume the query */
2257 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2258 rctx
->dcc_stats
[i
].query_active
= true;
2262 * Called when unbinding a color buffer.
2264 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2265 struct r600_texture
*tex
)
2267 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2268 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2270 assert(rctx
->dcc_stats
[i
].query_active
);
2271 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2273 /* pause or end the query */
2274 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2275 rctx
->dcc_stats
[i
].query_active
= false;
2278 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2280 /* The minimum number of fullscreen draws per frame that is required
2282 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2285 /* Called by fast clear. */
2286 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2287 struct r600_texture
*tex
)
2289 /* The intent is to use this with shared displayable back buffers,
2290 * but it's not strictly limited only to them.
2292 if (!tex
->resource
.b
.is_shared
||
2293 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2294 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2295 tex
->resource
.b
.b
.last_level
> 0 ||
2296 !tex
->surface
.dcc_size
)
2299 if (tex
->dcc_offset
)
2300 return; /* already enabled */
2302 /* Enable the DCC stat gathering. */
2303 if (!tex
->dcc_gather_statistics
) {
2304 tex
->dcc_gather_statistics
= true;
2305 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2308 if (!vi_should_enable_separate_dcc(tex
))
2309 return; /* stats show that DCC decompression is too expensive */
2311 assert(tex
->surface
.num_dcc_levels
);
2312 assert(!tex
->dcc_separate_buffer
);
2314 r600_texture_discard_cmask(rctx
->screen
, tex
);
2316 /* Get a DCC buffer. */
2317 if (tex
->last_dcc_separate_buffer
) {
2318 assert(tex
->dcc_gather_statistics
);
2319 assert(!tex
->dcc_separate_buffer
);
2320 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2321 tex
->last_dcc_separate_buffer
= NULL
;
2323 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2324 r600_aligned_buffer_create(rctx
->b
.screen
,
2325 R600_RESOURCE_FLAG_UNMAPPABLE
,
2327 tex
->surface
.dcc_size
,
2328 tex
->surface
.dcc_alignment
);
2329 if (!tex
->dcc_separate_buffer
)
2333 /* dcc_offset is the absolute GPUVM address. */
2334 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2336 /* no need to flag anything since this is called by fast clear that
2337 * flags framebuffer state
2342 * Called by pipe_context::flush_resource, the place where DCC decompression
2345 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2346 struct r600_texture
*tex
)
2348 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2349 struct pipe_query
*tmp
;
2350 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2351 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2352 bool disable
= false;
2354 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2355 union pipe_query_result result
;
2357 /* Read the results. */
2358 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2360 r600_query_hw_reset_buffers(rctx
,
2361 (struct r600_query_hw
*)
2362 rctx
->dcc_stats
[i
].ps_stats
[2]);
2364 /* Compute the approximate number of fullscreen draws. */
2365 tex
->ps_draw_ratio
=
2366 result
.pipeline_statistics
.ps_invocations
/
2367 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2368 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2370 disable
= tex
->dcc_separate_buffer
&&
2371 !vi_should_enable_separate_dcc(tex
);
2374 tex
->num_slow_clears
= 0;
2376 /* stop the statistics query for ps_stats[0] */
2378 vi_separate_dcc_stop_query(ctx
, tex
);
2380 /* Move the queries in the queue by one. */
2381 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2382 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2383 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2384 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2386 /* create and start a new query as ps_stats[0] */
2388 vi_separate_dcc_start_query(ctx
, tex
);
2391 assert(!tex
->last_dcc_separate_buffer
);
2392 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2393 tex
->dcc_separate_buffer
= NULL
;
2394 tex
->dcc_offset
= 0;
2395 /* no need to flag anything since this is called after
2396 * decompression that re-sets framebuffer state
2401 /* FAST COLOR CLEAR */
2403 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2404 enum pipe_format surface_format
,
2405 const union pipe_color_union
*color
)
2407 union util_color uc
;
2409 memset(&uc
, 0, sizeof(uc
));
2411 if (rtex
->surface
.bpe
== 16) {
2412 /* DCC fast clear only:
2413 * CLEAR_WORD0 = R = G = B
2416 assert(color
->ui
[0] == color
->ui
[1] &&
2417 color
->ui
[0] == color
->ui
[2]);
2418 uc
.ui
[0] = color
->ui
[0];
2419 uc
.ui
[1] = color
->ui
[3];
2420 } else if (util_format_is_pure_uint(surface_format
)) {
2421 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2422 } else if (util_format_is_pure_sint(surface_format
)) {
2423 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2425 util_pack_color(color
->f
, surface_format
, &uc
);
2428 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2431 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2432 const union pipe_color_union
*color
,
2433 uint32_t* reset_value
,
2434 bool* clear_words_needed
)
2436 bool values
[4] = {};
2438 bool main_value
= false;
2439 bool extra_value
= false;
2442 /* This is needed to get the correct DCC clear value for luminance formats.
2443 * 1) Get the linear format (because the next step can't handle L8_SRGB).
2444 * 2) Convert luminance to red. (the real hw format for luminance)
2446 surface_format
= util_format_linear(surface_format
);
2447 surface_format
= util_format_luminance_to_red(surface_format
);
2449 const struct util_format_description
*desc
= util_format_description(surface_format
);
2451 if (desc
->block
.bits
== 128 &&
2452 (color
->ui
[0] != color
->ui
[1] ||
2453 color
->ui
[0] != color
->ui
[2]))
2456 *clear_words_needed
= true;
2457 *reset_value
= 0x20202020U
;
2459 /* If we want to clear without needing a fast clear eliminate step, we
2460 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2461 * have two sets of flags, one for the last or first channel(extra) and
2462 * one for the other channels(main).
2465 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2466 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2467 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
||
2468 util_format_is_alpha(surface_format
)) {
2470 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2471 if(r600_translate_colorswap(surface_format
, false) <= 1)
2472 extra_channel
= desc
->nr_channels
- 1;
2478 for (i
= 0; i
< 4; ++i
) {
2479 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2481 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2482 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2485 if (desc
->channel
[i
].pure_integer
&&
2486 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2487 /* Use the maximum value for clamping the clear color. */
2488 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2490 values
[i
] = color
->i
[i
] != 0;
2491 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2493 } else if (desc
->channel
[i
].pure_integer
&&
2494 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2495 /* Use the maximum value for clamping the clear color. */
2496 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2498 values
[i
] = color
->ui
[i
] != 0U;
2499 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2502 values
[i
] = color
->f
[i
] != 0.0F
;
2503 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2507 if (index
== extra_channel
)
2508 extra_value
= values
[i
];
2510 main_value
= values
[i
];
2513 for (int i
= 0; i
< 4; ++i
)
2514 if (values
[i
] != main_value
&&
2515 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2516 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2517 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2520 *clear_words_needed
= false;
2522 *reset_value
|= 0x80808080U
;
2525 *reset_value
|= 0x40404040U
;
2529 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2530 struct r600_texture
*rtex
,
2531 unsigned level
, unsigned clear_value
)
2533 struct pipe_resource
*dcc_buffer
;
2534 uint64_t dcc_offset
, clear_size
;
2536 assert(vi_dcc_enabled(rtex
, level
));
2538 if (rtex
->dcc_separate_buffer
) {
2539 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2542 dcc_buffer
= &rtex
->resource
.b
.b
;
2543 dcc_offset
= rtex
->dcc_offset
;
2546 if (rctx
->chip_class
>= GFX9
) {
2547 /* Mipmap level clears aren't implemented. */
2548 assert(rtex
->resource
.b
.b
.last_level
== 0);
2549 /* MSAA needs a different clear size. */
2550 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
2551 clear_size
= rtex
->surface
.dcc_size
;
2553 dcc_offset
+= rtex
->surface
.u
.legacy
.level
[level
].dcc_offset
;
2554 clear_size
= rtex
->surface
.u
.legacy
.level
[level
].dcc_fast_clear_size
;
2557 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
, clear_size
,
2558 clear_value
, R600_COHERENCY_CB_META
);
2561 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2562 * This allows hitting the MSAA resolve fast path, which requires that both
2563 * src and dst micro tile modes match.
2565 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2566 struct r600_texture
*rtex
)
2568 if (rtex
->resource
.b
.is_shared
||
2569 rtex
->resource
.b
.b
.nr_samples
<= 1 ||
2570 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2573 assert(rscreen
->chip_class
>= GFX9
||
2574 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2575 assert(rtex
->resource
.b
.b
.last_level
== 0);
2577 if (rscreen
->chip_class
>= GFX9
) {
2578 /* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
2579 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
>= 4);
2581 /* If you do swizzle_mode % 4, you'll get:
2587 * Depth-sample order isn't allowed:
2589 assert(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
% 4 != 0);
2591 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2592 case RADEON_MICRO_MODE_DISPLAY
:
2593 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2594 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 2; /* D */
2596 case RADEON_MICRO_MODE_THIN
:
2597 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2598 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 1; /* S */
2600 case RADEON_MICRO_MODE_ROTATED
:
2601 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
&= ~0x3;
2602 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
+= 3; /* R */
2604 default: /* depth */
2605 assert(!"unexpected micro mode");
2608 } else if (rscreen
->chip_class
>= CIK
) {
2609 /* These magic numbers were copied from addrlib. It doesn't use
2610 * any definitions for them either. They are all 2D_TILED_THIN1
2611 * modes with different bpp and micro tile mode.
2613 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2614 case RADEON_MICRO_MODE_DISPLAY
:
2615 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2617 case RADEON_MICRO_MODE_THIN
:
2618 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2620 case RADEON_MICRO_MODE_ROTATED
:
2621 rtex
->surface
.u
.legacy
.tiling_index
[0] = 28;
2623 default: /* depth, thick */
2624 assert(!"unexpected micro mode");
2628 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2629 case RADEON_MICRO_MODE_DISPLAY
:
2630 switch (rtex
->surface
.bpe
) {
2632 rtex
->surface
.u
.legacy
.tiling_index
[0] = 10;
2635 rtex
->surface
.u
.legacy
.tiling_index
[0] = 11;
2638 rtex
->surface
.u
.legacy
.tiling_index
[0] = 12;
2642 case RADEON_MICRO_MODE_THIN
:
2643 switch (rtex
->surface
.bpe
) {
2645 rtex
->surface
.u
.legacy
.tiling_index
[0] = 14;
2648 rtex
->surface
.u
.legacy
.tiling_index
[0] = 15;
2651 rtex
->surface
.u
.legacy
.tiling_index
[0] = 16;
2653 default: /* 8, 16 */
2654 rtex
->surface
.u
.legacy
.tiling_index
[0] = 17;
2658 default: /* depth, thick */
2659 assert(!"unexpected micro mode");
2664 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2666 p_atomic_inc(&rscreen
->dirty_tex_counter
);
2669 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2670 struct pipe_framebuffer_state
*fb
,
2671 struct r600_atom
*fb_state
,
2672 unsigned *buffers
, ubyte
*dirty_cbufs
,
2673 const union pipe_color_union
*color
)
2677 /* This function is broken in BE, so just disable this path for now */
2678 #ifdef PIPE_ARCH_BIG_ENDIAN
2682 if (rctx
->render_cond
)
2685 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2686 struct r600_texture
*tex
;
2687 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2692 /* if this colorbuffer is not being cleared */
2693 if (!(*buffers
& clear_bit
))
2696 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2698 /* the clear is allowed if all layers are bound */
2699 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2700 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2704 /* cannot clear mipmapped textures */
2705 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2709 /* only supported on tiled surfaces */
2710 if (tex
->surface
.is_linear
) {
2714 /* shared textures can't use fast clear without an explicit flush,
2715 * because there is no way to communicate the clear color among
2718 if (tex
->resource
.b
.is_shared
&&
2719 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2722 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2723 if (rctx
->chip_class
== CIK
&&
2724 tex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2725 rctx
->screen
->info
.drm_major
== 2 &&
2726 rctx
->screen
->info
.drm_minor
< 38) {
2730 /* Fast clear is the most appropriate place to enable DCC for
2731 * displayable surfaces.
2733 if (rctx
->chip_class
>= VI
&&
2734 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2735 vi_separate_dcc_try_enable(rctx
, tex
);
2737 /* RB+ isn't supported with a CMASK clear only on Stoney,
2738 * so all clears are considered to be hypothetically slow
2739 * clears, which is weighed when determining whether to
2740 * enable separate DCC.
2742 if (tex
->dcc_gather_statistics
&&
2743 rctx
->family
== CHIP_STONEY
)
2744 tex
->num_slow_clears
++;
2747 /* Try to clear DCC first, otherwise try CMASK. */
2748 if (vi_dcc_enabled(tex
, 0)) {
2749 uint32_t reset_value
;
2750 bool clear_words_needed
;
2752 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2755 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2756 color
, &reset_value
,
2757 &clear_words_needed
))
2760 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2762 unsigned level_bit
= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2763 if (clear_words_needed
) {
2764 bool need_compressed_update
= !tex
->dirty_level_mask
;
2766 tex
->dirty_level_mask
|= level_bit
;
2768 if (need_compressed_update
)
2769 p_atomic_inc(&rctx
->screen
->compressed_colortex_counter
);
2771 tex
->separate_dcc_dirty
= true;
2773 /* 128-bit formats are unusupported */
2774 if (tex
->surface
.bpe
> 8) {
2778 /* RB+ doesn't work with CMASK fast clear on Stoney. */
2779 if (rctx
->family
== CHIP_STONEY
)
2782 /* ensure CMASK is enabled */
2783 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2784 if (tex
->cmask
.size
== 0) {
2788 /* Do the fast clear. */
2789 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2790 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2791 R600_COHERENCY_CB_META
);
2793 bool need_compressed_update
= !tex
->dirty_level_mask
;
2795 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2797 if (need_compressed_update
)
2798 p_atomic_inc(&rctx
->screen
->compressed_colortex_counter
);
2801 /* We can change the micro tile mode before a full clear. */
2802 if (rctx
->screen
->chip_class
>= SI
)
2803 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2805 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2808 *dirty_cbufs
|= 1 << i
;
2809 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2810 *buffers
&= ~clear_bit
;
2814 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2816 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2817 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2820 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2822 rctx
->b
.create_surface
= r600_create_surface
;
2823 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2824 rctx
->b
.clear_texture
= r600_clear_texture
;