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freedreno: wire up core pipe_debug_callback
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include <errno.h>
33 #include <inttypes.h>
34
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context *pipe,
37 struct pipe_resource *dst,
38 unsigned dst_level,
39 unsigned dstx, unsigned dsty, unsigned dstz,
40 struct pipe_resource *src,
41 unsigned src_level,
42 const struct pipe_box *src_box)
43 {
44 struct pipe_blit_info blit;
45
46 memset(&blit, 0, sizeof(blit));
47 blit.src.resource = src;
48 blit.src.format = src->format;
49 blit.src.level = src_level;
50 blit.src.box = *src_box;
51 blit.dst.resource = dst;
52 blit.dst.format = dst->format;
53 blit.dst.level = dst_level;
54 blit.dst.box.x = dstx;
55 blit.dst.box.y = dsty;
56 blit.dst.box.z = dstz;
57 blit.dst.box.width = src_box->width;
58 blit.dst.box.height = src_box->height;
59 blit.dst.box.depth = src_box->depth;
60 blit.mask = util_format_get_mask(src->format) &
61 util_format_get_mask(dst->format);
62 blit.filter = PIPE_TEX_FILTER_NEAREST;
63
64 if (blit.mask) {
65 pipe->blit(pipe, &blit);
66 }
67 }
68
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
71 {
72 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
73 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
74 struct pipe_resource *dst = &rtransfer->staging->b.b;
75 struct pipe_resource *src = transfer->resource;
76
77 if (src->nr_samples > 1) {
78 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
79 src, transfer->level, &transfer->box);
80 return;
81 }
82
83 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
84 &transfer->box);
85 }
86
87 /* Copy from a transfer's staging texture to a full GPU one. */
88 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
89 {
90 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
91 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
92 struct pipe_resource *dst = transfer->resource;
93 struct pipe_resource *src = &rtransfer->staging->b.b;
94 struct pipe_box sbox;
95
96 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
97
98 if (dst->nr_samples > 1) {
99 r600_copy_region_with_blit(ctx, dst, transfer->level,
100 transfer->box.x, transfer->box.y, transfer->box.z,
101 src, 0, &sbox);
102 return;
103 }
104
105 rctx->dma_copy(ctx, dst, transfer->level,
106 transfer->box.x, transfer->box.y, transfer->box.z,
107 src, 0, &sbox);
108 }
109
110 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
111 const struct pipe_box *box)
112 {
113 enum pipe_format format = rtex->resource.b.b.format;
114
115 return rtex->surface.level[level].offset +
116 box->z * rtex->surface.level[level].slice_size +
117 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
118 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
119 }
120
121 static int r600_init_surface(struct r600_common_screen *rscreen,
122 struct radeon_surf *surface,
123 const struct pipe_resource *ptex,
124 unsigned array_mode,
125 bool is_flushed_depth)
126 {
127 const struct util_format_description *desc =
128 util_format_description(ptex->format);
129 bool is_depth, is_stencil;
130
131 is_depth = util_format_has_depth(desc);
132 is_stencil = util_format_has_stencil(desc);
133
134 surface->npix_x = ptex->width0;
135 surface->npix_y = ptex->height0;
136 surface->npix_z = ptex->depth0;
137 surface->blk_w = util_format_get_blockwidth(ptex->format);
138 surface->blk_h = util_format_get_blockheight(ptex->format);
139 surface->blk_d = 1;
140 surface->array_size = 1;
141 surface->last_level = ptex->last_level;
142
143 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
144 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
145 surface->bpe = 4; /* stencil is allocated separately on evergreen */
146 } else {
147 surface->bpe = util_format_get_blocksize(ptex->format);
148 /* align byte per element on dword */
149 if (surface->bpe == 3) {
150 surface->bpe = 4;
151 }
152 }
153
154 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
155 surface->flags = RADEON_SURF_SET(array_mode, MODE);
156
157 switch (ptex->target) {
158 case PIPE_TEXTURE_1D:
159 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
160 break;
161 case PIPE_TEXTURE_RECT:
162 case PIPE_TEXTURE_2D:
163 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
164 break;
165 case PIPE_TEXTURE_3D:
166 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
167 break;
168 case PIPE_TEXTURE_1D_ARRAY:
169 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
170 surface->array_size = ptex->array_size;
171 break;
172 case PIPE_TEXTURE_2D_ARRAY:
173 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
175 surface->array_size = ptex->array_size;
176 break;
177 case PIPE_TEXTURE_CUBE:
178 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
179 break;
180 case PIPE_BUFFER:
181 default:
182 return -EINVAL;
183 }
184 if (ptex->bind & PIPE_BIND_SCANOUT) {
185 surface->flags |= RADEON_SURF_SCANOUT;
186 }
187
188 if (!is_flushed_depth && is_depth) {
189 surface->flags |= RADEON_SURF_ZBUFFER;
190
191 if (is_stencil) {
192 surface->flags |= RADEON_SURF_SBUFFER |
193 RADEON_SURF_HAS_SBUFFER_MIPTREE;
194 }
195 }
196 if (rscreen->chip_class >= SI) {
197 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
198 }
199 return 0;
200 }
201
202 static int r600_setup_surface(struct pipe_screen *screen,
203 struct r600_texture *rtex,
204 unsigned pitch_in_bytes_override,
205 unsigned offset)
206 {
207 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
208 unsigned i;
209 int r;
210
211 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
212 if (r) {
213 return r;
214 }
215
216 rtex->size = rtex->surface.bo_size;
217
218 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
219 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
220 * for those
221 */
222 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
223 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
224 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
225 }
226
227 if (offset) {
228 for (i = 0; i < Elements(rtex->surface.level); ++i)
229 rtex->surface.level[i].offset += offset;
230 }
231 return 0;
232 }
233
234 static void r600_texture_init_metadata(struct r600_texture *rtex,
235 struct radeon_bo_metadata *metadata)
236 {
237 struct radeon_surf *surface = &rtex->surface;
238
239 memset(metadata, 0, sizeof(*metadata));
240 metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
241 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
242 metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
243 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
244 metadata->pipe_config = surface->pipe_config;
245 metadata->bankw = surface->bankw;
246 metadata->bankh = surface->bankh;
247 metadata->tile_split = surface->tile_split;
248 metadata->stencil_tile_split = surface->stencil_tile_split;
249 metadata->mtilea = surface->mtilea;
250 metadata->num_banks = surface->num_banks;
251 metadata->stride = surface->level[0].pitch_bytes;
252 metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
253 }
254
255 static void r600_dirty_all_framebuffer_states(struct r600_common_screen *rscreen)
256 {
257 p_atomic_inc(&rscreen->dirty_fb_counter);
258 }
259
260 static void r600_eliminate_fast_color_clear(struct r600_common_screen *rscreen,
261 struct r600_texture *rtex)
262 {
263 struct pipe_context *ctx = rscreen->aux_context;
264
265 pipe_mutex_lock(rscreen->aux_context_lock);
266 ctx->flush_resource(ctx, &rtex->resource.b.b);
267 ctx->flush(ctx, NULL, 0);
268 pipe_mutex_unlock(rscreen->aux_context_lock);
269 }
270
271 static void r600_texture_disable_cmask(struct r600_common_screen *rscreen,
272 struct r600_texture *rtex)
273 {
274 if (!rtex->cmask.size)
275 return;
276
277 assert(rtex->resource.b.b.nr_samples <= 1);
278
279 /* Disable CMASK. */
280 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
281 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
282
283 if (rscreen->chip_class >= SI)
284 rtex->cb_color_info &= ~SI_S_028C70_FAST_CLEAR(1);
285 else
286 rtex->cb_color_info &= ~EG_S_028C70_FAST_CLEAR(1);
287
288 if (rtex->cmask_buffer != &rtex->resource)
289 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
290
291 /* Notify all contexts about the change. */
292 r600_dirty_all_framebuffer_states(rscreen);
293 p_atomic_inc(&rscreen->compressed_colortex_counter);
294 }
295
296 void r600_texture_disable_dcc(struct r600_common_screen *rscreen,
297 struct r600_texture *rtex)
298 {
299 struct r600_common_context *rctx =
300 (struct r600_common_context *)rscreen->aux_context;
301
302 if (!rtex->dcc_offset)
303 return;
304
305 /* Decompress DCC. */
306 pipe_mutex_lock(rscreen->aux_context_lock);
307 rctx->decompress_dcc(&rctx->b, rtex);
308 rctx->b.flush(&rctx->b, NULL, 0);
309 pipe_mutex_unlock(rscreen->aux_context_lock);
310
311 /* Disable DCC. */
312 rtex->dcc_offset = 0;
313 rtex->cb_color_info &= ~VI_S_028C70_DCC_ENABLE(1);
314
315 /* Notify all contexts about the change. */
316 r600_dirty_all_framebuffer_states(rscreen);
317 }
318
319 static boolean r600_texture_get_handle(struct pipe_screen* screen,
320 struct pipe_resource *resource,
321 struct winsys_handle *whandle,
322 unsigned usage)
323 {
324 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
325 struct r600_resource *res = (struct r600_resource*)resource;
326 struct r600_texture *rtex = (struct r600_texture*)resource;
327 struct radeon_bo_metadata metadata;
328 bool update_metadata = false;
329
330 /* This is not supported now, but it might be required for OpenCL
331 * interop in the future.
332 */
333 if (resource->target != PIPE_BUFFER &&
334 (resource->nr_samples > 1 || rtex->is_depth))
335 return false;
336
337 if (resource->target != PIPE_BUFFER) {
338 /* Since shader image stores don't support DCC on VI,
339 * disable it for external clients that want write
340 * access.
341 */
342 if (usage & PIPE_HANDLE_USAGE_WRITE && rtex->dcc_offset) {
343 r600_texture_disable_dcc(rscreen, rtex);
344 update_metadata = true;
345 }
346
347 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
348 rtex->cmask.size) {
349 /* Eliminate fast clear (both CMASK and DCC) */
350 r600_eliminate_fast_color_clear(rscreen, rtex);
351
352 /* Disable CMASK if flush_resource isn't going
353 * to be called.
354 */
355 r600_texture_disable_cmask(rscreen, rtex);
356 update_metadata = true;
357 }
358
359 /* Set metadata. */
360 if (!res->is_shared || update_metadata) {
361 r600_texture_init_metadata(rtex, &metadata);
362 if (rscreen->query_opaque_metadata)
363 rscreen->query_opaque_metadata(rscreen, rtex,
364 &metadata);
365
366 rscreen->ws->buffer_set_metadata(res->buf, &metadata);
367 }
368 }
369
370 if (res->is_shared) {
371 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
372 * doesn't set it.
373 */
374 res->external_usage |= usage & ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
375 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
376 res->external_usage &= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
377 } else {
378 res->is_shared = true;
379 res->external_usage = usage;
380 }
381
382 return rscreen->ws->buffer_get_handle(res->buf,
383 rtex->surface.level[0].pitch_bytes,
384 rtex->surface.level[0].offset,
385 rtex->surface.level[0].slice_size,
386 whandle);
387 }
388
389 static void r600_texture_destroy(struct pipe_screen *screen,
390 struct pipe_resource *ptex)
391 {
392 struct r600_texture *rtex = (struct r600_texture*)ptex;
393 struct r600_resource *resource = &rtex->resource;
394
395 if (rtex->flushed_depth_texture)
396 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
397
398 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
399 if (rtex->cmask_buffer != &rtex->resource) {
400 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
401 }
402 pb_reference(&resource->buf, NULL);
403 FREE(rtex);
404 }
405
406 static const struct u_resource_vtbl r600_texture_vtbl;
407
408 /* The number of samples can be specified independently of the texture. */
409 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
410 struct r600_texture *rtex,
411 unsigned nr_samples,
412 struct r600_fmask_info *out)
413 {
414 /* FMASK is allocated like an ordinary texture. */
415 struct radeon_surf fmask = rtex->surface;
416
417 memset(out, 0, sizeof(*out));
418
419 fmask.bo_alignment = 0;
420 fmask.bo_size = 0;
421 fmask.nsamples = 1;
422 fmask.flags |= RADEON_SURF_FMASK;
423
424 /* Force 2D tiling if it wasn't set. This may occur when creating
425 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
426 * destination buffer must have an FMASK too. */
427 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
428 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
429
430 if (rscreen->chip_class >= SI) {
431 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
432 }
433
434 switch (nr_samples) {
435 case 2:
436 case 4:
437 fmask.bpe = 1;
438 if (rscreen->chip_class <= CAYMAN) {
439 fmask.bankh = 4;
440 }
441 break;
442 case 8:
443 fmask.bpe = 4;
444 break;
445 default:
446 R600_ERR("Invalid sample count for FMASK allocation.\n");
447 return;
448 }
449
450 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
451 * This can be fixed by writing a separate FMASK allocator specifically
452 * for R600-R700 asics. */
453 if (rscreen->chip_class <= R700) {
454 fmask.bpe *= 2;
455 }
456
457 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
458 R600_ERR("Got error in surface_init while allocating FMASK.\n");
459 return;
460 }
461
462 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
463
464 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
465 if (out->slice_tile_max)
466 out->slice_tile_max -= 1;
467
468 out->tile_mode_index = fmask.tiling_index[0];
469 out->pitch_in_pixels = fmask.level[0].nblk_x;
470 out->bank_height = fmask.bankh;
471 out->alignment = MAX2(256, fmask.bo_alignment);
472 out->size = fmask.bo_size;
473 }
474
475 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
476 struct r600_texture *rtex)
477 {
478 r600_texture_get_fmask_info(rscreen, rtex,
479 rtex->resource.b.b.nr_samples, &rtex->fmask);
480
481 rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
482 rtex->size = rtex->fmask.offset + rtex->fmask.size;
483 }
484
485 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
486 struct r600_texture *rtex,
487 struct r600_cmask_info *out)
488 {
489 unsigned cmask_tile_width = 8;
490 unsigned cmask_tile_height = 8;
491 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
492 unsigned element_bits = 4;
493 unsigned cmask_cache_bits = 1024;
494 unsigned num_pipes = rscreen->info.num_tile_pipes;
495 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
496
497 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
498 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
499 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
500 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
501 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
502
503 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
504 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
505
506 unsigned base_align = num_pipes * pipe_interleave_bytes;
507 unsigned slice_bytes =
508 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
509
510 assert(macro_tile_width % 128 == 0);
511 assert(macro_tile_height % 128 == 0);
512
513 out->pitch = pitch_elements;
514 out->height = height;
515 out->xalign = macro_tile_width;
516 out->yalign = macro_tile_height;
517 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
518 out->alignment = MAX2(256, base_align);
519 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
520 align(slice_bytes, base_align);
521 }
522
523 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
524 struct r600_texture *rtex,
525 struct r600_cmask_info *out)
526 {
527 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
528 unsigned num_pipes = rscreen->info.num_tile_pipes;
529 unsigned cl_width, cl_height;
530
531 switch (num_pipes) {
532 case 2:
533 cl_width = 32;
534 cl_height = 16;
535 break;
536 case 4:
537 cl_width = 32;
538 cl_height = 32;
539 break;
540 case 8:
541 cl_width = 64;
542 cl_height = 32;
543 break;
544 case 16: /* Hawaii */
545 cl_width = 64;
546 cl_height = 64;
547 break;
548 default:
549 assert(0);
550 return;
551 }
552
553 unsigned base_align = num_pipes * pipe_interleave_bytes;
554
555 unsigned width = align(rtex->surface.npix_x, cl_width*8);
556 unsigned height = align(rtex->surface.npix_y, cl_height*8);
557 unsigned slice_elements = (width * height) / (8*8);
558
559 /* Each element of CMASK is a nibble. */
560 unsigned slice_bytes = slice_elements / 2;
561
562 out->pitch = width;
563 out->height = height;
564 out->xalign = cl_width * 8;
565 out->yalign = cl_height * 8;
566 out->slice_tile_max = (width * height) / (128*128);
567 if (out->slice_tile_max)
568 out->slice_tile_max -= 1;
569
570 out->alignment = MAX2(256, base_align);
571 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
572 align(slice_bytes, base_align);
573 }
574
575 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
576 struct r600_texture *rtex)
577 {
578 if (rscreen->chip_class >= SI) {
579 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
580 } else {
581 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
582 }
583
584 rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
585 rtex->size = rtex->cmask.offset + rtex->cmask.size;
586
587 if (rscreen->chip_class >= SI)
588 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
589 else
590 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
591 }
592
593 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
594 struct r600_texture *rtex)
595 {
596 if (rtex->cmask_buffer)
597 return;
598
599 assert(rtex->cmask.size == 0);
600
601 if (rscreen->chip_class >= SI) {
602 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
603 } else {
604 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
605 }
606
607 rtex->cmask_buffer = (struct r600_resource *)
608 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
609 PIPE_USAGE_DEFAULT, rtex->cmask.size);
610 if (rtex->cmask_buffer == NULL) {
611 rtex->cmask.size = 0;
612 return;
613 }
614
615 /* update colorbuffer state bits */
616 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
617
618 if (rscreen->chip_class >= SI)
619 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
620 else
621 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
622
623 p_atomic_inc(&rscreen->compressed_colortex_counter);
624 }
625
626 static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
627 struct r600_texture *rtex)
628 {
629 unsigned cl_width, cl_height, width, height;
630 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
631 unsigned num_pipes = rscreen->info.num_tile_pipes;
632
633 if (rscreen->chip_class <= EVERGREEN &&
634 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
635 return 0;
636
637 /* HW bug on R6xx. */
638 if (rscreen->chip_class == R600 &&
639 (rtex->surface.level[0].npix_x > 7680 ||
640 rtex->surface.level[0].npix_y > 7680))
641 return 0;
642
643 /* HTILE is broken with 1D tiling on old kernels and CIK. */
644 if (rscreen->chip_class >= CIK &&
645 rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
646 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
647 return 0;
648
649 /* Overalign HTILE on P2 configs to work around GPU hangs in
650 * piglit/depthstencil-render-miplevels 585.
651 *
652 * This has been confirmed to help Kabini & Stoney, where the hangs
653 * are always reproducible. I think I have seen the test hang
654 * on Carrizo too, though it was very rare there.
655 */
656 if (rscreen->chip_class >= CIK && num_pipes < 4)
657 num_pipes = 4;
658
659 switch (num_pipes) {
660 case 1:
661 cl_width = 32;
662 cl_height = 16;
663 break;
664 case 2:
665 cl_width = 32;
666 cl_height = 32;
667 break;
668 case 4:
669 cl_width = 64;
670 cl_height = 32;
671 break;
672 case 8:
673 cl_width = 64;
674 cl_height = 64;
675 break;
676 case 16:
677 cl_width = 128;
678 cl_height = 64;
679 break;
680 default:
681 assert(0);
682 return 0;
683 }
684
685 width = align(rtex->surface.npix_x, cl_width * 8);
686 height = align(rtex->surface.npix_y, cl_height * 8);
687
688 slice_elements = (width * height) / (8 * 8);
689 slice_bytes = slice_elements * 4;
690
691 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
692 base_align = num_pipes * pipe_interleave_bytes;
693
694 rtex->htile.pitch = width;
695 rtex->htile.height = height;
696 rtex->htile.xalign = cl_width * 8;
697 rtex->htile.yalign = cl_height * 8;
698
699 return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
700 align(slice_bytes, base_align);
701 }
702
703 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
704 struct r600_texture *rtex)
705 {
706 unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex);
707
708 if (!htile_size)
709 return;
710
711 rtex->htile_buffer = (struct r600_resource*)
712 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
713 PIPE_USAGE_DEFAULT, htile_size);
714 if (rtex->htile_buffer == NULL) {
715 /* this is not a fatal error as we can still keep rendering
716 * without htile buffer */
717 R600_ERR("Failed to create buffer object for htile buffer.\n");
718 } else {
719 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0,
720 htile_size, 0, R600_COHERENCY_NONE);
721 }
722 }
723
724 void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
725 {
726 int i;
727
728 fprintf(f, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
729 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
730 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
731 rtex->surface.npix_x, rtex->surface.npix_y,
732 rtex->surface.npix_z, rtex->surface.blk_w,
733 rtex->surface.blk_h, rtex->surface.blk_d,
734 rtex->surface.array_size, rtex->surface.last_level,
735 rtex->surface.bpe, rtex->surface.nsamples,
736 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
737
738 fprintf(f, " Layout: size=%"PRIu64", alignment=%"PRIu64", bankw=%u, "
739 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
740 rtex->surface.bo_size, rtex->surface.bo_alignment, rtex->surface.bankw,
741 rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
742 rtex->surface.tile_split, rtex->surface.pipe_config,
743 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
744
745 if (rtex->fmask.size)
746 fprintf(f, " FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, "
747 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
748 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
749 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
750 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
751
752 if (rtex->cmask.size)
753 fprintf(f, " CMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch=%u, "
754 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
755 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
756 rtex->cmask.pitch, rtex->cmask.height, rtex->cmask.xalign,
757 rtex->cmask.yalign, rtex->cmask.slice_tile_max);
758
759 if (rtex->htile_buffer)
760 fprintf(f, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
761 "xalign=%u, yalign=%u\n",
762 rtex->htile_buffer->b.b.width0,
763 rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
764 rtex->htile.height, rtex->htile.xalign, rtex->htile.yalign);
765
766 if (rtex->dcc_offset) {
767 fprintf(f, " DCC: offset=%"PRIu64", size=%"PRIu64", alignment=%"PRIu64"\n",
768 rtex->dcc_offset, rtex->surface.dcc_size,
769 rtex->surface.dcc_alignment);
770 for (i = 0; i <= rtex->surface.last_level; i++)
771 fprintf(f, " DCCLevel[%i]: offset=%"PRIu64"\n",
772 i, rtex->surface.level[i].dcc_offset);
773 }
774
775 for (i = 0; i <= rtex->surface.last_level; i++)
776 fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
777 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
778 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
779 i, rtex->surface.level[i].offset,
780 rtex->surface.level[i].slice_size,
781 u_minify(rtex->resource.b.b.width0, i),
782 u_minify(rtex->resource.b.b.height0, i),
783 u_minify(rtex->resource.b.b.depth0, i),
784 rtex->surface.level[i].nblk_x,
785 rtex->surface.level[i].nblk_y,
786 rtex->surface.level[i].nblk_z,
787 rtex->surface.level[i].pitch_bytes,
788 rtex->surface.level[i].mode);
789
790 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
791 for (i = 0; i <= rtex->surface.last_level; i++) {
792 fprintf(f, " StencilLayout: tilesplit=%u\n",
793 rtex->surface.stencil_tile_split);
794 fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
795 "slice_size=%"PRIu64", npix_x=%u, "
796 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
797 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
798 i, rtex->surface.stencil_level[i].offset,
799 rtex->surface.stencil_level[i].slice_size,
800 u_minify(rtex->resource.b.b.width0, i),
801 u_minify(rtex->resource.b.b.height0, i),
802 u_minify(rtex->resource.b.b.depth0, i),
803 rtex->surface.stencil_level[i].nblk_x,
804 rtex->surface.stencil_level[i].nblk_y,
805 rtex->surface.stencil_level[i].nblk_z,
806 rtex->surface.stencil_level[i].pitch_bytes,
807 rtex->surface.stencil_level[i].mode);
808 }
809 }
810 }
811
812 /* Common processing for r600_texture_create and r600_texture_from_handle */
813 static struct r600_texture *
814 r600_texture_create_object(struct pipe_screen *screen,
815 const struct pipe_resource *base,
816 unsigned pitch_in_bytes_override,
817 unsigned offset,
818 struct pb_buffer *buf,
819 struct radeon_surf *surface)
820 {
821 struct r600_texture *rtex;
822 struct r600_resource *resource;
823 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
824
825 rtex = CALLOC_STRUCT(r600_texture);
826 if (!rtex)
827 return NULL;
828
829 resource = &rtex->resource;
830 resource->b.b = *base;
831 resource->b.vtbl = &r600_texture_vtbl;
832 pipe_reference_init(&resource->b.b.reference, 1);
833 resource->b.b.screen = screen;
834
835 /* don't include stencil-only formats which we don't support for rendering */
836 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
837
838 rtex->surface = *surface;
839 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override, offset)) {
840 FREE(rtex);
841 return NULL;
842 }
843
844 /* Tiled depth textures utilize the non-displayable tile order.
845 * This must be done after r600_setup_surface.
846 * Applies to R600-Cayman. */
847 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
848
849 if (rtex->is_depth) {
850 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
851 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
852 !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
853
854 r600_texture_allocate_htile(rscreen, rtex);
855 }
856 } else {
857 if (base->nr_samples > 1) {
858 if (!buf) {
859 r600_texture_allocate_fmask(rscreen, rtex);
860 r600_texture_allocate_cmask(rscreen, rtex);
861 rtex->cmask_buffer = &rtex->resource;
862 }
863 if (!rtex->fmask.size || !rtex->cmask.size) {
864 FREE(rtex);
865 return NULL;
866 }
867 }
868
869 if (!buf && rtex->surface.dcc_size &&
870 !(rscreen->debug_flags & DBG_NO_DCC)) {
871 /* Reserve space for the DCC buffer. */
872 rtex->dcc_offset = align64(rtex->size, rtex->surface.dcc_alignment);
873 rtex->size = rtex->dcc_offset + rtex->surface.dcc_size;
874 rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
875 }
876 }
877
878 /* Now create the backing buffer. */
879 if (!buf) {
880 if (!r600_init_resource(rscreen, resource, rtex->size,
881 rtex->surface.bo_alignment)) {
882 FREE(rtex);
883 return NULL;
884 }
885 } else {
886 resource->buf = buf;
887 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
888 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
889 }
890
891 if (rtex->cmask.size) {
892 /* Initialize the cmask to 0xCC (= compressed state). */
893 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
894 rtex->cmask.offset, rtex->cmask.size,
895 0xCCCCCCCC, R600_COHERENCY_NONE);
896 }
897 if (rtex->dcc_offset) {
898 r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
899 rtex->dcc_offset,
900 rtex->surface.dcc_size,
901 0xFFFFFFFF, R600_COHERENCY_NONE);
902 }
903
904 /* Initialize the CMASK base register value. */
905 rtex->cmask.base_address_reg =
906 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
907
908 if (rscreen->debug_flags & DBG_VM) {
909 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
910 rtex->resource.gpu_address,
911 rtex->resource.gpu_address + rtex->resource.buf->size,
912 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
913 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
914 }
915
916 if (rscreen->debug_flags & DBG_TEX) {
917 puts("Texture:");
918 r600_print_texture_info(rtex, stdout);
919 }
920
921 return rtex;
922 }
923
924 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
925 const struct pipe_resource *templ)
926 {
927 const struct util_format_description *desc = util_format_description(templ->format);
928 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
929
930 /* MSAA resources must be 2D tiled. */
931 if (templ->nr_samples > 1)
932 return RADEON_SURF_MODE_2D;
933
934 /* Transfer resources should be linear. */
935 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
936 return RADEON_SURF_MODE_LINEAR_ALIGNED;
937
938 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
939 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
940 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
941 (templ->target == PIPE_TEXTURE_2D ||
942 templ->target == PIPE_TEXTURE_3D))
943 force_tiling = true;
944
945 /* Handle common candidates for the linear mode.
946 * Compressed textures and DB surfaces must always be tiled.
947 */
948 if (!force_tiling && !util_format_is_compressed(templ->format) &&
949 (!util_format_is_depth_or_stencil(templ->format) ||
950 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH)) {
951 if (rscreen->debug_flags & DBG_NO_TILING)
952 return RADEON_SURF_MODE_LINEAR_ALIGNED;
953
954 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
955 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
956 return RADEON_SURF_MODE_LINEAR_ALIGNED;
957
958 /* Cursors are linear on SI.
959 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
960 if (rscreen->chip_class >= SI &&
961 (templ->bind & PIPE_BIND_CURSOR))
962 return RADEON_SURF_MODE_LINEAR_ALIGNED;
963
964 if (templ->bind & PIPE_BIND_LINEAR)
965 return RADEON_SURF_MODE_LINEAR_ALIGNED;
966
967 /* Textures with a very small height are recommended to be linear. */
968 if (templ->target == PIPE_TEXTURE_1D ||
969 templ->target == PIPE_TEXTURE_1D_ARRAY ||
970 templ->height0 <= 4)
971 return RADEON_SURF_MODE_LINEAR_ALIGNED;
972
973 /* Textures likely to be mapped often. */
974 if (templ->usage == PIPE_USAGE_STAGING ||
975 templ->usage == PIPE_USAGE_STREAM)
976 return RADEON_SURF_MODE_LINEAR_ALIGNED;
977 }
978
979 /* Make small textures 1D tiled. */
980 if (templ->width0 <= 16 || templ->height0 <= 16 ||
981 (rscreen->debug_flags & DBG_NO_2D_TILING))
982 return RADEON_SURF_MODE_1D;
983
984 /* The allocator will switch to 1D if needed. */
985 return RADEON_SURF_MODE_2D;
986 }
987
988 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
989 const struct pipe_resource *templ)
990 {
991 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
992 struct radeon_surf surface = {0};
993 int r;
994
995 r = r600_init_surface(rscreen, &surface, templ,
996 r600_choose_tiling(rscreen, templ),
997 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
998 if (r) {
999 return NULL;
1000 }
1001 r = rscreen->ws->surface_best(rscreen->ws, &surface);
1002 if (r) {
1003 return NULL;
1004 }
1005 return (struct pipe_resource *)r600_texture_create_object(screen, templ, 0,
1006 0, NULL, &surface);
1007 }
1008
1009 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
1010 const struct pipe_resource *templ,
1011 struct winsys_handle *whandle,
1012 unsigned usage)
1013 {
1014 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1015 struct pb_buffer *buf = NULL;
1016 unsigned stride = 0, offset = 0;
1017 unsigned array_mode;
1018 struct radeon_surf surface;
1019 int r;
1020 struct radeon_bo_metadata metadata = {};
1021 struct r600_texture *rtex;
1022
1023 /* Support only 2D textures without mipmaps */
1024 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
1025 templ->depth0 != 1 || templ->last_level != 0)
1026 return NULL;
1027
1028 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride, &offset);
1029 if (!buf)
1030 return NULL;
1031
1032 rscreen->ws->buffer_get_metadata(buf, &metadata);
1033
1034 surface.bankw = metadata.bankw;
1035 surface.bankh = metadata.bankh;
1036 surface.tile_split = metadata.tile_split;
1037 surface.stencil_tile_split = metadata.stencil_tile_split;
1038 surface.mtilea = metadata.mtilea;
1039
1040 if (metadata.macrotile == RADEON_LAYOUT_TILED)
1041 array_mode = RADEON_SURF_MODE_2D;
1042 else if (metadata.microtile == RADEON_LAYOUT_TILED)
1043 array_mode = RADEON_SURF_MODE_1D;
1044 else
1045 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1046
1047 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
1048 if (r) {
1049 return NULL;
1050 }
1051
1052 if (metadata.scanout)
1053 surface.flags |= RADEON_SURF_SCANOUT;
1054
1055 rtex = r600_texture_create_object(screen, templ, stride,
1056 offset, buf, &surface);
1057 if (!rtex)
1058 return NULL;
1059
1060 rtex->resource.is_shared = true;
1061 rtex->resource.external_usage = usage;
1062 return &rtex->resource.b.b;
1063 }
1064
1065 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
1066 struct pipe_resource *texture,
1067 struct r600_texture **staging)
1068 {
1069 struct r600_texture *rtex = (struct r600_texture*)texture;
1070 struct pipe_resource resource;
1071 struct r600_texture **flushed_depth_texture = staging ?
1072 staging : &rtex->flushed_depth_texture;
1073
1074 if (!staging && rtex->flushed_depth_texture)
1075 return true; /* it's ready */
1076
1077 resource.target = texture->target;
1078 resource.format = texture->format;
1079 resource.width0 = texture->width0;
1080 resource.height0 = texture->height0;
1081 resource.depth0 = texture->depth0;
1082 resource.array_size = texture->array_size;
1083 resource.last_level = texture->last_level;
1084 resource.nr_samples = texture->nr_samples;
1085 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1086 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
1087 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1088
1089 if (staging)
1090 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
1091
1092 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
1093 if (*flushed_depth_texture == NULL) {
1094 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1095 return false;
1096 }
1097
1098 (*flushed_depth_texture)->is_flushing_texture = TRUE;
1099 (*flushed_depth_texture)->non_disp_tiling = false;
1100 return true;
1101 }
1102
1103 /**
1104 * Initialize the pipe_resource descriptor to be of the same size as the box,
1105 * which is supposed to hold a subregion of the texture "orig" at the given
1106 * mipmap level.
1107 */
1108 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
1109 struct pipe_resource *orig,
1110 const struct pipe_box *box,
1111 unsigned level, unsigned flags)
1112 {
1113 memset(res, 0, sizeof(*res));
1114 res->format = orig->format;
1115 res->width0 = box->width;
1116 res->height0 = box->height;
1117 res->depth0 = 1;
1118 res->array_size = 1;
1119 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1120 res->flags = flags;
1121
1122 /* We must set the correct texture target and dimensions for a 3D box. */
1123 if (box->depth > 1 && util_max_layer(orig, level) > 0)
1124 res->target = orig->target;
1125 else
1126 res->target = PIPE_TEXTURE_2D;
1127
1128 switch (res->target) {
1129 case PIPE_TEXTURE_1D_ARRAY:
1130 case PIPE_TEXTURE_2D_ARRAY:
1131 case PIPE_TEXTURE_CUBE_ARRAY:
1132 res->array_size = box->depth;
1133 break;
1134 case PIPE_TEXTURE_3D:
1135 res->depth0 = box->depth;
1136 break;
1137 default:;
1138 }
1139 }
1140
1141 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1142 struct pipe_resource *texture,
1143 unsigned level,
1144 unsigned usage,
1145 const struct pipe_box *box,
1146 struct pipe_transfer **ptransfer)
1147 {
1148 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1149 struct r600_texture *rtex = (struct r600_texture*)texture;
1150 struct r600_transfer *trans;
1151 boolean use_staging_texture = FALSE;
1152 struct r600_resource *buf;
1153 unsigned offset = 0;
1154 char *map;
1155
1156 /* We cannot map a tiled texture directly because the data is
1157 * in a different order, therefore we do detiling using a blit.
1158 *
1159 * Also, use a temporary in GTT memory for read transfers, as
1160 * the CPU is much happier reading out of cached system memory
1161 * than uncached VRAM.
1162 */
1163 if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
1164 use_staging_texture = TRUE;
1165 } else if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
1166 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
1167 /* Untiled buffers in VRAM, which is slow for CPU reads */
1168 use_staging_texture = TRUE;
1169 } else if (!(usage & PIPE_TRANSFER_READ) &&
1170 (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf, RADEON_USAGE_READWRITE) ||
1171 !rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) {
1172 /* Use a staging texture for uploads if the underlying BO is busy. */
1173 use_staging_texture = TRUE;
1174 }
1175
1176 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
1177 use_staging_texture = FALSE;
1178 }
1179
1180 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
1181 return NULL;
1182 }
1183
1184 trans = CALLOC_STRUCT(r600_transfer);
1185 if (!trans)
1186 return NULL;
1187 trans->transfer.resource = texture;
1188 trans->transfer.level = level;
1189 trans->transfer.usage = usage;
1190 trans->transfer.box = *box;
1191
1192 if (rtex->is_depth) {
1193 struct r600_texture *staging_depth;
1194
1195 if (rtex->resource.b.b.nr_samples > 1) {
1196 /* MSAA depth buffers need to be converted to single sample buffers.
1197 *
1198 * Mapping MSAA depth buffers can occur if ReadPixels is called
1199 * with a multisample GLX visual.
1200 *
1201 * First downsample the depth buffer to a temporary texture,
1202 * then decompress the temporary one to staging.
1203 *
1204 * Only the region being mapped is transfered.
1205 */
1206 struct pipe_resource resource;
1207
1208 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1209
1210 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1211 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1212 FREE(trans);
1213 return NULL;
1214 }
1215
1216 if (usage & PIPE_TRANSFER_READ) {
1217 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1218 if (!temp) {
1219 R600_ERR("failed to create a temporary depth texture\n");
1220 FREE(trans);
1221 return NULL;
1222 }
1223
1224 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1225 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1226 0, 0, 0, box->depth, 0, 0);
1227 pipe_resource_reference(&temp, NULL);
1228 }
1229 }
1230 else {
1231 /* XXX: only readback the rectangle which is being mapped? */
1232 /* XXX: when discard is true, no need to read back from depth texture */
1233 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1234 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1235 FREE(trans);
1236 return NULL;
1237 }
1238
1239 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1240 level, level,
1241 box->z, box->z + box->depth - 1,
1242 0, 0);
1243
1244 offset = r600_texture_get_offset(staging_depth, level, box);
1245 }
1246
1247 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
1248 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1249 trans->staging = (struct r600_resource*)staging_depth;
1250 } else if (use_staging_texture) {
1251 struct pipe_resource resource;
1252 struct r600_texture *staging;
1253
1254 r600_init_temp_resource_from_box(&resource, texture, box, level,
1255 R600_RESOURCE_FLAG_TRANSFER);
1256 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1257 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1258
1259 /* Create the temporary texture. */
1260 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1261 if (!staging) {
1262 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1263 FREE(trans);
1264 return NULL;
1265 }
1266 trans->staging = &staging->resource;
1267 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1268 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1269 if (usage & PIPE_TRANSFER_READ) {
1270 r600_copy_to_staging_texture(ctx, trans);
1271 }
1272 } else {
1273 /* the resource is mapped directly */
1274 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1275 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1276 offset = r600_texture_get_offset(rtex, level, box);
1277 }
1278
1279 if (trans->staging) {
1280 buf = trans->staging;
1281 if (!rtex->is_depth && !(usage & PIPE_TRANSFER_READ))
1282 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1283 } else {
1284 buf = &rtex->resource;
1285 }
1286
1287 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1288 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1289 FREE(trans);
1290 return NULL;
1291 }
1292
1293 *ptransfer = &trans->transfer;
1294 return map + offset;
1295 }
1296
1297 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1298 struct pipe_transfer* transfer)
1299 {
1300 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1301 struct pipe_resource *texture = transfer->resource;
1302 struct r600_texture *rtex = (struct r600_texture*)texture;
1303
1304 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1305 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1306 ctx->resource_copy_region(ctx, texture, transfer->level,
1307 transfer->box.x, transfer->box.y, transfer->box.z,
1308 &rtransfer->staging->b.b, transfer->level,
1309 &transfer->box);
1310 } else {
1311 r600_copy_from_staging_texture(ctx, rtransfer);
1312 }
1313 }
1314
1315 if (rtransfer->staging)
1316 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1317
1318 FREE(transfer);
1319 }
1320
1321 static const struct u_resource_vtbl r600_texture_vtbl =
1322 {
1323 NULL, /* get_handle */
1324 r600_texture_destroy, /* resource_destroy */
1325 r600_texture_transfer_map, /* transfer_map */
1326 u_default_transfer_flush_region, /* transfer_flush_region */
1327 r600_texture_transfer_unmap, /* transfer_unmap */
1328 NULL /* transfer_inline_write */
1329 };
1330
1331 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1332 struct pipe_resource *texture,
1333 const struct pipe_surface *templ,
1334 unsigned width, unsigned height)
1335 {
1336 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1337
1338 if (!surface)
1339 return NULL;
1340
1341 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1342 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1343
1344 pipe_reference_init(&surface->base.reference, 1);
1345 pipe_resource_reference(&surface->base.texture, texture);
1346 surface->base.context = pipe;
1347 surface->base.format = templ->format;
1348 surface->base.width = width;
1349 surface->base.height = height;
1350 surface->base.u = templ->u;
1351 return &surface->base;
1352 }
1353
1354 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1355 struct pipe_resource *tex,
1356 const struct pipe_surface *templ)
1357 {
1358 unsigned level = templ->u.tex.level;
1359 unsigned width = u_minify(tex->width0, level);
1360 unsigned height = u_minify(tex->height0, level);
1361
1362 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1363 const struct util_format_description *tex_desc
1364 = util_format_description(tex->format);
1365 const struct util_format_description *templ_desc
1366 = util_format_description(templ->format);
1367
1368 assert(tex_desc->block.bits == templ_desc->block.bits);
1369
1370 /* Adjust size of surface if and only if the block width or
1371 * height is changed. */
1372 if (tex_desc->block.width != templ_desc->block.width ||
1373 tex_desc->block.height != templ_desc->block.height) {
1374 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1375 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1376
1377 width = nblks_x * templ_desc->block.width;
1378 height = nblks_y * templ_desc->block.height;
1379 }
1380 }
1381
1382 return r600_create_surface_custom(pipe, tex, templ, width, height);
1383 }
1384
1385 static void r600_surface_destroy(struct pipe_context *pipe,
1386 struct pipe_surface *surface)
1387 {
1388 struct r600_surface *surf = (struct r600_surface*)surface;
1389 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1390 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1391 pipe_resource_reference(&surface->texture, NULL);
1392 FREE(surface);
1393 }
1394
1395 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap)
1396 {
1397 const struct util_format_description *desc = util_format_description(format);
1398
1399 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1400
1401 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1402 return V_0280A0_SWAP_STD;
1403
1404 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1405 return ~0U;
1406
1407 switch (desc->nr_channels) {
1408 case 1:
1409 if (HAS_SWIZZLE(0,X))
1410 return V_0280A0_SWAP_STD; /* X___ */
1411 else if (HAS_SWIZZLE(3,X))
1412 return V_0280A0_SWAP_ALT_REV; /* ___X */
1413 break;
1414 case 2:
1415 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1416 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1417 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1418 return V_0280A0_SWAP_STD; /* XY__ */
1419 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1420 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1421 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1422 /* YX__ */
1423 return (do_endian_swap ? V_0280A0_SWAP_STD : V_0280A0_SWAP_STD_REV);
1424 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1425 return V_0280A0_SWAP_ALT; /* X__Y */
1426 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1427 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1428 break;
1429 case 3:
1430 if (HAS_SWIZZLE(0,X))
1431 return (do_endian_swap ? V_0280A0_SWAP_STD_REV : V_0280A0_SWAP_STD);
1432 else if (HAS_SWIZZLE(0,Z))
1433 return V_0280A0_SWAP_STD_REV; /* ZYX */
1434 break;
1435 case 4:
1436 /* check the middle channels, the 1st and 4th channel can be NONE */
1437 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) {
1438 return V_0280A0_SWAP_STD; /* XYZW */
1439 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) {
1440 return V_0280A0_SWAP_STD_REV; /* WZYX */
1441 } else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) {
1442 return V_0280A0_SWAP_ALT; /* ZYXW */
1443 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W)) {
1444 /* YZWX */
1445 if (desc->is_array)
1446 return V_0280A0_SWAP_ALT_REV;
1447 else
1448 return (do_endian_swap ? V_0280A0_SWAP_ALT : V_0280A0_SWAP_ALT_REV);
1449 }
1450 break;
1451 }
1452 return ~0U;
1453 }
1454
1455 static void evergreen_set_clear_color(struct r600_texture *rtex,
1456 enum pipe_format surface_format,
1457 const union pipe_color_union *color)
1458 {
1459 union util_color uc;
1460
1461 memset(&uc, 0, sizeof(uc));
1462
1463 if (util_format_is_pure_uint(surface_format)) {
1464 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1465 } else if (util_format_is_pure_sint(surface_format)) {
1466 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1467 } else {
1468 util_pack_color(color->f, surface_format, &uc);
1469 }
1470
1471 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1472 }
1473
1474 static void vi_get_fast_clear_parameters(enum pipe_format surface_format,
1475 const union pipe_color_union *color,
1476 uint32_t* reset_value,
1477 bool* clear_words_needed)
1478 {
1479 bool values[4] = {};
1480 int i;
1481 bool main_value = false;
1482 bool extra_value = false;
1483 int extra_channel;
1484 const struct util_format_description *desc = util_format_description(surface_format);
1485
1486 *clear_words_needed = true;
1487 *reset_value = 0x20202020U;
1488
1489 /* If we want to clear without needing a fast clear eliminate step, we
1490 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1491 * have two sets of flags, one for the last or first channel(extra) and
1492 * one for the other channels(main).
1493 */
1494
1495 if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
1496 surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
1497 surface_format == PIPE_FORMAT_B5G6R5_SRGB) {
1498 extra_channel = -1;
1499 } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
1500 if(r600_translate_colorswap(surface_format, FALSE) <= 1)
1501 extra_channel = desc->nr_channels - 1;
1502 else
1503 extra_channel = 0;
1504 } else
1505 return;
1506
1507 for (i = 0; i < 4; ++i) {
1508 int index = desc->swizzle[i] - PIPE_SWIZZLE_X;
1509
1510 if (desc->swizzle[i] < PIPE_SWIZZLE_X ||
1511 desc->swizzle[i] > PIPE_SWIZZLE_W)
1512 continue;
1513
1514 if (util_format_is_pure_sint(surface_format)) {
1515 values[i] = color->i[i] != 0;
1516 if (color->i[i] != 0 && color->i[i] != INT32_MAX)
1517 return;
1518 } else if (util_format_is_pure_uint(surface_format)) {
1519 values[i] = color->ui[i] != 0U;
1520 if (color->ui[i] != 0U && color->ui[i] != UINT32_MAX)
1521 return;
1522 } else {
1523 values[i] = color->f[i] != 0.0F;
1524 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
1525 return;
1526 }
1527
1528 if (index == extra_channel)
1529 extra_value = values[i];
1530 else
1531 main_value = values[i];
1532 }
1533
1534 for (int i = 0; i < 4; ++i)
1535 if (values[i] != main_value &&
1536 desc->swizzle[i] - PIPE_SWIZZLE_X != extra_channel &&
1537 desc->swizzle[i] >= PIPE_SWIZZLE_X &&
1538 desc->swizzle[i] <= PIPE_SWIZZLE_W)
1539 return;
1540
1541 *clear_words_needed = false;
1542 if (main_value)
1543 *reset_value |= 0x80808080U;
1544
1545 if (extra_value)
1546 *reset_value |= 0x40404040U;
1547 }
1548
1549 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1550 struct pipe_framebuffer_state *fb,
1551 struct r600_atom *fb_state,
1552 unsigned *buffers, unsigned *dirty_cbufs,
1553 const union pipe_color_union *color)
1554 {
1555 int i;
1556
1557 /* This function is broken in BE, so just disable this path for now */
1558 #ifdef PIPE_ARCH_BIG_ENDIAN
1559 return;
1560 #endif
1561
1562 if (rctx->render_cond)
1563 return;
1564
1565 for (i = 0; i < fb->nr_cbufs; i++) {
1566 struct r600_texture *tex;
1567 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1568
1569 if (!fb->cbufs[i])
1570 continue;
1571
1572 /* if this colorbuffer is not being cleared */
1573 if (!(*buffers & clear_bit))
1574 continue;
1575
1576 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1577
1578 /* 128-bit formats are unusupported */
1579 if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
1580 continue;
1581 }
1582
1583 /* the clear is allowed if all layers are bound */
1584 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1585 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1586 continue;
1587 }
1588
1589 /* cannot clear mipmapped textures */
1590 if (fb->cbufs[i]->texture->last_level != 0) {
1591 continue;
1592 }
1593
1594 /* only supported on tiled surfaces */
1595 if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
1596 continue;
1597 }
1598
1599 /* shared textures can't use fast clear without an explicit flush,
1600 * because there is no way to communicate the clear color among
1601 * all clients
1602 */
1603 if (tex->resource.is_shared &&
1604 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
1605 continue;
1606
1607 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1608 if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
1609 rctx->chip_class >= CIK &&
1610 rctx->screen->info.drm_major == 2 &&
1611 rctx->screen->info.drm_minor < 38) {
1612 continue;
1613 }
1614
1615 if (tex->dcc_offset) {
1616 uint32_t reset_value;
1617 bool clear_words_needed;
1618
1619 if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
1620 continue;
1621
1622 vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed);
1623
1624 rctx->clear_buffer(&rctx->b, &tex->resource.b.b,
1625 tex->dcc_offset, tex->surface.dcc_size,
1626 reset_value, R600_COHERENCY_CB_META);
1627
1628 if (clear_words_needed)
1629 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1630 } else {
1631 /* Stoney/RB+ doesn't work with CMASK fast clear. */
1632 if (rctx->family == CHIP_STONEY)
1633 continue;
1634
1635 /* ensure CMASK is enabled */
1636 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1637 if (tex->cmask.size == 0) {
1638 continue;
1639 }
1640
1641 /* Do the fast clear. */
1642 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1643 tex->cmask.offset, tex->cmask.size, 0,
1644 R600_COHERENCY_CB_META);
1645
1646 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1647 }
1648
1649 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1650
1651 if (dirty_cbufs)
1652 *dirty_cbufs |= 1 << i;
1653 rctx->set_atom_dirty(rctx, fb_state, true);
1654 *buffers &= ~clear_bit;
1655 }
1656 }
1657
1658 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1659 {
1660 rscreen->b.resource_from_handle = r600_texture_from_handle;
1661 rscreen->b.resource_get_handle = r600_texture_get_handle;
1662 }
1663
1664 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1665 {
1666 rctx->b.create_surface = r600_create_surface;
1667 rctx->b.surface_destroy = r600_surface_destroy;
1668 }