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Merge remote-tracking branch 'public/master' into vulkan
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include <errno.h>
33 #include <inttypes.h>
34
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context *pipe,
37 struct pipe_resource *dst,
38 unsigned dst_level,
39 unsigned dstx, unsigned dsty, unsigned dstz,
40 struct pipe_resource *src,
41 unsigned src_level,
42 const struct pipe_box *src_box)
43 {
44 struct pipe_blit_info blit;
45
46 memset(&blit, 0, sizeof(blit));
47 blit.src.resource = src;
48 blit.src.format = src->format;
49 blit.src.level = src_level;
50 blit.src.box = *src_box;
51 blit.dst.resource = dst;
52 blit.dst.format = dst->format;
53 blit.dst.level = dst_level;
54 blit.dst.box.x = dstx;
55 blit.dst.box.y = dsty;
56 blit.dst.box.z = dstz;
57 blit.dst.box.width = src_box->width;
58 blit.dst.box.height = src_box->height;
59 blit.dst.box.depth = src_box->depth;
60 blit.mask = util_format_get_mask(src->format) &
61 util_format_get_mask(dst->format);
62 blit.filter = PIPE_TEX_FILTER_NEAREST;
63
64 if (blit.mask) {
65 pipe->blit(pipe, &blit);
66 }
67 }
68
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
71 {
72 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
73 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
74 struct pipe_resource *dst = &rtransfer->staging->b.b;
75 struct pipe_resource *src = transfer->resource;
76
77 if (src->nr_samples > 1) {
78 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
79 src, transfer->level, &transfer->box);
80 return;
81 }
82
83 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
84 &transfer->box);
85 }
86
87 /* Copy from a transfer's staging texture to a full GPU one. */
88 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
89 {
90 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
91 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
92 struct pipe_resource *dst = transfer->resource;
93 struct pipe_resource *src = &rtransfer->staging->b.b;
94 struct pipe_box sbox;
95
96 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
97
98 if (dst->nr_samples > 1) {
99 r600_copy_region_with_blit(ctx, dst, transfer->level,
100 transfer->box.x, transfer->box.y, transfer->box.z,
101 src, 0, &sbox);
102 return;
103 }
104
105 rctx->dma_copy(ctx, dst, transfer->level,
106 transfer->box.x, transfer->box.y, transfer->box.z,
107 src, 0, &sbox);
108 }
109
110 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
111 const struct pipe_box *box)
112 {
113 enum pipe_format format = rtex->resource.b.b.format;
114
115 return rtex->surface.level[level].offset +
116 box->z * rtex->surface.level[level].slice_size +
117 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
118 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
119 }
120
121 static int r600_init_surface(struct r600_common_screen *rscreen,
122 struct radeon_surf *surface,
123 const struct pipe_resource *ptex,
124 unsigned array_mode,
125 bool is_flushed_depth)
126 {
127 const struct util_format_description *desc =
128 util_format_description(ptex->format);
129 bool is_depth, is_stencil;
130
131 is_depth = util_format_has_depth(desc);
132 is_stencil = util_format_has_stencil(desc);
133
134 surface->npix_x = ptex->width0;
135 surface->npix_y = ptex->height0;
136 surface->npix_z = ptex->depth0;
137 surface->blk_w = util_format_get_blockwidth(ptex->format);
138 surface->blk_h = util_format_get_blockheight(ptex->format);
139 surface->blk_d = 1;
140 surface->array_size = 1;
141 surface->last_level = ptex->last_level;
142
143 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
144 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
145 surface->bpe = 4; /* stencil is allocated separately on evergreen */
146 } else {
147 surface->bpe = util_format_get_blocksize(ptex->format);
148 /* align byte per element on dword */
149 if (surface->bpe == 3) {
150 surface->bpe = 4;
151 }
152 }
153
154 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
155 surface->flags = RADEON_SURF_SET(array_mode, MODE);
156
157 switch (ptex->target) {
158 case PIPE_TEXTURE_1D:
159 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
160 break;
161 case PIPE_TEXTURE_RECT:
162 case PIPE_TEXTURE_2D:
163 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
164 break;
165 case PIPE_TEXTURE_3D:
166 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
167 break;
168 case PIPE_TEXTURE_1D_ARRAY:
169 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
170 surface->array_size = ptex->array_size;
171 break;
172 case PIPE_TEXTURE_2D_ARRAY:
173 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
175 surface->array_size = ptex->array_size;
176 break;
177 case PIPE_TEXTURE_CUBE:
178 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
179 break;
180 case PIPE_BUFFER:
181 default:
182 return -EINVAL;
183 }
184 if (ptex->bind & PIPE_BIND_SCANOUT) {
185 surface->flags |= RADEON_SURF_SCANOUT;
186 }
187
188 if (!is_flushed_depth && is_depth) {
189 surface->flags |= RADEON_SURF_ZBUFFER;
190
191 if (is_stencil) {
192 surface->flags |= RADEON_SURF_SBUFFER |
193 RADEON_SURF_HAS_SBUFFER_MIPTREE;
194 }
195 }
196 if (rscreen->chip_class >= SI) {
197 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
198 }
199 return 0;
200 }
201
202 static int r600_setup_surface(struct pipe_screen *screen,
203 struct r600_texture *rtex,
204 unsigned pitch_in_bytes_override,
205 unsigned offset)
206 {
207 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
208 unsigned i;
209 int r;
210
211 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
212 if (r) {
213 return r;
214 }
215
216 rtex->size = rtex->surface.bo_size;
217
218 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
219 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
220 * for those
221 */
222 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
223 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
224 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
225 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
226 rtex->surface.stencil_offset =
227 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
228 }
229 }
230
231 if (offset) {
232 for (i = 0; i < Elements(rtex->surface.level); ++i)
233 rtex->surface.level[i].offset += offset;
234 }
235 return 0;
236 }
237
238 static void r600_texture_init_metadata(struct r600_texture *rtex,
239 struct radeon_bo_metadata *metadata)
240 {
241 struct radeon_surf *surface = &rtex->surface;
242
243 memset(metadata, 0, sizeof(*metadata));
244 metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
245 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
246 metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
247 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
248 metadata->pipe_config = surface->pipe_config;
249 metadata->bankw = surface->bankw;
250 metadata->bankh = surface->bankh;
251 metadata->tile_split = surface->tile_split;
252 metadata->stencil_tile_split = surface->stencil_tile_split;
253 metadata->mtilea = surface->mtilea;
254 metadata->num_banks = surface->num_banks;
255 metadata->stride = surface->level[0].pitch_bytes;
256 metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
257 }
258
259 static void r600_dirty_all_framebuffer_states(struct r600_common_screen *rscreen)
260 {
261 p_atomic_inc(&rscreen->dirty_fb_counter);
262 }
263
264 static void r600_eliminate_fast_color_clear(struct r600_common_screen *rscreen,
265 struct r600_texture *rtex)
266 {
267 struct pipe_context *ctx = rscreen->aux_context;
268
269 pipe_mutex_lock(rscreen->aux_context_lock);
270 ctx->flush_resource(ctx, &rtex->resource.b.b);
271 ctx->flush(ctx, NULL, 0);
272 pipe_mutex_unlock(rscreen->aux_context_lock);
273 }
274
275 static void r600_texture_disable_cmask(struct r600_common_screen *rscreen,
276 struct r600_texture *rtex)
277 {
278 if (!rtex->cmask.size)
279 return;
280
281 assert(rtex->resource.b.b.nr_samples <= 1);
282
283 /* Disable CMASK. */
284 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
285 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
286
287 if (rscreen->chip_class >= SI)
288 rtex->cb_color_info &= ~SI_S_028C70_FAST_CLEAR(1);
289 else
290 rtex->cb_color_info &= ~EG_S_028C70_FAST_CLEAR(1);
291
292 if (rtex->cmask_buffer != &rtex->resource)
293 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
294
295 /* Notify all contexts about the change. */
296 r600_dirty_all_framebuffer_states(rscreen);
297 p_atomic_inc(&rscreen->compressed_colortex_counter);
298 }
299
300 void r600_texture_disable_dcc(struct r600_common_screen *rscreen,
301 struct r600_texture *rtex)
302 {
303 struct r600_common_context *rctx =
304 (struct r600_common_context *)rscreen->aux_context;
305
306 if (!rtex->dcc_offset)
307 return;
308
309 /* Decompress DCC. */
310 pipe_mutex_lock(rscreen->aux_context_lock);
311 rctx->decompress_dcc(&rctx->b, rtex);
312 rctx->b.flush(&rctx->b, NULL, 0);
313 pipe_mutex_unlock(rscreen->aux_context_lock);
314
315 /* Disable DCC. */
316 rtex->dcc_offset = 0;
317 rtex->cb_color_info &= ~VI_S_028C70_DCC_ENABLE(1);
318
319 /* Notify all contexts about the change. */
320 r600_dirty_all_framebuffer_states(rscreen);
321 }
322
323 static boolean r600_texture_get_handle(struct pipe_screen* screen,
324 struct pipe_resource *resource,
325 struct winsys_handle *whandle,
326 unsigned usage)
327 {
328 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
329 struct r600_resource *res = (struct r600_resource*)resource;
330 struct r600_texture *rtex = (struct r600_texture*)resource;
331 struct radeon_bo_metadata metadata;
332 bool update_metadata = false;
333
334 /* This is not supported now, but it might be required for OpenCL
335 * interop in the future.
336 */
337 if (resource->target != PIPE_BUFFER &&
338 (resource->nr_samples > 1 || rtex->is_depth))
339 return false;
340
341 if (resource->target != PIPE_BUFFER) {
342 /* Since shader image stores don't support DCC on VI,
343 * disable it for external clients that want write
344 * access.
345 */
346 if (usage & PIPE_HANDLE_USAGE_WRITE && rtex->dcc_offset) {
347 r600_texture_disable_dcc(rscreen, rtex);
348 update_metadata = true;
349 }
350
351 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
352 rtex->cmask.size) {
353 /* Eliminate fast clear (both CMASK and DCC) */
354 r600_eliminate_fast_color_clear(rscreen, rtex);
355
356 /* Disable CMASK if flush_resource isn't going
357 * to be called.
358 */
359 r600_texture_disable_cmask(rscreen, rtex);
360 update_metadata = true;
361 }
362
363 /* Set metadata. */
364 if (!res->is_shared || update_metadata) {
365 r600_texture_init_metadata(rtex, &metadata);
366 if (rscreen->query_opaque_metadata)
367 rscreen->query_opaque_metadata(rscreen, rtex,
368 &metadata);
369
370 rscreen->ws->buffer_set_metadata(res->buf, &metadata);
371 }
372 }
373
374 if (res->is_shared) {
375 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
376 * doesn't set it.
377 */
378 res->external_usage |= usage & ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
379 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
380 res->external_usage &= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
381 } else {
382 res->is_shared = true;
383 res->external_usage = usage;
384 }
385
386 return rscreen->ws->buffer_get_handle(res->buf,
387 rtex->surface.level[0].pitch_bytes,
388 rtex->surface.level[0].offset,
389 rtex->surface.level[0].slice_size,
390 whandle);
391 }
392
393 static void r600_texture_destroy(struct pipe_screen *screen,
394 struct pipe_resource *ptex)
395 {
396 struct r600_texture *rtex = (struct r600_texture*)ptex;
397 struct r600_resource *resource = &rtex->resource;
398
399 if (rtex->flushed_depth_texture)
400 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
401
402 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
403 if (rtex->cmask_buffer != &rtex->resource) {
404 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
405 }
406 pb_reference(&resource->buf, NULL);
407 FREE(rtex);
408 }
409
410 static const struct u_resource_vtbl r600_texture_vtbl;
411
412 /* The number of samples can be specified independently of the texture. */
413 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
414 struct r600_texture *rtex,
415 unsigned nr_samples,
416 struct r600_fmask_info *out)
417 {
418 /* FMASK is allocated like an ordinary texture. */
419 struct radeon_surf fmask = rtex->surface;
420
421 memset(out, 0, sizeof(*out));
422
423 fmask.bo_alignment = 0;
424 fmask.bo_size = 0;
425 fmask.nsamples = 1;
426 fmask.flags |= RADEON_SURF_FMASK;
427
428 /* Force 2D tiling if it wasn't set. This may occur when creating
429 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
430 * destination buffer must have an FMASK too. */
431 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
432 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
433
434 if (rscreen->chip_class >= SI) {
435 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
436 }
437
438 switch (nr_samples) {
439 case 2:
440 case 4:
441 fmask.bpe = 1;
442 if (rscreen->chip_class <= CAYMAN) {
443 fmask.bankh = 4;
444 }
445 break;
446 case 8:
447 fmask.bpe = 4;
448 break;
449 default:
450 R600_ERR("Invalid sample count for FMASK allocation.\n");
451 return;
452 }
453
454 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
455 * This can be fixed by writing a separate FMASK allocator specifically
456 * for R600-R700 asics. */
457 if (rscreen->chip_class <= R700) {
458 fmask.bpe *= 2;
459 }
460
461 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
462 R600_ERR("Got error in surface_init while allocating FMASK.\n");
463 return;
464 }
465
466 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
467
468 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
469 if (out->slice_tile_max)
470 out->slice_tile_max -= 1;
471
472 out->tile_mode_index = fmask.tiling_index[0];
473 out->pitch_in_pixels = fmask.level[0].nblk_x;
474 out->bank_height = fmask.bankh;
475 out->alignment = MAX2(256, fmask.bo_alignment);
476 out->size = fmask.bo_size;
477 }
478
479 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
480 struct r600_texture *rtex)
481 {
482 r600_texture_get_fmask_info(rscreen, rtex,
483 rtex->resource.b.b.nr_samples, &rtex->fmask);
484
485 rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
486 rtex->size = rtex->fmask.offset + rtex->fmask.size;
487 }
488
489 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
490 struct r600_texture *rtex,
491 struct r600_cmask_info *out)
492 {
493 unsigned cmask_tile_width = 8;
494 unsigned cmask_tile_height = 8;
495 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
496 unsigned element_bits = 4;
497 unsigned cmask_cache_bits = 1024;
498 unsigned num_pipes = rscreen->info.num_tile_pipes;
499 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
500
501 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
502 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
503 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
504 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
505 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
506
507 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
508 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
509
510 unsigned base_align = num_pipes * pipe_interleave_bytes;
511 unsigned slice_bytes =
512 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
513
514 assert(macro_tile_width % 128 == 0);
515 assert(macro_tile_height % 128 == 0);
516
517 out->pitch = pitch_elements;
518 out->height = height;
519 out->xalign = macro_tile_width;
520 out->yalign = macro_tile_height;
521 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
522 out->alignment = MAX2(256, base_align);
523 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
524 align(slice_bytes, base_align);
525 }
526
527 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
528 struct r600_texture *rtex,
529 struct r600_cmask_info *out)
530 {
531 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
532 unsigned num_pipes = rscreen->info.num_tile_pipes;
533 unsigned cl_width, cl_height;
534
535 switch (num_pipes) {
536 case 2:
537 cl_width = 32;
538 cl_height = 16;
539 break;
540 case 4:
541 cl_width = 32;
542 cl_height = 32;
543 break;
544 case 8:
545 cl_width = 64;
546 cl_height = 32;
547 break;
548 case 16: /* Hawaii */
549 cl_width = 64;
550 cl_height = 64;
551 break;
552 default:
553 assert(0);
554 return;
555 }
556
557 unsigned base_align = num_pipes * pipe_interleave_bytes;
558
559 unsigned width = align(rtex->surface.npix_x, cl_width*8);
560 unsigned height = align(rtex->surface.npix_y, cl_height*8);
561 unsigned slice_elements = (width * height) / (8*8);
562
563 /* Each element of CMASK is a nibble. */
564 unsigned slice_bytes = slice_elements / 2;
565
566 out->pitch = width;
567 out->height = height;
568 out->xalign = cl_width * 8;
569 out->yalign = cl_height * 8;
570 out->slice_tile_max = (width * height) / (128*128);
571 if (out->slice_tile_max)
572 out->slice_tile_max -= 1;
573
574 out->alignment = MAX2(256, base_align);
575 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
576 align(slice_bytes, base_align);
577 }
578
579 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
580 struct r600_texture *rtex)
581 {
582 if (rscreen->chip_class >= SI) {
583 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
584 } else {
585 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
586 }
587
588 rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
589 rtex->size = rtex->cmask.offset + rtex->cmask.size;
590
591 if (rscreen->chip_class >= SI)
592 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
593 else
594 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
595 }
596
597 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
598 struct r600_texture *rtex)
599 {
600 if (rtex->cmask_buffer)
601 return;
602
603 assert(rtex->cmask.size == 0);
604
605 if (rscreen->chip_class >= SI) {
606 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
607 } else {
608 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
609 }
610
611 rtex->cmask_buffer = (struct r600_resource *)
612 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
613 PIPE_USAGE_DEFAULT, rtex->cmask.size);
614 if (rtex->cmask_buffer == NULL) {
615 rtex->cmask.size = 0;
616 return;
617 }
618
619 /* update colorbuffer state bits */
620 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
621
622 if (rscreen->chip_class >= SI)
623 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
624 else
625 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
626
627 p_atomic_inc(&rscreen->compressed_colortex_counter);
628 }
629
630 static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
631 struct r600_texture *rtex)
632 {
633 unsigned cl_width, cl_height, width, height;
634 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
635 unsigned num_pipes = rscreen->info.num_tile_pipes;
636
637 if (rscreen->chip_class <= EVERGREEN &&
638 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
639 return 0;
640
641 /* HW bug on R6xx. */
642 if (rscreen->chip_class == R600 &&
643 (rtex->surface.level[0].npix_x > 7680 ||
644 rtex->surface.level[0].npix_y > 7680))
645 return 0;
646
647 /* HTILE is broken with 1D tiling on old kernels and CIK. */
648 if (rscreen->chip_class >= CIK &&
649 rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
650 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
651 return 0;
652
653 /* Overalign HTILE on P2 configs to work around GPU hangs in
654 * piglit/depthstencil-render-miplevels 585.
655 *
656 * This has been confirmed to help Kabini & Stoney, where the hangs
657 * are always reproducible. I think I have seen the test hang
658 * on Carrizo too, though it was very rare there.
659 */
660 if (rscreen->chip_class >= CIK && num_pipes < 4)
661 num_pipes = 4;
662
663 switch (num_pipes) {
664 case 1:
665 cl_width = 32;
666 cl_height = 16;
667 break;
668 case 2:
669 cl_width = 32;
670 cl_height = 32;
671 break;
672 case 4:
673 cl_width = 64;
674 cl_height = 32;
675 break;
676 case 8:
677 cl_width = 64;
678 cl_height = 64;
679 break;
680 case 16:
681 cl_width = 128;
682 cl_height = 64;
683 break;
684 default:
685 assert(0);
686 return 0;
687 }
688
689 width = align(rtex->surface.npix_x, cl_width * 8);
690 height = align(rtex->surface.npix_y, cl_height * 8);
691
692 slice_elements = (width * height) / (8 * 8);
693 slice_bytes = slice_elements * 4;
694
695 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
696 base_align = num_pipes * pipe_interleave_bytes;
697
698 rtex->htile.pitch = width;
699 rtex->htile.height = height;
700 rtex->htile.xalign = cl_width * 8;
701 rtex->htile.yalign = cl_height * 8;
702
703 return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
704 align(slice_bytes, base_align);
705 }
706
707 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
708 struct r600_texture *rtex)
709 {
710 unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex);
711
712 if (!htile_size)
713 return;
714
715 rtex->htile_buffer = (struct r600_resource*)
716 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
717 PIPE_USAGE_DEFAULT, htile_size);
718 if (rtex->htile_buffer == NULL) {
719 /* this is not a fatal error as we can still keep rendering
720 * without htile buffer */
721 R600_ERR("Failed to create buffer object for htile buffer.\n");
722 } else {
723 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0,
724 htile_size, 0, true);
725 }
726 }
727
728 void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
729 {
730 int i;
731
732 fprintf(f, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
733 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
734 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
735 rtex->surface.npix_x, rtex->surface.npix_y,
736 rtex->surface.npix_z, rtex->surface.blk_w,
737 rtex->surface.blk_h, rtex->surface.blk_d,
738 rtex->surface.array_size, rtex->surface.last_level,
739 rtex->surface.bpe, rtex->surface.nsamples,
740 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
741
742 fprintf(f, " Layout: size=%"PRIu64", alignment=%"PRIu64", bankw=%u, "
743 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
744 rtex->surface.bo_size, rtex->surface.bo_alignment, rtex->surface.bankw,
745 rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
746 rtex->surface.tile_split, rtex->surface.pipe_config,
747 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
748
749 if (rtex->fmask.size)
750 fprintf(f, " FMask: offset=%u, size=%u, alignment=%u, pitch_in_pixels=%u, "
751 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
752 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
753 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
754 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
755
756 if (rtex->cmask.size)
757 fprintf(f, " CMask: offset=%u, size=%u, alignment=%u, pitch=%u, "
758 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
759 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
760 rtex->cmask.pitch, rtex->cmask.height, rtex->cmask.xalign,
761 rtex->cmask.yalign, rtex->cmask.slice_tile_max);
762
763 if (rtex->htile_buffer)
764 fprintf(f, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
765 "xalign=%u, yalign=%u\n",
766 rtex->htile_buffer->b.b.width0,
767 rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
768 rtex->htile.height, rtex->htile.xalign, rtex->htile.yalign);
769
770 if (rtex->dcc_offset) {
771 fprintf(f, " DCC: offset=%u, size=%"PRIu64", alignment=%"PRIu64"\n",
772 rtex->dcc_offset, rtex->surface.dcc_size,
773 rtex->surface.dcc_alignment);
774 for (i = 0; i <= rtex->surface.last_level; i++)
775 fprintf(f, " DCCLevel[%i]: offset=%"PRIu64"\n",
776 i, rtex->surface.level[i].dcc_offset);
777 }
778
779 for (i = 0; i <= rtex->surface.last_level; i++)
780 fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
781 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
782 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
783 i, rtex->surface.level[i].offset,
784 rtex->surface.level[i].slice_size,
785 u_minify(rtex->resource.b.b.width0, i),
786 u_minify(rtex->resource.b.b.height0, i),
787 u_minify(rtex->resource.b.b.depth0, i),
788 rtex->surface.level[i].nblk_x,
789 rtex->surface.level[i].nblk_y,
790 rtex->surface.level[i].nblk_z,
791 rtex->surface.level[i].pitch_bytes,
792 rtex->surface.level[i].mode);
793
794 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
795 for (i = 0; i <= rtex->surface.last_level; i++) {
796 fprintf(f, " StencilLayout: tilesplit=%u\n",
797 rtex->surface.stencil_tile_split);
798 fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
799 "slice_size=%"PRIu64", npix_x=%u, "
800 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
801 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
802 i, rtex->surface.stencil_level[i].offset,
803 rtex->surface.stencil_level[i].slice_size,
804 u_minify(rtex->resource.b.b.width0, i),
805 u_minify(rtex->resource.b.b.height0, i),
806 u_minify(rtex->resource.b.b.depth0, i),
807 rtex->surface.stencil_level[i].nblk_x,
808 rtex->surface.stencil_level[i].nblk_y,
809 rtex->surface.stencil_level[i].nblk_z,
810 rtex->surface.stencil_level[i].pitch_bytes,
811 rtex->surface.stencil_level[i].mode);
812 }
813 }
814 }
815
816 /* Common processing for r600_texture_create and r600_texture_from_handle */
817 static struct r600_texture *
818 r600_texture_create_object(struct pipe_screen *screen,
819 const struct pipe_resource *base,
820 unsigned pitch_in_bytes_override,
821 unsigned offset,
822 struct pb_buffer *buf,
823 struct radeon_surf *surface)
824 {
825 struct r600_texture *rtex;
826 struct r600_resource *resource;
827 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
828
829 rtex = CALLOC_STRUCT(r600_texture);
830 if (!rtex)
831 return NULL;
832
833 resource = &rtex->resource;
834 resource->b.b = *base;
835 resource->b.vtbl = &r600_texture_vtbl;
836 pipe_reference_init(&resource->b.b.reference, 1);
837 resource->b.b.screen = screen;
838
839 /* don't include stencil-only formats which we don't support for rendering */
840 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
841
842 rtex->surface = *surface;
843 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override, offset)) {
844 FREE(rtex);
845 return NULL;
846 }
847
848 /* Tiled depth textures utilize the non-displayable tile order.
849 * This must be done after r600_setup_surface.
850 * Applies to R600-Cayman. */
851 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
852
853 if (rtex->is_depth) {
854 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
855 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
856 !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
857
858 r600_texture_allocate_htile(rscreen, rtex);
859 }
860 } else {
861 if (base->nr_samples > 1) {
862 if (!buf) {
863 r600_texture_allocate_fmask(rscreen, rtex);
864 r600_texture_allocate_cmask(rscreen, rtex);
865 rtex->cmask_buffer = &rtex->resource;
866 }
867 if (!rtex->fmask.size || !rtex->cmask.size) {
868 FREE(rtex);
869 return NULL;
870 }
871 }
872
873 if (!buf && rtex->surface.dcc_size &&
874 !(rscreen->debug_flags & DBG_NO_DCC)) {
875 /* Reserve space for the DCC buffer. */
876 rtex->dcc_offset = align(rtex->size, rtex->surface.dcc_alignment);
877 rtex->size = rtex->dcc_offset + rtex->surface.dcc_size;
878 rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
879 }
880 }
881
882 /* Now create the backing buffer. */
883 if (!buf) {
884 if (!r600_init_resource(rscreen, resource, rtex->size,
885 rtex->surface.bo_alignment, TRUE)) {
886 FREE(rtex);
887 return NULL;
888 }
889 } else {
890 resource->buf = buf;
891 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
892 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
893 }
894
895 if (rtex->cmask.size) {
896 /* Initialize the cmask to 0xCC (= compressed state). */
897 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
898 rtex->cmask.offset, rtex->cmask.size,
899 0xCCCCCCCC, true);
900 }
901 if (rtex->dcc_offset) {
902 r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
903 rtex->dcc_offset,
904 rtex->surface.dcc_size,
905 0xFFFFFFFF, true);
906 }
907
908 /* Initialize the CMASK base register value. */
909 rtex->cmask.base_address_reg =
910 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
911
912 if (rscreen->debug_flags & DBG_VM) {
913 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
914 rtex->resource.gpu_address,
915 rtex->resource.gpu_address + rtex->resource.buf->size,
916 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
917 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
918 }
919
920 if (rscreen->debug_flags & DBG_TEX) {
921 puts("Texture:");
922 r600_print_texture_info(rtex, stdout);
923 }
924
925 return rtex;
926 }
927
928 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
929 const struct pipe_resource *templ)
930 {
931 const struct util_format_description *desc = util_format_description(templ->format);
932 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
933
934 /* MSAA resources must be 2D tiled. */
935 if (templ->nr_samples > 1)
936 return RADEON_SURF_MODE_2D;
937
938 /* Transfer resources should be linear. */
939 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
940 return RADEON_SURF_MODE_LINEAR_ALIGNED;
941
942 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
943 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
944 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
945 (templ->target == PIPE_TEXTURE_2D ||
946 templ->target == PIPE_TEXTURE_3D))
947 force_tiling = true;
948
949 /* Handle common candidates for the linear mode.
950 * Compressed textures must always be tiled. */
951 if (!force_tiling && !util_format_is_compressed(templ->format)) {
952 /* Not everything can be linear, so we cannot enforce it
953 * for all textures. */
954 if ((rscreen->debug_flags & DBG_NO_TILING) &&
955 (!util_format_is_depth_or_stencil(templ->format) ||
956 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH)))
957 return RADEON_SURF_MODE_LINEAR_ALIGNED;
958
959 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
960 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
961 return RADEON_SURF_MODE_LINEAR_ALIGNED;
962
963 /* Cursors are linear on SI.
964 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
965 if (rscreen->chip_class >= SI &&
966 (templ->bind & PIPE_BIND_CURSOR))
967 return RADEON_SURF_MODE_LINEAR_ALIGNED;
968
969 if (templ->bind & PIPE_BIND_LINEAR)
970 return RADEON_SURF_MODE_LINEAR_ALIGNED;
971
972 /* Textures with a very small height are recommended to be linear. */
973 if (templ->target == PIPE_TEXTURE_1D ||
974 templ->target == PIPE_TEXTURE_1D_ARRAY ||
975 templ->height0 <= 4)
976 return RADEON_SURF_MODE_LINEAR_ALIGNED;
977
978 /* Textures likely to be mapped often. */
979 if (templ->usage == PIPE_USAGE_STAGING ||
980 templ->usage == PIPE_USAGE_STREAM)
981 return RADEON_SURF_MODE_LINEAR_ALIGNED;
982 }
983
984 /* Make small textures 1D tiled. */
985 if (templ->width0 <= 16 || templ->height0 <= 16 ||
986 (rscreen->debug_flags & DBG_NO_2D_TILING))
987 return RADEON_SURF_MODE_1D;
988
989 /* The allocator will switch to 1D if needed. */
990 return RADEON_SURF_MODE_2D;
991 }
992
993 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
994 const struct pipe_resource *templ)
995 {
996 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
997 struct radeon_surf surface = {0};
998 int r;
999
1000 r = r600_init_surface(rscreen, &surface, templ,
1001 r600_choose_tiling(rscreen, templ),
1002 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
1003 if (r) {
1004 return NULL;
1005 }
1006 r = rscreen->ws->surface_best(rscreen->ws, &surface);
1007 if (r) {
1008 return NULL;
1009 }
1010 return (struct pipe_resource *)r600_texture_create_object(screen, templ, 0,
1011 0, NULL, &surface);
1012 }
1013
1014 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
1015 const struct pipe_resource *templ,
1016 struct winsys_handle *whandle,
1017 unsigned usage)
1018 {
1019 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1020 struct pb_buffer *buf = NULL;
1021 unsigned stride = 0, offset = 0;
1022 unsigned array_mode;
1023 struct radeon_surf surface;
1024 int r;
1025 struct radeon_bo_metadata metadata = {};
1026 struct r600_texture *rtex;
1027
1028 /* Support only 2D textures without mipmaps */
1029 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
1030 templ->depth0 != 1 || templ->last_level != 0)
1031 return NULL;
1032
1033 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride, &offset);
1034 if (!buf)
1035 return NULL;
1036
1037 rscreen->ws->buffer_get_metadata(buf, &metadata);
1038
1039 surface.bankw = metadata.bankw;
1040 surface.bankh = metadata.bankh;
1041 surface.tile_split = metadata.tile_split;
1042 surface.stencil_tile_split = metadata.stencil_tile_split;
1043 surface.mtilea = metadata.mtilea;
1044
1045 if (metadata.macrotile == RADEON_LAYOUT_TILED)
1046 array_mode = RADEON_SURF_MODE_2D;
1047 else if (metadata.microtile == RADEON_LAYOUT_TILED)
1048 array_mode = RADEON_SURF_MODE_1D;
1049 else
1050 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1051
1052 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
1053 if (r) {
1054 return NULL;
1055 }
1056
1057 if (metadata.scanout)
1058 surface.flags |= RADEON_SURF_SCANOUT;
1059
1060 rtex = r600_texture_create_object(screen, templ, stride,
1061 offset, buf, &surface);
1062 if (!rtex)
1063 return NULL;
1064
1065 rtex->resource.is_shared = true;
1066 rtex->resource.external_usage = usage;
1067 return &rtex->resource.b.b;
1068 }
1069
1070 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
1071 struct pipe_resource *texture,
1072 struct r600_texture **staging)
1073 {
1074 struct r600_texture *rtex = (struct r600_texture*)texture;
1075 struct pipe_resource resource;
1076 struct r600_texture **flushed_depth_texture = staging ?
1077 staging : &rtex->flushed_depth_texture;
1078
1079 if (!staging && rtex->flushed_depth_texture)
1080 return true; /* it's ready */
1081
1082 resource.target = texture->target;
1083 resource.format = texture->format;
1084 resource.width0 = texture->width0;
1085 resource.height0 = texture->height0;
1086 resource.depth0 = texture->depth0;
1087 resource.array_size = texture->array_size;
1088 resource.last_level = texture->last_level;
1089 resource.nr_samples = texture->nr_samples;
1090 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1091 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
1092 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1093
1094 if (staging)
1095 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
1096
1097 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
1098 if (*flushed_depth_texture == NULL) {
1099 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1100 return false;
1101 }
1102
1103 (*flushed_depth_texture)->is_flushing_texture = TRUE;
1104 (*flushed_depth_texture)->non_disp_tiling = false;
1105 return true;
1106 }
1107
1108 /**
1109 * Initialize the pipe_resource descriptor to be of the same size as the box,
1110 * which is supposed to hold a subregion of the texture "orig" at the given
1111 * mipmap level.
1112 */
1113 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
1114 struct pipe_resource *orig,
1115 const struct pipe_box *box,
1116 unsigned level, unsigned flags)
1117 {
1118 memset(res, 0, sizeof(*res));
1119 res->format = orig->format;
1120 res->width0 = box->width;
1121 res->height0 = box->height;
1122 res->depth0 = 1;
1123 res->array_size = 1;
1124 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1125 res->flags = flags;
1126
1127 /* We must set the correct texture target and dimensions for a 3D box. */
1128 if (box->depth > 1 && util_max_layer(orig, level) > 0)
1129 res->target = orig->target;
1130 else
1131 res->target = PIPE_TEXTURE_2D;
1132
1133 switch (res->target) {
1134 case PIPE_TEXTURE_1D_ARRAY:
1135 case PIPE_TEXTURE_2D_ARRAY:
1136 case PIPE_TEXTURE_CUBE_ARRAY:
1137 res->array_size = box->depth;
1138 break;
1139 case PIPE_TEXTURE_3D:
1140 res->depth0 = box->depth;
1141 break;
1142 default:;
1143 }
1144 }
1145
1146 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1147 struct pipe_resource *texture,
1148 unsigned level,
1149 unsigned usage,
1150 const struct pipe_box *box,
1151 struct pipe_transfer **ptransfer)
1152 {
1153 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1154 struct r600_texture *rtex = (struct r600_texture*)texture;
1155 struct r600_transfer *trans;
1156 boolean use_staging_texture = FALSE;
1157 struct r600_resource *buf;
1158 unsigned offset = 0;
1159 char *map;
1160
1161 /* We cannot map a tiled texture directly because the data is
1162 * in a different order, therefore we do detiling using a blit.
1163 *
1164 * Also, use a temporary in GTT memory for read transfers, as
1165 * the CPU is much happier reading out of cached system memory
1166 * than uncached VRAM.
1167 */
1168 if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
1169 use_staging_texture = TRUE;
1170 } else if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
1171 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
1172 /* Untiled buffers in VRAM, which is slow for CPU reads */
1173 use_staging_texture = TRUE;
1174 } else if (!(usage & PIPE_TRANSFER_READ) &&
1175 (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf, RADEON_USAGE_READWRITE) ||
1176 !rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) {
1177 /* Use a staging texture for uploads if the underlying BO is busy. */
1178 use_staging_texture = TRUE;
1179 }
1180
1181 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
1182 use_staging_texture = FALSE;
1183 }
1184
1185 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
1186 return NULL;
1187 }
1188
1189 trans = CALLOC_STRUCT(r600_transfer);
1190 if (!trans)
1191 return NULL;
1192 trans->transfer.resource = texture;
1193 trans->transfer.level = level;
1194 trans->transfer.usage = usage;
1195 trans->transfer.box = *box;
1196
1197 if (rtex->is_depth) {
1198 struct r600_texture *staging_depth;
1199
1200 if (rtex->resource.b.b.nr_samples > 1) {
1201 /* MSAA depth buffers need to be converted to single sample buffers.
1202 *
1203 * Mapping MSAA depth buffers can occur if ReadPixels is called
1204 * with a multisample GLX visual.
1205 *
1206 * First downsample the depth buffer to a temporary texture,
1207 * then decompress the temporary one to staging.
1208 *
1209 * Only the region being mapped is transfered.
1210 */
1211 struct pipe_resource resource;
1212
1213 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1214
1215 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1216 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1217 FREE(trans);
1218 return NULL;
1219 }
1220
1221 if (usage & PIPE_TRANSFER_READ) {
1222 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1223 if (!temp) {
1224 R600_ERR("failed to create a temporary depth texture\n");
1225 FREE(trans);
1226 return NULL;
1227 }
1228
1229 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1230 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1231 0, 0, 0, box->depth, 0, 0);
1232 pipe_resource_reference(&temp, NULL);
1233 }
1234 }
1235 else {
1236 /* XXX: only readback the rectangle which is being mapped? */
1237 /* XXX: when discard is true, no need to read back from depth texture */
1238 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1239 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1240 FREE(trans);
1241 return NULL;
1242 }
1243
1244 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1245 level, level,
1246 box->z, box->z + box->depth - 1,
1247 0, 0);
1248
1249 offset = r600_texture_get_offset(staging_depth, level, box);
1250 }
1251
1252 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
1253 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1254 trans->staging = (struct r600_resource*)staging_depth;
1255 } else if (use_staging_texture) {
1256 struct pipe_resource resource;
1257 struct r600_texture *staging;
1258
1259 r600_init_temp_resource_from_box(&resource, texture, box, level,
1260 R600_RESOURCE_FLAG_TRANSFER);
1261 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1262 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1263
1264 /* Create the temporary texture. */
1265 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1266 if (!staging) {
1267 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1268 FREE(trans);
1269 return NULL;
1270 }
1271 trans->staging = &staging->resource;
1272 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1273 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1274 if (usage & PIPE_TRANSFER_READ) {
1275 r600_copy_to_staging_texture(ctx, trans);
1276 }
1277 } else {
1278 /* the resource is mapped directly */
1279 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1280 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1281 offset = r600_texture_get_offset(rtex, level, box);
1282 }
1283
1284 if (trans->staging) {
1285 buf = trans->staging;
1286 if (!rtex->is_depth && !(usage & PIPE_TRANSFER_READ))
1287 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1288 } else {
1289 buf = &rtex->resource;
1290 }
1291
1292 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1293 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1294 FREE(trans);
1295 return NULL;
1296 }
1297
1298 *ptransfer = &trans->transfer;
1299 return map + offset;
1300 }
1301
1302 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1303 struct pipe_transfer* transfer)
1304 {
1305 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1306 struct pipe_resource *texture = transfer->resource;
1307 struct r600_texture *rtex = (struct r600_texture*)texture;
1308
1309 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1310 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1311 ctx->resource_copy_region(ctx, texture, transfer->level,
1312 transfer->box.x, transfer->box.y, transfer->box.z,
1313 &rtransfer->staging->b.b, transfer->level,
1314 &transfer->box);
1315 } else {
1316 r600_copy_from_staging_texture(ctx, rtransfer);
1317 }
1318 }
1319
1320 if (rtransfer->staging)
1321 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1322
1323 FREE(transfer);
1324 }
1325
1326 static const struct u_resource_vtbl r600_texture_vtbl =
1327 {
1328 NULL, /* get_handle */
1329 r600_texture_destroy, /* resource_destroy */
1330 r600_texture_transfer_map, /* transfer_map */
1331 u_default_transfer_flush_region, /* transfer_flush_region */
1332 r600_texture_transfer_unmap, /* transfer_unmap */
1333 NULL /* transfer_inline_write */
1334 };
1335
1336 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1337 struct pipe_resource *texture,
1338 const struct pipe_surface *templ,
1339 unsigned width, unsigned height)
1340 {
1341 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1342
1343 if (!surface)
1344 return NULL;
1345
1346 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1347 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1348
1349 pipe_reference_init(&surface->base.reference, 1);
1350 pipe_resource_reference(&surface->base.texture, texture);
1351 surface->base.context = pipe;
1352 surface->base.format = templ->format;
1353 surface->base.width = width;
1354 surface->base.height = height;
1355 surface->base.u = templ->u;
1356 return &surface->base;
1357 }
1358
1359 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1360 struct pipe_resource *tex,
1361 const struct pipe_surface *templ)
1362 {
1363 unsigned level = templ->u.tex.level;
1364 unsigned width = u_minify(tex->width0, level);
1365 unsigned height = u_minify(tex->height0, level);
1366
1367 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1368 const struct util_format_description *tex_desc
1369 = util_format_description(tex->format);
1370 const struct util_format_description *templ_desc
1371 = util_format_description(templ->format);
1372
1373 assert(tex_desc->block.bits == templ_desc->block.bits);
1374
1375 /* Adjust size of surface if and only if the block width or
1376 * height is changed. */
1377 if (tex_desc->block.width != templ_desc->block.width ||
1378 tex_desc->block.height != templ_desc->block.height) {
1379 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1380 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1381
1382 width = nblks_x * templ_desc->block.width;
1383 height = nblks_y * templ_desc->block.height;
1384 }
1385 }
1386
1387 return r600_create_surface_custom(pipe, tex, templ, width, height);
1388 }
1389
1390 static void r600_surface_destroy(struct pipe_context *pipe,
1391 struct pipe_surface *surface)
1392 {
1393 struct r600_surface *surf = (struct r600_surface*)surface;
1394 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1395 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1396 pipe_resource_reference(&surface->texture, NULL);
1397 FREE(surface);
1398 }
1399
1400 unsigned r600_translate_colorswap(enum pipe_format format)
1401 {
1402 const struct util_format_description *desc = util_format_description(format);
1403
1404 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1405
1406 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1407 return V_0280A0_SWAP_STD;
1408
1409 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1410 return ~0U;
1411
1412 switch (desc->nr_channels) {
1413 case 1:
1414 if (HAS_SWIZZLE(0,X))
1415 return V_0280A0_SWAP_STD; /* X___ */
1416 else if (HAS_SWIZZLE(3,X))
1417 return V_0280A0_SWAP_ALT_REV; /* ___X */
1418 break;
1419 case 2:
1420 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1421 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1422 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1423 return V_0280A0_SWAP_STD; /* XY__ */
1424 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1425 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1426 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1427 return V_0280A0_SWAP_STD_REV; /* YX__ */
1428 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1429 return V_0280A0_SWAP_ALT; /* X__Y */
1430 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1431 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1432 break;
1433 case 3:
1434 if (HAS_SWIZZLE(0,X))
1435 return V_0280A0_SWAP_STD; /* XYZ */
1436 else if (HAS_SWIZZLE(0,Z))
1437 return V_0280A0_SWAP_STD_REV; /* ZYX */
1438 break;
1439 case 4:
1440 /* check the middle channels, the 1st and 4th channel can be NONE */
1441 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
1442 return V_0280A0_SWAP_STD; /* XYZW */
1443 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
1444 return V_0280A0_SWAP_STD_REV; /* WZYX */
1445 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
1446 return V_0280A0_SWAP_ALT; /* ZYXW */
1447 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W))
1448 return V_0280A0_SWAP_ALT_REV; /* YZWX */
1449 break;
1450 }
1451 return ~0U;
1452 }
1453
1454 static void evergreen_set_clear_color(struct r600_texture *rtex,
1455 enum pipe_format surface_format,
1456 const union pipe_color_union *color)
1457 {
1458 union util_color uc;
1459
1460 memset(&uc, 0, sizeof(uc));
1461
1462 if (util_format_is_pure_uint(surface_format)) {
1463 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1464 } else if (util_format_is_pure_sint(surface_format)) {
1465 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1466 } else {
1467 util_pack_color(color->f, surface_format, &uc);
1468 }
1469
1470 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1471 }
1472
1473 static void vi_get_fast_clear_parameters(enum pipe_format surface_format,
1474 const union pipe_color_union *color,
1475 uint32_t* reset_value,
1476 bool* clear_words_needed)
1477 {
1478 bool values[4] = {};
1479 int i;
1480 bool main_value = false;
1481 bool extra_value = false;
1482 int extra_channel;
1483 const struct util_format_description *desc = util_format_description(surface_format);
1484
1485 *clear_words_needed = true;
1486 *reset_value = 0x20202020U;
1487
1488 /* If we want to clear without needing a fast clear eliminate step, we
1489 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1490 * have two sets of flags, one for the last or first channel(extra) and
1491 * one for the other channels(main).
1492 */
1493
1494 if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
1495 surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
1496 surface_format == PIPE_FORMAT_B5G6R5_SRGB) {
1497 extra_channel = -1;
1498 } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
1499 if(r600_translate_colorswap(surface_format) <= 1)
1500 extra_channel = desc->nr_channels - 1;
1501 else
1502 extra_channel = 0;
1503 } else
1504 return;
1505
1506 for (i = 0; i < 4; ++i) {
1507 int index = desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X;
1508
1509 if (desc->swizzle[i] < UTIL_FORMAT_SWIZZLE_X ||
1510 desc->swizzle[i] > UTIL_FORMAT_SWIZZLE_W)
1511 continue;
1512
1513 if (util_format_is_pure_sint(surface_format)) {
1514 values[i] = color->i[i] != 0;
1515 if (color->i[i] != 0 && color->i[i] != INT32_MAX)
1516 return;
1517 } else if (util_format_is_pure_uint(surface_format)) {
1518 values[i] = color->ui[i] != 0U;
1519 if (color->ui[i] != 0U && color->ui[i] != UINT32_MAX)
1520 return;
1521 } else {
1522 values[i] = color->f[i] != 0.0F;
1523 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
1524 return;
1525 }
1526
1527 if (index == extra_channel)
1528 extra_value = values[i];
1529 else
1530 main_value = values[i];
1531 }
1532
1533 for (int i = 0; i < 4; ++i)
1534 if (values[i] != main_value &&
1535 desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X != extra_channel &&
1536 desc->swizzle[i] >= UTIL_FORMAT_SWIZZLE_X &&
1537 desc->swizzle[i] <= UTIL_FORMAT_SWIZZLE_W)
1538 return;
1539
1540 *clear_words_needed = false;
1541 if (main_value)
1542 *reset_value |= 0x80808080U;
1543
1544 if (extra_value)
1545 *reset_value |= 0x40404040U;
1546 }
1547
1548 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1549 struct pipe_framebuffer_state *fb,
1550 struct r600_atom *fb_state,
1551 unsigned *buffers, unsigned *dirty_cbufs,
1552 const union pipe_color_union *color)
1553 {
1554 int i;
1555
1556 /* This function is broken in BE, so just disable this path for now */
1557 #ifdef PIPE_ARCH_BIG_ENDIAN
1558 return;
1559 #endif
1560
1561 if (rctx->render_cond)
1562 return;
1563
1564 for (i = 0; i < fb->nr_cbufs; i++) {
1565 struct r600_texture *tex;
1566 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1567
1568 if (!fb->cbufs[i])
1569 continue;
1570
1571 /* if this colorbuffer is not being cleared */
1572 if (!(*buffers & clear_bit))
1573 continue;
1574
1575 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1576
1577 /* 128-bit formats are unusupported */
1578 if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
1579 continue;
1580 }
1581
1582 /* the clear is allowed if all layers are bound */
1583 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1584 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1585 continue;
1586 }
1587
1588 /* cannot clear mipmapped textures */
1589 if (fb->cbufs[i]->texture->last_level != 0) {
1590 continue;
1591 }
1592
1593 /* only supported on tiled surfaces */
1594 if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
1595 continue;
1596 }
1597
1598 /* shared textures can't use fast clear without an explicit flush,
1599 * because there is no way to communicate the clear color among
1600 * all clients
1601 */
1602 if (tex->resource.is_shared &&
1603 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
1604 continue;
1605
1606 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1607 if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
1608 rctx->chip_class >= CIK &&
1609 rctx->screen->info.drm_major == 2 &&
1610 rctx->screen->info.drm_minor < 38) {
1611 continue;
1612 }
1613
1614 if (tex->dcc_offset) {
1615 uint32_t reset_value;
1616 bool clear_words_needed;
1617
1618 if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
1619 continue;
1620
1621 vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed);
1622
1623 rctx->clear_buffer(&rctx->b, &tex->resource.b.b,
1624 tex->dcc_offset, tex->surface.dcc_size,
1625 reset_value, true);
1626
1627 if (clear_words_needed)
1628 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1629 } else {
1630 /* Stoney/RB+ doesn't work with CMASK fast clear. */
1631 if (rctx->family == CHIP_STONEY)
1632 continue;
1633
1634 /* ensure CMASK is enabled */
1635 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1636 if (tex->cmask.size == 0) {
1637 continue;
1638 }
1639
1640 /* Do the fast clear. */
1641 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1642 tex->cmask.offset, tex->cmask.size, 0, true);
1643
1644 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1645 }
1646
1647 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1648
1649 if (dirty_cbufs)
1650 *dirty_cbufs |= 1 << i;
1651 rctx->set_atom_dirty(rctx, fb_state, true);
1652 *buffers &= ~clear_bit;
1653 }
1654 }
1655
1656 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1657 {
1658 rscreen->b.resource_from_handle = r600_texture_from_handle;
1659 rscreen->b.resource_get_handle = r600_texture_get_handle;
1660 }
1661
1662 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1663 {
1664 rctx->b.create_surface = r600_create_surface;
1665 rctx->b.surface_destroy = r600_surface_destroy;
1666 }