2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
41 const struct pipe_resource
*templ
);
44 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
45 struct r600_texture
*rdst
,
46 unsigned dst_level
, unsigned dstx
,
47 unsigned dsty
, unsigned dstz
,
48 struct r600_texture
*rsrc
,
50 const struct pipe_box
*src_box
)
55 if (util_format_get_blocksizebits(rdst
->resource
.b
.b
.format
) !=
56 util_format_get_blocksizebits(rsrc
->resource
.b
.b
.format
))
59 /* MSAA: Blits don't exist in the real world. */
60 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
61 rdst
->resource
.b
.b
.nr_samples
> 1)
64 /* Depth-stencil surfaces:
65 * When dst is linear, the DB->CB copy preserves HTILE.
66 * When dst is tiled, the 3D path must be used to update HTILE.
68 if (rsrc
->is_depth
|| rdst
->is_depth
)
72 * src: Use the 3D path. DCC decompression is expensive.
73 * dst: Use the 3D path to compress the pixels with DCC.
75 if ((rsrc
->dcc_offset
&& rsrc
->surface
.level
[src_level
].dcc_enabled
) ||
76 (rdst
->dcc_offset
&& rdst
->surface
.level
[dst_level
].dcc_enabled
))
80 * src: Both texture and SDMA paths need decompression. Use SDMA.
81 * dst: If overwriting the whole texture, discard CMASK and use
82 * SDMA. Otherwise, use the 3D path.
84 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
85 /* The CMASK clear is only enabled for the first level. */
86 assert(dst_level
== 0);
87 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
88 dstx
, dsty
, dstz
, src_box
->width
,
89 src_box
->height
, src_box
->depth
))
92 r600_texture_discard_cmask(rctx
->screen
, rdst
);
95 /* All requirements are met. Prepare textures for SDMA. */
96 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
97 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
99 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
100 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
105 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
106 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
107 struct pipe_resource
*dst
,
109 unsigned dstx
, unsigned dsty
, unsigned dstz
,
110 struct pipe_resource
*src
,
112 const struct pipe_box
*src_box
)
114 struct pipe_blit_info blit
;
116 memset(&blit
, 0, sizeof(blit
));
117 blit
.src
.resource
= src
;
118 blit
.src
.format
= src
->format
;
119 blit
.src
.level
= src_level
;
120 blit
.src
.box
= *src_box
;
121 blit
.dst
.resource
= dst
;
122 blit
.dst
.format
= dst
->format
;
123 blit
.dst
.level
= dst_level
;
124 blit
.dst
.box
.x
= dstx
;
125 blit
.dst
.box
.y
= dsty
;
126 blit
.dst
.box
.z
= dstz
;
127 blit
.dst
.box
.width
= src_box
->width
;
128 blit
.dst
.box
.height
= src_box
->height
;
129 blit
.dst
.box
.depth
= src_box
->depth
;
130 blit
.mask
= util_format_get_mask(src
->format
) &
131 util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
142 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
144 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1) {
148 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
160 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1) {
169 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
176 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
180 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
181 const struct pipe_box
*box
)
183 enum pipe_format format
= rtex
->resource
.b
.b
.format
;
185 return rtex
->surface
.level
[level
].offset
+
186 box
->z
* rtex
->surface
.level
[level
].slice_size
+
187 box
->y
/ util_format_get_blockheight(format
) * rtex
->surface
.level
[level
].pitch_bytes
+
188 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
191 static int r600_init_surface(struct r600_common_screen
*rscreen
,
192 struct radeon_surf
*surface
,
193 const struct pipe_resource
*ptex
,
195 bool is_flushed_depth
)
197 const struct util_format_description
*desc
=
198 util_format_description(ptex
->format
);
199 bool is_depth
, is_stencil
;
201 is_depth
= util_format_has_depth(desc
);
202 is_stencil
= util_format_has_stencil(desc
);
204 surface
->npix_x
= ptex
->width0
;
205 surface
->npix_y
= ptex
->height0
;
206 surface
->npix_z
= ptex
->depth0
;
207 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
208 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
210 surface
->array_size
= 1;
211 surface
->last_level
= ptex
->last_level
;
213 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
214 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
215 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
217 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
218 /* align byte per element on dword */
219 if (surface
->bpe
== 3) {
224 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
225 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
227 switch (ptex
->target
) {
228 case PIPE_TEXTURE_1D
:
229 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
231 case PIPE_TEXTURE_RECT
:
232 case PIPE_TEXTURE_2D
:
233 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
235 case PIPE_TEXTURE_3D
:
236 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
238 case PIPE_TEXTURE_1D_ARRAY
:
239 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
240 surface
->array_size
= ptex
->array_size
;
242 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d array */
243 assert(ptex
->array_size
% 6 == 0);
244 case PIPE_TEXTURE_2D_ARRAY
:
245 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
246 surface
->array_size
= ptex
->array_size
;
248 case PIPE_TEXTURE_CUBE
:
249 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
256 if (!is_flushed_depth
&& is_depth
) {
257 surface
->flags
|= RADEON_SURF_ZBUFFER
;
260 surface
->flags
|= RADEON_SURF_SBUFFER
|
261 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
264 if (rscreen
->chip_class
>= SI
) {
265 surface
->flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
268 if (rscreen
->chip_class
>= VI
&&
269 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
270 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
271 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
273 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
274 /* This should catch bugs in gallium users setting incorrect flags. */
275 assert(surface
->nsamples
== 1 &&
276 surface
->array_size
== 1 &&
277 surface
->npix_z
== 1 &&
278 surface
->last_level
== 0 &&
279 !(surface
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
281 surface
->flags
|= RADEON_SURF_SCANOUT
;
286 static int r600_setup_surface(struct pipe_screen
*screen
,
287 struct r600_texture
*rtex
,
288 unsigned pitch_in_bytes_override
,
291 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
295 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
300 rtex
->size
= rtex
->surface
.bo_size
;
302 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
303 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
306 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
307 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
308 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
312 for (i
= 0; i
< ARRAY_SIZE(rtex
->surface
.level
); ++i
)
313 rtex
->surface
.level
[i
].offset
+= offset
;
318 static void r600_texture_init_metadata(struct r600_texture
*rtex
,
319 struct radeon_bo_metadata
*metadata
)
321 struct radeon_surf
*surface
= &rtex
->surface
;
323 memset(metadata
, 0, sizeof(*metadata
));
324 metadata
->microtile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
325 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
326 metadata
->macrotile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
327 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
328 metadata
->pipe_config
= surface
->pipe_config
;
329 metadata
->bankw
= surface
->bankw
;
330 metadata
->bankh
= surface
->bankh
;
331 metadata
->tile_split
= surface
->tile_split
;
332 metadata
->mtilea
= surface
->mtilea
;
333 metadata
->num_banks
= surface
->num_banks
;
334 metadata
->stride
= surface
->level
[0].pitch_bytes
;
335 metadata
->scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
338 static void r600_dirty_all_framebuffer_states(struct r600_common_screen
*rscreen
)
340 p_atomic_inc(&rscreen
->dirty_fb_counter
);
343 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
344 struct r600_texture
*rtex
)
346 struct r600_common_screen
*rscreen
= rctx
->screen
;
347 struct pipe_context
*ctx
= &rctx
->b
;
349 if (ctx
== rscreen
->aux_context
)
350 pipe_mutex_lock(rscreen
->aux_context_lock
);
352 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
353 ctx
->flush(ctx
, NULL
, 0);
355 if (ctx
== rscreen
->aux_context
)
356 pipe_mutex_unlock(rscreen
->aux_context_lock
);
359 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
360 struct r600_texture
*rtex
)
362 if (!rtex
->cmask
.size
)
365 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
368 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
369 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
370 rtex
->dirty_level_mask
= 0;
372 if (rscreen
->chip_class
>= SI
)
373 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
375 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
377 if (rtex
->cmask_buffer
!= &rtex
->resource
)
378 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
380 /* Notify all contexts about the change. */
381 r600_dirty_all_framebuffer_states(rscreen
);
382 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
385 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
387 /* We can't disable DCC if it can be written by another process. */
388 return rtex
->dcc_offset
&&
389 (!rtex
->resource
.is_shared
||
390 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
393 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
394 struct r600_texture
*rtex
)
396 if (!r600_can_disable_dcc(rtex
))
399 assert(rtex
->dcc_separate_buffer
== NULL
);
402 rtex
->dcc_offset
= 0;
404 /* Notify all contexts about the change. */
405 r600_dirty_all_framebuffer_states(rscreen
);
410 * Disable DCC for the texture. (first decompress, then discard metadata).
412 * There is unresolved multi-context synchronization issue between
413 * screen::aux_context and the current context. If applications do this with
414 * multiple contexts, it's already undefined behavior for them and we don't
415 * have to worry about that. The scenario is:
417 * If context 1 disables DCC and context 2 has queued commands that write
418 * to the texture via CB with DCC enabled, and the order of operations is
420 * context 2 queues draw calls rendering to the texture, but doesn't flush
421 * context 1 disables DCC and flushes
422 * context 1 & 2 reset descriptors and FB state
423 * context 2 flushes (new compressed tiles written by the draw calls)
424 * context 1 & 2 read garbage, because DCC is disabled, yet there are
427 * \param rctx the current context if you have one, or rscreen->aux_context
430 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
431 struct r600_texture
*rtex
)
433 struct r600_common_screen
*rscreen
= rctx
->screen
;
435 if (!r600_can_disable_dcc(rtex
))
438 if (&rctx
->b
== rscreen
->aux_context
)
439 pipe_mutex_lock(rscreen
->aux_context_lock
);
441 /* Decompress DCC. */
442 rctx
->decompress_dcc(&rctx
->b
, rtex
);
443 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
445 if (&rctx
->b
== rscreen
->aux_context
)
446 pipe_mutex_unlock(rscreen
->aux_context_lock
);
448 return r600_texture_discard_dcc(rscreen
, rtex
);
451 static void r600_degrade_tile_mode_to_linear(struct r600_common_context
*rctx
,
452 struct r600_texture
*rtex
,
453 bool invalidate_storage
)
455 struct pipe_screen
*screen
= rctx
->b
.screen
;
456 struct r600_texture
*new_tex
;
457 struct pipe_resource templ
= rtex
->resource
.b
.b
;
460 templ
.bind
|= PIPE_BIND_LINEAR
;
462 /* r600g doesn't react to dirty_tex_descriptor_counter */
463 if (rctx
->chip_class
< SI
)
466 if (rtex
->resource
.is_shared
||
467 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
)
470 /* This fails with MSAA, depth, and compressed textures. */
471 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
472 RADEON_SURF_MODE_LINEAR_ALIGNED
)
475 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
479 /* Copy the pixels to the new texture. */
480 if (!invalidate_storage
) {
481 for (i
= 0; i
<= templ
.last_level
; i
++) {
485 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
486 util_max_layer(&templ
, i
) + 1, &box
);
488 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
489 &rtex
->resource
.b
.b
, i
, &box
);
493 r600_texture_discard_cmask(rctx
->screen
, rtex
);
494 r600_texture_discard_dcc(rctx
->screen
, rtex
);
496 /* Replace the structure fields of rtex. */
497 rtex
->resource
.b
.b
.bind
= templ
.bind
;
498 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
499 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
500 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
501 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
502 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
503 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
504 rtex
->resource
.domains
= new_tex
->resource
.domains
;
505 rtex
->resource
.flags
= new_tex
->resource
.flags
;
506 rtex
->size
= new_tex
->size
;
507 rtex
->surface
= new_tex
->surface
;
508 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
509 rtex
->cb_color_info
= new_tex
->cb_color_info
;
510 rtex
->cmask
= new_tex
->cmask
; /* needed even without CMASK */
512 assert(!rtex
->htile_buffer
);
513 assert(!rtex
->cmask
.size
);
514 assert(!rtex
->fmask
.size
);
515 assert(!rtex
->dcc_offset
);
516 assert(!rtex
->is_depth
);
518 r600_texture_reference(&new_tex
, NULL
);
520 r600_dirty_all_framebuffer_states(rctx
->screen
);
521 p_atomic_inc(&rctx
->screen
->dirty_tex_descriptor_counter
);
524 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
525 struct pipe_context
*ctx
,
526 struct pipe_resource
*resource
,
527 struct winsys_handle
*whandle
,
530 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
531 struct r600_common_context
*rctx
= (struct r600_common_context
*)
532 (ctx
? ctx
: rscreen
->aux_context
);
533 struct r600_resource
*res
= (struct r600_resource
*)resource
;
534 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
535 struct radeon_bo_metadata metadata
;
536 bool update_metadata
= false;
538 /* This is not supported now, but it might be required for OpenCL
539 * interop in the future.
541 if (resource
->target
!= PIPE_BUFFER
&&
542 (resource
->nr_samples
> 1 || rtex
->is_depth
))
545 if (resource
->target
!= PIPE_BUFFER
) {
546 /* Since shader image stores don't support DCC on VI,
547 * disable it for external clients that want write
550 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
551 if (r600_texture_disable_dcc(rctx
, rtex
))
552 update_metadata
= true;
555 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
556 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
557 /* Eliminate fast clear (both CMASK and DCC) */
558 r600_eliminate_fast_color_clear(rctx
, rtex
);
560 /* Disable CMASK if flush_resource isn't going
563 if (rtex
->cmask
.size
)
564 r600_texture_discard_cmask(rscreen
, rtex
);
568 if (!res
->is_shared
|| update_metadata
) {
569 r600_texture_init_metadata(rtex
, &metadata
);
570 if (rscreen
->query_opaque_metadata
)
571 rscreen
->query_opaque_metadata(rscreen
, rtex
,
574 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
578 if (res
->is_shared
) {
579 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
582 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
583 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
584 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
586 res
->is_shared
= true;
587 res
->external_usage
= usage
;
590 return rscreen
->ws
->buffer_get_handle(res
->buf
,
591 rtex
->surface
.level
[0].pitch_bytes
,
592 rtex
->surface
.level
[0].offset
,
593 rtex
->surface
.level
[0].slice_size
,
597 static void r600_texture_destroy(struct pipe_screen
*screen
,
598 struct pipe_resource
*ptex
)
600 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
601 struct r600_resource
*resource
= &rtex
->resource
;
603 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
605 r600_resource_reference(&rtex
->htile_buffer
, NULL
);
606 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
607 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
609 pb_reference(&resource
->buf
, NULL
);
610 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
611 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
615 static const struct u_resource_vtbl r600_texture_vtbl
;
617 /* The number of samples can be specified independently of the texture. */
618 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
619 struct r600_texture
*rtex
,
621 struct r600_fmask_info
*out
)
623 /* FMASK is allocated like an ordinary texture. */
624 struct radeon_surf fmask
= rtex
->surface
;
626 memset(out
, 0, sizeof(*out
));
628 fmask
.bo_alignment
= 0;
631 fmask
.flags
|= RADEON_SURF_FMASK
;
633 /* Force 2D tiling if it wasn't set. This may occur when creating
634 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
635 * destination buffer must have an FMASK too. */
636 fmask
.flags
= RADEON_SURF_CLR(fmask
.flags
, MODE
);
637 fmask
.flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
639 if (rscreen
->chip_class
>= SI
) {
640 fmask
.flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
643 switch (nr_samples
) {
647 if (rscreen
->chip_class
<= CAYMAN
) {
655 R600_ERR("Invalid sample count for FMASK allocation.\n");
659 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
660 * This can be fixed by writing a separate FMASK allocator specifically
661 * for R600-R700 asics. */
662 if (rscreen
->chip_class
<= R700
) {
666 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
667 R600_ERR("Got error in surface_init while allocating FMASK.\n");
671 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
673 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
674 if (out
->slice_tile_max
)
675 out
->slice_tile_max
-= 1;
677 out
->tile_mode_index
= fmask
.tiling_index
[0];
678 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
679 out
->bank_height
= fmask
.bankh
;
680 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
681 out
->size
= fmask
.bo_size
;
684 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
685 struct r600_texture
*rtex
)
687 r600_texture_get_fmask_info(rscreen
, rtex
,
688 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
690 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
691 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
694 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
695 struct r600_texture
*rtex
,
696 struct r600_cmask_info
*out
)
698 unsigned cmask_tile_width
= 8;
699 unsigned cmask_tile_height
= 8;
700 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
701 unsigned element_bits
= 4;
702 unsigned cmask_cache_bits
= 1024;
703 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
704 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
706 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
707 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
708 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
709 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
710 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
712 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
713 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
715 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
716 unsigned slice_bytes
=
717 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
719 assert(macro_tile_width
% 128 == 0);
720 assert(macro_tile_height
% 128 == 0);
722 out
->pitch
= pitch_elements
;
723 out
->height
= height
;
724 out
->xalign
= macro_tile_width
;
725 out
->yalign
= macro_tile_height
;
726 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
727 out
->alignment
= MAX2(256, base_align
);
728 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
729 align(slice_bytes
, base_align
);
732 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
733 struct r600_texture
*rtex
,
734 struct r600_cmask_info
*out
)
736 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
737 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
738 unsigned cl_width
, cl_height
;
753 case 16: /* Hawaii */
762 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
764 unsigned width
= align(rtex
->surface
.npix_x
, cl_width
*8);
765 unsigned height
= align(rtex
->surface
.npix_y
, cl_height
*8);
766 unsigned slice_elements
= (width
* height
) / (8*8);
768 /* Each element of CMASK is a nibble. */
769 unsigned slice_bytes
= slice_elements
/ 2;
772 out
->height
= height
;
773 out
->xalign
= cl_width
* 8;
774 out
->yalign
= cl_height
* 8;
775 out
->slice_tile_max
= (width
* height
) / (128*128);
776 if (out
->slice_tile_max
)
777 out
->slice_tile_max
-= 1;
779 out
->alignment
= MAX2(256, base_align
);
780 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
781 align(slice_bytes
, base_align
);
784 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
785 struct r600_texture
*rtex
)
787 if (rscreen
->chip_class
>= SI
) {
788 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
790 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
793 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
794 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
796 if (rscreen
->chip_class
>= SI
)
797 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
799 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
802 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
803 struct r600_texture
*rtex
)
805 if (rtex
->cmask_buffer
)
808 assert(rtex
->cmask
.size
== 0);
810 if (rscreen
->chip_class
>= SI
) {
811 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
813 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
816 rtex
->cmask_buffer
= (struct r600_resource
*)
817 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
818 PIPE_USAGE_DEFAULT
, rtex
->cmask
.size
);
819 if (rtex
->cmask_buffer
== NULL
) {
820 rtex
->cmask
.size
= 0;
824 /* update colorbuffer state bits */
825 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
827 if (rscreen
->chip_class
>= SI
)
828 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
830 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
832 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
835 static unsigned r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
836 struct r600_texture
*rtex
)
838 unsigned cl_width
, cl_height
, width
, height
;
839 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
840 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
842 if (rscreen
->chip_class
<= EVERGREEN
&&
843 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
846 /* HW bug on R6xx. */
847 if (rscreen
->chip_class
== R600
&&
848 (rtex
->surface
.level
[0].npix_x
> 7680 ||
849 rtex
->surface
.level
[0].npix_y
> 7680))
852 /* HTILE is broken with 1D tiling on old kernels and CIK. */
853 if (rscreen
->chip_class
>= CIK
&&
854 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
855 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
858 /* Overalign HTILE on P2 configs to work around GPU hangs in
859 * piglit/depthstencil-render-miplevels 585.
861 * This has been confirmed to help Kabini & Stoney, where the hangs
862 * are always reproducible. I think I have seen the test hang
863 * on Carrizo too, though it was very rare there.
865 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
894 width
= align(rtex
->surface
.npix_x
, cl_width
* 8);
895 height
= align(rtex
->surface
.npix_y
, cl_height
* 8);
897 slice_elements
= (width
* height
) / (8 * 8);
898 slice_bytes
= slice_elements
* 4;
900 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
901 base_align
= num_pipes
* pipe_interleave_bytes
;
903 rtex
->htile
.pitch
= width
;
904 rtex
->htile
.height
= height
;
905 rtex
->htile
.xalign
= cl_width
* 8;
906 rtex
->htile
.yalign
= cl_height
* 8;
908 return (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
909 align(slice_bytes
, base_align
);
912 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
913 struct r600_texture
*rtex
)
915 unsigned htile_size
= r600_texture_get_htile_size(rscreen
, rtex
);
920 rtex
->htile_buffer
= (struct r600_resource
*)
921 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
922 PIPE_USAGE_DEFAULT
, htile_size
);
923 if (rtex
->htile_buffer
== NULL
) {
924 /* this is not a fatal error as we can still keep rendering
925 * without htile buffer */
926 R600_ERR("Failed to create buffer object for htile buffer.\n");
928 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
, 0,
929 htile_size
, 0, R600_COHERENCY_NONE
);
933 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
)
937 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
938 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
939 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
940 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
941 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
942 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
943 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
944 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
945 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
947 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%"PRIu64
", bankw=%u, "
948 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
949 rtex
->surface
.bo_size
, rtex
->surface
.bo_alignment
, rtex
->surface
.bankw
,
950 rtex
->surface
.bankh
, rtex
->surface
.num_banks
, rtex
->surface
.mtilea
,
951 rtex
->surface
.tile_split
, rtex
->surface
.pipe_config
,
952 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
954 if (rtex
->fmask
.size
)
955 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
956 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
957 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
958 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
959 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
961 if (rtex
->cmask
.size
)
962 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch=%u, "
963 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
964 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
965 rtex
->cmask
.pitch
, rtex
->cmask
.height
, rtex
->cmask
.xalign
,
966 rtex
->cmask
.yalign
, rtex
->cmask
.slice_tile_max
);
968 if (rtex
->htile_buffer
)
969 fprintf(f
, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
970 "xalign=%u, yalign=%u\n",
971 rtex
->htile_buffer
->b
.b
.width0
,
972 rtex
->htile_buffer
->buf
->alignment
, rtex
->htile
.pitch
,
973 rtex
->htile
.height
, rtex
->htile
.xalign
, rtex
->htile
.yalign
);
975 if (rtex
->dcc_offset
) {
976 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%"PRIu64
"\n",
977 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
978 rtex
->surface
.dcc_alignment
);
979 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
980 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
981 "fast_clear_size=%"PRIu64
"\n",
982 i
, rtex
->surface
.level
[i
].dcc_enabled
,
983 rtex
->surface
.level
[i
].dcc_offset
,
984 rtex
->surface
.level
[i
].dcc_fast_clear_size
);
987 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
988 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
989 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
990 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
991 i
, rtex
->surface
.level
[i
].offset
,
992 rtex
->surface
.level
[i
].slice_size
,
993 u_minify(rtex
->resource
.b
.b
.width0
, i
),
994 u_minify(rtex
->resource
.b
.b
.height0
, i
),
995 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
996 rtex
->surface
.level
[i
].nblk_x
,
997 rtex
->surface
.level
[i
].nblk_y
,
998 rtex
->surface
.level
[i
].nblk_z
,
999 rtex
->surface
.level
[i
].pitch_bytes
,
1000 rtex
->surface
.level
[i
].mode
);
1002 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1003 fprintf(f
, " StencilLayout: tilesplit=%u\n",
1004 rtex
->surface
.stencil_tile_split
);
1005 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
1006 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
1007 "slice_size=%"PRIu64
", npix_x=%u, "
1008 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1009 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
1010 i
, rtex
->surface
.stencil_level
[i
].offset
,
1011 rtex
->surface
.stencil_level
[i
].slice_size
,
1012 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1013 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1014 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1015 rtex
->surface
.stencil_level
[i
].nblk_x
,
1016 rtex
->surface
.stencil_level
[i
].nblk_y
,
1017 rtex
->surface
.stencil_level
[i
].nblk_z
,
1018 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
1019 rtex
->surface
.stencil_level
[i
].mode
);
1024 /* Common processing for r600_texture_create and r600_texture_from_handle */
1025 static struct r600_texture
*
1026 r600_texture_create_object(struct pipe_screen
*screen
,
1027 const struct pipe_resource
*base
,
1028 unsigned pitch_in_bytes_override
,
1030 struct pb_buffer
*buf
,
1031 struct radeon_surf
*surface
)
1033 struct r600_texture
*rtex
;
1034 struct r600_resource
*resource
;
1035 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1037 rtex
= CALLOC_STRUCT(r600_texture
);
1041 resource
= &rtex
->resource
;
1042 resource
->b
.b
= *base
;
1043 resource
->b
.b
.next
= NULL
;
1044 resource
->b
.vtbl
= &r600_texture_vtbl
;
1045 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1046 resource
->b
.b
.screen
= screen
;
1048 /* don't include stencil-only formats which we don't support for rendering */
1049 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1051 rtex
->surface
= *surface
;
1052 if (r600_setup_surface(screen
, rtex
, pitch_in_bytes_override
, offset
)) {
1057 /* Tiled depth textures utilize the non-displayable tile order.
1058 * This must be done after r600_setup_surface.
1059 * Applies to R600-Cayman. */
1060 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1061 /* Applies to GCN. */
1062 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1064 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1065 * between frames, so the only thing that can enable separate DCC
1066 * with DRI2 is multiple slow clears within a frame.
1068 rtex
->ps_draw_ratio
= 0;
1070 if (rtex
->is_depth
) {
1071 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1072 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1073 rscreen
->chip_class
>= EVERGREEN
) {
1074 rtex
->can_sample_z
= !rtex
->surface
.depth_adjusted
;
1075 rtex
->can_sample_s
= !rtex
->surface
.stencil_adjusted
;
1077 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1078 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1079 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1080 rtex
->can_sample_z
= true;
1083 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1084 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1085 rtex
->db_compatible
= true;
1087 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1088 r600_texture_allocate_htile(rscreen
, rtex
);
1091 if (base
->nr_samples
> 1) {
1093 r600_texture_allocate_fmask(rscreen
, rtex
);
1094 r600_texture_allocate_cmask(rscreen
, rtex
);
1095 rtex
->cmask_buffer
= &rtex
->resource
;
1097 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1103 /* Shared textures must always set up DCC here.
1104 * If it's not present, it will be disabled by
1105 * apply_opaque_metadata later.
1107 if (rtex
->surface
.dcc_size
&&
1108 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1109 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1110 /* Reserve space for the DCC buffer. */
1111 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1112 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1116 /* Now create the backing buffer. */
1118 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
1119 rtex
->surface
.bo_alignment
);
1121 resource
->flags
|= RADEON_FLAG_HANDLE
;
1123 if (!r600_alloc_resource(rscreen
, resource
)) {
1128 resource
->buf
= buf
;
1129 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1130 resource
->bo_size
= buf
->size
;
1131 resource
->bo_alignment
= buf
->alignment
;
1132 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1133 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1134 resource
->vram_usage
= buf
->size
;
1135 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1136 resource
->gart_usage
= buf
->size
;
1139 if (rtex
->cmask
.size
) {
1140 /* Initialize the cmask to 0xCC (= compressed state). */
1141 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1142 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1143 0xCCCCCCCC, R600_COHERENCY_NONE
);
1146 /* Initialize DCC only if the texture is not being imported. */
1147 if (!buf
&& rtex
->dcc_offset
) {
1148 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1150 rtex
->surface
.dcc_size
,
1151 0xFFFFFFFF, R600_COHERENCY_NONE
);
1154 /* Initialize the CMASK base register value. */
1155 rtex
->cmask
.base_address_reg
=
1156 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1158 if (rscreen
->debug_flags
& DBG_VM
) {
1159 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1160 rtex
->resource
.gpu_address
,
1161 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1162 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1163 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1166 if (rscreen
->debug_flags
& DBG_TEX
) {
1168 r600_print_texture_info(rtex
, stdout
);
1175 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
1176 const struct pipe_resource
*templ
)
1178 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1179 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1181 /* MSAA resources must be 2D tiled. */
1182 if (templ
->nr_samples
> 1)
1183 return RADEON_SURF_MODE_2D
;
1185 /* Transfer resources should be linear. */
1186 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1187 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1189 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1190 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1191 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1192 (templ
->target
== PIPE_TEXTURE_2D
||
1193 templ
->target
== PIPE_TEXTURE_3D
))
1194 force_tiling
= true;
1196 /* Handle common candidates for the linear mode.
1197 * Compressed textures and DB surfaces must always be tiled.
1199 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
1200 (!util_format_is_depth_or_stencil(templ
->format
) ||
1201 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
1202 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1203 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1205 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1206 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1207 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1209 /* Cursors are linear on SI.
1210 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1211 if (rscreen
->chip_class
>= SI
&&
1212 (templ
->bind
& PIPE_BIND_CURSOR
))
1213 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1215 if (templ
->bind
& PIPE_BIND_LINEAR
)
1216 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1218 /* Textures with a very small height are recommended to be linear. */
1219 if (templ
->target
== PIPE_TEXTURE_1D
||
1220 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1221 templ
->height0
<= 4)
1222 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1224 /* Textures likely to be mapped often. */
1225 if (templ
->usage
== PIPE_USAGE_STAGING
||
1226 templ
->usage
== PIPE_USAGE_STREAM
)
1227 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1230 /* Make small textures 1D tiled. */
1231 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1232 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1233 return RADEON_SURF_MODE_1D
;
1235 /* The allocator will switch to 1D if needed. */
1236 return RADEON_SURF_MODE_2D
;
1239 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1240 const struct pipe_resource
*templ
)
1242 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1243 struct radeon_surf surface
= {0};
1246 r
= r600_init_surface(rscreen
, &surface
, templ
,
1247 r600_choose_tiling(rscreen
, templ
),
1248 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1252 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
1256 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, 0,
1260 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1261 const struct pipe_resource
*templ
,
1262 struct winsys_handle
*whandle
,
1265 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1266 struct pb_buffer
*buf
= NULL
;
1267 unsigned stride
= 0, offset
= 0;
1268 unsigned array_mode
;
1269 struct radeon_surf surface
;
1271 struct radeon_bo_metadata metadata
= {};
1272 struct r600_texture
*rtex
;
1274 /* Support only 2D textures without mipmaps */
1275 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1276 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1279 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1283 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1285 surface
.pipe_config
= metadata
.pipe_config
;
1286 surface
.bankw
= metadata
.bankw
;
1287 surface
.bankh
= metadata
.bankh
;
1288 surface
.tile_split
= metadata
.tile_split
;
1289 surface
.mtilea
= metadata
.mtilea
;
1290 surface
.num_banks
= metadata
.num_banks
;
1292 if (metadata
.macrotile
== RADEON_LAYOUT_TILED
)
1293 array_mode
= RADEON_SURF_MODE_2D
;
1294 else if (metadata
.microtile
== RADEON_LAYOUT_TILED
)
1295 array_mode
= RADEON_SURF_MODE_1D
;
1297 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1299 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, false);
1304 if (metadata
.scanout
)
1305 surface
.flags
|= RADEON_SURF_SCANOUT
;
1307 rtex
= r600_texture_create_object(screen
, templ
, stride
,
1308 offset
, buf
, &surface
);
1312 rtex
->resource
.is_shared
= true;
1313 rtex
->resource
.external_usage
= usage
;
1315 if (rscreen
->apply_opaque_metadata
)
1316 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1318 return &rtex
->resource
.b
.b
;
1321 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1322 struct pipe_resource
*texture
,
1323 struct r600_texture
**staging
)
1325 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1326 struct pipe_resource resource
;
1327 struct r600_texture
**flushed_depth_texture
= staging
?
1328 staging
: &rtex
->flushed_depth_texture
;
1329 enum pipe_format pipe_format
= texture
->format
;
1332 if (rtex
->flushed_depth_texture
)
1333 return true; /* it's ready */
1335 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1336 switch (pipe_format
) {
1337 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1338 /* Save memory by not allocating the S plane. */
1339 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1341 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1342 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1343 /* Save memory bandwidth by not copying the
1344 * stencil part during flush.
1346 * This potentially increases memory bandwidth
1347 * if an application uses both Z and S texturing
1348 * simultaneously (a flushed Z24S8 texture
1349 * would be stored compactly), but how often
1350 * does that really happen?
1352 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1356 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1357 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1359 /* DB->CB copies to an 8bpp surface don't work. */
1360 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1364 resource
.target
= texture
->target
;
1365 resource
.format
= pipe_format
;
1366 resource
.width0
= texture
->width0
;
1367 resource
.height0
= texture
->height0
;
1368 resource
.depth0
= texture
->depth0
;
1369 resource
.array_size
= texture
->array_size
;
1370 resource
.last_level
= texture
->last_level
;
1371 resource
.nr_samples
= texture
->nr_samples
;
1372 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1373 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1374 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1377 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1379 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1380 if (*flushed_depth_texture
== NULL
) {
1381 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1385 (*flushed_depth_texture
)->non_disp_tiling
= false;
1390 * Initialize the pipe_resource descriptor to be of the same size as the box,
1391 * which is supposed to hold a subregion of the texture "orig" at the given
1394 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1395 struct pipe_resource
*orig
,
1396 const struct pipe_box
*box
,
1397 unsigned level
, unsigned flags
)
1399 memset(res
, 0, sizeof(*res
));
1400 res
->format
= orig
->format
;
1401 res
->width0
= box
->width
;
1402 res
->height0
= box
->height
;
1404 res
->array_size
= 1;
1405 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1408 /* We must set the correct texture target and dimensions for a 3D box. */
1409 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1410 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1411 res
->array_size
= box
->depth
;
1413 res
->target
= PIPE_TEXTURE_2D
;
1417 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1418 struct r600_texture
*rtex
,
1419 unsigned transfer_usage
,
1420 const struct pipe_box
*box
)
1422 /* r600g doesn't react to dirty_tex_descriptor_counter */
1423 return rscreen
->chip_class
>= SI
&&
1424 !rtex
->resource
.is_shared
&&
1425 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1426 rtex
->resource
.b
.b
.last_level
== 0 &&
1427 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1428 box
->x
, box
->y
, box
->z
,
1429 box
->width
, box
->height
,
1433 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1434 struct r600_texture
*rtex
)
1436 struct r600_common_screen
*rscreen
= rctx
->screen
;
1438 /* There is no point in discarding depth and tiled buffers. */
1439 assert(!rtex
->is_depth
);
1440 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
);
1442 /* Reallocate the buffer in the same pipe_resource. */
1443 r600_alloc_resource(rscreen
, &rtex
->resource
);
1445 /* Initialize the CMASK base address (needed even without CMASK). */
1446 rtex
->cmask
.base_address_reg
=
1447 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1449 r600_dirty_all_framebuffer_states(rscreen
);
1450 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
1452 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1455 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1456 struct pipe_resource
*texture
,
1459 const struct pipe_box
*box
,
1460 struct pipe_transfer
**ptransfer
)
1462 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1463 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1464 struct r600_transfer
*trans
;
1465 struct r600_resource
*buf
;
1466 unsigned offset
= 0;
1468 bool use_staging_texture
= false;
1470 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1472 /* Depth textures use staging unconditionally. */
1473 if (!rtex
->is_depth
) {
1474 /* Degrade the tile mode if we get too many transfers on APUs.
1475 * On dGPUs, the staging texture is always faster.
1476 * Only count uploads that are at least 4x4 pixels large.
1478 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1480 box
->width
>= 4 && box
->height
>= 4 &&
1481 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1482 bool can_invalidate
=
1483 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1486 r600_degrade_tile_mode_to_linear(rctx
, rtex
,
1490 /* Tiled textures need to be converted into a linear texture for CPU
1491 * access. The staging texture is always linear and is placed in GART.
1493 * Reading from VRAM is slow, always use the staging texture in
1496 * Use the staging texture for uploads if the underlying BO
1499 if (rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
)
1500 use_staging_texture
= true;
1501 else if (usage
& PIPE_TRANSFER_READ
)
1502 use_staging_texture
= (rtex
->resource
.domains
&
1503 RADEON_DOMAIN_VRAM
) != 0;
1504 /* Write & linear only: */
1505 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1506 RADEON_USAGE_READWRITE
) ||
1507 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1508 RADEON_USAGE_READWRITE
)) {
1510 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1512 r600_texture_invalidate_storage(rctx
, rtex
);
1514 use_staging_texture
= true;
1518 trans
= CALLOC_STRUCT(r600_transfer
);
1521 trans
->transfer
.resource
= texture
;
1522 trans
->transfer
.level
= level
;
1523 trans
->transfer
.usage
= usage
;
1524 trans
->transfer
.box
= *box
;
1526 if (rtex
->is_depth
) {
1527 struct r600_texture
*staging_depth
;
1529 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1530 /* MSAA depth buffers need to be converted to single sample buffers.
1532 * Mapping MSAA depth buffers can occur if ReadPixels is called
1533 * with a multisample GLX visual.
1535 * First downsample the depth buffer to a temporary texture,
1536 * then decompress the temporary one to staging.
1538 * Only the region being mapped is transfered.
1540 struct pipe_resource resource
;
1542 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1544 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1545 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1550 if (usage
& PIPE_TRANSFER_READ
) {
1551 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1553 R600_ERR("failed to create a temporary depth texture\n");
1558 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1559 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1560 0, 0, 0, box
->depth
, 0, 0);
1561 pipe_resource_reference(&temp
, NULL
);
1565 /* XXX: only readback the rectangle which is being mapped? */
1566 /* XXX: when discard is true, no need to read back from depth texture */
1567 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1568 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1573 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1575 box
->z
, box
->z
+ box
->depth
- 1,
1578 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1581 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
1582 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
1583 trans
->staging
= (struct r600_resource
*)staging_depth
;
1584 buf
= trans
->staging
;
1585 } else if (use_staging_texture
) {
1586 struct pipe_resource resource
;
1587 struct r600_texture
*staging
;
1589 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1590 R600_RESOURCE_FLAG_TRANSFER
);
1591 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1592 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1594 /* Create the temporary texture. */
1595 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1597 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1601 trans
->staging
= &staging
->resource
;
1602 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
1603 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1605 if (usage
& PIPE_TRANSFER_READ
)
1606 r600_copy_to_staging_texture(ctx
, trans
);
1608 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1610 buf
= trans
->staging
;
1612 /* the resource is mapped directly */
1613 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
1614 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1615 offset
= r600_texture_get_offset(rtex
, level
, box
);
1616 buf
= &rtex
->resource
;
1619 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1620 r600_resource_reference(&trans
->staging
, NULL
);
1625 *ptransfer
= &trans
->transfer
;
1626 return map
+ offset
;
1629 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1630 struct pipe_transfer
* transfer
)
1632 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1633 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1634 struct pipe_resource
*texture
= transfer
->resource
;
1635 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1637 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1638 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1639 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1640 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1641 &rtransfer
->staging
->b
.b
, transfer
->level
,
1644 r600_copy_from_staging_texture(ctx
, rtransfer
);
1648 if (rtransfer
->staging
) {
1649 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1650 r600_resource_reference(&rtransfer
->staging
, NULL
);
1653 /* Heuristic for {upload, draw, upload, draw, ..}:
1655 * Flush the gfx IB if we've allocated too much texture storage.
1657 * The idea is that we don't want to build IBs that use too much
1658 * memory and put pressure on the kernel memory manager and we also
1659 * want to make temporary and invalidated buffers go idle ASAP to
1660 * decrease the total memory usage or make them reusable. The memory
1661 * usage will be slightly higher than given here because of the buffer
1662 * cache in the winsys.
1664 * The result is that the kernel memory manager is never a bottleneck.
1666 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1667 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1668 rctx
->num_alloc_tex_transfer_bytes
= 0;
1674 static const struct u_resource_vtbl r600_texture_vtbl
=
1676 NULL
, /* get_handle */
1677 r600_texture_destroy
, /* resource_destroy */
1678 r600_texture_transfer_map
, /* transfer_map */
1679 u_default_transfer_flush_region
, /* transfer_flush_region */
1680 r600_texture_transfer_unmap
, /* transfer_unmap */
1683 /* DCC channel type categories within which formats can be reinterpreted
1684 * while keeping the same DCC encoding. The swizzle must also match. */
1685 enum dcc_channel_type
{
1686 dcc_channel_float32
,
1689 dcc_channel_float16
,
1692 dcc_channel_uint_10_10_10_2
,
1695 dcc_channel_incompatible
,
1698 /* Return the type of DCC encoding. */
1699 static enum dcc_channel_type
1700 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1704 /* Find the first non-void channel. */
1705 for (i
= 0; i
< desc
->nr_channels
; i
++)
1706 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1708 if (i
== desc
->nr_channels
)
1709 return dcc_channel_incompatible
;
1711 switch (desc
->channel
[i
].size
) {
1713 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1714 return dcc_channel_float32
;
1715 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1716 return dcc_channel_uint32
;
1717 return dcc_channel_sint32
;
1719 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1720 return dcc_channel_float16
;
1721 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1722 return dcc_channel_uint16
;
1723 return dcc_channel_sint16
;
1725 return dcc_channel_uint_10_10_10_2
;
1727 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1728 return dcc_channel_uint8
;
1729 return dcc_channel_sint8
;
1731 return dcc_channel_incompatible
;
1735 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1736 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1737 enum pipe_format format2
)
1739 const struct util_format_description
*desc1
, *desc2
;
1740 enum dcc_channel_type type1
, type2
;
1743 if (format1
== format2
)
1746 desc1
= util_format_description(format1
);
1747 desc2
= util_format_description(format2
);
1749 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1752 /* Swizzles must be the same. */
1753 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1754 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1755 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1756 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1759 type1
= vi_get_dcc_channel_type(desc1
);
1760 type2
= vi_get_dcc_channel_type(desc2
);
1762 return type1
!= dcc_channel_incompatible
&&
1763 type2
!= dcc_channel_incompatible
&&
1767 void vi_dcc_disable_if_incompatible_format(struct r600_common_context
*rctx
,
1768 struct pipe_resource
*tex
,
1770 enum pipe_format view_format
)
1772 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1774 if (rtex
->dcc_offset
&&
1775 rtex
->surface
.level
[level
].dcc_enabled
&&
1776 !vi_dcc_formats_compatible(tex
->format
, view_format
))
1777 if (!r600_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1778 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1781 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1782 struct pipe_resource
*texture
,
1783 const struct pipe_surface
*templ
,
1784 unsigned width
, unsigned height
)
1786 struct r600_common_context
*rctx
= (struct r600_common_context
*)pipe
;
1787 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1788 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1793 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1794 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1796 pipe_reference_init(&surface
->base
.reference
, 1);
1797 pipe_resource_reference(&surface
->base
.texture
, texture
);
1798 surface
->base
.context
= pipe
;
1799 surface
->base
.format
= templ
->format
;
1800 surface
->base
.width
= width
;
1801 surface
->base
.height
= height
;
1802 surface
->base
.u
= templ
->u
;
1803 surface
->level_info
= &rtex
->surface
.level
[templ
->u
.tex
.level
];
1805 if (texture
->target
!= PIPE_BUFFER
)
1806 vi_dcc_disable_if_incompatible_format(rctx
, texture
,
1810 return &surface
->base
;
1813 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1814 struct pipe_resource
*tex
,
1815 const struct pipe_surface
*templ
)
1817 unsigned level
= templ
->u
.tex
.level
;
1818 unsigned width
= u_minify(tex
->width0
, level
);
1819 unsigned height
= u_minify(tex
->height0
, level
);
1821 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1822 const struct util_format_description
*tex_desc
1823 = util_format_description(tex
->format
);
1824 const struct util_format_description
*templ_desc
1825 = util_format_description(templ
->format
);
1827 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1829 /* Adjust size of surface if and only if the block width or
1830 * height is changed. */
1831 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1832 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1833 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1834 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1836 width
= nblks_x
* templ_desc
->block
.width
;
1837 height
= nblks_y
* templ_desc
->block
.height
;
1841 return r600_create_surface_custom(pipe
, tex
, templ
, width
, height
);
1844 static void r600_surface_destroy(struct pipe_context
*pipe
,
1845 struct pipe_surface
*surface
)
1847 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1848 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1849 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1850 pipe_resource_reference(&surface
->texture
, NULL
);
1854 static void r600_clear_texture(struct pipe_context
*pipe
,
1855 struct pipe_resource
*tex
,
1857 const struct pipe_box
*box
,
1860 struct pipe_screen
*screen
= pipe
->screen
;
1861 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1862 struct pipe_surface tmpl
= {{0}};
1863 struct pipe_surface
*sf
;
1864 const struct util_format_description
*desc
=
1865 util_format_description(tex
->format
);
1867 tmpl
.format
= tex
->format
;
1868 tmpl
.u
.tex
.first_layer
= box
->z
;
1869 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
1870 tmpl
.u
.tex
.level
= level
;
1871 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
1875 if (rtex
->is_depth
) {
1878 uint8_t stencil
= 0;
1880 /* Depth is always present. */
1881 clear
= PIPE_CLEAR_DEPTH
;
1882 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
1884 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1885 clear
|= PIPE_CLEAR_STENCIL
;
1886 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
1889 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
1891 box
->width
, box
->height
, false);
1893 union pipe_color_union color
;
1895 /* pipe_color_union requires the full vec4 representation. */
1896 if (util_format_is_pure_uint(tex
->format
))
1897 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
1898 else if (util_format_is_pure_sint(tex
->format
))
1899 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
1901 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
1903 if (screen
->is_format_supported(screen
, tex
->format
,
1905 PIPE_BIND_RENDER_TARGET
)) {
1906 pipe
->clear_render_target(pipe
, sf
, &color
,
1908 box
->width
, box
->height
, false);
1910 /* Software fallback - just for R9G9B9E5_FLOAT */
1911 util_clear_render_target(pipe
, sf
, &color
,
1913 box
->width
, box
->height
);
1916 pipe_surface_reference(&sf
, NULL
);
1919 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1921 const struct util_format_description
*desc
= util_format_description(format
);
1923 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1925 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1926 return V_0280A0_SWAP_STD
;
1928 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1931 switch (desc
->nr_channels
) {
1933 if (HAS_SWIZZLE(0,X
))
1934 return V_0280A0_SWAP_STD
; /* X___ */
1935 else if (HAS_SWIZZLE(3,X
))
1936 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1939 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1940 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1941 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1942 return V_0280A0_SWAP_STD
; /* XY__ */
1943 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1944 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1945 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1947 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
1948 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1949 return V_0280A0_SWAP_ALT
; /* X__Y */
1950 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1951 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1954 if (HAS_SWIZZLE(0,X
))
1955 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
1956 else if (HAS_SWIZZLE(0,Z
))
1957 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1960 /* check the middle channels, the 1st and 4th channel can be NONE */
1961 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
1962 return V_0280A0_SWAP_STD
; /* XYZW */
1963 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
1964 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1965 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
1966 return V_0280A0_SWAP_ALT
; /* ZYXW */
1967 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
1970 return V_0280A0_SWAP_ALT_REV
;
1972 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
1979 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
1981 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
1986 if (rctx
->dcc_stats
[slot
].query_active
)
1987 vi_separate_dcc_stop_query(&rctx
->b
,
1988 rctx
->dcc_stats
[slot
].tex
);
1990 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
1991 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
1992 rctx
->b
.destroy_query(&rctx
->b
,
1993 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
1994 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
1997 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2001 * Return the per-context slot where DCC statistics queries for the texture live.
2003 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2004 struct r600_texture
*tex
)
2006 int i
, empty_slot
= -1;
2008 /* Remove zombie textures (textures kept alive by this array only). */
2009 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2010 if (rctx
->dcc_stats
[i
].tex
&&
2011 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2012 vi_dcc_clean_up_context_slot(rctx
, i
);
2014 /* Find the texture. */
2015 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2016 /* Return if found. */
2017 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2018 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2022 /* Record the first seen empty slot. */
2023 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2027 /* Not found. Remove the oldest member to make space in the array. */
2028 if (empty_slot
== -1) {
2029 int oldest_slot
= 0;
2031 /* Find the oldest slot. */
2032 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2033 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2034 rctx
->dcc_stats
[i
].last_use_timestamp
)
2037 /* Clean up the oldest slot. */
2038 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2039 empty_slot
= oldest_slot
;
2042 /* Add the texture to the new slot. */
2043 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2044 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2048 static struct pipe_query
*
2049 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2051 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2052 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2054 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2055 return (struct pipe_query
*)query
;
2059 * Called when binding a color buffer.
2061 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2062 struct r600_texture
*tex
)
2064 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2065 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2067 assert(!rctx
->dcc_stats
[i
].query_active
);
2069 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2070 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2072 /* begin or resume the query */
2073 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2074 rctx
->dcc_stats
[i
].query_active
= true;
2078 * Called when unbinding a color buffer.
2080 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2081 struct r600_texture
*tex
)
2083 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2084 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2086 assert(rctx
->dcc_stats
[i
].query_active
);
2087 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2089 /* pause or end the query */
2090 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2091 rctx
->dcc_stats
[i
].query_active
= false;
2094 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2096 /* The minimum number of fullscreen draws per frame that is required
2098 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2101 /* Called by fast clear. */
2102 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2103 struct r600_texture
*tex
)
2105 /* The intent is to use this with shared displayable back buffers,
2106 * but it's not strictly limited only to them.
2108 if (!tex
->resource
.is_shared
||
2109 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2110 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2111 tex
->surface
.last_level
> 0 ||
2112 !tex
->surface
.dcc_size
)
2115 if (tex
->dcc_offset
)
2116 return; /* already enabled */
2118 /* Enable the DCC stat gathering. */
2119 if (!tex
->dcc_gather_statistics
) {
2120 tex
->dcc_gather_statistics
= true;
2121 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2124 if (!vi_should_enable_separate_dcc(tex
))
2125 return; /* stats show that DCC decompression is too expensive */
2127 assert(tex
->surface
.level
[0].dcc_enabled
);
2128 assert(!tex
->dcc_separate_buffer
);
2130 r600_texture_discard_cmask(rctx
->screen
, tex
);
2132 /* Get a DCC buffer. */
2133 if (tex
->last_dcc_separate_buffer
) {
2134 assert(tex
->dcc_gather_statistics
);
2135 assert(!tex
->dcc_separate_buffer
);
2136 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2137 tex
->last_dcc_separate_buffer
= NULL
;
2139 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2140 r600_aligned_buffer_create(rctx
->b
.screen
, 0,
2142 tex
->surface
.dcc_size
,
2143 tex
->surface
.dcc_alignment
);
2144 if (!tex
->dcc_separate_buffer
)
2148 /* dcc_offset is the absolute GPUVM address. */
2149 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2151 /* no need to flag anything since this is called by fast clear that
2152 * flags framebuffer state
2157 * Called by pipe_context::flush_resource, the place where DCC decompression
2160 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2161 struct r600_texture
*tex
)
2163 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2164 struct pipe_query
*tmp
;
2165 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2166 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2167 bool disable
= false;
2169 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2170 union pipe_query_result result
;
2172 /* Read the results. */
2173 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2175 r600_query_hw_reset_buffers(rctx
,
2176 (struct r600_query_hw
*)
2177 rctx
->dcc_stats
[i
].ps_stats
[2]);
2179 /* Compute the approximate number of fullscreen draws. */
2180 tex
->ps_draw_ratio
=
2181 result
.pipeline_statistics
.ps_invocations
/
2182 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2183 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2185 disable
= tex
->dcc_separate_buffer
&&
2186 !vi_should_enable_separate_dcc(tex
);
2189 tex
->num_slow_clears
= 0;
2191 /* stop the statistics query for ps_stats[0] */
2193 vi_separate_dcc_stop_query(ctx
, tex
);
2195 /* Move the queries in the queue by one. */
2196 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2197 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2198 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2199 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2201 /* create and start a new query as ps_stats[0] */
2203 vi_separate_dcc_start_query(ctx
, tex
);
2206 assert(!tex
->last_dcc_separate_buffer
);
2207 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2208 tex
->dcc_separate_buffer
= NULL
;
2209 tex
->dcc_offset
= 0;
2210 /* no need to flag anything since this is called after
2211 * decompression that re-sets framebuffer state
2216 /* FAST COLOR CLEAR */
2218 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2219 enum pipe_format surface_format
,
2220 const union pipe_color_union
*color
)
2222 union util_color uc
;
2224 memset(&uc
, 0, sizeof(uc
));
2226 if (util_format_get_blocksizebits(surface_format
) == 128) {
2227 /* DCC fast clear only:
2228 * CLEAR_WORD0 = R = G = B
2231 assert(color
->ui
[0] == color
->ui
[1] &&
2232 color
->ui
[0] == color
->ui
[2]);
2233 uc
.ui
[0] = color
->ui
[0];
2234 uc
.ui
[1] = color
->ui
[3];
2235 } else if (util_format_is_pure_uint(surface_format
)) {
2236 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2237 } else if (util_format_is_pure_sint(surface_format
)) {
2238 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2240 util_pack_color(color
->f
, surface_format
, &uc
);
2243 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2246 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2247 const union pipe_color_union
*color
,
2248 uint32_t* reset_value
,
2249 bool* clear_words_needed
)
2251 bool values
[4] = {};
2253 bool main_value
= false;
2254 bool extra_value
= false;
2256 const struct util_format_description
*desc
= util_format_description(surface_format
);
2258 if (desc
->block
.bits
== 128 &&
2259 (color
->ui
[0] != color
->ui
[1] ||
2260 color
->ui
[0] != color
->ui
[2]))
2263 *clear_words_needed
= true;
2264 *reset_value
= 0x20202020U
;
2266 /* If we want to clear without needing a fast clear eliminate step, we
2267 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2268 * have two sets of flags, one for the last or first channel(extra) and
2269 * one for the other channels(main).
2272 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2273 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2274 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
2276 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2277 if(r600_translate_colorswap(surface_format
, false) <= 1)
2278 extra_channel
= desc
->nr_channels
- 1;
2284 for (i
= 0; i
< 4; ++i
) {
2285 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2287 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2288 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2291 if (desc
->channel
[i
].pure_integer
&&
2292 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2293 /* Use the maximum value for clamping the clear color. */
2294 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2296 values
[i
] = color
->i
[i
] != 0;
2297 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2299 } else if (desc
->channel
[i
].pure_integer
&&
2300 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2301 /* Use the maximum value for clamping the clear color. */
2302 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2304 values
[i
] = color
->ui
[i
] != 0U;
2305 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2308 values
[i
] = color
->f
[i
] != 0.0F
;
2309 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2313 if (index
== extra_channel
)
2314 extra_value
= values
[i
];
2316 main_value
= values
[i
];
2319 for (int i
= 0; i
< 4; ++i
)
2320 if (values
[i
] != main_value
&&
2321 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2322 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2323 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2326 *clear_words_needed
= false;
2328 *reset_value
|= 0x80808080U
;
2331 *reset_value
|= 0x40404040U
;
2335 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2336 struct r600_texture
*rtex
,
2337 unsigned level
, unsigned clear_value
)
2339 struct pipe_resource
*dcc_buffer
;
2340 uint64_t dcc_offset
;
2342 assert(rtex
->dcc_offset
&& rtex
->surface
.level
[level
].dcc_enabled
);
2344 if (rtex
->dcc_separate_buffer
) {
2345 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2348 dcc_buffer
= &rtex
->resource
.b
.b
;
2349 dcc_offset
= rtex
->dcc_offset
;
2352 dcc_offset
+= rtex
->surface
.level
[level
].dcc_offset
;
2354 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
,
2355 rtex
->surface
.level
[level
].dcc_fast_clear_size
,
2356 clear_value
, R600_COHERENCY_CB_META
);
2359 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2360 * This allows hitting the MSAA resolve fast path, which requires that both
2361 * src and dst micro tile modes match.
2363 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2364 struct r600_texture
*rtex
)
2366 if (rtex
->resource
.is_shared
||
2367 rtex
->surface
.nsamples
<= 1 ||
2368 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2371 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2372 assert(rtex
->surface
.last_level
== 0);
2374 /* These magic numbers were copied from addrlib. It doesn't use any
2375 * definitions for them either. They are all 2D_TILED_THIN1 modes with
2376 * different bpp and micro tile mode.
2378 if (rscreen
->chip_class
>= CIK
) {
2379 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2380 case 0: /* displayable */
2381 rtex
->surface
.tiling_index
[0] = 10;
2384 rtex
->surface
.tiling_index
[0] = 14;
2386 case 3: /* rotated */
2387 rtex
->surface
.tiling_index
[0] = 28;
2389 default: /* depth, thick */
2390 assert(!"unexpected micro mode");
2394 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2395 case 0: /* displayable */
2396 switch (rtex
->surface
.bpe
) {
2398 rtex
->surface
.tiling_index
[0] = 10;
2401 rtex
->surface
.tiling_index
[0] = 11;
2403 default: /* 32, 64 */
2404 rtex
->surface
.tiling_index
[0] = 12;
2409 switch (rtex
->surface
.bpe
) {
2411 rtex
->surface
.tiling_index
[0] = 14;
2414 rtex
->surface
.tiling_index
[0] = 15;
2417 rtex
->surface
.tiling_index
[0] = 16;
2419 default: /* 64, 128 */
2420 rtex
->surface
.tiling_index
[0] = 17;
2424 default: /* depth, thick */
2425 assert(!"unexpected micro mode");
2430 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2432 p_atomic_inc(&rscreen
->dirty_fb_counter
);
2433 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
2436 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2437 struct pipe_framebuffer_state
*fb
,
2438 struct r600_atom
*fb_state
,
2439 unsigned *buffers
, unsigned *dirty_cbufs
,
2440 const union pipe_color_union
*color
)
2444 /* This function is broken in BE, so just disable this path for now */
2445 #ifdef PIPE_ARCH_BIG_ENDIAN
2449 if (rctx
->render_cond
)
2452 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2453 struct r600_texture
*tex
;
2454 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2459 /* if this colorbuffer is not being cleared */
2460 if (!(*buffers
& clear_bit
))
2463 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2465 /* the clear is allowed if all layers are bound */
2466 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2467 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2471 /* cannot clear mipmapped textures */
2472 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2476 /* only supported on tiled surfaces */
2477 if (tex
->surface
.level
[0].mode
< RADEON_SURF_MODE_1D
) {
2481 /* shared textures can't use fast clear without an explicit flush,
2482 * because there is no way to communicate the clear color among
2485 if (tex
->resource
.is_shared
&&
2486 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2489 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2490 if (tex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2491 rctx
->chip_class
>= CIK
&&
2492 rctx
->screen
->info
.drm_major
== 2 &&
2493 rctx
->screen
->info
.drm_minor
< 38) {
2497 /* Fast clear is the most appropriate place to enable DCC for
2498 * displayable surfaces.
2500 if (rctx
->chip_class
>= VI
&&
2501 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2502 vi_separate_dcc_try_enable(rctx
, tex
);
2504 /* Stoney can't do a CMASK-based clear, so all clears are
2505 * considered to be hypothetically slow clears, which
2506 * is weighed when determining to enable separate DCC.
2508 if (tex
->dcc_gather_statistics
&&
2509 rctx
->family
== CHIP_STONEY
)
2510 tex
->num_slow_clears
++;
2513 /* Try to clear DCC first, otherwise try CMASK. */
2514 if (tex
->dcc_offset
&& tex
->surface
.level
[0].dcc_enabled
) {
2515 uint32_t reset_value
;
2516 bool clear_words_needed
;
2518 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2521 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2522 color
, &reset_value
,
2523 &clear_words_needed
))
2526 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2528 if (clear_words_needed
)
2529 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2530 tex
->separate_dcc_dirty
= true;
2532 /* 128-bit formats are unusupported */
2533 if (util_format_get_blocksizebits(fb
->cbufs
[i
]->format
) > 64) {
2537 /* Stoney/RB+ doesn't work with CMASK fast clear. */
2538 if (rctx
->family
== CHIP_STONEY
)
2541 /* ensure CMASK is enabled */
2542 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2543 if (tex
->cmask
.size
== 0) {
2547 /* Do the fast clear. */
2548 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2549 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2550 R600_COHERENCY_CB_META
);
2552 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2555 /* We can change the micro tile mode before a full clear. */
2556 if (rctx
->screen
->chip_class
>= SI
)
2557 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2559 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2562 *dirty_cbufs
|= 1 << i
;
2563 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2564 *buffers
&= ~clear_bit
;
2568 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2570 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2571 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2574 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2576 rctx
->b
.create_surface
= r600_create_surface
;
2577 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2578 rctx
->b
.clear_texture
= r600_clear_texture
;