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anv/pipeline: Get rid of the no kernel input parameters hack
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include <errno.h>
33 #include <inttypes.h>
34
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context *pipe,
37 struct pipe_resource *dst,
38 unsigned dst_level,
39 unsigned dstx, unsigned dsty, unsigned dstz,
40 struct pipe_resource *src,
41 unsigned src_level,
42 const struct pipe_box *src_box)
43 {
44 struct pipe_blit_info blit;
45
46 memset(&blit, 0, sizeof(blit));
47 blit.src.resource = src;
48 blit.src.format = src->format;
49 blit.src.level = src_level;
50 blit.src.box = *src_box;
51 blit.dst.resource = dst;
52 blit.dst.format = dst->format;
53 blit.dst.level = dst_level;
54 blit.dst.box.x = dstx;
55 blit.dst.box.y = dsty;
56 blit.dst.box.z = dstz;
57 blit.dst.box.width = src_box->width;
58 blit.dst.box.height = src_box->height;
59 blit.dst.box.depth = src_box->depth;
60 blit.mask = util_format_get_mask(src->format) &
61 util_format_get_mask(dst->format);
62 blit.filter = PIPE_TEX_FILTER_NEAREST;
63
64 if (blit.mask) {
65 pipe->blit(pipe, &blit);
66 }
67 }
68
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
71 {
72 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
73 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
74 struct pipe_resource *dst = &rtransfer->staging->b.b;
75 struct pipe_resource *src = transfer->resource;
76
77 if (src->nr_samples > 1) {
78 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
79 src, transfer->level, &transfer->box);
80 return;
81 }
82
83 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
84 &transfer->box);
85 }
86
87 /* Copy from a transfer's staging texture to a full GPU one. */
88 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
89 {
90 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
91 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
92 struct pipe_resource *dst = transfer->resource;
93 struct pipe_resource *src = &rtransfer->staging->b.b;
94 struct pipe_box sbox;
95
96 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
97
98 if (dst->nr_samples > 1) {
99 r600_copy_region_with_blit(ctx, dst, transfer->level,
100 transfer->box.x, transfer->box.y, transfer->box.z,
101 src, 0, &sbox);
102 return;
103 }
104
105 rctx->dma_copy(ctx, dst, transfer->level,
106 transfer->box.x, transfer->box.y, transfer->box.z,
107 src, 0, &sbox);
108 }
109
110 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
111 const struct pipe_box *box)
112 {
113 enum pipe_format format = rtex->resource.b.b.format;
114
115 return rtex->surface.level[level].offset +
116 box->z * rtex->surface.level[level].slice_size +
117 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
118 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
119 }
120
121 static int r600_init_surface(struct r600_common_screen *rscreen,
122 struct radeon_surf *surface,
123 const struct pipe_resource *ptex,
124 unsigned array_mode,
125 bool is_flushed_depth)
126 {
127 const struct util_format_description *desc =
128 util_format_description(ptex->format);
129 bool is_depth, is_stencil;
130
131 is_depth = util_format_has_depth(desc);
132 is_stencil = util_format_has_stencil(desc);
133
134 surface->npix_x = ptex->width0;
135 surface->npix_y = ptex->height0;
136 surface->npix_z = ptex->depth0;
137 surface->blk_w = util_format_get_blockwidth(ptex->format);
138 surface->blk_h = util_format_get_blockheight(ptex->format);
139 surface->blk_d = 1;
140 surface->array_size = 1;
141 surface->last_level = ptex->last_level;
142
143 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
144 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
145 surface->bpe = 4; /* stencil is allocated separately on evergreen */
146 } else {
147 surface->bpe = util_format_get_blocksize(ptex->format);
148 /* align byte per element on dword */
149 if (surface->bpe == 3) {
150 surface->bpe = 4;
151 }
152 }
153
154 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
155 surface->flags = RADEON_SURF_SET(array_mode, MODE);
156
157 switch (ptex->target) {
158 case PIPE_TEXTURE_1D:
159 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
160 break;
161 case PIPE_TEXTURE_RECT:
162 case PIPE_TEXTURE_2D:
163 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
164 break;
165 case PIPE_TEXTURE_3D:
166 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
167 break;
168 case PIPE_TEXTURE_1D_ARRAY:
169 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
170 surface->array_size = ptex->array_size;
171 break;
172 case PIPE_TEXTURE_2D_ARRAY:
173 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
175 surface->array_size = ptex->array_size;
176 break;
177 case PIPE_TEXTURE_CUBE:
178 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
179 break;
180 case PIPE_BUFFER:
181 default:
182 return -EINVAL;
183 }
184 if (ptex->bind & PIPE_BIND_SCANOUT) {
185 surface->flags |= RADEON_SURF_SCANOUT;
186 }
187
188 if (!is_flushed_depth && is_depth) {
189 surface->flags |= RADEON_SURF_ZBUFFER;
190
191 if (is_stencil) {
192 surface->flags |= RADEON_SURF_SBUFFER |
193 RADEON_SURF_HAS_SBUFFER_MIPTREE;
194 }
195 }
196 if (rscreen->chip_class >= SI) {
197 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
198 }
199 return 0;
200 }
201
202 static int r600_setup_surface(struct pipe_screen *screen,
203 struct r600_texture *rtex,
204 unsigned pitch_in_bytes_override)
205 {
206 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
207 int r;
208
209 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
210 if (r) {
211 return r;
212 }
213
214 rtex->size = rtex->surface.bo_size;
215
216 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
217 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
218 * for those
219 */
220 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
221 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
222 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
223 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
224 rtex->surface.stencil_offset =
225 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
226 }
227 }
228 return 0;
229 }
230
231 static boolean r600_texture_get_handle(struct pipe_screen* screen,
232 struct pipe_resource *ptex,
233 struct winsys_handle *whandle)
234 {
235 struct r600_texture *rtex = (struct r600_texture*)ptex;
236 struct r600_resource *resource = &rtex->resource;
237 struct radeon_surf *surface = &rtex->surface;
238 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
239
240 rscreen->ws->buffer_set_tiling(resource->buf,
241 NULL,
242 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
243 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
244 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
245 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
246 surface->pipe_config,
247 surface->bankw, surface->bankh,
248 surface->tile_split,
249 surface->stencil_tile_split,
250 surface->mtilea, surface->num_banks,
251 surface->level[0].pitch_bytes,
252 (surface->flags & RADEON_SURF_SCANOUT) != 0);
253
254 return rscreen->ws->buffer_get_handle(resource->buf,
255 surface->level[0].pitch_bytes, whandle);
256 }
257
258 static void r600_texture_destroy(struct pipe_screen *screen,
259 struct pipe_resource *ptex)
260 {
261 struct r600_texture *rtex = (struct r600_texture*)ptex;
262 struct r600_resource *resource = &rtex->resource;
263
264 if (rtex->flushed_depth_texture)
265 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
266
267 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
268 if (rtex->cmask_buffer != &rtex->resource) {
269 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
270 }
271 pipe_resource_reference((struct pipe_resource**)&rtex->dcc_buffer, NULL);
272 pb_reference(&resource->buf, NULL);
273 FREE(rtex);
274 }
275
276 static const struct u_resource_vtbl r600_texture_vtbl;
277
278 /* The number of samples can be specified independently of the texture. */
279 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
280 struct r600_texture *rtex,
281 unsigned nr_samples,
282 struct r600_fmask_info *out)
283 {
284 /* FMASK is allocated like an ordinary texture. */
285 struct radeon_surf fmask = rtex->surface;
286
287 memset(out, 0, sizeof(*out));
288
289 fmask.bo_alignment = 0;
290 fmask.bo_size = 0;
291 fmask.nsamples = 1;
292 fmask.flags |= RADEON_SURF_FMASK;
293
294 /* Force 2D tiling if it wasn't set. This may occur when creating
295 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
296 * destination buffer must have an FMASK too. */
297 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
298 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
299
300 if (rscreen->chip_class >= SI) {
301 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
302 }
303
304 switch (nr_samples) {
305 case 2:
306 case 4:
307 fmask.bpe = 1;
308 if (rscreen->chip_class <= CAYMAN) {
309 fmask.bankh = 4;
310 }
311 break;
312 case 8:
313 fmask.bpe = 4;
314 break;
315 default:
316 R600_ERR("Invalid sample count for FMASK allocation.\n");
317 return;
318 }
319
320 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
321 * This can be fixed by writing a separate FMASK allocator specifically
322 * for R600-R700 asics. */
323 if (rscreen->chip_class <= R700) {
324 fmask.bpe *= 2;
325 }
326
327 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
328 R600_ERR("Got error in surface_init while allocating FMASK.\n");
329 return;
330 }
331
332 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
333
334 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
335 if (out->slice_tile_max)
336 out->slice_tile_max -= 1;
337
338 out->tile_mode_index = fmask.tiling_index[0];
339 out->pitch_in_pixels = fmask.level[0].nblk_x;
340 out->bank_height = fmask.bankh;
341 out->alignment = MAX2(256, fmask.bo_alignment);
342 out->size = fmask.bo_size;
343 }
344
345 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
346 struct r600_texture *rtex)
347 {
348 r600_texture_get_fmask_info(rscreen, rtex,
349 rtex->resource.b.b.nr_samples, &rtex->fmask);
350
351 rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
352 rtex->size = rtex->fmask.offset + rtex->fmask.size;
353 }
354
355 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
356 struct r600_texture *rtex,
357 struct r600_cmask_info *out)
358 {
359 unsigned cmask_tile_width = 8;
360 unsigned cmask_tile_height = 8;
361 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
362 unsigned element_bits = 4;
363 unsigned cmask_cache_bits = 1024;
364 unsigned num_pipes = rscreen->tiling_info.num_channels;
365 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
366
367 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
368 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
369 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
370 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
371 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
372
373 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
374 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
375
376 unsigned base_align = num_pipes * pipe_interleave_bytes;
377 unsigned slice_bytes =
378 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
379
380 assert(macro_tile_width % 128 == 0);
381 assert(macro_tile_height % 128 == 0);
382
383 out->pitch = pitch_elements;
384 out->height = height;
385 out->xalign = macro_tile_width;
386 out->yalign = macro_tile_height;
387 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
388 out->alignment = MAX2(256, base_align);
389 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
390 align(slice_bytes, base_align);
391 }
392
393 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
394 struct r600_texture *rtex,
395 struct r600_cmask_info *out)
396 {
397 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
398 unsigned num_pipes = rscreen->tiling_info.num_channels;
399 unsigned cl_width, cl_height;
400
401 switch (num_pipes) {
402 case 2:
403 cl_width = 32;
404 cl_height = 16;
405 break;
406 case 4:
407 cl_width = 32;
408 cl_height = 32;
409 break;
410 case 8:
411 cl_width = 64;
412 cl_height = 32;
413 break;
414 case 16: /* Hawaii */
415 cl_width = 64;
416 cl_height = 64;
417 break;
418 default:
419 assert(0);
420 return;
421 }
422
423 unsigned base_align = num_pipes * pipe_interleave_bytes;
424
425 unsigned width = align(rtex->surface.npix_x, cl_width*8);
426 unsigned height = align(rtex->surface.npix_y, cl_height*8);
427 unsigned slice_elements = (width * height) / (8*8);
428
429 /* Each element of CMASK is a nibble. */
430 unsigned slice_bytes = slice_elements / 2;
431
432 out->pitch = width;
433 out->height = height;
434 out->xalign = cl_width * 8;
435 out->yalign = cl_height * 8;
436 out->slice_tile_max = (width * height) / (128*128);
437 if (out->slice_tile_max)
438 out->slice_tile_max -= 1;
439
440 out->alignment = MAX2(256, base_align);
441 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
442 align(slice_bytes, base_align);
443 }
444
445 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
446 struct r600_texture *rtex)
447 {
448 if (rscreen->chip_class >= SI) {
449 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
450 } else {
451 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
452 }
453
454 rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
455 rtex->size = rtex->cmask.offset + rtex->cmask.size;
456
457 if (rscreen->chip_class >= SI)
458 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
459 else
460 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
461 }
462
463 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
464 struct r600_texture *rtex)
465 {
466 if (rtex->cmask_buffer)
467 return;
468
469 assert(rtex->cmask.size == 0);
470
471 if (rscreen->chip_class >= SI) {
472 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
473 } else {
474 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
475 }
476
477 rtex->cmask_buffer = (struct r600_resource *)
478 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
479 PIPE_USAGE_DEFAULT, rtex->cmask.size);
480 if (rtex->cmask_buffer == NULL) {
481 rtex->cmask.size = 0;
482 return;
483 }
484
485 /* update colorbuffer state bits */
486 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
487
488 if (rscreen->chip_class >= SI)
489 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
490 else
491 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
492 }
493
494 static void vi_texture_alloc_dcc_separate(struct r600_common_screen *rscreen,
495 struct r600_texture *rtex)
496 {
497 if (rscreen->debug_flags & DBG_NO_DCC)
498 return;
499
500 /* TODO: DCC is broken on Stoney */
501 if (rscreen->family == CHIP_STONEY)
502 return;
503
504 rtex->dcc_buffer = (struct r600_resource *)
505 r600_aligned_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
506 PIPE_USAGE_DEFAULT, rtex->surface.dcc_size, rtex->surface.dcc_alignment);
507 if (rtex->dcc_buffer == NULL) {
508 return;
509 }
510
511 r600_screen_clear_buffer(rscreen, &rtex->dcc_buffer->b.b, 0, rtex->surface.dcc_size,
512 0xFFFFFFFF, true);
513
514 rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
515 }
516
517 static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
518 struct r600_texture *rtex)
519 {
520 unsigned cl_width, cl_height, width, height;
521 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
522 unsigned num_pipes = rscreen->tiling_info.num_channels;
523
524 if (rscreen->chip_class <= EVERGREEN &&
525 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
526 return 0;
527
528 /* HW bug on R6xx. */
529 if (rscreen->chip_class == R600 &&
530 (rtex->surface.level[0].npix_x > 7680 ||
531 rtex->surface.level[0].npix_y > 7680))
532 return 0;
533
534 /* HTILE is broken with 1D tiling on old kernels and CIK. */
535 if (rscreen->chip_class >= CIK &&
536 rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
537 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
538 return 0;
539
540 switch (num_pipes) {
541 case 1:
542 cl_width = 32;
543 cl_height = 16;
544 break;
545 case 2:
546 cl_width = 32;
547 cl_height = 32;
548 break;
549 case 4:
550 cl_width = 64;
551 cl_height = 32;
552 break;
553 case 8:
554 cl_width = 64;
555 cl_height = 64;
556 break;
557 case 16:
558 cl_width = 128;
559 cl_height = 64;
560 break;
561 default:
562 assert(0);
563 return 0;
564 }
565
566 width = align(rtex->surface.npix_x, cl_width * 8);
567 height = align(rtex->surface.npix_y, cl_height * 8);
568
569 slice_elements = (width * height) / (8 * 8);
570 slice_bytes = slice_elements * 4;
571
572 pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
573 base_align = num_pipes * pipe_interleave_bytes;
574
575 rtex->htile.pitch = width;
576 rtex->htile.height = height;
577 rtex->htile.xalign = cl_width * 8;
578 rtex->htile.yalign = cl_height * 8;
579
580 return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
581 align(slice_bytes, base_align);
582 }
583
584 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
585 struct r600_texture *rtex)
586 {
587 unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex);
588
589 if (!htile_size)
590 return;
591
592 rtex->htile_buffer = (struct r600_resource*)
593 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
594 PIPE_USAGE_DEFAULT, htile_size);
595 if (rtex->htile_buffer == NULL) {
596 /* this is not a fatal error as we can still keep rendering
597 * without htile buffer */
598 R600_ERR("Failed to create buffer object for htile buffer.\n");
599 } else {
600 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0,
601 htile_size, 0, true);
602 }
603 }
604
605 void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
606 {
607 int i;
608
609 fprintf(f, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
610 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
611 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
612 rtex->surface.npix_x, rtex->surface.npix_y,
613 rtex->surface.npix_z, rtex->surface.blk_w,
614 rtex->surface.blk_h, rtex->surface.blk_d,
615 rtex->surface.array_size, rtex->surface.last_level,
616 rtex->surface.bpe, rtex->surface.nsamples,
617 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
618
619 fprintf(f, " Layout: size=%"PRIu64", alignment=%"PRIu64", bankw=%u, "
620 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
621 rtex->surface.bo_size, rtex->surface.bo_alignment, rtex->surface.bankw,
622 rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
623 rtex->surface.tile_split, rtex->surface.pipe_config,
624 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
625
626 if (rtex->fmask.size)
627 fprintf(f, " FMask: offset=%u, size=%u, alignment=%u, pitch_in_pixels=%u, "
628 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
629 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
630 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
631 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
632
633 if (rtex->cmask.size)
634 fprintf(f, " CMask: offset=%u, size=%u, alignment=%u, pitch=%u, "
635 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
636 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
637 rtex->cmask.pitch, rtex->cmask.height, rtex->cmask.xalign,
638 rtex->cmask.yalign, rtex->cmask.slice_tile_max);
639
640 if (rtex->htile_buffer)
641 fprintf(f, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
642 "xalign=%u, yalign=%u\n",
643 rtex->htile_buffer->b.b.width0,
644 rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
645 rtex->htile.height, rtex->htile.xalign, rtex->htile.yalign);
646
647 if (rtex->dcc_buffer) {
648 fprintf(f, " DCC: size=%u, alignment=%u\n",
649 rtex->dcc_buffer->b.b.width0,
650 rtex->dcc_buffer->buf->alignment);
651 for (i = 0; i <= rtex->surface.last_level; i++)
652 fprintf(f, " DCCLevel[%i]: offset=%"PRIu64"\n",
653 i, rtex->surface.level[i].dcc_offset);
654 }
655
656 for (i = 0; i <= rtex->surface.last_level; i++)
657 fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
658 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
659 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
660 i, rtex->surface.level[i].offset,
661 rtex->surface.level[i].slice_size,
662 u_minify(rtex->resource.b.b.width0, i),
663 u_minify(rtex->resource.b.b.height0, i),
664 u_minify(rtex->resource.b.b.depth0, i),
665 rtex->surface.level[i].nblk_x,
666 rtex->surface.level[i].nblk_y,
667 rtex->surface.level[i].nblk_z,
668 rtex->surface.level[i].pitch_bytes,
669 rtex->surface.level[i].mode);
670
671 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
672 for (i = 0; i <= rtex->surface.last_level; i++) {
673 fprintf(f, " StencilLayout: tilesplit=%u\n",
674 rtex->surface.stencil_tile_split);
675 fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
676 "slice_size=%"PRIu64", npix_x=%u, "
677 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
678 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
679 i, rtex->surface.stencil_level[i].offset,
680 rtex->surface.stencil_level[i].slice_size,
681 u_minify(rtex->resource.b.b.width0, i),
682 u_minify(rtex->resource.b.b.height0, i),
683 u_minify(rtex->resource.b.b.depth0, i),
684 rtex->surface.stencil_level[i].nblk_x,
685 rtex->surface.stencil_level[i].nblk_y,
686 rtex->surface.stencil_level[i].nblk_z,
687 rtex->surface.stencil_level[i].pitch_bytes,
688 rtex->surface.stencil_level[i].mode);
689 }
690 }
691 }
692
693 /* Common processing for r600_texture_create and r600_texture_from_handle */
694 static struct r600_texture *
695 r600_texture_create_object(struct pipe_screen *screen,
696 const struct pipe_resource *base,
697 unsigned pitch_in_bytes_override,
698 struct pb_buffer *buf,
699 struct radeon_surf *surface)
700 {
701 struct r600_texture *rtex;
702 struct r600_resource *resource;
703 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
704
705 rtex = CALLOC_STRUCT(r600_texture);
706 if (!rtex)
707 return NULL;
708
709 resource = &rtex->resource;
710 resource->b.b = *base;
711 resource->b.vtbl = &r600_texture_vtbl;
712 pipe_reference_init(&resource->b.b.reference, 1);
713 resource->b.b.screen = screen;
714
715 /* don't include stencil-only formats which we don't support for rendering */
716 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
717
718 rtex->surface = *surface;
719 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override)) {
720 FREE(rtex);
721 return NULL;
722 }
723
724 /* Tiled depth textures utilize the non-displayable tile order.
725 * This must be done after r600_setup_surface.
726 * Applies to R600-Cayman. */
727 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
728
729 if (rtex->is_depth) {
730 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
731 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
732 !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
733
734 r600_texture_allocate_htile(rscreen, rtex);
735 }
736 } else {
737 if (base->nr_samples > 1) {
738 if (!buf) {
739 r600_texture_allocate_fmask(rscreen, rtex);
740 r600_texture_allocate_cmask(rscreen, rtex);
741 rtex->cmask_buffer = &rtex->resource;
742 }
743 if (!rtex->fmask.size || !rtex->cmask.size) {
744 FREE(rtex);
745 return NULL;
746 }
747 }
748 if (rtex->surface.dcc_size)
749 vi_texture_alloc_dcc_separate(rscreen, rtex);
750 }
751
752 /* Now create the backing buffer. */
753 if (!buf) {
754 if (!r600_init_resource(rscreen, resource, rtex->size,
755 rtex->surface.bo_alignment, TRUE)) {
756 FREE(rtex);
757 return NULL;
758 }
759 } else {
760 resource->buf = buf;
761 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
762 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->cs_buf);
763 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->cs_buf);
764 }
765
766 if (rtex->cmask.size) {
767 /* Initialize the cmask to 0xCC (= compressed state). */
768 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
769 rtex->cmask.offset, rtex->cmask.size,
770 0xCCCCCCCC, true);
771 }
772
773 /* Initialize the CMASK base register value. */
774 rtex->cmask.base_address_reg =
775 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
776
777 if (rscreen->debug_flags & DBG_VM) {
778 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
779 rtex->resource.gpu_address,
780 rtex->resource.gpu_address + rtex->resource.buf->size,
781 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
782 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
783 }
784
785 if (rscreen->debug_flags & DBG_TEX) {
786 puts("Texture:");
787 r600_print_texture_info(rtex, stdout);
788 }
789
790 return rtex;
791 }
792
793 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
794 const struct pipe_resource *templ)
795 {
796 const struct util_format_description *desc = util_format_description(templ->format);
797 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
798
799 /* MSAA resources must be 2D tiled. */
800 if (templ->nr_samples > 1)
801 return RADEON_SURF_MODE_2D;
802
803 /* Transfer resources should be linear. */
804 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
805 return RADEON_SURF_MODE_LINEAR_ALIGNED;
806
807 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
808 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
809 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
810 (templ->target == PIPE_TEXTURE_2D ||
811 templ->target == PIPE_TEXTURE_3D))
812 force_tiling = true;
813
814 /* Handle common candidates for the linear mode.
815 * Compressed textures must always be tiled. */
816 if (!force_tiling && !util_format_is_compressed(templ->format)) {
817 /* Not everything can be linear, so we cannot enforce it
818 * for all textures. */
819 if ((rscreen->debug_flags & DBG_NO_TILING) &&
820 (!util_format_is_depth_or_stencil(templ->format) ||
821 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH)))
822 return RADEON_SURF_MODE_LINEAR_ALIGNED;
823
824 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
825 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
826 return RADEON_SURF_MODE_LINEAR_ALIGNED;
827
828 /* Cursors are linear on SI.
829 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
830 if (rscreen->chip_class >= SI &&
831 (templ->bind & PIPE_BIND_CURSOR))
832 return RADEON_SURF_MODE_LINEAR_ALIGNED;
833
834 if (templ->bind & PIPE_BIND_LINEAR)
835 return RADEON_SURF_MODE_LINEAR_ALIGNED;
836
837 /* Textures with a very small height are recommended to be linear. */
838 if (templ->target == PIPE_TEXTURE_1D ||
839 templ->target == PIPE_TEXTURE_1D_ARRAY ||
840 templ->height0 <= 4)
841 return RADEON_SURF_MODE_LINEAR_ALIGNED;
842
843 /* Textures likely to be mapped often. */
844 if (templ->usage == PIPE_USAGE_STAGING ||
845 templ->usage == PIPE_USAGE_STREAM)
846 return RADEON_SURF_MODE_LINEAR_ALIGNED;
847 }
848
849 /* Make small textures 1D tiled. */
850 if (templ->width0 <= 16 || templ->height0 <= 16 ||
851 (rscreen->debug_flags & DBG_NO_2D_TILING))
852 return RADEON_SURF_MODE_1D;
853
854 /* The allocator will switch to 1D if needed. */
855 return RADEON_SURF_MODE_2D;
856 }
857
858 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
859 const struct pipe_resource *templ)
860 {
861 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
862 struct radeon_surf surface = {0};
863 int r;
864
865 r = r600_init_surface(rscreen, &surface, templ,
866 r600_choose_tiling(rscreen, templ),
867 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
868 if (r) {
869 return NULL;
870 }
871 r = rscreen->ws->surface_best(rscreen->ws, &surface);
872 if (r) {
873 return NULL;
874 }
875 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
876 0, NULL, &surface);
877 }
878
879 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
880 const struct pipe_resource *templ,
881 struct winsys_handle *whandle)
882 {
883 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
884 struct pb_buffer *buf = NULL;
885 unsigned stride = 0;
886 unsigned array_mode;
887 enum radeon_bo_layout micro, macro;
888 struct radeon_surf surface;
889 bool scanout;
890 int r;
891
892 /* Support only 2D textures without mipmaps */
893 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
894 templ->depth0 != 1 || templ->last_level != 0)
895 return NULL;
896
897 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
898 if (!buf)
899 return NULL;
900
901 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
902 &surface.bankw, &surface.bankh,
903 &surface.tile_split,
904 &surface.stencil_tile_split,
905 &surface.mtilea, &scanout);
906
907 if (macro == RADEON_LAYOUT_TILED)
908 array_mode = RADEON_SURF_MODE_2D;
909 else if (micro == RADEON_LAYOUT_TILED)
910 array_mode = RADEON_SURF_MODE_1D;
911 else
912 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
913
914 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
915 if (r) {
916 return NULL;
917 }
918
919 if (scanout)
920 surface.flags |= RADEON_SURF_SCANOUT;
921
922 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
923 stride, buf, &surface);
924 }
925
926 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
927 struct pipe_resource *texture,
928 struct r600_texture **staging)
929 {
930 struct r600_texture *rtex = (struct r600_texture*)texture;
931 struct pipe_resource resource;
932 struct r600_texture **flushed_depth_texture = staging ?
933 staging : &rtex->flushed_depth_texture;
934
935 if (!staging && rtex->flushed_depth_texture)
936 return true; /* it's ready */
937
938 resource.target = texture->target;
939 resource.format = texture->format;
940 resource.width0 = texture->width0;
941 resource.height0 = texture->height0;
942 resource.depth0 = texture->depth0;
943 resource.array_size = texture->array_size;
944 resource.last_level = texture->last_level;
945 resource.nr_samples = texture->nr_samples;
946 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
947 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
948 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
949
950 if (staging)
951 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
952
953 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
954 if (*flushed_depth_texture == NULL) {
955 R600_ERR("failed to create temporary texture to hold flushed depth\n");
956 return false;
957 }
958
959 (*flushed_depth_texture)->is_flushing_texture = TRUE;
960 (*flushed_depth_texture)->non_disp_tiling = false;
961 return true;
962 }
963
964 /**
965 * Initialize the pipe_resource descriptor to be of the same size as the box,
966 * which is supposed to hold a subregion of the texture "orig" at the given
967 * mipmap level.
968 */
969 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
970 struct pipe_resource *orig,
971 const struct pipe_box *box,
972 unsigned level, unsigned flags)
973 {
974 memset(res, 0, sizeof(*res));
975 res->format = orig->format;
976 res->width0 = box->width;
977 res->height0 = box->height;
978 res->depth0 = 1;
979 res->array_size = 1;
980 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
981 res->flags = flags;
982
983 /* We must set the correct texture target and dimensions for a 3D box. */
984 if (box->depth > 1 && util_max_layer(orig, level) > 0)
985 res->target = orig->target;
986 else
987 res->target = PIPE_TEXTURE_2D;
988
989 switch (res->target) {
990 case PIPE_TEXTURE_1D_ARRAY:
991 case PIPE_TEXTURE_2D_ARRAY:
992 case PIPE_TEXTURE_CUBE_ARRAY:
993 res->array_size = box->depth;
994 break;
995 case PIPE_TEXTURE_3D:
996 res->depth0 = box->depth;
997 break;
998 default:;
999 }
1000 }
1001
1002 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1003 struct pipe_resource *texture,
1004 unsigned level,
1005 unsigned usage,
1006 const struct pipe_box *box,
1007 struct pipe_transfer **ptransfer)
1008 {
1009 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1010 struct r600_texture *rtex = (struct r600_texture*)texture;
1011 struct r600_transfer *trans;
1012 boolean use_staging_texture = FALSE;
1013 struct r600_resource *buf;
1014 unsigned offset = 0;
1015 char *map;
1016
1017 /* We cannot map a tiled texture directly because the data is
1018 * in a different order, therefore we do detiling using a blit.
1019 *
1020 * Also, use a temporary in GTT memory for read transfers, as
1021 * the CPU is much happier reading out of cached system memory
1022 * than uncached VRAM.
1023 */
1024 if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
1025 use_staging_texture = TRUE;
1026 } else if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
1027 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
1028 /* Untiled buffers in VRAM, which is slow for CPU reads */
1029 use_staging_texture = TRUE;
1030 } else if (!(usage & PIPE_TRANSFER_READ) &&
1031 (r600_rings_is_buffer_referenced(rctx, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
1032 !rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) {
1033 /* Use a staging texture for uploads if the underlying BO is busy. */
1034 use_staging_texture = TRUE;
1035 }
1036
1037 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
1038 use_staging_texture = FALSE;
1039 }
1040
1041 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
1042 return NULL;
1043 }
1044
1045 trans = CALLOC_STRUCT(r600_transfer);
1046 if (!trans)
1047 return NULL;
1048 trans->transfer.resource = texture;
1049 trans->transfer.level = level;
1050 trans->transfer.usage = usage;
1051 trans->transfer.box = *box;
1052
1053 if (rtex->is_depth) {
1054 struct r600_texture *staging_depth;
1055
1056 if (rtex->resource.b.b.nr_samples > 1) {
1057 /* MSAA depth buffers need to be converted to single sample buffers.
1058 *
1059 * Mapping MSAA depth buffers can occur if ReadPixels is called
1060 * with a multisample GLX visual.
1061 *
1062 * First downsample the depth buffer to a temporary texture,
1063 * then decompress the temporary one to staging.
1064 *
1065 * Only the region being mapped is transfered.
1066 */
1067 struct pipe_resource resource;
1068
1069 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1070
1071 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1072 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1073 FREE(trans);
1074 return NULL;
1075 }
1076
1077 if (usage & PIPE_TRANSFER_READ) {
1078 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1079 if (!temp) {
1080 R600_ERR("failed to create a temporary depth texture\n");
1081 FREE(trans);
1082 return NULL;
1083 }
1084
1085 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1086 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1087 0, 0, 0, box->depth, 0, 0);
1088 pipe_resource_reference(&temp, NULL);
1089 }
1090 }
1091 else {
1092 /* XXX: only readback the rectangle which is being mapped? */
1093 /* XXX: when discard is true, no need to read back from depth texture */
1094 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1095 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1096 FREE(trans);
1097 return NULL;
1098 }
1099
1100 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1101 level, level,
1102 box->z, box->z + box->depth - 1,
1103 0, 0);
1104
1105 offset = r600_texture_get_offset(staging_depth, level, box);
1106 }
1107
1108 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
1109 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1110 trans->staging = (struct r600_resource*)staging_depth;
1111 } else if (use_staging_texture) {
1112 struct pipe_resource resource;
1113 struct r600_texture *staging;
1114
1115 r600_init_temp_resource_from_box(&resource, texture, box, level,
1116 R600_RESOURCE_FLAG_TRANSFER);
1117 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1118 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1119
1120 /* Create the temporary texture. */
1121 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1122 if (!staging) {
1123 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1124 FREE(trans);
1125 return NULL;
1126 }
1127 trans->staging = &staging->resource;
1128 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1129 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1130 if (usage & PIPE_TRANSFER_READ) {
1131 r600_copy_to_staging_texture(ctx, trans);
1132 }
1133 } else {
1134 /* the resource is mapped directly */
1135 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1136 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1137 offset = r600_texture_get_offset(rtex, level, box);
1138 }
1139
1140 if (trans->staging) {
1141 buf = trans->staging;
1142 if (!rtex->is_depth && !(usage & PIPE_TRANSFER_READ))
1143 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1144 } else {
1145 buf = &rtex->resource;
1146 }
1147
1148 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1149 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1150 FREE(trans);
1151 return NULL;
1152 }
1153
1154 *ptransfer = &trans->transfer;
1155 return map + offset;
1156 }
1157
1158 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1159 struct pipe_transfer* transfer)
1160 {
1161 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1162 struct pipe_resource *texture = transfer->resource;
1163 struct r600_texture *rtex = (struct r600_texture*)texture;
1164
1165 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1166 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1167 ctx->resource_copy_region(ctx, texture, transfer->level,
1168 transfer->box.x, transfer->box.y, transfer->box.z,
1169 &rtransfer->staging->b.b, transfer->level,
1170 &transfer->box);
1171 } else {
1172 r600_copy_from_staging_texture(ctx, rtransfer);
1173 }
1174 }
1175
1176 if (rtransfer->staging)
1177 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1178
1179 FREE(transfer);
1180 }
1181
1182 static const struct u_resource_vtbl r600_texture_vtbl =
1183 {
1184 NULL, /* get_handle */
1185 r600_texture_destroy, /* resource_destroy */
1186 r600_texture_transfer_map, /* transfer_map */
1187 u_default_transfer_flush_region, /* transfer_flush_region */
1188 r600_texture_transfer_unmap, /* transfer_unmap */
1189 NULL /* transfer_inline_write */
1190 };
1191
1192 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1193 struct pipe_resource *texture,
1194 const struct pipe_surface *templ,
1195 unsigned width, unsigned height)
1196 {
1197 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1198
1199 if (!surface)
1200 return NULL;
1201
1202 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1203 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1204
1205 pipe_reference_init(&surface->base.reference, 1);
1206 pipe_resource_reference(&surface->base.texture, texture);
1207 surface->base.context = pipe;
1208 surface->base.format = templ->format;
1209 surface->base.width = width;
1210 surface->base.height = height;
1211 surface->base.u = templ->u;
1212 return &surface->base;
1213 }
1214
1215 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1216 struct pipe_resource *tex,
1217 const struct pipe_surface *templ)
1218 {
1219 unsigned level = templ->u.tex.level;
1220
1221 return r600_create_surface_custom(pipe, tex, templ,
1222 u_minify(tex->width0, level),
1223 u_minify(tex->height0, level));
1224 }
1225
1226 static void r600_surface_destroy(struct pipe_context *pipe,
1227 struct pipe_surface *surface)
1228 {
1229 struct r600_surface *surf = (struct r600_surface*)surface;
1230 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1231 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1232 pipe_resource_reference(&surface->texture, NULL);
1233 FREE(surface);
1234 }
1235
1236 unsigned r600_translate_colorswap(enum pipe_format format)
1237 {
1238 const struct util_format_description *desc = util_format_description(format);
1239
1240 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1241
1242 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1243 return V_0280A0_SWAP_STD;
1244
1245 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1246 return ~0U;
1247
1248 switch (desc->nr_channels) {
1249 case 1:
1250 if (HAS_SWIZZLE(0,X))
1251 return V_0280A0_SWAP_STD; /* X___ */
1252 else if (HAS_SWIZZLE(3,X))
1253 return V_0280A0_SWAP_ALT_REV; /* ___X */
1254 break;
1255 case 2:
1256 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1257 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1258 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1259 return V_0280A0_SWAP_STD; /* XY__ */
1260 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1261 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1262 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1263 return V_0280A0_SWAP_STD_REV; /* YX__ */
1264 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1265 return V_0280A0_SWAP_ALT; /* X__Y */
1266 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1267 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1268 break;
1269 case 3:
1270 if (HAS_SWIZZLE(0,X))
1271 return V_0280A0_SWAP_STD; /* XYZ */
1272 else if (HAS_SWIZZLE(0,Z))
1273 return V_0280A0_SWAP_STD_REV; /* ZYX */
1274 break;
1275 case 4:
1276 /* check the middle channels, the 1st and 4th channel can be NONE */
1277 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
1278 return V_0280A0_SWAP_STD; /* XYZW */
1279 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
1280 return V_0280A0_SWAP_STD_REV; /* WZYX */
1281 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
1282 return V_0280A0_SWAP_ALT; /* ZYXW */
1283 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
1284 return V_0280A0_SWAP_ALT_REV; /* WXYZ */
1285 break;
1286 }
1287 return ~0U;
1288 }
1289
1290 static void evergreen_set_clear_color(struct r600_texture *rtex,
1291 enum pipe_format surface_format,
1292 const union pipe_color_union *color)
1293 {
1294 union util_color uc;
1295
1296 memset(&uc, 0, sizeof(uc));
1297
1298 if (util_format_is_pure_uint(surface_format)) {
1299 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1300 } else if (util_format_is_pure_sint(surface_format)) {
1301 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1302 } else {
1303 util_pack_color(color->f, surface_format, &uc);
1304 }
1305
1306 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1307 }
1308
1309 static void vi_get_fast_clear_parameters(enum pipe_format surface_format,
1310 const union pipe_color_union *color,
1311 uint32_t* reset_value,
1312 bool* clear_words_needed)
1313 {
1314 bool values[4] = {};
1315 int i;
1316 bool main_value = false;
1317 bool extra_value = false;
1318 int extra_channel;
1319 const struct util_format_description *desc = util_format_description(surface_format);
1320
1321 *clear_words_needed = true;
1322 *reset_value = 0x20202020U;
1323
1324 /* If we want to clear without needing a fast clear eliminate step, we
1325 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1326 * have two sets of flags, one for the last or first channel(extra) and
1327 * one for the other channels(main).
1328 */
1329
1330 if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
1331 surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
1332 surface_format == PIPE_FORMAT_B5G6R5_SRGB) {
1333 extra_channel = -1;
1334 } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
1335 if(r600_translate_colorswap(surface_format) <= 1)
1336 extra_channel = desc->nr_channels - 1;
1337 else
1338 extra_channel = 0;
1339 } else
1340 return;
1341
1342 for (i = 0; i < 4; ++i) {
1343 int index = desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X;
1344
1345 if (desc->swizzle[i] < UTIL_FORMAT_SWIZZLE_X ||
1346 desc->swizzle[i] > UTIL_FORMAT_SWIZZLE_W)
1347 continue;
1348
1349 if (util_format_is_pure_sint(surface_format)) {
1350 values[i] = color->i[i] != 0;
1351 if (color->i[i] != 0 && color->i[i] != INT32_MAX)
1352 return;
1353 } else if (util_format_is_pure_uint(surface_format)) {
1354 values[i] = color->ui[i] != 0U;
1355 if (color->ui[i] != 0U && color->ui[i] != UINT32_MAX)
1356 return;
1357 } else {
1358 values[i] = color->f[i] != 0.0F;
1359 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
1360 return;
1361 }
1362
1363 if (index == extra_channel)
1364 extra_value = values[i];
1365 else
1366 main_value = values[i];
1367 }
1368
1369 for (int i = 0; i < 4; ++i)
1370 if (values[i] != main_value &&
1371 desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X != extra_channel &&
1372 desc->swizzle[i] >= UTIL_FORMAT_SWIZZLE_X &&
1373 desc->swizzle[i] <= UTIL_FORMAT_SWIZZLE_W)
1374 return;
1375
1376 *clear_words_needed = false;
1377 if (main_value)
1378 *reset_value |= 0x80808080U;
1379
1380 if (extra_value)
1381 *reset_value |= 0x40404040U;
1382 }
1383
1384 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1385 struct pipe_framebuffer_state *fb,
1386 struct r600_atom *fb_state,
1387 unsigned *buffers, unsigned *dirty_cbufs,
1388 const union pipe_color_union *color)
1389 {
1390 int i;
1391
1392 if (rctx->render_cond)
1393 return;
1394
1395 for (i = 0; i < fb->nr_cbufs; i++) {
1396 struct r600_texture *tex;
1397 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1398
1399 if (!fb->cbufs[i])
1400 continue;
1401
1402 /* if this colorbuffer is not being cleared */
1403 if (!(*buffers & clear_bit))
1404 continue;
1405
1406 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1407
1408 /* 128-bit formats are unusupported */
1409 if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
1410 continue;
1411 }
1412
1413 /* the clear is allowed if all layers are bound */
1414 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1415 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1416 continue;
1417 }
1418
1419 /* cannot clear mipmapped textures */
1420 if (fb->cbufs[i]->texture->last_level != 0) {
1421 continue;
1422 }
1423
1424 /* only supported on tiled surfaces */
1425 if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
1426 continue;
1427 }
1428
1429 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1430 if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
1431 rctx->chip_class >= CIK &&
1432 rctx->screen->info.drm_major == 2 &&
1433 rctx->screen->info.drm_minor < 38) {
1434 continue;
1435 }
1436
1437 if (tex->dcc_buffer) {
1438 uint32_t reset_value;
1439 bool clear_words_needed;
1440
1441 if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
1442 continue;
1443
1444 vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed);
1445
1446 rctx->clear_buffer(&rctx->b, &tex->dcc_buffer->b.b,
1447 0, tex->surface.dcc_size, reset_value, true);
1448
1449 if (clear_words_needed)
1450 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1451 } else {
1452 /* ensure CMASK is enabled */
1453 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1454 if (tex->cmask.size == 0) {
1455 continue;
1456 }
1457
1458 /* Do the fast clear. */
1459 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1460 tex->cmask.offset, tex->cmask.size, 0, true);
1461
1462 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1463 }
1464
1465 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1466
1467 if (dirty_cbufs)
1468 *dirty_cbufs |= 1 << i;
1469 rctx->set_atom_dirty(rctx, fb_state, true);
1470 *buffers &= ~clear_bit;
1471 }
1472 }
1473
1474 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1475 {
1476 rscreen->b.resource_from_handle = r600_texture_from_handle;
1477 rscreen->b.resource_get_handle = r600_texture_get_handle;
1478 }
1479
1480 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1481 {
1482 rctx->b.create_surface = r600_create_surface;
1483 rctx->b.surface_destroy = r600_surface_destroy;
1484 }