2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
41 const struct pipe_resource
*templ
);
44 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
45 struct r600_texture
*rdst
,
46 unsigned dst_level
, unsigned dstx
,
47 unsigned dsty
, unsigned dstz
,
48 struct r600_texture
*rsrc
,
50 const struct pipe_box
*src_box
)
55 if (util_format_get_blocksizebits(rdst
->resource
.b
.b
.format
) !=
56 util_format_get_blocksizebits(rsrc
->resource
.b
.b
.format
))
59 /* MSAA: Blits don't exist in the real world. */
60 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
61 rdst
->resource
.b
.b
.nr_samples
> 1)
64 /* Depth-stencil surfaces:
65 * When dst is linear, the DB->CB copy preserves HTILE.
66 * When dst is tiled, the 3D path must be used to update HTILE.
68 if (rsrc
->is_depth
|| rdst
->is_depth
)
72 * src: Use the 3D path. DCC decompression is expensive.
73 * dst: Use the 3D path to compress the pixels with DCC.
75 if ((rsrc
->dcc_offset
&& rsrc
->surface
.level
[src_level
].dcc_enabled
) ||
76 (rdst
->dcc_offset
&& rdst
->surface
.level
[dst_level
].dcc_enabled
))
80 * src: Both texture and SDMA paths need decompression. Use SDMA.
81 * dst: If overwriting the whole texture, discard CMASK and use
82 * SDMA. Otherwise, use the 3D path.
84 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
85 /* The CMASK clear is only enabled for the first level. */
86 assert(dst_level
== 0);
87 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
88 dstx
, dsty
, dstz
, src_box
->width
,
89 src_box
->height
, src_box
->depth
))
92 r600_texture_discard_cmask(rctx
->screen
, rdst
);
95 /* All requirements are met. Prepare textures for SDMA. */
96 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
97 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
99 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
100 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
105 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
106 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
107 struct pipe_resource
*dst
,
109 unsigned dstx
, unsigned dsty
, unsigned dstz
,
110 struct pipe_resource
*src
,
112 const struct pipe_box
*src_box
)
114 struct pipe_blit_info blit
;
116 memset(&blit
, 0, sizeof(blit
));
117 blit
.src
.resource
= src
;
118 blit
.src
.format
= src
->format
;
119 blit
.src
.level
= src_level
;
120 blit
.src
.box
= *src_box
;
121 blit
.dst
.resource
= dst
;
122 blit
.dst
.format
= dst
->format
;
123 blit
.dst
.level
= dst_level
;
124 blit
.dst
.box
.x
= dstx
;
125 blit
.dst
.box
.y
= dsty
;
126 blit
.dst
.box
.z
= dstz
;
127 blit
.dst
.box
.width
= src_box
->width
;
128 blit
.dst
.box
.height
= src_box
->height
;
129 blit
.dst
.box
.depth
= src_box
->depth
;
130 blit
.mask
= util_format_get_mask(src
->format
) &
131 util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
142 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
144 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1) {
148 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
160 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1) {
169 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
176 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
180 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
181 const struct pipe_box
*box
)
183 enum pipe_format format
= rtex
->resource
.b
.b
.format
;
185 return rtex
->surface
.level
[level
].offset
+
186 box
->z
* rtex
->surface
.level
[level
].slice_size
+
187 box
->y
/ util_format_get_blockheight(format
) * rtex
->surface
.level
[level
].pitch_bytes
+
188 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
191 static int r600_init_surface(struct r600_common_screen
*rscreen
,
192 struct radeon_surf
*surface
,
193 const struct pipe_resource
*ptex
,
195 bool is_flushed_depth
)
197 const struct util_format_description
*desc
=
198 util_format_description(ptex
->format
);
199 bool is_depth
, is_stencil
;
201 is_depth
= util_format_has_depth(desc
);
202 is_stencil
= util_format_has_stencil(desc
);
204 surface
->npix_x
= ptex
->width0
;
205 surface
->npix_y
= ptex
->height0
;
206 surface
->npix_z
= ptex
->depth0
;
207 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
208 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
210 surface
->array_size
= 1;
211 surface
->last_level
= ptex
->last_level
;
213 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
214 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
215 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
217 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
218 /* align byte per element on dword */
219 if (surface
->bpe
== 3) {
224 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
225 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
227 switch (ptex
->target
) {
228 case PIPE_TEXTURE_1D
:
229 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
231 case PIPE_TEXTURE_RECT
:
232 case PIPE_TEXTURE_2D
:
233 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
235 case PIPE_TEXTURE_3D
:
236 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
238 case PIPE_TEXTURE_1D_ARRAY
:
239 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
240 surface
->array_size
= ptex
->array_size
;
242 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d array */
243 assert(ptex
->array_size
% 6 == 0);
244 case PIPE_TEXTURE_2D_ARRAY
:
245 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
246 surface
->array_size
= ptex
->array_size
;
248 case PIPE_TEXTURE_CUBE
:
249 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
256 if (!is_flushed_depth
&& is_depth
) {
257 surface
->flags
|= RADEON_SURF_ZBUFFER
;
260 surface
->flags
|= RADEON_SURF_SBUFFER
|
261 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
264 if (rscreen
->chip_class
>= SI
) {
265 surface
->flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
268 if (rscreen
->chip_class
>= VI
&&
269 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
270 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
271 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
273 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
274 /* This should catch bugs in gallium users setting incorrect flags. */
275 assert(surface
->nsamples
== 1 &&
276 surface
->array_size
== 1 &&
277 surface
->npix_z
== 1 &&
278 surface
->last_level
== 0 &&
279 !(surface
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
281 surface
->flags
|= RADEON_SURF_SCANOUT
;
286 static int r600_setup_surface(struct pipe_screen
*screen
,
287 struct r600_texture
*rtex
,
288 unsigned pitch_in_bytes_override
,
291 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
295 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
300 rtex
->size
= rtex
->surface
.bo_size
;
302 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
303 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
306 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
307 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
308 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
312 for (i
= 0; i
< ARRAY_SIZE(rtex
->surface
.level
); ++i
)
313 rtex
->surface
.level
[i
].offset
+= offset
;
318 static void r600_texture_init_metadata(struct r600_texture
*rtex
,
319 struct radeon_bo_metadata
*metadata
)
321 struct radeon_surf
*surface
= &rtex
->surface
;
323 memset(metadata
, 0, sizeof(*metadata
));
324 metadata
->microtile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
325 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
326 metadata
->macrotile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
327 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
328 metadata
->pipe_config
= surface
->pipe_config
;
329 metadata
->bankw
= surface
->bankw
;
330 metadata
->bankh
= surface
->bankh
;
331 metadata
->tile_split
= surface
->tile_split
;
332 metadata
->mtilea
= surface
->mtilea
;
333 metadata
->num_banks
= surface
->num_banks
;
334 metadata
->stride
= surface
->level
[0].pitch_bytes
;
335 metadata
->scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
338 static void r600_dirty_all_framebuffer_states(struct r600_common_screen
*rscreen
)
340 p_atomic_inc(&rscreen
->dirty_fb_counter
);
343 static void r600_eliminate_fast_color_clear(struct r600_common_screen
*rscreen
,
344 struct r600_texture
*rtex
)
346 struct pipe_context
*ctx
= rscreen
->aux_context
;
348 pipe_mutex_lock(rscreen
->aux_context_lock
);
349 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
350 ctx
->flush(ctx
, NULL
, 0);
351 pipe_mutex_unlock(rscreen
->aux_context_lock
);
354 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
355 struct r600_texture
*rtex
)
357 if (!rtex
->cmask
.size
)
360 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
363 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
364 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
366 if (rscreen
->chip_class
>= SI
)
367 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
369 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
371 if (rtex
->cmask_buffer
!= &rtex
->resource
)
372 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
374 /* Notify all contexts about the change. */
375 r600_dirty_all_framebuffer_states(rscreen
);
376 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
379 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
381 /* We can't disable DCC if it can be written by another process. */
382 return rtex
->dcc_offset
&&
383 (!rtex
->resource
.is_shared
||
384 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
387 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
388 struct r600_texture
*rtex
)
390 if (!r600_can_disable_dcc(rtex
))
393 assert(rtex
->dcc_separate_buffer
== NULL
);
396 rtex
->dcc_offset
= 0;
398 /* Notify all contexts about the change. */
399 r600_dirty_all_framebuffer_states(rscreen
);
404 * Disable DCC for the texture. (first decompress, then discard metadata).
406 * There is unresolved multi-context synchronization issue between
407 * screen::aux_context and the current context. If applications do this with
408 * multiple contexts, it's already undefined behavior for them and we don't
409 * have to worry about that. The scenario is:
411 * If context 1 disables DCC and context 2 has queued commands that write
412 * to the texture via CB with DCC enabled, and the order of operations is
414 * context 2 queues draw calls rendering to the texture, but doesn't flush
415 * context 1 disables DCC and flushes
416 * context 1 & 2 reset descriptors and FB state
417 * context 2 flushes (new compressed tiles written by the draw calls)
418 * context 1 & 2 read garbage, because DCC is disabled, yet there are
421 * \param rctx the current context if you have one, or rscreen->aux_context
424 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
425 struct r600_texture
*rtex
)
427 struct r600_common_screen
*rscreen
= rctx
->screen
;
429 if (!r600_can_disable_dcc(rtex
))
432 if (&rctx
->b
== rscreen
->aux_context
)
433 pipe_mutex_lock(rscreen
->aux_context_lock
);
435 /* Decompress DCC. */
436 rctx
->decompress_dcc(&rctx
->b
, rtex
);
437 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
439 if (&rctx
->b
== rscreen
->aux_context
)
440 pipe_mutex_unlock(rscreen
->aux_context_lock
);
442 return r600_texture_discard_dcc(rscreen
, rtex
);
445 static void r600_degrade_tile_mode_to_linear(struct r600_common_context
*rctx
,
446 struct r600_texture
*rtex
,
447 bool invalidate_storage
)
449 struct pipe_screen
*screen
= rctx
->b
.screen
;
450 struct r600_texture
*new_tex
;
451 struct pipe_resource templ
= rtex
->resource
.b
.b
;
454 templ
.bind
|= PIPE_BIND_LINEAR
;
456 /* r600g doesn't react to dirty_tex_descriptor_counter */
457 if (rctx
->chip_class
< SI
)
460 if (rtex
->resource
.is_shared
||
461 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
)
464 /* This fails with MSAA, depth, and compressed textures. */
465 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
466 RADEON_SURF_MODE_LINEAR_ALIGNED
)
469 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
473 /* Copy the pixels to the new texture. */
474 if (!invalidate_storage
) {
475 for (i
= 0; i
<= templ
.last_level
; i
++) {
479 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
480 util_max_layer(&templ
, i
) + 1, &box
);
482 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
483 &rtex
->resource
.b
.b
, i
, &box
);
487 r600_texture_discard_cmask(rctx
->screen
, rtex
);
488 r600_texture_discard_dcc(rctx
->screen
, rtex
);
490 /* Replace the structure fields of rtex. */
491 rtex
->resource
.b
.b
.bind
= templ
.bind
;
492 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
493 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
494 rtex
->resource
.domains
= new_tex
->resource
.domains
;
495 rtex
->size
= new_tex
->size
;
496 rtex
->surface
= new_tex
->surface
;
497 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
498 rtex
->cb_color_info
= new_tex
->cb_color_info
;
499 rtex
->cmask
= new_tex
->cmask
; /* needed even without CMASK */
501 assert(!rtex
->htile_buffer
);
502 assert(!rtex
->cmask
.size
);
503 assert(!rtex
->fmask
.size
);
504 assert(!rtex
->dcc_offset
);
505 assert(!rtex
->is_depth
);
507 r600_texture_reference(&new_tex
, NULL
);
509 r600_dirty_all_framebuffer_states(rctx
->screen
);
510 p_atomic_inc(&rctx
->screen
->dirty_tex_descriptor_counter
);
513 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
514 struct pipe_resource
*resource
,
515 struct winsys_handle
*whandle
,
518 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
519 struct r600_common_context
*aux_context
=
520 (struct r600_common_context
*)rscreen
->aux_context
;
521 struct r600_resource
*res
= (struct r600_resource
*)resource
;
522 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
523 struct radeon_bo_metadata metadata
;
524 bool update_metadata
= false;
526 /* This is not supported now, but it might be required for OpenCL
527 * interop in the future.
529 if (resource
->target
!= PIPE_BUFFER
&&
530 (resource
->nr_samples
> 1 || rtex
->is_depth
))
533 if (resource
->target
!= PIPE_BUFFER
) {
534 /* Since shader image stores don't support DCC on VI,
535 * disable it for external clients that want write
538 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
539 if (r600_texture_disable_dcc(aux_context
, rtex
))
540 update_metadata
= true;
543 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
545 /* Eliminate fast clear (both CMASK and DCC) */
546 r600_eliminate_fast_color_clear(rscreen
, rtex
);
548 /* Disable CMASK if flush_resource isn't going
551 r600_texture_discard_cmask(rscreen
, rtex
);
555 if (!res
->is_shared
|| update_metadata
) {
556 r600_texture_init_metadata(rtex
, &metadata
);
557 if (rscreen
->query_opaque_metadata
)
558 rscreen
->query_opaque_metadata(rscreen
, rtex
,
561 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
565 if (res
->is_shared
) {
566 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
569 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
570 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
571 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
573 res
->is_shared
= true;
574 res
->external_usage
= usage
;
577 return rscreen
->ws
->buffer_get_handle(res
->buf
,
578 rtex
->surface
.level
[0].pitch_bytes
,
579 rtex
->surface
.level
[0].offset
,
580 rtex
->surface
.level
[0].slice_size
,
584 static void r600_texture_destroy(struct pipe_screen
*screen
,
585 struct pipe_resource
*ptex
)
587 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
588 struct r600_resource
*resource
= &rtex
->resource
;
590 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
592 r600_resource_reference(&rtex
->htile_buffer
, NULL
);
593 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
594 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
596 pb_reference(&resource
->buf
, NULL
);
597 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
598 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
602 static const struct u_resource_vtbl r600_texture_vtbl
;
604 /* The number of samples can be specified independently of the texture. */
605 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
606 struct r600_texture
*rtex
,
608 struct r600_fmask_info
*out
)
610 /* FMASK is allocated like an ordinary texture. */
611 struct radeon_surf fmask
= rtex
->surface
;
613 memset(out
, 0, sizeof(*out
));
615 fmask
.bo_alignment
= 0;
618 fmask
.flags
|= RADEON_SURF_FMASK
;
620 /* Force 2D tiling if it wasn't set. This may occur when creating
621 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
622 * destination buffer must have an FMASK too. */
623 fmask
.flags
= RADEON_SURF_CLR(fmask
.flags
, MODE
);
624 fmask
.flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
626 if (rscreen
->chip_class
>= SI
) {
627 fmask
.flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
630 switch (nr_samples
) {
634 if (rscreen
->chip_class
<= CAYMAN
) {
642 R600_ERR("Invalid sample count for FMASK allocation.\n");
646 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
647 * This can be fixed by writing a separate FMASK allocator specifically
648 * for R600-R700 asics. */
649 if (rscreen
->chip_class
<= R700
) {
653 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
654 R600_ERR("Got error in surface_init while allocating FMASK.\n");
658 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
660 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
661 if (out
->slice_tile_max
)
662 out
->slice_tile_max
-= 1;
664 out
->tile_mode_index
= fmask
.tiling_index
[0];
665 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
666 out
->bank_height
= fmask
.bankh
;
667 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
668 out
->size
= fmask
.bo_size
;
671 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
672 struct r600_texture
*rtex
)
674 r600_texture_get_fmask_info(rscreen
, rtex
,
675 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
677 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
678 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
681 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
682 struct r600_texture
*rtex
,
683 struct r600_cmask_info
*out
)
685 unsigned cmask_tile_width
= 8;
686 unsigned cmask_tile_height
= 8;
687 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
688 unsigned element_bits
= 4;
689 unsigned cmask_cache_bits
= 1024;
690 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
691 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
693 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
694 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
695 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
696 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
697 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
699 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
700 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
702 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
703 unsigned slice_bytes
=
704 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
706 assert(macro_tile_width
% 128 == 0);
707 assert(macro_tile_height
% 128 == 0);
709 out
->pitch
= pitch_elements
;
710 out
->height
= height
;
711 out
->xalign
= macro_tile_width
;
712 out
->yalign
= macro_tile_height
;
713 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
714 out
->alignment
= MAX2(256, base_align
);
715 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
716 align(slice_bytes
, base_align
);
719 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
720 struct r600_texture
*rtex
,
721 struct r600_cmask_info
*out
)
723 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
724 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
725 unsigned cl_width
, cl_height
;
740 case 16: /* Hawaii */
749 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
751 unsigned width
= align(rtex
->surface
.npix_x
, cl_width
*8);
752 unsigned height
= align(rtex
->surface
.npix_y
, cl_height
*8);
753 unsigned slice_elements
= (width
* height
) / (8*8);
755 /* Each element of CMASK is a nibble. */
756 unsigned slice_bytes
= slice_elements
/ 2;
759 out
->height
= height
;
760 out
->xalign
= cl_width
* 8;
761 out
->yalign
= cl_height
* 8;
762 out
->slice_tile_max
= (width
* height
) / (128*128);
763 if (out
->slice_tile_max
)
764 out
->slice_tile_max
-= 1;
766 out
->alignment
= MAX2(256, base_align
);
767 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
768 align(slice_bytes
, base_align
);
771 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
772 struct r600_texture
*rtex
)
774 if (rscreen
->chip_class
>= SI
) {
775 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
777 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
780 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
781 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
783 if (rscreen
->chip_class
>= SI
)
784 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
786 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
789 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
790 struct r600_texture
*rtex
)
792 if (rtex
->cmask_buffer
)
795 assert(rtex
->cmask
.size
== 0);
797 if (rscreen
->chip_class
>= SI
) {
798 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
800 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
803 rtex
->cmask_buffer
= (struct r600_resource
*)
804 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
805 PIPE_USAGE_DEFAULT
, rtex
->cmask
.size
);
806 if (rtex
->cmask_buffer
== NULL
) {
807 rtex
->cmask
.size
= 0;
811 /* update colorbuffer state bits */
812 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
814 if (rscreen
->chip_class
>= SI
)
815 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
817 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
819 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
822 static unsigned r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
823 struct r600_texture
*rtex
)
825 unsigned cl_width
, cl_height
, width
, height
;
826 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
827 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
829 if (rscreen
->chip_class
<= EVERGREEN
&&
830 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
833 /* HW bug on R6xx. */
834 if (rscreen
->chip_class
== R600
&&
835 (rtex
->surface
.level
[0].npix_x
> 7680 ||
836 rtex
->surface
.level
[0].npix_y
> 7680))
839 /* HTILE is broken with 1D tiling on old kernels and CIK. */
840 if (rscreen
->chip_class
>= CIK
&&
841 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
842 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
845 /* Overalign HTILE on P2 configs to work around GPU hangs in
846 * piglit/depthstencil-render-miplevels 585.
848 * This has been confirmed to help Kabini & Stoney, where the hangs
849 * are always reproducible. I think I have seen the test hang
850 * on Carrizo too, though it was very rare there.
852 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
881 width
= align(rtex
->surface
.npix_x
, cl_width
* 8);
882 height
= align(rtex
->surface
.npix_y
, cl_height
* 8);
884 slice_elements
= (width
* height
) / (8 * 8);
885 slice_bytes
= slice_elements
* 4;
887 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
888 base_align
= num_pipes
* pipe_interleave_bytes
;
890 rtex
->htile
.pitch
= width
;
891 rtex
->htile
.height
= height
;
892 rtex
->htile
.xalign
= cl_width
* 8;
893 rtex
->htile
.yalign
= cl_height
* 8;
895 return (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
896 align(slice_bytes
, base_align
);
899 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
900 struct r600_texture
*rtex
)
902 unsigned htile_size
= r600_texture_get_htile_size(rscreen
, rtex
);
907 rtex
->htile_buffer
= (struct r600_resource
*)
908 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
909 PIPE_USAGE_DEFAULT
, htile_size
);
910 if (rtex
->htile_buffer
== NULL
) {
911 /* this is not a fatal error as we can still keep rendering
912 * without htile buffer */
913 R600_ERR("Failed to create buffer object for htile buffer.\n");
915 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
, 0,
916 htile_size
, 0, R600_COHERENCY_NONE
);
920 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
)
924 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
925 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
926 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
927 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
928 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
929 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
930 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
931 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
932 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
934 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%"PRIu64
", bankw=%u, "
935 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
936 rtex
->surface
.bo_size
, rtex
->surface
.bo_alignment
, rtex
->surface
.bankw
,
937 rtex
->surface
.bankh
, rtex
->surface
.num_banks
, rtex
->surface
.mtilea
,
938 rtex
->surface
.tile_split
, rtex
->surface
.pipe_config
,
939 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
941 if (rtex
->fmask
.size
)
942 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
943 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
944 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
945 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
946 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
948 if (rtex
->cmask
.size
)
949 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch=%u, "
950 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
951 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
952 rtex
->cmask
.pitch
, rtex
->cmask
.height
, rtex
->cmask
.xalign
,
953 rtex
->cmask
.yalign
, rtex
->cmask
.slice_tile_max
);
955 if (rtex
->htile_buffer
)
956 fprintf(f
, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
957 "xalign=%u, yalign=%u\n",
958 rtex
->htile_buffer
->b
.b
.width0
,
959 rtex
->htile_buffer
->buf
->alignment
, rtex
->htile
.pitch
,
960 rtex
->htile
.height
, rtex
->htile
.xalign
, rtex
->htile
.yalign
);
962 if (rtex
->dcc_offset
) {
963 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%"PRIu64
"\n",
964 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
965 rtex
->surface
.dcc_alignment
);
966 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
967 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
968 "fast_clear_size=%"PRIu64
"\n",
969 i
, rtex
->surface
.level
[i
].dcc_enabled
,
970 rtex
->surface
.level
[i
].dcc_offset
,
971 rtex
->surface
.level
[i
].dcc_fast_clear_size
);
974 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
975 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
976 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
977 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
978 i
, rtex
->surface
.level
[i
].offset
,
979 rtex
->surface
.level
[i
].slice_size
,
980 u_minify(rtex
->resource
.b
.b
.width0
, i
),
981 u_minify(rtex
->resource
.b
.b
.height0
, i
),
982 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
983 rtex
->surface
.level
[i
].nblk_x
,
984 rtex
->surface
.level
[i
].nblk_y
,
985 rtex
->surface
.level
[i
].nblk_z
,
986 rtex
->surface
.level
[i
].pitch_bytes
,
987 rtex
->surface
.level
[i
].mode
);
989 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
990 fprintf(f
, " StencilLayout: tilesplit=%u\n",
991 rtex
->surface
.stencil_tile_split
);
992 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
993 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
994 "slice_size=%"PRIu64
", npix_x=%u, "
995 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
996 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
997 i
, rtex
->surface
.stencil_level
[i
].offset
,
998 rtex
->surface
.stencil_level
[i
].slice_size
,
999 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1000 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1001 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1002 rtex
->surface
.stencil_level
[i
].nblk_x
,
1003 rtex
->surface
.stencil_level
[i
].nblk_y
,
1004 rtex
->surface
.stencil_level
[i
].nblk_z
,
1005 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
1006 rtex
->surface
.stencil_level
[i
].mode
);
1011 /* Common processing for r600_texture_create and r600_texture_from_handle */
1012 static struct r600_texture
*
1013 r600_texture_create_object(struct pipe_screen
*screen
,
1014 const struct pipe_resource
*base
,
1015 unsigned pitch_in_bytes_override
,
1017 struct pb_buffer
*buf
,
1018 struct radeon_surf
*surface
)
1020 struct r600_texture
*rtex
;
1021 struct r600_resource
*resource
;
1022 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1024 rtex
= CALLOC_STRUCT(r600_texture
);
1028 resource
= &rtex
->resource
;
1029 resource
->b
.b
= *base
;
1030 resource
->b
.vtbl
= &r600_texture_vtbl
;
1031 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1032 resource
->b
.b
.screen
= screen
;
1034 /* don't include stencil-only formats which we don't support for rendering */
1035 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1037 rtex
->surface
= *surface
;
1038 if (r600_setup_surface(screen
, rtex
, pitch_in_bytes_override
, offset
)) {
1043 /* Tiled depth textures utilize the non-displayable tile order.
1044 * This must be done after r600_setup_surface.
1045 * Applies to R600-Cayman. */
1046 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1047 /* Applies to GCN. */
1048 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1050 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1051 * between frames, so the only thing that can enable separate DCC
1052 * with DRI2 is multiple slow clears within a frame.
1054 rtex
->ps_draw_ratio
= 0;
1056 if (rtex
->is_depth
) {
1057 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1058 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1059 rscreen
->chip_class
>= EVERGREEN
) {
1060 rtex
->can_sample_z
= !rtex
->surface
.depth_adjusted
;
1061 rtex
->can_sample_s
= !rtex
->surface
.stencil_adjusted
;
1063 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1064 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1065 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1066 rtex
->can_sample_z
= true;
1069 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1070 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1071 rtex
->db_compatible
= true;
1073 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1074 r600_texture_allocate_htile(rscreen
, rtex
);
1077 if (base
->nr_samples
> 1) {
1079 r600_texture_allocate_fmask(rscreen
, rtex
);
1080 r600_texture_allocate_cmask(rscreen
, rtex
);
1081 rtex
->cmask_buffer
= &rtex
->resource
;
1083 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1089 /* Shared textures must always set up DCC here.
1090 * If it's not present, it will be disabled by
1091 * apply_opaque_metadata later.
1093 if (rtex
->surface
.dcc_size
&&
1094 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1095 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1096 /* Reserve space for the DCC buffer. */
1097 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1098 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1102 /* Now create the backing buffer. */
1104 if (!r600_init_resource(rscreen
, resource
, rtex
->size
,
1105 rtex
->surface
.bo_alignment
)) {
1110 resource
->buf
= buf
;
1111 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1112 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1115 if (rtex
->cmask
.size
) {
1116 /* Initialize the cmask to 0xCC (= compressed state). */
1117 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1118 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1119 0xCCCCCCCC, R600_COHERENCY_NONE
);
1122 /* Initialize DCC only if the texture is not being imported. */
1123 if (!buf
&& rtex
->dcc_offset
) {
1124 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1126 rtex
->surface
.dcc_size
,
1127 0xFFFFFFFF, R600_COHERENCY_NONE
);
1130 /* Initialize the CMASK base register value. */
1131 rtex
->cmask
.base_address_reg
=
1132 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1134 if (rscreen
->debug_flags
& DBG_VM
) {
1135 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1136 rtex
->resource
.gpu_address
,
1137 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1138 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1139 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1142 if (rscreen
->debug_flags
& DBG_TEX
) {
1144 r600_print_texture_info(rtex
, stdout
);
1151 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
1152 const struct pipe_resource
*templ
)
1154 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1155 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1157 /* MSAA resources must be 2D tiled. */
1158 if (templ
->nr_samples
> 1)
1159 return RADEON_SURF_MODE_2D
;
1161 /* Transfer resources should be linear. */
1162 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1163 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1165 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1166 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1167 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1168 (templ
->target
== PIPE_TEXTURE_2D
||
1169 templ
->target
== PIPE_TEXTURE_3D
))
1170 force_tiling
= true;
1172 /* Handle common candidates for the linear mode.
1173 * Compressed textures and DB surfaces must always be tiled.
1175 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
1176 (!util_format_is_depth_or_stencil(templ
->format
) ||
1177 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
1178 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1179 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1181 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1182 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1183 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1185 /* Cursors are linear on SI.
1186 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1187 if (rscreen
->chip_class
>= SI
&&
1188 (templ
->bind
& PIPE_BIND_CURSOR
))
1189 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1191 if (templ
->bind
& PIPE_BIND_LINEAR
)
1192 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1194 /* Textures with a very small height are recommended to be linear. */
1195 if (templ
->target
== PIPE_TEXTURE_1D
||
1196 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1197 templ
->height0
<= 4)
1198 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1200 /* Textures likely to be mapped often. */
1201 if (templ
->usage
== PIPE_USAGE_STAGING
||
1202 templ
->usage
== PIPE_USAGE_STREAM
)
1203 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1206 /* Make small textures 1D tiled. */
1207 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1208 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1209 return RADEON_SURF_MODE_1D
;
1211 /* The allocator will switch to 1D if needed. */
1212 return RADEON_SURF_MODE_2D
;
1215 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1216 const struct pipe_resource
*templ
)
1218 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1219 struct radeon_surf surface
= {0};
1222 r
= r600_init_surface(rscreen
, &surface
, templ
,
1223 r600_choose_tiling(rscreen
, templ
),
1224 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1228 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
1232 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, 0,
1236 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1237 const struct pipe_resource
*templ
,
1238 struct winsys_handle
*whandle
,
1241 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1242 struct pb_buffer
*buf
= NULL
;
1243 unsigned stride
= 0, offset
= 0;
1244 unsigned array_mode
;
1245 struct radeon_surf surface
;
1247 struct radeon_bo_metadata metadata
= {};
1248 struct r600_texture
*rtex
;
1250 /* Support only 2D textures without mipmaps */
1251 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1252 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1255 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1259 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1261 surface
.pipe_config
= metadata
.pipe_config
;
1262 surface
.bankw
= metadata
.bankw
;
1263 surface
.bankh
= metadata
.bankh
;
1264 surface
.tile_split
= metadata
.tile_split
;
1265 surface
.mtilea
= metadata
.mtilea
;
1266 surface
.num_banks
= metadata
.num_banks
;
1268 if (metadata
.macrotile
== RADEON_LAYOUT_TILED
)
1269 array_mode
= RADEON_SURF_MODE_2D
;
1270 else if (metadata
.microtile
== RADEON_LAYOUT_TILED
)
1271 array_mode
= RADEON_SURF_MODE_1D
;
1273 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1275 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, false);
1280 if (metadata
.scanout
)
1281 surface
.flags
|= RADEON_SURF_SCANOUT
;
1283 rtex
= r600_texture_create_object(screen
, templ
, stride
,
1284 offset
, buf
, &surface
);
1288 rtex
->resource
.is_shared
= true;
1289 rtex
->resource
.external_usage
= usage
;
1291 if (rscreen
->apply_opaque_metadata
)
1292 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1294 return &rtex
->resource
.b
.b
;
1297 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1298 struct pipe_resource
*texture
,
1299 struct r600_texture
**staging
)
1301 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1302 struct pipe_resource resource
;
1303 struct r600_texture
**flushed_depth_texture
= staging
?
1304 staging
: &rtex
->flushed_depth_texture
;
1305 enum pipe_format pipe_format
= texture
->format
;
1308 if (rtex
->flushed_depth_texture
)
1309 return true; /* it's ready */
1311 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1312 switch (pipe_format
) {
1313 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1314 /* Save memory by not allocating the S plane. */
1315 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1317 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1318 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1319 /* Save memory bandwidth by not copying the
1320 * stencil part during flush.
1322 * This potentially increases memory bandwidth
1323 * if an application uses both Z and S texturing
1324 * simultaneously (a flushed Z24S8 texture
1325 * would be stored compactly), but how often
1326 * does that really happen?
1328 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1332 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1333 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1335 /* DB->CB copies to an 8bpp surface don't work. */
1336 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1340 resource
.target
= texture
->target
;
1341 resource
.format
= pipe_format
;
1342 resource
.width0
= texture
->width0
;
1343 resource
.height0
= texture
->height0
;
1344 resource
.depth0
= texture
->depth0
;
1345 resource
.array_size
= texture
->array_size
;
1346 resource
.last_level
= texture
->last_level
;
1347 resource
.nr_samples
= texture
->nr_samples
;
1348 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1349 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1350 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1353 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1355 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1356 if (*flushed_depth_texture
== NULL
) {
1357 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1361 (*flushed_depth_texture
)->non_disp_tiling
= false;
1366 * Initialize the pipe_resource descriptor to be of the same size as the box,
1367 * which is supposed to hold a subregion of the texture "orig" at the given
1370 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1371 struct pipe_resource
*orig
,
1372 const struct pipe_box
*box
,
1373 unsigned level
, unsigned flags
)
1375 memset(res
, 0, sizeof(*res
));
1376 res
->format
= orig
->format
;
1377 res
->width0
= box
->width
;
1378 res
->height0
= box
->height
;
1380 res
->array_size
= 1;
1381 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1384 /* We must set the correct texture target and dimensions for a 3D box. */
1385 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1386 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1387 res
->array_size
= box
->depth
;
1389 res
->target
= PIPE_TEXTURE_2D
;
1393 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1394 struct r600_texture
*rtex
,
1395 unsigned transfer_usage
,
1396 const struct pipe_box
*box
)
1398 /* r600g doesn't react to dirty_tex_descriptor_counter */
1399 return rscreen
->chip_class
>= SI
&&
1400 !rtex
->resource
.is_shared
&&
1401 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1402 rtex
->resource
.b
.b
.last_level
== 0 &&
1403 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1404 box
->x
, box
->y
, box
->z
,
1405 box
->width
, box
->height
,
1409 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1410 struct r600_texture
*rtex
)
1412 struct r600_common_screen
*rscreen
= rctx
->screen
;
1414 /* There is no point in discarding depth and tiled buffers. */
1415 assert(!rtex
->is_depth
);
1416 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
);
1418 /* Reallocate the buffer in the same pipe_resource. */
1419 r600_init_resource(rscreen
, &rtex
->resource
, rtex
->size
,
1420 rtex
->surface
.bo_alignment
);
1422 /* Initialize the CMASK base address (needed even without CMASK). */
1423 rtex
->cmask
.base_address_reg
=
1424 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1426 r600_dirty_all_framebuffer_states(rscreen
);
1427 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
1429 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1432 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1433 struct pipe_resource
*texture
,
1436 const struct pipe_box
*box
,
1437 struct pipe_transfer
**ptransfer
)
1439 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1440 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1441 struct r600_transfer
*trans
;
1442 struct r600_resource
*buf
;
1443 unsigned offset
= 0;
1445 bool use_staging_texture
= false;
1447 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1449 /* Depth textures use staging unconditionally. */
1450 if (!rtex
->is_depth
) {
1451 /* Degrade the tile mode if we get too many transfers on APUs.
1452 * On dGPUs, the staging texture is always faster.
1453 * Only count uploads that are at least 4x4 pixels large.
1455 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1457 box
->width
>= 4 && box
->height
>= 4 &&
1458 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1459 bool can_invalidate
=
1460 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1463 r600_degrade_tile_mode_to_linear(rctx
, rtex
,
1467 /* Tiled textures need to be converted into a linear texture for CPU
1468 * access. The staging texture is always linear and is placed in GART.
1470 * Reading from VRAM is slow, always use the staging texture in
1473 * Use the staging texture for uploads if the underlying BO
1476 if (rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
)
1477 use_staging_texture
= true;
1478 else if (usage
& PIPE_TRANSFER_READ
)
1479 use_staging_texture
= (rtex
->resource
.domains
&
1480 RADEON_DOMAIN_VRAM
) != 0;
1481 /* Write & linear only: */
1482 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1483 RADEON_USAGE_READWRITE
) ||
1484 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1485 RADEON_USAGE_READWRITE
)) {
1487 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1489 r600_texture_invalidate_storage(rctx
, rtex
);
1491 use_staging_texture
= true;
1495 trans
= CALLOC_STRUCT(r600_transfer
);
1498 trans
->transfer
.resource
= texture
;
1499 trans
->transfer
.level
= level
;
1500 trans
->transfer
.usage
= usage
;
1501 trans
->transfer
.box
= *box
;
1503 if (rtex
->is_depth
) {
1504 struct r600_texture
*staging_depth
;
1506 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1507 /* MSAA depth buffers need to be converted to single sample buffers.
1509 * Mapping MSAA depth buffers can occur if ReadPixels is called
1510 * with a multisample GLX visual.
1512 * First downsample the depth buffer to a temporary texture,
1513 * then decompress the temporary one to staging.
1515 * Only the region being mapped is transfered.
1517 struct pipe_resource resource
;
1519 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1521 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1522 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1527 if (usage
& PIPE_TRANSFER_READ
) {
1528 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1530 R600_ERR("failed to create a temporary depth texture\n");
1535 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1536 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1537 0, 0, 0, box
->depth
, 0, 0);
1538 pipe_resource_reference(&temp
, NULL
);
1542 /* XXX: only readback the rectangle which is being mapped? */
1543 /* XXX: when discard is true, no need to read back from depth texture */
1544 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1545 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1550 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1552 box
->z
, box
->z
+ box
->depth
- 1,
1555 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1558 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
1559 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
1560 trans
->staging
= (struct r600_resource
*)staging_depth
;
1561 buf
= trans
->staging
;
1562 } else if (use_staging_texture
) {
1563 struct pipe_resource resource
;
1564 struct r600_texture
*staging
;
1566 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1567 R600_RESOURCE_FLAG_TRANSFER
);
1568 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1569 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1571 /* Create the temporary texture. */
1572 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1574 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1578 trans
->staging
= &staging
->resource
;
1579 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
1580 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1582 if (usage
& PIPE_TRANSFER_READ
)
1583 r600_copy_to_staging_texture(ctx
, trans
);
1585 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1587 buf
= trans
->staging
;
1589 /* the resource is mapped directly */
1590 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
1591 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1592 offset
= r600_texture_get_offset(rtex
, level
, box
);
1593 buf
= &rtex
->resource
;
1596 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1597 r600_resource_reference(&trans
->staging
, NULL
);
1602 *ptransfer
= &trans
->transfer
;
1603 return map
+ offset
;
1606 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1607 struct pipe_transfer
* transfer
)
1609 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1610 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1611 struct pipe_resource
*texture
= transfer
->resource
;
1612 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1614 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1615 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1616 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1617 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1618 &rtransfer
->staging
->b
.b
, transfer
->level
,
1621 r600_copy_from_staging_texture(ctx
, rtransfer
);
1625 if (rtransfer
->staging
) {
1626 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1627 r600_resource_reference(&rtransfer
->staging
, NULL
);
1630 /* Heuristic for {upload, draw, upload, draw, ..}:
1632 * Flush the gfx IB if we've allocated too much texture storage.
1634 * The idea is that we don't want to build IBs that use too much
1635 * memory and put pressure on the kernel memory manager and we also
1636 * want to make temporary and invalidated buffers go idle ASAP to
1637 * decrease the total memory usage or make them reusable. The memory
1638 * usage will be slightly higher than given here because of the buffer
1639 * cache in the winsys.
1641 * The result is that the kernel memory manager is never a bottleneck.
1643 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1644 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1645 rctx
->num_alloc_tex_transfer_bytes
= 0;
1651 static const struct u_resource_vtbl r600_texture_vtbl
=
1653 NULL
, /* get_handle */
1654 r600_texture_destroy
, /* resource_destroy */
1655 r600_texture_transfer_map
, /* transfer_map */
1656 u_default_transfer_flush_region
, /* transfer_flush_region */
1657 r600_texture_transfer_unmap
, /* transfer_unmap */
1660 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1661 struct pipe_resource
*texture
,
1662 const struct pipe_surface
*templ
,
1663 unsigned width
, unsigned height
)
1665 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1666 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1671 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1672 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1674 pipe_reference_init(&surface
->base
.reference
, 1);
1675 pipe_resource_reference(&surface
->base
.texture
, texture
);
1676 surface
->base
.context
= pipe
;
1677 surface
->base
.format
= templ
->format
;
1678 surface
->base
.width
= width
;
1679 surface
->base
.height
= height
;
1680 surface
->base
.u
= templ
->u
;
1681 surface
->level_info
= &rtex
->surface
.level
[templ
->u
.tex
.level
];
1682 return &surface
->base
;
1685 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1686 struct pipe_resource
*tex
,
1687 const struct pipe_surface
*templ
)
1689 unsigned level
= templ
->u
.tex
.level
;
1690 unsigned width
= u_minify(tex
->width0
, level
);
1691 unsigned height
= u_minify(tex
->height0
, level
);
1693 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1694 const struct util_format_description
*tex_desc
1695 = util_format_description(tex
->format
);
1696 const struct util_format_description
*templ_desc
1697 = util_format_description(templ
->format
);
1699 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1701 /* Adjust size of surface if and only if the block width or
1702 * height is changed. */
1703 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1704 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1705 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1706 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1708 width
= nblks_x
* templ_desc
->block
.width
;
1709 height
= nblks_y
* templ_desc
->block
.height
;
1713 return r600_create_surface_custom(pipe
, tex
, templ
, width
, height
);
1716 static void r600_surface_destroy(struct pipe_context
*pipe
,
1717 struct pipe_surface
*surface
)
1719 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1720 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1721 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1722 pipe_resource_reference(&surface
->texture
, NULL
);
1726 static void r600_clear_texture(struct pipe_context
*pipe
,
1727 struct pipe_resource
*tex
,
1729 const struct pipe_box
*box
,
1732 struct pipe_screen
*screen
= pipe
->screen
;
1733 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1734 struct pipe_surface tmpl
= {{0}};
1735 struct pipe_surface
*sf
;
1736 const struct util_format_description
*desc
=
1737 util_format_description(tex
->format
);
1739 tmpl
.format
= tex
->format
;
1740 tmpl
.u
.tex
.first_layer
= box
->z
;
1741 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
1742 tmpl
.u
.tex
.level
= level
;
1743 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
1747 if (rtex
->is_depth
) {
1750 uint8_t stencil
= 0;
1752 /* Depth is always present. */
1753 clear
= PIPE_CLEAR_DEPTH
;
1754 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
1756 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1757 clear
|= PIPE_CLEAR_STENCIL
;
1758 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
1761 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
1763 box
->width
, box
->height
, false);
1765 union pipe_color_union color
;
1767 /* pipe_color_union requires the full vec4 representation. */
1768 if (util_format_is_pure_uint(tex
->format
))
1769 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
1770 else if (util_format_is_pure_sint(tex
->format
))
1771 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
1773 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
1775 if (screen
->is_format_supported(screen
, tex
->format
,
1777 PIPE_BIND_RENDER_TARGET
)) {
1778 pipe
->clear_render_target(pipe
, sf
, &color
,
1780 box
->width
, box
->height
, false);
1782 /* Software fallback - just for R9G9B9E5_FLOAT */
1783 util_clear_render_target(pipe
, sf
, &color
,
1785 box
->width
, box
->height
);
1788 pipe_surface_reference(&sf
, NULL
);
1791 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1793 const struct util_format_description
*desc
= util_format_description(format
);
1795 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1797 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1798 return V_0280A0_SWAP_STD
;
1800 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1803 switch (desc
->nr_channels
) {
1805 if (HAS_SWIZZLE(0,X
))
1806 return V_0280A0_SWAP_STD
; /* X___ */
1807 else if (HAS_SWIZZLE(3,X
))
1808 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1811 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1812 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1813 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1814 return V_0280A0_SWAP_STD
; /* XY__ */
1815 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1816 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1817 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1819 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
1820 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1821 return V_0280A0_SWAP_ALT
; /* X__Y */
1822 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1823 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1826 if (HAS_SWIZZLE(0,X
))
1827 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
1828 else if (HAS_SWIZZLE(0,Z
))
1829 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1832 /* check the middle channels, the 1st and 4th channel can be NONE */
1833 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
1834 return V_0280A0_SWAP_STD
; /* XYZW */
1835 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
1836 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1837 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
1838 return V_0280A0_SWAP_ALT
; /* ZYXW */
1839 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
1842 return V_0280A0_SWAP_ALT_REV
;
1844 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
1851 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
1853 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
1858 if (rctx
->dcc_stats
[slot
].query_active
)
1859 vi_separate_dcc_stop_query(&rctx
->b
,
1860 rctx
->dcc_stats
[slot
].tex
);
1862 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
1863 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
1864 rctx
->b
.destroy_query(&rctx
->b
,
1865 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
1866 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
1869 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
1873 * Return the per-context slot where DCC statistics queries for the texture live.
1875 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
1876 struct r600_texture
*tex
)
1878 int i
, empty_slot
= -1;
1880 /* Remove zombie textures (textures kept alive by this array only). */
1881 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
1882 if (rctx
->dcc_stats
[i
].tex
&&
1883 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
1884 vi_dcc_clean_up_context_slot(rctx
, i
);
1886 /* Find the texture. */
1887 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
1888 /* Return if found. */
1889 if (rctx
->dcc_stats
[i
].tex
== tex
) {
1890 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
1894 /* Record the first seen empty slot. */
1895 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
1899 /* Not found. Remove the oldest member to make space in the array. */
1900 if (empty_slot
== -1) {
1901 int oldest_slot
= 0;
1903 /* Find the oldest slot. */
1904 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
1905 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
1906 rctx
->dcc_stats
[i
].last_use_timestamp
)
1909 /* Clean up the oldest slot. */
1910 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
1911 empty_slot
= oldest_slot
;
1914 /* Add the texture to the new slot. */
1915 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
1916 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
1920 static struct pipe_query
*
1921 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
1923 struct r600_query_hw
*query
= (struct r600_query_hw
*)
1924 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
1926 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
1927 return (struct pipe_query
*)query
;
1931 * Called when binding a color buffer.
1933 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
1934 struct r600_texture
*tex
)
1936 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1937 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
1939 assert(!rctx
->dcc_stats
[i
].query_active
);
1941 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
1942 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
1944 /* begin or resume the query */
1945 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
1946 rctx
->dcc_stats
[i
].query_active
= true;
1950 * Called when unbinding a color buffer.
1952 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
1953 struct r600_texture
*tex
)
1955 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1956 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
1958 assert(rctx
->dcc_stats
[i
].query_active
);
1959 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
1961 /* pause or end the query */
1962 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
1963 rctx
->dcc_stats
[i
].query_active
= false;
1966 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
1968 /* The minimum number of fullscreen draws per frame that is required
1970 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
1973 /* Called by fast clear. */
1974 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
1975 struct r600_texture
*tex
)
1977 /* The intent is to use this with shared displayable back buffers,
1978 * but it's not strictly limited only to them.
1980 if (!tex
->resource
.is_shared
||
1981 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
1982 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
1983 tex
->surface
.last_level
> 0 ||
1984 !tex
->surface
.dcc_size
)
1987 if (tex
->dcc_offset
)
1988 return; /* already enabled */
1990 /* Enable the DCC stat gathering. */
1991 if (!tex
->dcc_gather_statistics
) {
1992 tex
->dcc_gather_statistics
= true;
1993 vi_separate_dcc_start_query(&rctx
->b
, tex
);
1996 if (!vi_should_enable_separate_dcc(tex
))
1997 return; /* stats show that DCC decompression is too expensive */
1999 assert(tex
->surface
.level
[0].dcc_enabled
);
2000 assert(!tex
->dcc_separate_buffer
);
2002 r600_texture_discard_cmask(rctx
->screen
, tex
);
2004 /* Get a DCC buffer. */
2005 if (tex
->last_dcc_separate_buffer
) {
2006 assert(tex
->dcc_gather_statistics
);
2007 assert(!tex
->dcc_separate_buffer
);
2008 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2009 tex
->last_dcc_separate_buffer
= NULL
;
2011 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2012 r600_aligned_buffer_create(rctx
->b
.screen
, 0,
2014 tex
->surface
.dcc_size
,
2015 tex
->surface
.dcc_alignment
);
2016 if (!tex
->dcc_separate_buffer
)
2020 /* dcc_offset is the absolute GPUVM address. */
2021 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2023 /* no need to flag anything since this is called by fast clear that
2024 * flags framebuffer state
2029 * Called by pipe_context::flush_resource, the place where DCC decompression
2032 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2033 struct r600_texture
*tex
)
2035 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2036 struct pipe_query
*tmp
;
2037 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2038 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2039 bool disable
= false;
2041 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2042 union pipe_query_result result
;
2044 /* Read the results. */
2045 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2047 r600_query_hw_reset_buffers(rctx
,
2048 (struct r600_query_hw
*)
2049 rctx
->dcc_stats
[i
].ps_stats
[2]);
2051 /* Compute the approximate number of fullscreen draws. */
2052 tex
->ps_draw_ratio
=
2053 result
.pipeline_statistics
.ps_invocations
/
2054 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2055 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2057 disable
= tex
->dcc_separate_buffer
&&
2058 !vi_should_enable_separate_dcc(tex
);
2061 tex
->num_slow_clears
= 0;
2063 /* stop the statistics query for ps_stats[0] */
2065 vi_separate_dcc_stop_query(ctx
, tex
);
2067 /* Move the queries in the queue by one. */
2068 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2069 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2070 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2071 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2073 /* create and start a new query as ps_stats[0] */
2075 vi_separate_dcc_start_query(ctx
, tex
);
2078 assert(!tex
->last_dcc_separate_buffer
);
2079 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2080 tex
->dcc_separate_buffer
= NULL
;
2081 tex
->dcc_offset
= 0;
2082 /* no need to flag anything since this is called after
2083 * decompression that re-sets framebuffer state
2088 /* FAST COLOR CLEAR */
2090 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2091 enum pipe_format surface_format
,
2092 const union pipe_color_union
*color
)
2094 union util_color uc
;
2096 memset(&uc
, 0, sizeof(uc
));
2098 if (util_format_is_pure_uint(surface_format
)) {
2099 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2100 } else if (util_format_is_pure_sint(surface_format
)) {
2101 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2103 util_pack_color(color
->f
, surface_format
, &uc
);
2106 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2109 static void vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2110 const union pipe_color_union
*color
,
2111 uint32_t* reset_value
,
2112 bool* clear_words_needed
)
2114 bool values
[4] = {};
2116 bool main_value
= false;
2117 bool extra_value
= false;
2119 const struct util_format_description
*desc
= util_format_description(surface_format
);
2121 *clear_words_needed
= true;
2122 *reset_value
= 0x20202020U
;
2124 /* If we want to clear without needing a fast clear eliminate step, we
2125 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2126 * have two sets of flags, one for the last or first channel(extra) and
2127 * one for the other channels(main).
2130 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2131 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2132 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
2134 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2135 if(r600_translate_colorswap(surface_format
, false) <= 1)
2136 extra_channel
= desc
->nr_channels
- 1;
2142 for (i
= 0; i
< 4; ++i
) {
2143 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2145 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2146 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2149 if (util_format_is_pure_sint(surface_format
)) {
2150 values
[i
] = color
->i
[i
] != 0;
2151 if (color
->i
[i
] != 0 && color
->i
[i
] != INT32_MAX
)
2153 } else if (util_format_is_pure_uint(surface_format
)) {
2154 values
[i
] = color
->ui
[i
] != 0U;
2155 if (color
->ui
[i
] != 0U && color
->ui
[i
] != UINT32_MAX
)
2158 values
[i
] = color
->f
[i
] != 0.0F
;
2159 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2163 if (index
== extra_channel
)
2164 extra_value
= values
[i
];
2166 main_value
= values
[i
];
2169 for (int i
= 0; i
< 4; ++i
)
2170 if (values
[i
] != main_value
&&
2171 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2172 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2173 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2176 *clear_words_needed
= false;
2178 *reset_value
|= 0x80808080U
;
2181 *reset_value
|= 0x40404040U
;
2184 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2185 struct r600_texture
*rtex
,
2186 unsigned level
, unsigned clear_value
)
2188 struct pipe_resource
*dcc_buffer
;
2189 uint64_t dcc_offset
;
2191 assert(rtex
->dcc_offset
&& rtex
->surface
.level
[level
].dcc_enabled
);
2193 if (rtex
->dcc_separate_buffer
) {
2194 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2197 dcc_buffer
= &rtex
->resource
.b
.b
;
2198 dcc_offset
= rtex
->dcc_offset
;
2201 dcc_offset
+= rtex
->surface
.level
[level
].dcc_offset
;
2203 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
,
2204 rtex
->surface
.level
[level
].dcc_fast_clear_size
,
2205 clear_value
, R600_COHERENCY_CB_META
);
2208 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2209 * This allows hitting the MSAA resolve fast path, which requires that both
2210 * src and dst micro tile modes match.
2212 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2213 struct r600_texture
*rtex
)
2215 if (rtex
->resource
.is_shared
||
2216 rtex
->surface
.nsamples
<= 1 ||
2217 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2220 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2221 assert(rtex
->surface
.last_level
== 0);
2223 /* These magic numbers were copied from addrlib. It doesn't use any
2224 * definitions for them either. They are all 2D_TILED_THIN1 modes with
2225 * different bpp and micro tile mode.
2227 if (rscreen
->chip_class
>= CIK
) {
2228 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2229 case 0: /* displayable */
2230 rtex
->surface
.tiling_index
[0] = 10;
2233 rtex
->surface
.tiling_index
[0] = 14;
2235 case 3: /* rotated */
2236 rtex
->surface
.tiling_index
[0] = 28;
2238 default: /* depth, thick */
2239 assert(!"unexpected micro mode");
2243 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2244 case 0: /* displayable */
2245 switch (rtex
->surface
.bpe
) {
2247 rtex
->surface
.tiling_index
[0] = 10;
2250 rtex
->surface
.tiling_index
[0] = 11;
2252 default: /* 32, 64 */
2253 rtex
->surface
.tiling_index
[0] = 12;
2258 switch (rtex
->surface
.bpe
) {
2260 rtex
->surface
.tiling_index
[0] = 14;
2263 rtex
->surface
.tiling_index
[0] = 15;
2266 rtex
->surface
.tiling_index
[0] = 16;
2268 default: /* 64, 128 */
2269 rtex
->surface
.tiling_index
[0] = 17;
2273 default: /* depth, thick */
2274 assert(!"unexpected micro mode");
2279 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2281 p_atomic_inc(&rscreen
->dirty_fb_counter
);
2282 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
2285 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2286 struct pipe_framebuffer_state
*fb
,
2287 struct r600_atom
*fb_state
,
2288 unsigned *buffers
, unsigned *dirty_cbufs
,
2289 const union pipe_color_union
*color
)
2293 /* This function is broken in BE, so just disable this path for now */
2294 #ifdef PIPE_ARCH_BIG_ENDIAN
2298 if (rctx
->render_cond
)
2301 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2302 struct r600_texture
*tex
;
2303 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2308 /* if this colorbuffer is not being cleared */
2309 if (!(*buffers
& clear_bit
))
2312 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2314 /* 128-bit formats are unusupported */
2315 if (util_format_get_blocksizebits(fb
->cbufs
[i
]->format
) > 64) {
2319 /* the clear is allowed if all layers are bound */
2320 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2321 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2325 /* cannot clear mipmapped textures */
2326 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2330 /* only supported on tiled surfaces */
2331 if (tex
->surface
.level
[0].mode
< RADEON_SURF_MODE_1D
) {
2335 /* shared textures can't use fast clear without an explicit flush,
2336 * because there is no way to communicate the clear color among
2339 if (tex
->resource
.is_shared
&&
2340 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2343 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2344 if (tex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2345 rctx
->chip_class
>= CIK
&&
2346 rctx
->screen
->info
.drm_major
== 2 &&
2347 rctx
->screen
->info
.drm_minor
< 38) {
2351 /* Fast clear is the most appropriate place to enable DCC for
2352 * displayable surfaces.
2354 if (rctx
->chip_class
>= VI
&&
2355 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2356 vi_separate_dcc_try_enable(rctx
, tex
);
2358 /* Stoney can't do a CMASK-based clear, so all clears are
2359 * considered to be hypothetically slow clears, which
2360 * is weighed when determining to enable separate DCC.
2362 if (tex
->dcc_gather_statistics
&&
2363 rctx
->family
== CHIP_STONEY
)
2364 tex
->num_slow_clears
++;
2367 /* Try to clear DCC first, otherwise try CMASK. */
2368 if (tex
->dcc_offset
&& tex
->surface
.level
[0].dcc_enabled
) {
2369 uint32_t reset_value
;
2370 bool clear_words_needed
;
2372 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2375 /* We can change the micro tile mode before a full clear. */
2376 if (rctx
->screen
->chip_class
>= SI
)
2377 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2379 vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
, color
, &reset_value
, &clear_words_needed
);
2380 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2382 if (clear_words_needed
)
2383 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2384 tex
->separate_dcc_dirty
= true;
2386 /* Stoney/RB+ doesn't work with CMASK fast clear. */
2387 if (rctx
->family
== CHIP_STONEY
)
2390 /* ensure CMASK is enabled */
2391 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2392 if (tex
->cmask
.size
== 0) {
2396 /* We can change the micro tile mode before a full clear. */
2397 if (rctx
->screen
->chip_class
>= SI
)
2398 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2400 /* Do the fast clear. */
2401 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2402 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2403 R600_COHERENCY_CB_META
);
2405 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2408 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2411 *dirty_cbufs
|= 1 << i
;
2412 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2413 *buffers
&= ~clear_bit
;
2417 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2419 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2420 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2423 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2425 rctx
->b
.create_surface
= r600_create_surface
;
2426 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2427 rctx
->b
.clear_texture
= r600_clear_texture
;