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gallium/radeon: remember that texture_from_handle was called and its flags
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include <errno.h>
33 #include <inttypes.h>
34
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context *pipe,
37 struct pipe_resource *dst,
38 unsigned dst_level,
39 unsigned dstx, unsigned dsty, unsigned dstz,
40 struct pipe_resource *src,
41 unsigned src_level,
42 const struct pipe_box *src_box)
43 {
44 struct pipe_blit_info blit;
45
46 memset(&blit, 0, sizeof(blit));
47 blit.src.resource = src;
48 blit.src.format = src->format;
49 blit.src.level = src_level;
50 blit.src.box = *src_box;
51 blit.dst.resource = dst;
52 blit.dst.format = dst->format;
53 blit.dst.level = dst_level;
54 blit.dst.box.x = dstx;
55 blit.dst.box.y = dsty;
56 blit.dst.box.z = dstz;
57 blit.dst.box.width = src_box->width;
58 blit.dst.box.height = src_box->height;
59 blit.dst.box.depth = src_box->depth;
60 blit.mask = util_format_get_mask(src->format) &
61 util_format_get_mask(dst->format);
62 blit.filter = PIPE_TEX_FILTER_NEAREST;
63
64 if (blit.mask) {
65 pipe->blit(pipe, &blit);
66 }
67 }
68
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
71 {
72 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
73 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
74 struct pipe_resource *dst = &rtransfer->staging->b.b;
75 struct pipe_resource *src = transfer->resource;
76
77 if (src->nr_samples > 1) {
78 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
79 src, transfer->level, &transfer->box);
80 return;
81 }
82
83 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
84 &transfer->box);
85 }
86
87 /* Copy from a transfer's staging texture to a full GPU one. */
88 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
89 {
90 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
91 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
92 struct pipe_resource *dst = transfer->resource;
93 struct pipe_resource *src = &rtransfer->staging->b.b;
94 struct pipe_box sbox;
95
96 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
97
98 if (dst->nr_samples > 1) {
99 r600_copy_region_with_blit(ctx, dst, transfer->level,
100 transfer->box.x, transfer->box.y, transfer->box.z,
101 src, 0, &sbox);
102 return;
103 }
104
105 rctx->dma_copy(ctx, dst, transfer->level,
106 transfer->box.x, transfer->box.y, transfer->box.z,
107 src, 0, &sbox);
108 }
109
110 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
111 const struct pipe_box *box)
112 {
113 enum pipe_format format = rtex->resource.b.b.format;
114
115 return rtex->surface.level[level].offset +
116 box->z * rtex->surface.level[level].slice_size +
117 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
118 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
119 }
120
121 static int r600_init_surface(struct r600_common_screen *rscreen,
122 struct radeon_surf *surface,
123 const struct pipe_resource *ptex,
124 unsigned array_mode,
125 bool is_flushed_depth)
126 {
127 const struct util_format_description *desc =
128 util_format_description(ptex->format);
129 bool is_depth, is_stencil;
130
131 is_depth = util_format_has_depth(desc);
132 is_stencil = util_format_has_stencil(desc);
133
134 surface->npix_x = ptex->width0;
135 surface->npix_y = ptex->height0;
136 surface->npix_z = ptex->depth0;
137 surface->blk_w = util_format_get_blockwidth(ptex->format);
138 surface->blk_h = util_format_get_blockheight(ptex->format);
139 surface->blk_d = 1;
140 surface->array_size = 1;
141 surface->last_level = ptex->last_level;
142
143 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
144 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
145 surface->bpe = 4; /* stencil is allocated separately on evergreen */
146 } else {
147 surface->bpe = util_format_get_blocksize(ptex->format);
148 /* align byte per element on dword */
149 if (surface->bpe == 3) {
150 surface->bpe = 4;
151 }
152 }
153
154 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
155 surface->flags = RADEON_SURF_SET(array_mode, MODE);
156
157 switch (ptex->target) {
158 case PIPE_TEXTURE_1D:
159 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
160 break;
161 case PIPE_TEXTURE_RECT:
162 case PIPE_TEXTURE_2D:
163 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
164 break;
165 case PIPE_TEXTURE_3D:
166 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
167 break;
168 case PIPE_TEXTURE_1D_ARRAY:
169 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
170 surface->array_size = ptex->array_size;
171 break;
172 case PIPE_TEXTURE_2D_ARRAY:
173 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
175 surface->array_size = ptex->array_size;
176 break;
177 case PIPE_TEXTURE_CUBE:
178 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
179 break;
180 case PIPE_BUFFER:
181 default:
182 return -EINVAL;
183 }
184 if (ptex->bind & PIPE_BIND_SCANOUT) {
185 surface->flags |= RADEON_SURF_SCANOUT;
186 }
187
188 if (!is_flushed_depth && is_depth) {
189 surface->flags |= RADEON_SURF_ZBUFFER;
190
191 if (is_stencil) {
192 surface->flags |= RADEON_SURF_SBUFFER |
193 RADEON_SURF_HAS_SBUFFER_MIPTREE;
194 }
195 }
196 if (rscreen->chip_class >= SI) {
197 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
198 }
199 return 0;
200 }
201
202 static int r600_setup_surface(struct pipe_screen *screen,
203 struct r600_texture *rtex,
204 unsigned pitch_in_bytes_override)
205 {
206 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
207 int r;
208
209 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
210 if (r) {
211 return r;
212 }
213
214 rtex->size = rtex->surface.bo_size;
215
216 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
217 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
218 * for those
219 */
220 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
221 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
222 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
223 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
224 rtex->surface.stencil_offset =
225 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
226 }
227 }
228 return 0;
229 }
230
231 static void r600_texture_init_metadata(struct r600_texture *rtex,
232 struct radeon_bo_metadata *metadata)
233 {
234 struct radeon_surf *surface = &rtex->surface;
235
236 memset(metadata, 0, sizeof(*metadata));
237 metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
238 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
239 metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
240 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
241 metadata->pipe_config = surface->pipe_config;
242 metadata->bankw = surface->bankw;
243 metadata->bankh = surface->bankh;
244 metadata->tile_split = surface->tile_split;
245 metadata->stencil_tile_split = surface->stencil_tile_split;
246 metadata->mtilea = surface->mtilea;
247 metadata->num_banks = surface->num_banks;
248 metadata->stride = surface->level[0].pitch_bytes;
249 metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
250 }
251
252 static boolean r600_texture_get_handle(struct pipe_screen* screen,
253 struct pipe_resource *resource,
254 struct winsys_handle *whandle,
255 unsigned usage)
256 {
257 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
258 struct r600_resource *res = (struct r600_resource*)resource;
259 struct r600_texture *rtex = (struct r600_texture*)resource;
260 struct radeon_bo_metadata metadata;
261
262 if (!res->is_shared) {
263 res->is_shared = true;
264 res->external_usage = usage;
265
266 if (resource->target != PIPE_BUFFER) {
267 r600_texture_init_metadata(rtex, &metadata);
268 rscreen->ws->buffer_set_metadata(res->buf, &metadata);
269 }
270 } else {
271 assert(res->external_usage == usage);
272 }
273
274 return rscreen->ws->buffer_get_handle(res->buf,
275 rtex->surface.level[0].pitch_bytes,
276 whandle);
277 }
278
279 static void r600_texture_destroy(struct pipe_screen *screen,
280 struct pipe_resource *ptex)
281 {
282 struct r600_texture *rtex = (struct r600_texture*)ptex;
283 struct r600_resource *resource = &rtex->resource;
284
285 if (rtex->flushed_depth_texture)
286 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
287
288 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
289 if (rtex->cmask_buffer != &rtex->resource) {
290 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
291 }
292 pipe_resource_reference((struct pipe_resource**)&rtex->dcc_buffer, NULL);
293 pb_reference(&resource->buf, NULL);
294 FREE(rtex);
295 }
296
297 static const struct u_resource_vtbl r600_texture_vtbl;
298
299 /* The number of samples can be specified independently of the texture. */
300 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
301 struct r600_texture *rtex,
302 unsigned nr_samples,
303 struct r600_fmask_info *out)
304 {
305 /* FMASK is allocated like an ordinary texture. */
306 struct radeon_surf fmask = rtex->surface;
307
308 memset(out, 0, sizeof(*out));
309
310 fmask.bo_alignment = 0;
311 fmask.bo_size = 0;
312 fmask.nsamples = 1;
313 fmask.flags |= RADEON_SURF_FMASK;
314
315 /* Force 2D tiling if it wasn't set. This may occur when creating
316 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
317 * destination buffer must have an FMASK too. */
318 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
319 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
320
321 if (rscreen->chip_class >= SI) {
322 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
323 }
324
325 switch (nr_samples) {
326 case 2:
327 case 4:
328 fmask.bpe = 1;
329 if (rscreen->chip_class <= CAYMAN) {
330 fmask.bankh = 4;
331 }
332 break;
333 case 8:
334 fmask.bpe = 4;
335 break;
336 default:
337 R600_ERR("Invalid sample count for FMASK allocation.\n");
338 return;
339 }
340
341 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
342 * This can be fixed by writing a separate FMASK allocator specifically
343 * for R600-R700 asics. */
344 if (rscreen->chip_class <= R700) {
345 fmask.bpe *= 2;
346 }
347
348 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
349 R600_ERR("Got error in surface_init while allocating FMASK.\n");
350 return;
351 }
352
353 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
354
355 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
356 if (out->slice_tile_max)
357 out->slice_tile_max -= 1;
358
359 out->tile_mode_index = fmask.tiling_index[0];
360 out->pitch_in_pixels = fmask.level[0].nblk_x;
361 out->bank_height = fmask.bankh;
362 out->alignment = MAX2(256, fmask.bo_alignment);
363 out->size = fmask.bo_size;
364 }
365
366 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
367 struct r600_texture *rtex)
368 {
369 r600_texture_get_fmask_info(rscreen, rtex,
370 rtex->resource.b.b.nr_samples, &rtex->fmask);
371
372 rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
373 rtex->size = rtex->fmask.offset + rtex->fmask.size;
374 }
375
376 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
377 struct r600_texture *rtex,
378 struct r600_cmask_info *out)
379 {
380 unsigned cmask_tile_width = 8;
381 unsigned cmask_tile_height = 8;
382 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
383 unsigned element_bits = 4;
384 unsigned cmask_cache_bits = 1024;
385 unsigned num_pipes = rscreen->info.num_tile_pipes;
386 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
387
388 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
389 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
390 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
391 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
392 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
393
394 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
395 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
396
397 unsigned base_align = num_pipes * pipe_interleave_bytes;
398 unsigned slice_bytes =
399 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
400
401 assert(macro_tile_width % 128 == 0);
402 assert(macro_tile_height % 128 == 0);
403
404 out->pitch = pitch_elements;
405 out->height = height;
406 out->xalign = macro_tile_width;
407 out->yalign = macro_tile_height;
408 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
409 out->alignment = MAX2(256, base_align);
410 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
411 align(slice_bytes, base_align);
412 }
413
414 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
415 struct r600_texture *rtex,
416 struct r600_cmask_info *out)
417 {
418 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
419 unsigned num_pipes = rscreen->info.num_tile_pipes;
420 unsigned cl_width, cl_height;
421
422 switch (num_pipes) {
423 case 2:
424 cl_width = 32;
425 cl_height = 16;
426 break;
427 case 4:
428 cl_width = 32;
429 cl_height = 32;
430 break;
431 case 8:
432 cl_width = 64;
433 cl_height = 32;
434 break;
435 case 16: /* Hawaii */
436 cl_width = 64;
437 cl_height = 64;
438 break;
439 default:
440 assert(0);
441 return;
442 }
443
444 unsigned base_align = num_pipes * pipe_interleave_bytes;
445
446 unsigned width = align(rtex->surface.npix_x, cl_width*8);
447 unsigned height = align(rtex->surface.npix_y, cl_height*8);
448 unsigned slice_elements = (width * height) / (8*8);
449
450 /* Each element of CMASK is a nibble. */
451 unsigned slice_bytes = slice_elements / 2;
452
453 out->pitch = width;
454 out->height = height;
455 out->xalign = cl_width * 8;
456 out->yalign = cl_height * 8;
457 out->slice_tile_max = (width * height) / (128*128);
458 if (out->slice_tile_max)
459 out->slice_tile_max -= 1;
460
461 out->alignment = MAX2(256, base_align);
462 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
463 align(slice_bytes, base_align);
464 }
465
466 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
467 struct r600_texture *rtex)
468 {
469 if (rscreen->chip_class >= SI) {
470 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
471 } else {
472 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
473 }
474
475 rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
476 rtex->size = rtex->cmask.offset + rtex->cmask.size;
477
478 if (rscreen->chip_class >= SI)
479 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
480 else
481 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
482 }
483
484 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
485 struct r600_texture *rtex)
486 {
487 if (rtex->cmask_buffer)
488 return;
489
490 assert(rtex->cmask.size == 0);
491
492 if (rscreen->chip_class >= SI) {
493 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
494 } else {
495 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
496 }
497
498 rtex->cmask_buffer = (struct r600_resource *)
499 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
500 PIPE_USAGE_DEFAULT, rtex->cmask.size);
501 if (rtex->cmask_buffer == NULL) {
502 rtex->cmask.size = 0;
503 return;
504 }
505
506 /* update colorbuffer state bits */
507 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
508
509 if (rscreen->chip_class >= SI)
510 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
511 else
512 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
513 }
514
515 static void vi_texture_alloc_dcc_separate(struct r600_common_screen *rscreen,
516 struct r600_texture *rtex)
517 {
518 if (rscreen->debug_flags & DBG_NO_DCC)
519 return;
520
521 rtex->dcc_buffer = (struct r600_resource *)
522 r600_aligned_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
523 PIPE_USAGE_DEFAULT, rtex->surface.dcc_size, rtex->surface.dcc_alignment);
524 if (rtex->dcc_buffer == NULL) {
525 return;
526 }
527
528 r600_screen_clear_buffer(rscreen, &rtex->dcc_buffer->b.b, 0, rtex->surface.dcc_size,
529 0xFFFFFFFF, true);
530
531 rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
532 }
533
534 static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
535 struct r600_texture *rtex)
536 {
537 unsigned cl_width, cl_height, width, height;
538 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
539 unsigned num_pipes = rscreen->info.num_tile_pipes;
540
541 if (rscreen->chip_class <= EVERGREEN &&
542 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
543 return 0;
544
545 /* HW bug on R6xx. */
546 if (rscreen->chip_class == R600 &&
547 (rtex->surface.level[0].npix_x > 7680 ||
548 rtex->surface.level[0].npix_y > 7680))
549 return 0;
550
551 /* HTILE is broken with 1D tiling on old kernels and CIK. */
552 if (rscreen->chip_class >= CIK &&
553 rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
554 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
555 return 0;
556
557 /* Overalign HTILE on Stoney to fix piglit/depthstencil-render-miplevels 585. */
558 if (rscreen->family == CHIP_STONEY)
559 num_pipes = 4;
560
561 switch (num_pipes) {
562 case 1:
563 cl_width = 32;
564 cl_height = 16;
565 break;
566 case 2:
567 cl_width = 32;
568 cl_height = 32;
569 break;
570 case 4:
571 cl_width = 64;
572 cl_height = 32;
573 break;
574 case 8:
575 cl_width = 64;
576 cl_height = 64;
577 break;
578 case 16:
579 cl_width = 128;
580 cl_height = 64;
581 break;
582 default:
583 assert(0);
584 return 0;
585 }
586
587 width = align(rtex->surface.npix_x, cl_width * 8);
588 height = align(rtex->surface.npix_y, cl_height * 8);
589
590 slice_elements = (width * height) / (8 * 8);
591 slice_bytes = slice_elements * 4;
592
593 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
594 base_align = num_pipes * pipe_interleave_bytes;
595
596 rtex->htile.pitch = width;
597 rtex->htile.height = height;
598 rtex->htile.xalign = cl_width * 8;
599 rtex->htile.yalign = cl_height * 8;
600
601 return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
602 align(slice_bytes, base_align);
603 }
604
605 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
606 struct r600_texture *rtex)
607 {
608 unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex);
609
610 if (!htile_size)
611 return;
612
613 rtex->htile_buffer = (struct r600_resource*)
614 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
615 PIPE_USAGE_DEFAULT, htile_size);
616 if (rtex->htile_buffer == NULL) {
617 /* this is not a fatal error as we can still keep rendering
618 * without htile buffer */
619 R600_ERR("Failed to create buffer object for htile buffer.\n");
620 } else {
621 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0,
622 htile_size, 0, true);
623 }
624 }
625
626 void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
627 {
628 int i;
629
630 fprintf(f, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
631 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
632 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
633 rtex->surface.npix_x, rtex->surface.npix_y,
634 rtex->surface.npix_z, rtex->surface.blk_w,
635 rtex->surface.blk_h, rtex->surface.blk_d,
636 rtex->surface.array_size, rtex->surface.last_level,
637 rtex->surface.bpe, rtex->surface.nsamples,
638 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
639
640 fprintf(f, " Layout: size=%"PRIu64", alignment=%"PRIu64", bankw=%u, "
641 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
642 rtex->surface.bo_size, rtex->surface.bo_alignment, rtex->surface.bankw,
643 rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
644 rtex->surface.tile_split, rtex->surface.pipe_config,
645 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
646
647 if (rtex->fmask.size)
648 fprintf(f, " FMask: offset=%u, size=%u, alignment=%u, pitch_in_pixels=%u, "
649 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
650 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
651 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
652 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
653
654 if (rtex->cmask.size)
655 fprintf(f, " CMask: offset=%u, size=%u, alignment=%u, pitch=%u, "
656 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
657 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
658 rtex->cmask.pitch, rtex->cmask.height, rtex->cmask.xalign,
659 rtex->cmask.yalign, rtex->cmask.slice_tile_max);
660
661 if (rtex->htile_buffer)
662 fprintf(f, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
663 "xalign=%u, yalign=%u\n",
664 rtex->htile_buffer->b.b.width0,
665 rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
666 rtex->htile.height, rtex->htile.xalign, rtex->htile.yalign);
667
668 if (rtex->dcc_buffer) {
669 fprintf(f, " DCC: size=%u, alignment=%u\n",
670 rtex->dcc_buffer->b.b.width0,
671 rtex->dcc_buffer->buf->alignment);
672 for (i = 0; i <= rtex->surface.last_level; i++)
673 fprintf(f, " DCCLevel[%i]: offset=%"PRIu64"\n",
674 i, rtex->surface.level[i].dcc_offset);
675 }
676
677 for (i = 0; i <= rtex->surface.last_level; i++)
678 fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
679 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
680 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
681 i, rtex->surface.level[i].offset,
682 rtex->surface.level[i].slice_size,
683 u_minify(rtex->resource.b.b.width0, i),
684 u_minify(rtex->resource.b.b.height0, i),
685 u_minify(rtex->resource.b.b.depth0, i),
686 rtex->surface.level[i].nblk_x,
687 rtex->surface.level[i].nblk_y,
688 rtex->surface.level[i].nblk_z,
689 rtex->surface.level[i].pitch_bytes,
690 rtex->surface.level[i].mode);
691
692 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
693 for (i = 0; i <= rtex->surface.last_level; i++) {
694 fprintf(f, " StencilLayout: tilesplit=%u\n",
695 rtex->surface.stencil_tile_split);
696 fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
697 "slice_size=%"PRIu64", npix_x=%u, "
698 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
699 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
700 i, rtex->surface.stencil_level[i].offset,
701 rtex->surface.stencil_level[i].slice_size,
702 u_minify(rtex->resource.b.b.width0, i),
703 u_minify(rtex->resource.b.b.height0, i),
704 u_minify(rtex->resource.b.b.depth0, i),
705 rtex->surface.stencil_level[i].nblk_x,
706 rtex->surface.stencil_level[i].nblk_y,
707 rtex->surface.stencil_level[i].nblk_z,
708 rtex->surface.stencil_level[i].pitch_bytes,
709 rtex->surface.stencil_level[i].mode);
710 }
711 }
712 }
713
714 /* Common processing for r600_texture_create and r600_texture_from_handle */
715 static struct r600_texture *
716 r600_texture_create_object(struct pipe_screen *screen,
717 const struct pipe_resource *base,
718 unsigned pitch_in_bytes_override,
719 struct pb_buffer *buf,
720 struct radeon_surf *surface)
721 {
722 struct r600_texture *rtex;
723 struct r600_resource *resource;
724 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
725
726 rtex = CALLOC_STRUCT(r600_texture);
727 if (!rtex)
728 return NULL;
729
730 resource = &rtex->resource;
731 resource->b.b = *base;
732 resource->b.vtbl = &r600_texture_vtbl;
733 pipe_reference_init(&resource->b.b.reference, 1);
734 resource->b.b.screen = screen;
735
736 /* don't include stencil-only formats which we don't support for rendering */
737 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
738
739 rtex->surface = *surface;
740 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override)) {
741 FREE(rtex);
742 return NULL;
743 }
744
745 /* Tiled depth textures utilize the non-displayable tile order.
746 * This must be done after r600_setup_surface.
747 * Applies to R600-Cayman. */
748 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
749
750 if (rtex->is_depth) {
751 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
752 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
753 !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
754
755 r600_texture_allocate_htile(rscreen, rtex);
756 }
757 } else {
758 if (base->nr_samples > 1) {
759 if (!buf) {
760 r600_texture_allocate_fmask(rscreen, rtex);
761 r600_texture_allocate_cmask(rscreen, rtex);
762 rtex->cmask_buffer = &rtex->resource;
763 }
764 if (!rtex->fmask.size || !rtex->cmask.size) {
765 FREE(rtex);
766 return NULL;
767 }
768 }
769 if (rtex->surface.dcc_size)
770 vi_texture_alloc_dcc_separate(rscreen, rtex);
771 }
772
773 /* Now create the backing buffer. */
774 if (!buf) {
775 if (!r600_init_resource(rscreen, resource, rtex->size,
776 rtex->surface.bo_alignment, TRUE)) {
777 FREE(rtex);
778 return NULL;
779 }
780 } else {
781 resource->buf = buf;
782 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
783 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
784 }
785
786 if (rtex->cmask.size) {
787 /* Initialize the cmask to 0xCC (= compressed state). */
788 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
789 rtex->cmask.offset, rtex->cmask.size,
790 0xCCCCCCCC, true);
791 }
792
793 /* Initialize the CMASK base register value. */
794 rtex->cmask.base_address_reg =
795 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
796
797 if (rscreen->debug_flags & DBG_VM) {
798 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
799 rtex->resource.gpu_address,
800 rtex->resource.gpu_address + rtex->resource.buf->size,
801 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
802 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
803 }
804
805 if (rscreen->debug_flags & DBG_TEX) {
806 puts("Texture:");
807 r600_print_texture_info(rtex, stdout);
808 }
809
810 return rtex;
811 }
812
813 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
814 const struct pipe_resource *templ)
815 {
816 const struct util_format_description *desc = util_format_description(templ->format);
817 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
818
819 /* MSAA resources must be 2D tiled. */
820 if (templ->nr_samples > 1)
821 return RADEON_SURF_MODE_2D;
822
823 /* Transfer resources should be linear. */
824 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
825 return RADEON_SURF_MODE_LINEAR_ALIGNED;
826
827 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
828 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
829 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
830 (templ->target == PIPE_TEXTURE_2D ||
831 templ->target == PIPE_TEXTURE_3D))
832 force_tiling = true;
833
834 /* Handle common candidates for the linear mode.
835 * Compressed textures must always be tiled. */
836 if (!force_tiling && !util_format_is_compressed(templ->format)) {
837 /* Not everything can be linear, so we cannot enforce it
838 * for all textures. */
839 if ((rscreen->debug_flags & DBG_NO_TILING) &&
840 (!util_format_is_depth_or_stencil(templ->format) ||
841 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH)))
842 return RADEON_SURF_MODE_LINEAR_ALIGNED;
843
844 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
845 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
846 return RADEON_SURF_MODE_LINEAR_ALIGNED;
847
848 /* Cursors are linear on SI.
849 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
850 if (rscreen->chip_class >= SI &&
851 (templ->bind & PIPE_BIND_CURSOR))
852 return RADEON_SURF_MODE_LINEAR_ALIGNED;
853
854 if (templ->bind & PIPE_BIND_LINEAR)
855 return RADEON_SURF_MODE_LINEAR_ALIGNED;
856
857 /* Textures with a very small height are recommended to be linear. */
858 if (templ->target == PIPE_TEXTURE_1D ||
859 templ->target == PIPE_TEXTURE_1D_ARRAY ||
860 templ->height0 <= 4)
861 return RADEON_SURF_MODE_LINEAR_ALIGNED;
862
863 /* Textures likely to be mapped often. */
864 if (templ->usage == PIPE_USAGE_STAGING ||
865 templ->usage == PIPE_USAGE_STREAM)
866 return RADEON_SURF_MODE_LINEAR_ALIGNED;
867 }
868
869 /* Make small textures 1D tiled. */
870 if (templ->width0 <= 16 || templ->height0 <= 16 ||
871 (rscreen->debug_flags & DBG_NO_2D_TILING))
872 return RADEON_SURF_MODE_1D;
873
874 /* The allocator will switch to 1D if needed. */
875 return RADEON_SURF_MODE_2D;
876 }
877
878 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
879 const struct pipe_resource *templ)
880 {
881 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
882 struct radeon_surf surface = {0};
883 int r;
884
885 r = r600_init_surface(rscreen, &surface, templ,
886 r600_choose_tiling(rscreen, templ),
887 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
888 if (r) {
889 return NULL;
890 }
891 r = rscreen->ws->surface_best(rscreen->ws, &surface);
892 if (r) {
893 return NULL;
894 }
895 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
896 0, NULL, &surface);
897 }
898
899 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
900 const struct pipe_resource *templ,
901 struct winsys_handle *whandle,
902 unsigned usage)
903 {
904 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
905 struct pb_buffer *buf = NULL;
906 unsigned stride = 0;
907 unsigned array_mode;
908 struct radeon_surf surface;
909 int r;
910 struct radeon_bo_metadata metadata = {};
911 struct r600_texture *rtex;
912
913 /* Support only 2D textures without mipmaps */
914 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
915 templ->depth0 != 1 || templ->last_level != 0)
916 return NULL;
917
918 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
919 if (!buf)
920 return NULL;
921
922 rscreen->ws->buffer_get_metadata(buf, &metadata);
923
924 surface.bankw = metadata.bankw;
925 surface.bankh = metadata.bankh;
926 surface.tile_split = metadata.tile_split;
927 surface.stencil_tile_split = metadata.stencil_tile_split;
928 surface.mtilea = metadata.mtilea;
929
930 if (metadata.macrotile == RADEON_LAYOUT_TILED)
931 array_mode = RADEON_SURF_MODE_2D;
932 else if (metadata.microtile == RADEON_LAYOUT_TILED)
933 array_mode = RADEON_SURF_MODE_1D;
934 else
935 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
936
937 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
938 if (r) {
939 return NULL;
940 }
941
942 if (metadata.scanout)
943 surface.flags |= RADEON_SURF_SCANOUT;
944
945 rtex = r600_texture_create_object(screen, templ,
946 stride, buf, &surface);
947 if (!rtex)
948 return NULL;
949
950 rtex->resource.is_shared = true;
951 rtex->resource.external_usage = usage;
952 return &rtex->resource.b.b;
953 }
954
955 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
956 struct pipe_resource *texture,
957 struct r600_texture **staging)
958 {
959 struct r600_texture *rtex = (struct r600_texture*)texture;
960 struct pipe_resource resource;
961 struct r600_texture **flushed_depth_texture = staging ?
962 staging : &rtex->flushed_depth_texture;
963
964 if (!staging && rtex->flushed_depth_texture)
965 return true; /* it's ready */
966
967 resource.target = texture->target;
968 resource.format = texture->format;
969 resource.width0 = texture->width0;
970 resource.height0 = texture->height0;
971 resource.depth0 = texture->depth0;
972 resource.array_size = texture->array_size;
973 resource.last_level = texture->last_level;
974 resource.nr_samples = texture->nr_samples;
975 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
976 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
977 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
978
979 if (staging)
980 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
981
982 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
983 if (*flushed_depth_texture == NULL) {
984 R600_ERR("failed to create temporary texture to hold flushed depth\n");
985 return false;
986 }
987
988 (*flushed_depth_texture)->is_flushing_texture = TRUE;
989 (*flushed_depth_texture)->non_disp_tiling = false;
990 return true;
991 }
992
993 /**
994 * Initialize the pipe_resource descriptor to be of the same size as the box,
995 * which is supposed to hold a subregion of the texture "orig" at the given
996 * mipmap level.
997 */
998 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
999 struct pipe_resource *orig,
1000 const struct pipe_box *box,
1001 unsigned level, unsigned flags)
1002 {
1003 memset(res, 0, sizeof(*res));
1004 res->format = orig->format;
1005 res->width0 = box->width;
1006 res->height0 = box->height;
1007 res->depth0 = 1;
1008 res->array_size = 1;
1009 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1010 res->flags = flags;
1011
1012 /* We must set the correct texture target and dimensions for a 3D box. */
1013 if (box->depth > 1 && util_max_layer(orig, level) > 0)
1014 res->target = orig->target;
1015 else
1016 res->target = PIPE_TEXTURE_2D;
1017
1018 switch (res->target) {
1019 case PIPE_TEXTURE_1D_ARRAY:
1020 case PIPE_TEXTURE_2D_ARRAY:
1021 case PIPE_TEXTURE_CUBE_ARRAY:
1022 res->array_size = box->depth;
1023 break;
1024 case PIPE_TEXTURE_3D:
1025 res->depth0 = box->depth;
1026 break;
1027 default:;
1028 }
1029 }
1030
1031 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1032 struct pipe_resource *texture,
1033 unsigned level,
1034 unsigned usage,
1035 const struct pipe_box *box,
1036 struct pipe_transfer **ptransfer)
1037 {
1038 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1039 struct r600_texture *rtex = (struct r600_texture*)texture;
1040 struct r600_transfer *trans;
1041 boolean use_staging_texture = FALSE;
1042 struct r600_resource *buf;
1043 unsigned offset = 0;
1044 char *map;
1045
1046 /* We cannot map a tiled texture directly because the data is
1047 * in a different order, therefore we do detiling using a blit.
1048 *
1049 * Also, use a temporary in GTT memory for read transfers, as
1050 * the CPU is much happier reading out of cached system memory
1051 * than uncached VRAM.
1052 */
1053 if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
1054 use_staging_texture = TRUE;
1055 } else if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
1056 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
1057 /* Untiled buffers in VRAM, which is slow for CPU reads */
1058 use_staging_texture = TRUE;
1059 } else if (!(usage & PIPE_TRANSFER_READ) &&
1060 (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf, RADEON_USAGE_READWRITE) ||
1061 !rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) {
1062 /* Use a staging texture for uploads if the underlying BO is busy. */
1063 use_staging_texture = TRUE;
1064 }
1065
1066 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
1067 use_staging_texture = FALSE;
1068 }
1069
1070 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
1071 return NULL;
1072 }
1073
1074 trans = CALLOC_STRUCT(r600_transfer);
1075 if (!trans)
1076 return NULL;
1077 trans->transfer.resource = texture;
1078 trans->transfer.level = level;
1079 trans->transfer.usage = usage;
1080 trans->transfer.box = *box;
1081
1082 if (rtex->is_depth) {
1083 struct r600_texture *staging_depth;
1084
1085 if (rtex->resource.b.b.nr_samples > 1) {
1086 /* MSAA depth buffers need to be converted to single sample buffers.
1087 *
1088 * Mapping MSAA depth buffers can occur if ReadPixels is called
1089 * with a multisample GLX visual.
1090 *
1091 * First downsample the depth buffer to a temporary texture,
1092 * then decompress the temporary one to staging.
1093 *
1094 * Only the region being mapped is transfered.
1095 */
1096 struct pipe_resource resource;
1097
1098 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1099
1100 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1101 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1102 FREE(trans);
1103 return NULL;
1104 }
1105
1106 if (usage & PIPE_TRANSFER_READ) {
1107 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1108 if (!temp) {
1109 R600_ERR("failed to create a temporary depth texture\n");
1110 FREE(trans);
1111 return NULL;
1112 }
1113
1114 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1115 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1116 0, 0, 0, box->depth, 0, 0);
1117 pipe_resource_reference(&temp, NULL);
1118 }
1119 }
1120 else {
1121 /* XXX: only readback the rectangle which is being mapped? */
1122 /* XXX: when discard is true, no need to read back from depth texture */
1123 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1124 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1125 FREE(trans);
1126 return NULL;
1127 }
1128
1129 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1130 level, level,
1131 box->z, box->z + box->depth - 1,
1132 0, 0);
1133
1134 offset = r600_texture_get_offset(staging_depth, level, box);
1135 }
1136
1137 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
1138 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1139 trans->staging = (struct r600_resource*)staging_depth;
1140 } else if (use_staging_texture) {
1141 struct pipe_resource resource;
1142 struct r600_texture *staging;
1143
1144 r600_init_temp_resource_from_box(&resource, texture, box, level,
1145 R600_RESOURCE_FLAG_TRANSFER);
1146 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1147 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1148
1149 /* Create the temporary texture. */
1150 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1151 if (!staging) {
1152 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1153 FREE(trans);
1154 return NULL;
1155 }
1156 trans->staging = &staging->resource;
1157 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1158 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1159 if (usage & PIPE_TRANSFER_READ) {
1160 r600_copy_to_staging_texture(ctx, trans);
1161 }
1162 } else {
1163 /* the resource is mapped directly */
1164 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1165 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1166 offset = r600_texture_get_offset(rtex, level, box);
1167 }
1168
1169 if (trans->staging) {
1170 buf = trans->staging;
1171 if (!rtex->is_depth && !(usage & PIPE_TRANSFER_READ))
1172 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1173 } else {
1174 buf = &rtex->resource;
1175 }
1176
1177 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1178 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1179 FREE(trans);
1180 return NULL;
1181 }
1182
1183 *ptransfer = &trans->transfer;
1184 return map + offset;
1185 }
1186
1187 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1188 struct pipe_transfer* transfer)
1189 {
1190 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1191 struct pipe_resource *texture = transfer->resource;
1192 struct r600_texture *rtex = (struct r600_texture*)texture;
1193
1194 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1195 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1196 ctx->resource_copy_region(ctx, texture, transfer->level,
1197 transfer->box.x, transfer->box.y, transfer->box.z,
1198 &rtransfer->staging->b.b, transfer->level,
1199 &transfer->box);
1200 } else {
1201 r600_copy_from_staging_texture(ctx, rtransfer);
1202 }
1203 }
1204
1205 if (rtransfer->staging)
1206 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1207
1208 FREE(transfer);
1209 }
1210
1211 static const struct u_resource_vtbl r600_texture_vtbl =
1212 {
1213 NULL, /* get_handle */
1214 r600_texture_destroy, /* resource_destroy */
1215 r600_texture_transfer_map, /* transfer_map */
1216 u_default_transfer_flush_region, /* transfer_flush_region */
1217 r600_texture_transfer_unmap, /* transfer_unmap */
1218 NULL /* transfer_inline_write */
1219 };
1220
1221 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1222 struct pipe_resource *texture,
1223 const struct pipe_surface *templ,
1224 unsigned width, unsigned height)
1225 {
1226 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1227
1228 if (!surface)
1229 return NULL;
1230
1231 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1232 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1233
1234 pipe_reference_init(&surface->base.reference, 1);
1235 pipe_resource_reference(&surface->base.texture, texture);
1236 surface->base.context = pipe;
1237 surface->base.format = templ->format;
1238 surface->base.width = width;
1239 surface->base.height = height;
1240 surface->base.u = templ->u;
1241 return &surface->base;
1242 }
1243
1244 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1245 struct pipe_resource *tex,
1246 const struct pipe_surface *templ)
1247 {
1248 unsigned level = templ->u.tex.level;
1249 unsigned width = u_minify(tex->width0, level);
1250 unsigned height = u_minify(tex->height0, level);
1251
1252 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1253 const struct util_format_description *tex_desc
1254 = util_format_description(tex->format);
1255 const struct util_format_description *templ_desc
1256 = util_format_description(templ->format);
1257
1258 assert(tex_desc->block.bits == templ_desc->block.bits);
1259
1260 /* Adjust size of surface if and only if the block width or
1261 * height is changed. */
1262 if (tex_desc->block.width != templ_desc->block.width ||
1263 tex_desc->block.height != templ_desc->block.height) {
1264 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1265 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1266
1267 width = nblks_x * templ_desc->block.width;
1268 height = nblks_y * templ_desc->block.height;
1269 }
1270 }
1271
1272 return r600_create_surface_custom(pipe, tex, templ, width, height);
1273 }
1274
1275 static void r600_surface_destroy(struct pipe_context *pipe,
1276 struct pipe_surface *surface)
1277 {
1278 struct r600_surface *surf = (struct r600_surface*)surface;
1279 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1280 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1281 pipe_resource_reference(&surface->texture, NULL);
1282 FREE(surface);
1283 }
1284
1285 unsigned r600_translate_colorswap(enum pipe_format format)
1286 {
1287 const struct util_format_description *desc = util_format_description(format);
1288
1289 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1290
1291 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1292 return V_0280A0_SWAP_STD;
1293
1294 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1295 return ~0U;
1296
1297 switch (desc->nr_channels) {
1298 case 1:
1299 if (HAS_SWIZZLE(0,X))
1300 return V_0280A0_SWAP_STD; /* X___ */
1301 else if (HAS_SWIZZLE(3,X))
1302 return V_0280A0_SWAP_ALT_REV; /* ___X */
1303 break;
1304 case 2:
1305 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1306 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1307 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1308 return V_0280A0_SWAP_STD; /* XY__ */
1309 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1310 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1311 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1312 return V_0280A0_SWAP_STD_REV; /* YX__ */
1313 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1314 return V_0280A0_SWAP_ALT; /* X__Y */
1315 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1316 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1317 break;
1318 case 3:
1319 if (HAS_SWIZZLE(0,X))
1320 return V_0280A0_SWAP_STD; /* XYZ */
1321 else if (HAS_SWIZZLE(0,Z))
1322 return V_0280A0_SWAP_STD_REV; /* ZYX */
1323 break;
1324 case 4:
1325 /* check the middle channels, the 1st and 4th channel can be NONE */
1326 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
1327 return V_0280A0_SWAP_STD; /* XYZW */
1328 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
1329 return V_0280A0_SWAP_STD_REV; /* WZYX */
1330 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
1331 return V_0280A0_SWAP_ALT; /* ZYXW */
1332 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W))
1333 return V_0280A0_SWAP_ALT_REV; /* YZWX */
1334 break;
1335 }
1336 return ~0U;
1337 }
1338
1339 static void evergreen_set_clear_color(struct r600_texture *rtex,
1340 enum pipe_format surface_format,
1341 const union pipe_color_union *color)
1342 {
1343 union util_color uc;
1344
1345 memset(&uc, 0, sizeof(uc));
1346
1347 if (util_format_is_pure_uint(surface_format)) {
1348 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1349 } else if (util_format_is_pure_sint(surface_format)) {
1350 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1351 } else {
1352 util_pack_color(color->f, surface_format, &uc);
1353 }
1354
1355 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1356 }
1357
1358 static void vi_get_fast_clear_parameters(enum pipe_format surface_format,
1359 const union pipe_color_union *color,
1360 uint32_t* reset_value,
1361 bool* clear_words_needed)
1362 {
1363 bool values[4] = {};
1364 int i;
1365 bool main_value = false;
1366 bool extra_value = false;
1367 int extra_channel;
1368 const struct util_format_description *desc = util_format_description(surface_format);
1369
1370 *clear_words_needed = true;
1371 *reset_value = 0x20202020U;
1372
1373 /* If we want to clear without needing a fast clear eliminate step, we
1374 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1375 * have two sets of flags, one for the last or first channel(extra) and
1376 * one for the other channels(main).
1377 */
1378
1379 if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
1380 surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
1381 surface_format == PIPE_FORMAT_B5G6R5_SRGB) {
1382 extra_channel = -1;
1383 } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
1384 if(r600_translate_colorswap(surface_format) <= 1)
1385 extra_channel = desc->nr_channels - 1;
1386 else
1387 extra_channel = 0;
1388 } else
1389 return;
1390
1391 for (i = 0; i < 4; ++i) {
1392 int index = desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X;
1393
1394 if (desc->swizzle[i] < UTIL_FORMAT_SWIZZLE_X ||
1395 desc->swizzle[i] > UTIL_FORMAT_SWIZZLE_W)
1396 continue;
1397
1398 if (util_format_is_pure_sint(surface_format)) {
1399 values[i] = color->i[i] != 0;
1400 if (color->i[i] != 0 && color->i[i] != INT32_MAX)
1401 return;
1402 } else if (util_format_is_pure_uint(surface_format)) {
1403 values[i] = color->ui[i] != 0U;
1404 if (color->ui[i] != 0U && color->ui[i] != UINT32_MAX)
1405 return;
1406 } else {
1407 values[i] = color->f[i] != 0.0F;
1408 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
1409 return;
1410 }
1411
1412 if (index == extra_channel)
1413 extra_value = values[i];
1414 else
1415 main_value = values[i];
1416 }
1417
1418 for (int i = 0; i < 4; ++i)
1419 if (values[i] != main_value &&
1420 desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X != extra_channel &&
1421 desc->swizzle[i] >= UTIL_FORMAT_SWIZZLE_X &&
1422 desc->swizzle[i] <= UTIL_FORMAT_SWIZZLE_W)
1423 return;
1424
1425 *clear_words_needed = false;
1426 if (main_value)
1427 *reset_value |= 0x80808080U;
1428
1429 if (extra_value)
1430 *reset_value |= 0x40404040U;
1431 }
1432
1433 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1434 struct pipe_framebuffer_state *fb,
1435 struct r600_atom *fb_state,
1436 unsigned *buffers, unsigned *dirty_cbufs,
1437 const union pipe_color_union *color)
1438 {
1439 int i;
1440
1441 /* This function is broken in BE, so just disable this path for now */
1442 #ifdef PIPE_ARCH_BIG_ENDIAN
1443 return;
1444 #endif
1445
1446 if (rctx->render_cond)
1447 return;
1448
1449 for (i = 0; i < fb->nr_cbufs; i++) {
1450 struct r600_texture *tex;
1451 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1452
1453 if (!fb->cbufs[i])
1454 continue;
1455
1456 /* if this colorbuffer is not being cleared */
1457 if (!(*buffers & clear_bit))
1458 continue;
1459
1460 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1461
1462 /* 128-bit formats are unusupported */
1463 if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
1464 continue;
1465 }
1466
1467 /* the clear is allowed if all layers are bound */
1468 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1469 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1470 continue;
1471 }
1472
1473 /* cannot clear mipmapped textures */
1474 if (fb->cbufs[i]->texture->last_level != 0) {
1475 continue;
1476 }
1477
1478 /* only supported on tiled surfaces */
1479 if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
1480 continue;
1481 }
1482
1483 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1484 if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
1485 rctx->chip_class >= CIK &&
1486 rctx->screen->info.drm_major == 2 &&
1487 rctx->screen->info.drm_minor < 38) {
1488 continue;
1489 }
1490
1491 if (tex->dcc_buffer) {
1492 uint32_t reset_value;
1493 bool clear_words_needed;
1494
1495 if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
1496 continue;
1497
1498 vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed);
1499
1500 rctx->clear_buffer(&rctx->b, &tex->dcc_buffer->b.b,
1501 0, tex->surface.dcc_size, reset_value, true);
1502
1503 if (clear_words_needed)
1504 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1505 } else {
1506 /* Stoney/RB+ doesn't work with CMASK fast clear. */
1507 if (rctx->family == CHIP_STONEY)
1508 continue;
1509
1510 /* ensure CMASK is enabled */
1511 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1512 if (tex->cmask.size == 0) {
1513 continue;
1514 }
1515
1516 /* Do the fast clear. */
1517 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1518 tex->cmask.offset, tex->cmask.size, 0, true);
1519
1520 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1521 }
1522
1523 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1524
1525 if (dirty_cbufs)
1526 *dirty_cbufs |= 1 << i;
1527 rctx->set_atom_dirty(rctx, fb_state, true);
1528 *buffers &= ~clear_bit;
1529 }
1530 }
1531
1532 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1533 {
1534 rscreen->b.resource_from_handle = r600_texture_from_handle;
1535 rscreen->b.resource_get_handle = r600_texture_get_handle;
1536 }
1537
1538 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1539 {
1540 rctx->b.create_surface = r600_create_surface;
1541 rctx->b.surface_destroy = r600_surface_destroy;
1542 }