2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "radeonsi/si_pipe.h"
28 #include "r600_query.h"
29 #include "util/u_format.h"
30 #include "util/u_log.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_resource.h"
34 #include "util/u_surface.h"
35 #include "util/os_time.h"
38 #include "state_tracker/drm_driver.h"
39 #include "amd/common/sid.h"
41 static enum radeon_surf_mode
42 r600_choose_tiling(struct si_screen
*sscreen
,
43 const struct pipe_resource
*templ
);
46 bool si_prepare_for_dma_blit(struct si_context
*sctx
,
47 struct r600_texture
*rdst
,
48 unsigned dst_level
, unsigned dstx
,
49 unsigned dsty
, unsigned dstz
,
50 struct r600_texture
*rsrc
,
52 const struct pipe_box
*src_box
)
57 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
60 /* MSAA: Blits don't exist in the real world. */
61 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
62 rdst
->resource
.b
.b
.nr_samples
> 1)
65 /* Depth-stencil surfaces:
66 * When dst is linear, the DB->CB copy preserves HTILE.
67 * When dst is tiled, the 3D path must be used to update HTILE.
69 if (rsrc
->is_depth
|| rdst
->is_depth
)
73 * src: Use the 3D path. DCC decompression is expensive.
74 * dst: Use the 3D path to compress the pixels with DCC.
76 if (vi_dcc_enabled(rsrc
, src_level
) ||
77 vi_dcc_enabled(rdst
, dst_level
))
81 * src: Both texture and SDMA paths need decompression. Use SDMA.
82 * dst: If overwriting the whole texture, discard CMASK and use
83 * SDMA. Otherwise, use the 3D path.
85 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
86 /* The CMASK clear is only enabled for the first level. */
87 assert(dst_level
== 0);
88 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
89 dstx
, dsty
, dstz
, src_box
->width
,
90 src_box
->height
, src_box
->depth
))
93 si_texture_discard_cmask(sctx
->screen
, rdst
);
96 /* All requirements are met. Prepare textures for SDMA. */
97 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
98 sctx
->b
.b
.flush_resource(&sctx
->b
.b
, &rsrc
->resource
.b
.b
);
100 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
101 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
106 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
107 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
108 struct pipe_resource
*dst
,
110 unsigned dstx
, unsigned dsty
, unsigned dstz
,
111 struct pipe_resource
*src
,
113 const struct pipe_box
*src_box
)
115 struct pipe_blit_info blit
;
117 memset(&blit
, 0, sizeof(blit
));
118 blit
.src
.resource
= src
;
119 blit
.src
.format
= src
->format
;
120 blit
.src
.level
= src_level
;
121 blit
.src
.box
= *src_box
;
122 blit
.dst
.resource
= dst
;
123 blit
.dst
.format
= dst
->format
;
124 blit
.dst
.level
= dst_level
;
125 blit
.dst
.box
.x
= dstx
;
126 blit
.dst
.box
.y
= dsty
;
127 blit
.dst
.box
.z
= dstz
;
128 blit
.dst
.box
.width
= src_box
->width
;
129 blit
.dst
.box
.height
= src_box
->height
;
130 blit
.dst
.box
.depth
= src_box
->depth
;
131 blit
.mask
= util_format_get_mask(src
->format
) &
132 util_format_get_mask(dst
->format
);
133 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
136 pipe
->blit(pipe
, &blit
);
140 /* Copy from a full GPU texture to a transfer's staging one. */
141 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
143 struct si_context
*sctx
= (struct si_context
*)ctx
;
144 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
145 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
146 struct pipe_resource
*src
= transfer
->resource
;
148 if (src
->nr_samples
> 1) {
149 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
150 src
, transfer
->level
, &transfer
->box
);
154 sctx
->b
.dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
158 /* Copy from a transfer's staging texture to a full GPU one. */
159 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
161 struct si_context
*sctx
= (struct si_context
*)ctx
;
162 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
163 struct pipe_resource
*dst
= transfer
->resource
;
164 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
165 struct pipe_box sbox
;
167 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
169 if (dst
->nr_samples
> 1) {
170 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
171 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
176 sctx
->b
.dma_copy(ctx
, dst
, transfer
->level
,
177 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
181 static unsigned r600_texture_get_offset(struct si_screen
*sscreen
,
182 struct r600_texture
*rtex
, unsigned level
,
183 const struct pipe_box
*box
,
185 unsigned *layer_stride
)
187 if (sscreen
->info
.chip_class
>= GFX9
) {
188 *stride
= rtex
->surface
.u
.gfx9
.surf_pitch
* rtex
->surface
.bpe
;
189 *layer_stride
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
194 /* Each texture is an array of slices. Each slice is an array
195 * of mipmap levels. */
196 return box
->z
* rtex
->surface
.u
.gfx9
.surf_slice_size
+
197 rtex
->surface
.u
.gfx9
.offset
[level
] +
198 (box
->y
/ rtex
->surface
.blk_h
*
199 rtex
->surface
.u
.gfx9
.surf_pitch
+
200 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
202 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
204 assert((uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
205 *layer_stride
= (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
208 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
210 /* Each texture is an array of mipmap levels. Each level is
211 * an array of slices. */
212 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
213 box
->z
* (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
214 (box
->y
/ rtex
->surface
.blk_h
*
215 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
216 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
220 static int r600_init_surface(struct si_screen
*sscreen
,
221 struct radeon_surf
*surface
,
222 const struct pipe_resource
*ptex
,
223 enum radeon_surf_mode array_mode
,
224 unsigned pitch_in_bytes_override
,
228 bool is_flushed_depth
,
229 bool tc_compatible_htile
)
231 const struct util_format_description
*desc
=
232 util_format_description(ptex
->format
);
233 bool is_depth
, is_stencil
;
235 unsigned i
, bpe
, flags
= 0;
237 is_depth
= util_format_has_depth(desc
);
238 is_stencil
= util_format_has_stencil(desc
);
240 if (!is_flushed_depth
&&
241 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
242 bpe
= 4; /* stencil is allocated separately on evergreen */
244 bpe
= util_format_get_blocksize(ptex
->format
);
245 assert(util_is_power_of_two_or_zero(bpe
));
248 if (!is_flushed_depth
&& is_depth
) {
249 flags
|= RADEON_SURF_ZBUFFER
;
251 if (tc_compatible_htile
&&
252 (sscreen
->info
.chip_class
>= GFX9
||
253 array_mode
== RADEON_SURF_MODE_2D
)) {
254 /* TC-compatible HTILE only supports Z32_FLOAT.
255 * GFX9 also supports Z16_UNORM.
256 * On VI, promote Z16 to Z32. DB->CB copies will convert
257 * the format for transfers.
259 if (sscreen
->info
.chip_class
== VI
)
262 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
266 flags
|= RADEON_SURF_SBUFFER
;
269 if (sscreen
->info
.chip_class
>= VI
&&
270 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
271 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
||
272 /* DCC MSAA array textures are disallowed due to incomplete clear impl. */
273 (ptex
->nr_samples
>= 2 &&
274 (!sscreen
->dcc_msaa_allowed
|| ptex
->array_size
> 1))))
275 flags
|= RADEON_SURF_DISABLE_DCC
;
277 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
278 /* This should catch bugs in gallium users setting incorrect flags. */
279 assert(ptex
->nr_samples
<= 1 &&
280 ptex
->array_size
== 1 &&
282 ptex
->last_level
== 0 &&
283 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
285 flags
|= RADEON_SURF_SCANOUT
;
288 if (ptex
->bind
& PIPE_BIND_SHARED
)
289 flags
|= RADEON_SURF_SHAREABLE
;
291 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
292 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
293 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
295 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
,
296 array_mode
, surface
);
301 unsigned pitch
= pitch_in_bytes_override
/ bpe
;
303 if (sscreen
->info
.chip_class
>= GFX9
) {
305 surface
->u
.gfx9
.surf_pitch
= pitch
;
306 surface
->u
.gfx9
.surf_slice_size
=
307 (uint64_t)pitch
* surface
->u
.gfx9
.surf_height
* bpe
;
309 surface
->u
.gfx9
.surf_offset
= offset
;
312 surface
->u
.legacy
.level
[0].nblk_x
= pitch
;
313 surface
->u
.legacy
.level
[0].slice_size_dw
=
314 ((uint64_t)pitch
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
317 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
318 surface
->u
.legacy
.level
[i
].offset
+= offset
;
324 static void r600_texture_init_metadata(struct si_screen
*sscreen
,
325 struct r600_texture
*rtex
,
326 struct radeon_bo_metadata
*metadata
)
328 struct radeon_surf
*surface
= &rtex
->surface
;
330 memset(metadata
, 0, sizeof(*metadata
));
332 if (sscreen
->info
.chip_class
>= GFX9
) {
333 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
335 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
336 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
337 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
338 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
339 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
340 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
341 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
342 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
343 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
344 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
345 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
346 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
350 static void r600_surface_import_metadata(struct si_screen
*sscreen
,
351 struct radeon_surf
*surf
,
352 struct radeon_bo_metadata
*metadata
,
353 enum radeon_surf_mode
*array_mode
,
356 if (sscreen
->info
.chip_class
>= GFX9
) {
357 if (metadata
->u
.gfx9
.swizzle_mode
> 0)
358 *array_mode
= RADEON_SURF_MODE_2D
;
360 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
362 *is_scanout
= metadata
->u
.gfx9
.swizzle_mode
== 0 ||
363 metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
365 surf
->u
.gfx9
.surf
.swizzle_mode
= metadata
->u
.gfx9
.swizzle_mode
;
367 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
368 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
369 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
370 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
371 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
372 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
374 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
375 *array_mode
= RADEON_SURF_MODE_2D
;
376 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
377 *array_mode
= RADEON_SURF_MODE_1D
;
379 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
381 *is_scanout
= metadata
->u
.legacy
.scanout
;
385 void si_eliminate_fast_color_clear(struct si_context
*sctx
,
386 struct r600_texture
*rtex
)
388 struct si_screen
*sscreen
= sctx
->screen
;
389 struct pipe_context
*ctx
= &sctx
->b
.b
;
391 if (ctx
== sscreen
->aux_context
)
392 mtx_lock(&sscreen
->aux_context_lock
);
394 unsigned n
= sctx
->b
.num_decompress_calls
;
395 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
397 /* Flush only if any fast clear elimination took place. */
398 if (n
!= sctx
->b
.num_decompress_calls
)
399 ctx
->flush(ctx
, NULL
, 0);
401 if (ctx
== sscreen
->aux_context
)
402 mtx_unlock(&sscreen
->aux_context_lock
);
405 void si_texture_discard_cmask(struct si_screen
*sscreen
,
406 struct r600_texture
*rtex
)
408 if (!rtex
->cmask
.size
)
411 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
414 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
415 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
416 rtex
->dirty_level_mask
= 0;
418 rtex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
420 if (rtex
->cmask_buffer
!= &rtex
->resource
)
421 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
423 /* Notify all contexts about the change. */
424 p_atomic_inc(&sscreen
->dirty_tex_counter
);
425 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
428 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
430 /* We can't disable DCC if it can be written by another process. */
431 return rtex
->dcc_offset
&&
432 (!rtex
->resource
.b
.is_shared
||
433 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
436 static bool r600_texture_discard_dcc(struct si_screen
*sscreen
,
437 struct r600_texture
*rtex
)
439 if (!r600_can_disable_dcc(rtex
))
442 assert(rtex
->dcc_separate_buffer
== NULL
);
445 rtex
->dcc_offset
= 0;
447 /* Notify all contexts about the change. */
448 p_atomic_inc(&sscreen
->dirty_tex_counter
);
453 * Disable DCC for the texture. (first decompress, then discard metadata).
455 * There is unresolved multi-context synchronization issue between
456 * screen::aux_context and the current context. If applications do this with
457 * multiple contexts, it's already undefined behavior for them and we don't
458 * have to worry about that. The scenario is:
460 * If context 1 disables DCC and context 2 has queued commands that write
461 * to the texture via CB with DCC enabled, and the order of operations is
463 * context 2 queues draw calls rendering to the texture, but doesn't flush
464 * context 1 disables DCC and flushes
465 * context 1 & 2 reset descriptors and FB state
466 * context 2 flushes (new compressed tiles written by the draw calls)
467 * context 1 & 2 read garbage, because DCC is disabled, yet there are
470 * \param sctx the current context if you have one, or rscreen->aux_context
473 bool si_texture_disable_dcc(struct si_context
*sctx
,
474 struct r600_texture
*rtex
)
476 struct si_screen
*sscreen
= sctx
->screen
;
478 if (!r600_can_disable_dcc(rtex
))
481 if (&sctx
->b
.b
== sscreen
->aux_context
)
482 mtx_lock(&sscreen
->aux_context_lock
);
484 /* Decompress DCC. */
485 si_decompress_dcc(&sctx
->b
.b
, rtex
);
486 sctx
->b
.b
.flush(&sctx
->b
.b
, NULL
, 0);
488 if (&sctx
->b
.b
== sscreen
->aux_context
)
489 mtx_unlock(&sscreen
->aux_context_lock
);
491 return r600_texture_discard_dcc(sscreen
, rtex
);
494 static void r600_reallocate_texture_inplace(struct si_context
*sctx
,
495 struct r600_texture
*rtex
,
496 unsigned new_bind_flag
,
497 bool invalidate_storage
)
499 struct pipe_screen
*screen
= sctx
->b
.b
.screen
;
500 struct r600_texture
*new_tex
;
501 struct pipe_resource templ
= rtex
->resource
.b
.b
;
504 templ
.bind
|= new_bind_flag
;
506 if (rtex
->resource
.b
.is_shared
)
509 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
510 if (rtex
->surface
.is_linear
)
513 /* This fails with MSAA, depth, and compressed textures. */
514 if (r600_choose_tiling(sctx
->screen
, &templ
) !=
515 RADEON_SURF_MODE_LINEAR_ALIGNED
)
519 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
523 /* Copy the pixels to the new texture. */
524 if (!invalidate_storage
) {
525 for (i
= 0; i
<= templ
.last_level
; i
++) {
529 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
530 util_num_layers(&templ
, i
), &box
);
532 sctx
->b
.dma_copy(&sctx
->b
.b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
533 &rtex
->resource
.b
.b
, i
, &box
);
537 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
538 si_texture_discard_cmask(sctx
->screen
, rtex
);
539 r600_texture_discard_dcc(sctx
->screen
, rtex
);
542 /* Replace the structure fields of rtex. */
543 rtex
->resource
.b
.b
.bind
= templ
.bind
;
544 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
545 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
546 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
547 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
548 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
549 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
550 rtex
->resource
.domains
= new_tex
->resource
.domains
;
551 rtex
->resource
.flags
= new_tex
->resource
.flags
;
552 rtex
->size
= new_tex
->size
;
553 rtex
->db_render_format
= new_tex
->db_render_format
;
554 rtex
->db_compatible
= new_tex
->db_compatible
;
555 rtex
->can_sample_z
= new_tex
->can_sample_z
;
556 rtex
->can_sample_s
= new_tex
->can_sample_s
;
557 rtex
->surface
= new_tex
->surface
;
558 rtex
->fmask
= new_tex
->fmask
;
559 rtex
->cmask
= new_tex
->cmask
;
560 rtex
->cb_color_info
= new_tex
->cb_color_info
;
561 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
562 rtex
->htile_offset
= new_tex
->htile_offset
;
563 rtex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
564 rtex
->depth_cleared
= new_tex
->depth_cleared
;
565 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
566 rtex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
567 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
569 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
570 assert(!rtex
->htile_offset
);
571 assert(!rtex
->cmask
.size
);
572 assert(!rtex
->fmask
.size
);
573 assert(!rtex
->dcc_offset
);
574 assert(!rtex
->is_depth
);
577 r600_texture_reference(&new_tex
, NULL
);
579 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
582 static uint32_t si_get_bo_metadata_word1(struct si_screen
*sscreen
)
584 return (ATI_VENDOR_ID
<< 16) | sscreen
->info
.pci_id
;
587 static void si_query_opaque_metadata(struct si_screen
*sscreen
,
588 struct r600_texture
*rtex
,
589 struct radeon_bo_metadata
*md
)
591 struct pipe_resource
*res
= &rtex
->resource
.b
.b
;
592 static const unsigned char swizzle
[] = {
599 bool is_array
= util_texture_is_array(res
->target
);
601 /* DRM 2.x.x doesn't support this. */
602 if (sscreen
->info
.drm_major
!= 3)
605 assert(rtex
->dcc_separate_buffer
== NULL
);
606 assert(rtex
->fmask
.size
== 0);
608 /* Metadata image format format version 1:
609 * [0] = 1 (metadata format identifier)
610 * [1] = (VENDOR_ID << 16) | PCI_ID
611 * [2:9] = image descriptor for the whole resource
612 * [2] is always 0, because the base address is cleared
613 * [9] is the DCC offset bits [39:8] from the beginning of
615 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
618 md
->metadata
[0] = 1; /* metadata image format version 1 */
620 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
621 md
->metadata
[1] = si_get_bo_metadata_word1(sscreen
);
623 si_make_texture_descriptor(sscreen
, rtex
, true,
624 res
->target
, res
->format
,
625 swizzle
, 0, res
->last_level
, 0,
626 is_array
? res
->array_size
- 1 : 0,
627 res
->width0
, res
->height0
, res
->depth0
,
630 si_set_mutable_tex_desc_fields(sscreen
, rtex
, &rtex
->surface
.u
.legacy
.level
[0],
631 0, 0, rtex
->surface
.blk_w
, false, desc
);
633 /* Clear the base address and set the relative DCC offset. */
635 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
636 desc
[7] = rtex
->dcc_offset
>> 8;
638 /* Dwords [2:9] contain the image descriptor. */
639 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
640 md
->size_metadata
= 10 * 4;
642 /* Dwords [10:..] contain the mipmap level offsets. */
643 if (sscreen
->info
.chip_class
<= VI
) {
644 for (i
= 0; i
<= res
->last_level
; i
++)
645 md
->metadata
[10+i
] = rtex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
647 md
->size_metadata
+= (1 + res
->last_level
) * 4;
651 static void si_apply_opaque_metadata(struct si_screen
*sscreen
,
652 struct r600_texture
*rtex
,
653 struct radeon_bo_metadata
*md
)
655 uint32_t *desc
= &md
->metadata
[2];
657 if (sscreen
->info
.chip_class
< VI
)
660 /* Return if DCC is enabled. The texture should be set up with it
663 if (md
->size_metadata
>= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
664 md
->metadata
[0] != 0 &&
665 md
->metadata
[1] == si_get_bo_metadata_word1(sscreen
) &&
666 G_008F28_COMPRESSION_EN(desc
[6])) {
667 rtex
->dcc_offset
= (uint64_t)desc
[7] << 8;
671 /* Disable DCC. These are always set by texture_from_handle and must
674 rtex
->dcc_offset
= 0;
677 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
678 struct pipe_context
*ctx
,
679 struct pipe_resource
*resource
,
680 struct winsys_handle
*whandle
,
683 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
684 struct si_context
*sctx
;
685 struct r600_resource
*res
= (struct r600_resource
*)resource
;
686 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
687 struct radeon_bo_metadata metadata
;
688 bool update_metadata
= false;
689 unsigned stride
, offset
, slice_size
;
692 ctx
= threaded_context_unwrap_sync(ctx
);
693 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
695 if (resource
->target
!= PIPE_BUFFER
) {
696 /* This is not supported now, but it might be required for OpenCL
697 * interop in the future.
699 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
702 /* Move a suballocated texture into a non-suballocated allocation. */
703 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
704 rtex
->surface
.tile_swizzle
||
705 (rtex
->resource
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
706 sscreen
->info
.has_local_buffers
&&
707 whandle
->type
!= DRM_API_HANDLE_TYPE_KMS
)) {
708 assert(!res
->b
.is_shared
);
709 r600_reallocate_texture_inplace(sctx
, rtex
,
710 PIPE_BIND_SHARED
, false);
712 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
713 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
714 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
715 assert(rtex
->surface
.tile_swizzle
== 0);
718 /* Since shader image stores don't support DCC on VI,
719 * disable it for external clients that want write
722 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
723 if (si_texture_disable_dcc(sctx
, rtex
)) {
724 update_metadata
= true;
725 /* si_texture_disable_dcc flushes the context */
730 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
731 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
732 /* Eliminate fast clear (both CMASK and DCC) */
733 si_eliminate_fast_color_clear(sctx
, rtex
);
734 /* eliminate_fast_color_clear flushes the context */
737 /* Disable CMASK if flush_resource isn't going
740 if (rtex
->cmask
.size
)
741 si_texture_discard_cmask(sscreen
, rtex
);
745 if (!res
->b
.is_shared
|| update_metadata
) {
746 r600_texture_init_metadata(sscreen
, rtex
, &metadata
);
747 si_query_opaque_metadata(sscreen
, rtex
, &metadata
);
749 sscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
752 if (sscreen
->info
.chip_class
>= GFX9
) {
753 offset
= rtex
->surface
.u
.gfx9
.surf_offset
;
754 stride
= rtex
->surface
.u
.gfx9
.surf_pitch
*
756 slice_size
= rtex
->surface
.u
.gfx9
.surf_slice_size
;
758 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
759 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
761 slice_size
= (uint64_t)rtex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
764 /* Buffer exports are for the OpenCL interop. */
765 /* Move a suballocated buffer into a non-suballocated allocation. */
766 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
767 /* A DMABUF export always fails if the BO is local. */
768 (rtex
->resource
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
769 sscreen
->info
.has_local_buffers
)) {
770 assert(!res
->b
.is_shared
);
772 /* Allocate a new buffer with PIPE_BIND_SHARED. */
773 struct pipe_resource templ
= res
->b
.b
;
774 templ
.bind
|= PIPE_BIND_SHARED
;
776 struct pipe_resource
*newb
=
777 screen
->resource_create(screen
, &templ
);
781 /* Copy the old buffer contents to the new one. */
783 u_box_1d(0, newb
->width0
, &box
);
784 sctx
->b
.b
.resource_copy_region(&sctx
->b
.b
, newb
, 0, 0, 0, 0,
787 /* Move the new buffer storage to the old pipe_resource. */
788 si_replace_buffer_storage(&sctx
->b
.b
, &res
->b
.b
, newb
);
789 pipe_resource_reference(&newb
, NULL
);
791 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
792 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
802 sctx
->b
.b
.flush(&sctx
->b
.b
, NULL
, 0);
804 if (res
->b
.is_shared
) {
805 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
808 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
809 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
810 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
812 res
->b
.is_shared
= true;
813 res
->external_usage
= usage
;
816 return sscreen
->ws
->buffer_get_handle(res
->buf
, stride
, offset
,
817 slice_size
, whandle
);
820 static void r600_texture_destroy(struct pipe_screen
*screen
,
821 struct pipe_resource
*ptex
)
823 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
824 struct r600_resource
*resource
= &rtex
->resource
;
826 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
828 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
829 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
831 pb_reference(&resource
->buf
, NULL
);
832 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
833 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
837 static const struct u_resource_vtbl r600_texture_vtbl
;
839 /* The number of samples can be specified independently of the texture. */
840 void si_texture_get_fmask_info(struct si_screen
*sscreen
,
841 struct r600_texture
*rtex
,
843 struct r600_fmask_info
*out
)
845 /* FMASK is allocated like an ordinary texture. */
846 struct pipe_resource templ
= rtex
->resource
.b
.b
;
847 struct radeon_surf fmask
= {};
850 memset(out
, 0, sizeof(*out
));
852 if (sscreen
->info
.chip_class
>= GFX9
) {
853 out
->alignment
= rtex
->surface
.u
.gfx9
.fmask_alignment
;
854 out
->size
= rtex
->surface
.u
.gfx9
.fmask_size
;
855 out
->tile_swizzle
= rtex
->surface
.u
.gfx9
.fmask_tile_swizzle
;
859 templ
.nr_samples
= 1;
860 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
862 switch (nr_samples
) {
871 R600_ERR("Invalid sample count for FMASK allocation.\n");
875 if (sscreen
->ws
->surface_init(sscreen
->ws
, &templ
, flags
, bpe
,
876 RADEON_SURF_MODE_2D
, &fmask
)) {
877 R600_ERR("Got error in surface_init while allocating FMASK.\n");
881 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
883 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
884 if (out
->slice_tile_max
)
885 out
->slice_tile_max
-= 1;
887 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
888 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
889 out
->bank_height
= fmask
.u
.legacy
.bankh
;
890 out
->tile_swizzle
= fmask
.tile_swizzle
;
891 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
892 out
->size
= fmask
.surf_size
;
895 static void r600_texture_allocate_fmask(struct si_screen
*sscreen
,
896 struct r600_texture
*rtex
)
898 si_texture_get_fmask_info(sscreen
, rtex
,
899 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
901 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
902 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
905 void si_texture_get_cmask_info(struct si_screen
*sscreen
,
906 struct r600_texture
*rtex
,
907 struct r600_cmask_info
*out
)
909 unsigned pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
910 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
911 unsigned cl_width
, cl_height
;
913 if (sscreen
->info
.chip_class
>= GFX9
) {
914 out
->alignment
= rtex
->surface
.u
.gfx9
.cmask_alignment
;
915 out
->size
= rtex
->surface
.u
.gfx9
.cmask_size
;
932 case 16: /* Hawaii */
941 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
943 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
944 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
945 unsigned slice_elements
= (width
* height
) / (8*8);
947 /* Each element of CMASK is a nibble. */
948 unsigned slice_bytes
= slice_elements
/ 2;
950 out
->slice_tile_max
= (width
* height
) / (128*128);
951 if (out
->slice_tile_max
)
952 out
->slice_tile_max
-= 1;
954 out
->alignment
= MAX2(256, base_align
);
955 out
->size
= util_num_layers(&rtex
->resource
.b
.b
, 0) *
956 align(slice_bytes
, base_align
);
959 static void r600_texture_allocate_cmask(struct si_screen
*sscreen
,
960 struct r600_texture
*rtex
)
962 si_texture_get_cmask_info(sscreen
, rtex
, &rtex
->cmask
);
964 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
965 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
967 rtex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
970 static void r600_texture_get_htile_size(struct si_screen
*sscreen
,
971 struct r600_texture
*rtex
)
973 unsigned cl_width
, cl_height
, width
, height
;
974 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
975 unsigned num_pipes
= sscreen
->info
.num_tile_pipes
;
977 assert(sscreen
->info
.chip_class
<= VI
);
979 rtex
->surface
.htile_size
= 0;
981 /* HTILE is broken with 1D tiling on old kernels and CIK. */
982 if (sscreen
->info
.chip_class
>= CIK
&&
983 rtex
->surface
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
984 sscreen
->info
.drm_major
== 2 && sscreen
->info
.drm_minor
< 38)
987 /* Overalign HTILE on P2 configs to work around GPU hangs in
988 * piglit/depthstencil-render-miplevels 585.
990 * This has been confirmed to help Kabini & Stoney, where the hangs
991 * are always reproducible. I think I have seen the test hang
992 * on Carrizo too, though it was very rare there.
994 if (sscreen
->info
.chip_class
>= CIK
&& num_pipes
< 4)
1023 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
1024 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
1026 slice_elements
= (width
* height
) / (8 * 8);
1027 slice_bytes
= slice_elements
* 4;
1029 pipe_interleave_bytes
= sscreen
->info
.pipe_interleave_bytes
;
1030 base_align
= num_pipes
* pipe_interleave_bytes
;
1032 rtex
->surface
.htile_alignment
= base_align
;
1033 rtex
->surface
.htile_size
=
1034 util_num_layers(&rtex
->resource
.b
.b
, 0) *
1035 align(slice_bytes
, base_align
);
1038 static void r600_texture_allocate_htile(struct si_screen
*sscreen
,
1039 struct r600_texture
*rtex
)
1041 if (sscreen
->info
.chip_class
<= VI
&& !rtex
->tc_compatible_htile
)
1042 r600_texture_get_htile_size(sscreen
, rtex
);
1044 if (!rtex
->surface
.htile_size
)
1047 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
1048 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
1051 void si_print_texture_info(struct si_screen
*sscreen
,
1052 struct r600_texture
*rtex
, struct u_log_context
*log
)
1056 /* Common parameters. */
1057 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
1058 "blk_h=%u, array_size=%u, last_level=%u, "
1059 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
1060 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
1061 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
1062 rtex
->surface
.blk_h
,
1063 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
1064 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
1065 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
1067 if (sscreen
->info
.chip_class
>= GFX9
) {
1068 u_log_printf(log
, " Surf: size=%"PRIu64
", slice_size=%"PRIu64
", "
1069 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
1070 rtex
->surface
.surf_size
,
1071 rtex
->surface
.u
.gfx9
.surf_slice_size
,
1072 rtex
->surface
.surf_alignment
,
1073 rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
1074 rtex
->surface
.u
.gfx9
.surf
.epitch
,
1075 rtex
->surface
.u
.gfx9
.surf_pitch
);
1077 if (rtex
->fmask
.size
) {
1078 u_log_printf(log
, " FMASK: offset=%"PRIu64
", size=%"PRIu64
", "
1079 "alignment=%u, swmode=%u, epitch=%u\n",
1081 rtex
->surface
.u
.gfx9
.fmask_size
,
1082 rtex
->surface
.u
.gfx9
.fmask_alignment
,
1083 rtex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
1084 rtex
->surface
.u
.gfx9
.fmask
.epitch
);
1087 if (rtex
->cmask
.size
) {
1088 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", "
1089 "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
1091 rtex
->surface
.u
.gfx9
.cmask_size
,
1092 rtex
->surface
.u
.gfx9
.cmask_alignment
,
1093 rtex
->surface
.u
.gfx9
.cmask
.rb_aligned
,
1094 rtex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
1097 if (rtex
->htile_offset
) {
1098 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, alignment=%u, "
1099 "rb_aligned=%u, pipe_aligned=%u\n",
1101 rtex
->surface
.htile_size
,
1102 rtex
->surface
.htile_alignment
,
1103 rtex
->surface
.u
.gfx9
.htile
.rb_aligned
,
1104 rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
1107 if (rtex
->dcc_offset
) {
1108 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, "
1109 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
1110 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1111 rtex
->surface
.dcc_alignment
,
1112 rtex
->surface
.u
.gfx9
.dcc_pitch_max
,
1113 rtex
->surface
.num_dcc_levels
);
1116 if (rtex
->surface
.u
.gfx9
.stencil_offset
) {
1117 u_log_printf(log
, " Stencil: offset=%"PRIu64
", swmode=%u, epitch=%u\n",
1118 rtex
->surface
.u
.gfx9
.stencil_offset
,
1119 rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
1120 rtex
->surface
.u
.gfx9
.stencil
.epitch
);
1125 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
1126 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
1127 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
1128 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
1129 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
1130 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
1132 if (rtex
->fmask
.size
)
1133 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
1134 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
1135 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
1136 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
1137 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
1139 if (rtex
->cmask
.size
)
1140 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
1141 "slice_tile_max=%u\n",
1142 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
1143 rtex
->cmask
.slice_tile_max
);
1145 if (rtex
->htile_offset
)
1146 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u, "
1147 "alignment=%u, TC_compatible = %u\n",
1148 rtex
->htile_offset
, rtex
->surface
.htile_size
,
1149 rtex
->surface
.htile_alignment
,
1150 rtex
->tc_compatible_htile
);
1152 if (rtex
->dcc_offset
) {
1153 u_log_printf(log
, " DCC: offset=%"PRIu64
", size=%u, alignment=%u\n",
1154 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1155 rtex
->surface
.dcc_alignment
);
1156 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1157 u_log_printf(log
, " DCCLevel[%i]: enabled=%u, offset=%u, "
1158 "fast_clear_size=%u\n",
1159 i
, i
< rtex
->surface
.num_dcc_levels
,
1160 rtex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
1161 rtex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
1164 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
1165 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1166 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1167 "mode=%u, tiling_index = %u\n",
1168 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
1169 (uint64_t)rtex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
1170 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1171 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1172 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1173 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
1174 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
1175 rtex
->surface
.u
.legacy
.level
[i
].mode
,
1176 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
1178 if (rtex
->surface
.has_stencil
) {
1179 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
1180 rtex
->surface
.u
.legacy
.stencil_tile_split
);
1181 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
1182 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
1183 "slice_size=%"PRIu64
", npix_x=%u, "
1184 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1185 "mode=%u, tiling_index = %u\n",
1186 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
1187 (uint64_t)rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
1188 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1189 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1190 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1191 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
1192 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
1193 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
1194 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
1199 /* Common processing for r600_texture_create and r600_texture_from_handle */
1200 static struct r600_texture
*
1201 r600_texture_create_object(struct pipe_screen
*screen
,
1202 const struct pipe_resource
*base
,
1203 struct pb_buffer
*buf
,
1204 struct radeon_surf
*surface
)
1206 struct r600_texture
*rtex
;
1207 struct r600_resource
*resource
;
1208 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1210 rtex
= CALLOC_STRUCT(r600_texture
);
1214 resource
= &rtex
->resource
;
1215 resource
->b
.b
= *base
;
1216 resource
->b
.b
.next
= NULL
;
1217 resource
->b
.vtbl
= &r600_texture_vtbl
;
1218 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1219 resource
->b
.b
.screen
= screen
;
1221 /* don't include stencil-only formats which we don't support for rendering */
1222 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1224 rtex
->surface
= *surface
;
1225 rtex
->size
= rtex
->surface
.surf_size
;
1227 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0 &&
1228 (rtex
->surface
.flags
&
1229 RADEON_SURF_TC_COMPATIBLE_HTILE
);
1231 /* TC-compatible HTILE:
1232 * - VI only supports Z32_FLOAT.
1233 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1234 if (rtex
->tc_compatible_htile
) {
1235 if (sscreen
->info
.chip_class
>= GFX9
&&
1236 base
->format
== PIPE_FORMAT_Z16_UNORM
)
1237 rtex
->db_render_format
= base
->format
;
1239 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1240 rtex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1241 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1244 rtex
->db_render_format
= base
->format
;
1247 /* Applies to GCN. */
1248 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1250 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1251 * between frames, so the only thing that can enable separate DCC
1252 * with DRI2 is multiple slow clears within a frame.
1254 rtex
->ps_draw_ratio
= 0;
1256 if (rtex
->is_depth
) {
1257 if (sscreen
->info
.chip_class
>= GFX9
) {
1258 rtex
->can_sample_z
= true;
1259 rtex
->can_sample_s
= true;
1261 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
1262 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
1265 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1266 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1267 rtex
->db_compatible
= true;
1269 if (!(sscreen
->debug_flags
& DBG(NO_HYPERZ
)))
1270 r600_texture_allocate_htile(sscreen
, rtex
);
1273 if (base
->nr_samples
> 1 &&
1275 !(sscreen
->debug_flags
& DBG(NO_FMASK
))) {
1276 r600_texture_allocate_fmask(sscreen
, rtex
);
1277 r600_texture_allocate_cmask(sscreen
, rtex
);
1278 rtex
->cmask_buffer
= &rtex
->resource
;
1280 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1286 /* Shared textures must always set up DCC here.
1287 * If it's not present, it will be disabled by
1288 * apply_opaque_metadata later.
1290 if (rtex
->surface
.dcc_size
&&
1291 (buf
|| !(sscreen
->debug_flags
& DBG(NO_DCC
))) &&
1292 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1293 /* Reserve space for the DCC buffer. */
1294 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1295 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1299 /* Now create the backing buffer. */
1301 si_init_resource_fields(sscreen
, resource
, rtex
->size
,
1302 rtex
->surface
.surf_alignment
);
1304 if (!si_alloc_resource(sscreen
, resource
)) {
1309 resource
->buf
= buf
;
1310 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1311 resource
->bo_size
= buf
->size
;
1312 resource
->bo_alignment
= buf
->alignment
;
1313 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1314 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1315 resource
->vram_usage
= buf
->size
;
1316 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1317 resource
->gart_usage
= buf
->size
;
1320 if (rtex
->cmask
.size
) {
1321 /* Initialize the cmask to 0xCC (= compressed state). */
1322 si_screen_clear_buffer(sscreen
, &rtex
->cmask_buffer
->b
.b
,
1323 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1326 if (rtex
->htile_offset
) {
1327 uint32_t clear_value
= 0;
1329 if (sscreen
->info
.chip_class
>= GFX9
|| rtex
->tc_compatible_htile
)
1330 clear_value
= 0x0000030F;
1332 si_screen_clear_buffer(sscreen
, &rtex
->resource
.b
.b
,
1334 rtex
->surface
.htile_size
,
1338 /* Initialize DCC only if the texture is not being imported. */
1339 if (!buf
&& rtex
->dcc_offset
) {
1340 si_screen_clear_buffer(sscreen
, &rtex
->resource
.b
.b
,
1342 rtex
->surface
.dcc_size
,
1346 /* Initialize the CMASK base register value. */
1347 rtex
->cmask
.base_address_reg
=
1348 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1350 if (sscreen
->debug_flags
& DBG(VM
)) {
1351 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1352 rtex
->resource
.gpu_address
,
1353 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1354 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1355 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1358 if (sscreen
->debug_flags
& DBG(TEX
)) {
1360 struct u_log_context log
;
1361 u_log_context_init(&log
);
1362 si_print_texture_info(sscreen
, rtex
, &log
);
1363 u_log_new_page_print(&log
, stdout
);
1365 u_log_context_destroy(&log
);
1371 static enum radeon_surf_mode
1372 r600_choose_tiling(struct si_screen
*sscreen
,
1373 const struct pipe_resource
*templ
)
1375 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1376 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1377 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1378 !(templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1380 /* MSAA resources must be 2D tiled. */
1381 if (templ
->nr_samples
> 1)
1382 return RADEON_SURF_MODE_2D
;
1384 /* Transfer resources should be linear. */
1385 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1386 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1388 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
1389 * which requires 2D tiling.
1391 if (sscreen
->info
.chip_class
== VI
&&
1393 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
))
1394 return RADEON_SURF_MODE_2D
;
1396 /* Handle common candidates for the linear mode.
1397 * Compressed textures and DB surfaces must always be tiled.
1399 if (!force_tiling
&&
1400 !is_depth_stencil
&&
1401 !util_format_is_compressed(templ
->format
)) {
1402 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1403 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1405 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1406 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1407 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1409 /* Cursors are linear on SI.
1410 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1411 if (templ
->bind
& PIPE_BIND_CURSOR
)
1412 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1414 if (templ
->bind
& PIPE_BIND_LINEAR
)
1415 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1417 /* Textures with a very small height are recommended to be linear. */
1418 if (templ
->target
== PIPE_TEXTURE_1D
||
1419 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1420 /* Only very thin and long 2D textures should benefit from
1421 * linear_aligned. */
1422 (templ
->width0
> 8 && templ
->height0
<= 2))
1423 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1425 /* Textures likely to be mapped often. */
1426 if (templ
->usage
== PIPE_USAGE_STAGING
||
1427 templ
->usage
== PIPE_USAGE_STREAM
)
1428 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1431 /* Make small textures 1D tiled. */
1432 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1433 (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1434 return RADEON_SURF_MODE_1D
;
1436 /* The allocator will switch to 1D if needed. */
1437 return RADEON_SURF_MODE_2D
;
1440 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1441 const struct pipe_resource
*templ
)
1443 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1444 struct radeon_surf surface
= {0};
1445 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1446 bool tc_compatible_htile
=
1447 sscreen
->info
.chip_class
>= VI
&&
1448 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1449 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) &&
1450 !is_flushed_depth
&&
1451 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1452 util_format_is_depth_or_stencil(templ
->format
);
1456 r
= r600_init_surface(sscreen
, &surface
, templ
,
1457 r600_choose_tiling(sscreen
, templ
), 0, 0,
1458 false, false, is_flushed_depth
,
1459 tc_compatible_htile
);
1464 return (struct pipe_resource
*)
1465 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1468 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1469 const struct pipe_resource
*templ
,
1470 struct winsys_handle
*whandle
,
1473 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1474 struct pb_buffer
*buf
= NULL
;
1475 unsigned stride
= 0, offset
= 0;
1476 enum radeon_surf_mode array_mode
;
1477 struct radeon_surf surface
= {};
1479 struct radeon_bo_metadata metadata
= {};
1480 struct r600_texture
*rtex
;
1483 /* Support only 2D textures without mipmaps */
1484 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1485 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1488 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, &stride
, &offset
);
1492 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1493 r600_surface_import_metadata(sscreen
, &surface
, &metadata
,
1494 &array_mode
, &is_scanout
);
1496 r
= r600_init_surface(sscreen
, &surface
, templ
, array_mode
, stride
,
1497 offset
, true, is_scanout
, false, false);
1502 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1506 rtex
->resource
.b
.is_shared
= true;
1507 rtex
->resource
.external_usage
= usage
;
1509 si_apply_opaque_metadata(sscreen
, rtex
, &metadata
);
1511 assert(rtex
->surface
.tile_swizzle
== 0);
1512 return &rtex
->resource
.b
.b
;
1515 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
,
1516 struct pipe_resource
*texture
,
1517 struct r600_texture
**staging
)
1519 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1520 struct pipe_resource resource
;
1521 struct r600_texture
**flushed_depth_texture
= staging
?
1522 staging
: &rtex
->flushed_depth_texture
;
1523 enum pipe_format pipe_format
= texture
->format
;
1526 if (rtex
->flushed_depth_texture
)
1527 return true; /* it's ready */
1529 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1530 switch (pipe_format
) {
1531 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1532 /* Save memory by not allocating the S plane. */
1533 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1535 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1536 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1537 /* Save memory bandwidth by not copying the
1538 * stencil part during flush.
1540 * This potentially increases memory bandwidth
1541 * if an application uses both Z and S texturing
1542 * simultaneously (a flushed Z24S8 texture
1543 * would be stored compactly), but how often
1544 * does that really happen?
1546 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1550 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1551 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1553 /* DB->CB copies to an 8bpp surface don't work. */
1554 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1558 memset(&resource
, 0, sizeof(resource
));
1559 resource
.target
= texture
->target
;
1560 resource
.format
= pipe_format
;
1561 resource
.width0
= texture
->width0
;
1562 resource
.height0
= texture
->height0
;
1563 resource
.depth0
= texture
->depth0
;
1564 resource
.array_size
= texture
->array_size
;
1565 resource
.last_level
= texture
->last_level
;
1566 resource
.nr_samples
= texture
->nr_samples
;
1567 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1568 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1569 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1572 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1574 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1575 if (*flushed_depth_texture
== NULL
) {
1576 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1583 * Initialize the pipe_resource descriptor to be of the same size as the box,
1584 * which is supposed to hold a subregion of the texture "orig" at the given
1587 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1588 struct pipe_resource
*orig
,
1589 const struct pipe_box
*box
,
1590 unsigned level
, unsigned flags
)
1592 memset(res
, 0, sizeof(*res
));
1593 res
->format
= orig
->format
;
1594 res
->width0
= box
->width
;
1595 res
->height0
= box
->height
;
1597 res
->array_size
= 1;
1598 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1601 /* We must set the correct texture target and dimensions for a 3D box. */
1602 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1603 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1604 res
->array_size
= box
->depth
;
1606 res
->target
= PIPE_TEXTURE_2D
;
1610 static bool r600_can_invalidate_texture(struct si_screen
*sscreen
,
1611 struct r600_texture
*rtex
,
1612 unsigned transfer_usage
,
1613 const struct pipe_box
*box
)
1615 return !rtex
->resource
.b
.is_shared
&&
1616 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1617 rtex
->resource
.b
.b
.last_level
== 0 &&
1618 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1619 box
->x
, box
->y
, box
->z
,
1620 box
->width
, box
->height
,
1624 static void r600_texture_invalidate_storage(struct si_context
*sctx
,
1625 struct r600_texture
*rtex
)
1627 struct si_screen
*sscreen
= sctx
->screen
;
1629 /* There is no point in discarding depth and tiled buffers. */
1630 assert(!rtex
->is_depth
);
1631 assert(rtex
->surface
.is_linear
);
1633 /* Reallocate the buffer in the same pipe_resource. */
1634 si_alloc_resource(sscreen
, &rtex
->resource
);
1636 /* Initialize the CMASK base address (needed even without CMASK). */
1637 rtex
->cmask
.base_address_reg
=
1638 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1640 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1642 sctx
->b
.num_alloc_tex_transfer_bytes
+= rtex
->size
;
1645 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1646 struct pipe_resource
*texture
,
1649 const struct pipe_box
*box
,
1650 struct pipe_transfer
**ptransfer
)
1652 struct si_context
*sctx
= (struct si_context
*)ctx
;
1653 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1654 struct r600_transfer
*trans
;
1655 struct r600_resource
*buf
;
1656 unsigned offset
= 0;
1658 bool use_staging_texture
= false;
1660 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1661 assert(box
->width
&& box
->height
&& box
->depth
);
1663 /* Depth textures use staging unconditionally. */
1664 if (!rtex
->is_depth
) {
1665 /* Degrade the tile mode if we get too many transfers on APUs.
1666 * On dGPUs, the staging texture is always faster.
1667 * Only count uploads that are at least 4x4 pixels large.
1669 if (!sctx
->screen
->info
.has_dedicated_vram
&&
1671 box
->width
>= 4 && box
->height
>= 4 &&
1672 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1673 bool can_invalidate
=
1674 r600_can_invalidate_texture(sctx
->screen
, rtex
,
1677 r600_reallocate_texture_inplace(sctx
, rtex
,
1682 /* Tiled textures need to be converted into a linear texture for CPU
1683 * access. The staging texture is always linear and is placed in GART.
1685 * Reading from VRAM or GTT WC is slow, always use the staging
1686 * texture in this case.
1688 * Use the staging texture for uploads if the underlying BO
1691 if (!rtex
->surface
.is_linear
)
1692 use_staging_texture
= true;
1693 else if (usage
& PIPE_TRANSFER_READ
)
1694 use_staging_texture
=
1695 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1696 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1697 /* Write & linear only: */
1698 else if (si_rings_is_buffer_referenced(sctx
, rtex
->resource
.buf
,
1699 RADEON_USAGE_READWRITE
) ||
1700 !sctx
->b
.ws
->buffer_wait(rtex
->resource
.buf
, 0,
1701 RADEON_USAGE_READWRITE
)) {
1703 if (r600_can_invalidate_texture(sctx
->screen
, rtex
,
1705 r600_texture_invalidate_storage(sctx
, rtex
);
1707 use_staging_texture
= true;
1711 trans
= CALLOC_STRUCT(r600_transfer
);
1714 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1715 trans
->b
.b
.level
= level
;
1716 trans
->b
.b
.usage
= usage
;
1717 trans
->b
.b
.box
= *box
;
1719 if (rtex
->is_depth
) {
1720 struct r600_texture
*staging_depth
;
1722 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1723 /* MSAA depth buffers need to be converted to single sample buffers.
1725 * Mapping MSAA depth buffers can occur if ReadPixels is called
1726 * with a multisample GLX visual.
1728 * First downsample the depth buffer to a temporary texture,
1729 * then decompress the temporary one to staging.
1731 * Only the region being mapped is transfered.
1733 struct pipe_resource resource
;
1735 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1737 if (!si_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1738 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1743 if (usage
& PIPE_TRANSFER_READ
) {
1744 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1746 R600_ERR("failed to create a temporary depth texture\n");
1751 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1752 si_blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1753 0, 0, 0, box
->depth
, 0, 0);
1754 pipe_resource_reference(&temp
, NULL
);
1757 /* Just get the strides. */
1758 r600_texture_get_offset(sctx
->screen
, staging_depth
, level
, NULL
,
1760 &trans
->b
.b
.layer_stride
);
1762 /* XXX: only readback the rectangle which is being mapped? */
1763 /* XXX: when discard is true, no need to read back from depth texture */
1764 if (!si_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1765 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1770 si_blit_decompress_depth(ctx
, rtex
, staging_depth
,
1772 box
->z
, box
->z
+ box
->depth
- 1,
1775 offset
= r600_texture_get_offset(sctx
->screen
, staging_depth
,
1778 &trans
->b
.b
.layer_stride
);
1781 trans
->staging
= (struct r600_resource
*)staging_depth
;
1782 buf
= trans
->staging
;
1783 } else if (use_staging_texture
) {
1784 struct pipe_resource resource
;
1785 struct r600_texture
*staging
;
1787 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1788 R600_RESOURCE_FLAG_TRANSFER
);
1789 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1790 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1792 /* Create the temporary texture. */
1793 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1795 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1799 trans
->staging
= &staging
->resource
;
1801 /* Just get the strides. */
1802 r600_texture_get_offset(sctx
->screen
, staging
, 0, NULL
,
1804 &trans
->b
.b
.layer_stride
);
1806 if (usage
& PIPE_TRANSFER_READ
)
1807 r600_copy_to_staging_texture(ctx
, trans
);
1809 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1811 buf
= trans
->staging
;
1813 /* the resource is mapped directly */
1814 offset
= r600_texture_get_offset(sctx
->screen
, rtex
, level
, box
,
1816 &trans
->b
.b
.layer_stride
);
1817 buf
= &rtex
->resource
;
1820 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
))) {
1821 r600_resource_reference(&trans
->staging
, NULL
);
1826 *ptransfer
= &trans
->b
.b
;
1827 return map
+ offset
;
1830 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1831 struct pipe_transfer
* transfer
)
1833 struct si_context
*sctx
= (struct si_context
*)ctx
;
1834 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1835 struct pipe_resource
*texture
= transfer
->resource
;
1836 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1838 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1839 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1840 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1841 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1842 &rtransfer
->staging
->b
.b
, transfer
->level
,
1845 r600_copy_from_staging_texture(ctx
, rtransfer
);
1849 if (rtransfer
->staging
) {
1850 sctx
->b
.num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1851 r600_resource_reference(&rtransfer
->staging
, NULL
);
1854 /* Heuristic for {upload, draw, upload, draw, ..}:
1856 * Flush the gfx IB if we've allocated too much texture storage.
1858 * The idea is that we don't want to build IBs that use too much
1859 * memory and put pressure on the kernel memory manager and we also
1860 * want to make temporary and invalidated buffers go idle ASAP to
1861 * decrease the total memory usage or make them reusable. The memory
1862 * usage will be slightly higher than given here because of the buffer
1863 * cache in the winsys.
1865 * The result is that the kernel memory manager is never a bottleneck.
1867 if (sctx
->b
.num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
1868 si_flush_gfx_cs(sctx
, PIPE_FLUSH_ASYNC
, NULL
);
1869 sctx
->b
.num_alloc_tex_transfer_bytes
= 0;
1872 pipe_resource_reference(&transfer
->resource
, NULL
);
1876 static const struct u_resource_vtbl r600_texture_vtbl
=
1878 NULL
, /* get_handle */
1879 r600_texture_destroy
, /* resource_destroy */
1880 r600_texture_transfer_map
, /* transfer_map */
1881 u_default_transfer_flush_region
, /* transfer_flush_region */
1882 r600_texture_transfer_unmap
, /* transfer_unmap */
1885 /* DCC channel type categories within which formats can be reinterpreted
1886 * while keeping the same DCC encoding. The swizzle must also match. */
1887 enum dcc_channel_type
{
1889 /* uint and sint can be merged if we never use TC-compatible DCC clear
1890 * encoding with the clear value of 1. */
1893 dcc_channel_uint_10_10_10_2
,
1894 dcc_channel_incompatible
,
1897 /* Return the type of DCC encoding. */
1898 static enum dcc_channel_type
1899 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1903 /* Find the first non-void channel. */
1904 for (i
= 0; i
< desc
->nr_channels
; i
++)
1905 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1907 if (i
== desc
->nr_channels
)
1908 return dcc_channel_incompatible
;
1910 switch (desc
->channel
[i
].size
) {
1914 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1915 return dcc_channel_float
;
1916 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1917 return dcc_channel_uint
;
1918 return dcc_channel_sint
;
1920 return dcc_channel_uint_10_10_10_2
;
1922 return dcc_channel_incompatible
;
1926 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1927 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1928 enum pipe_format format2
)
1930 const struct util_format_description
*desc1
, *desc2
;
1931 enum dcc_channel_type type1
, type2
;
1934 if (format1
== format2
)
1937 desc1
= util_format_description(format1
);
1938 desc2
= util_format_description(format2
);
1940 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1943 /* Swizzles must be the same. */
1944 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1945 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1946 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1947 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1950 type1
= vi_get_dcc_channel_type(desc1
);
1951 type2
= vi_get_dcc_channel_type(desc2
);
1953 return type1
!= dcc_channel_incompatible
&&
1954 type2
!= dcc_channel_incompatible
&&
1958 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
,
1960 enum pipe_format view_format
)
1962 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1964 return vi_dcc_enabled(rtex
, level
) &&
1965 !vi_dcc_formats_compatible(tex
->format
, view_format
);
1968 /* This can't be merged with the above function, because
1969 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1970 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
,
1971 struct pipe_resource
*tex
,
1973 enum pipe_format view_format
)
1975 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1977 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
1978 if (!si_texture_disable_dcc(sctx
, (struct r600_texture
*)tex
))
1979 si_decompress_dcc(&sctx
->b
.b
, rtex
);
1982 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1983 struct pipe_resource
*texture
,
1984 const struct pipe_surface
*templ
,
1985 unsigned width0
, unsigned height0
,
1986 unsigned width
, unsigned height
)
1988 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1993 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1994 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1996 pipe_reference_init(&surface
->base
.reference
, 1);
1997 pipe_resource_reference(&surface
->base
.texture
, texture
);
1998 surface
->base
.context
= pipe
;
1999 surface
->base
.format
= templ
->format
;
2000 surface
->base
.width
= width
;
2001 surface
->base
.height
= height
;
2002 surface
->base
.u
= templ
->u
;
2004 surface
->width0
= width0
;
2005 surface
->height0
= height0
;
2007 surface
->dcc_incompatible
=
2008 texture
->target
!= PIPE_BUFFER
&&
2009 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
,
2011 return &surface
->base
;
2014 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
2015 struct pipe_resource
*tex
,
2016 const struct pipe_surface
*templ
)
2018 unsigned level
= templ
->u
.tex
.level
;
2019 unsigned width
= u_minify(tex
->width0
, level
);
2020 unsigned height
= u_minify(tex
->height0
, level
);
2021 unsigned width0
= tex
->width0
;
2022 unsigned height0
= tex
->height0
;
2024 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
2025 const struct util_format_description
*tex_desc
2026 = util_format_description(tex
->format
);
2027 const struct util_format_description
*templ_desc
2028 = util_format_description(templ
->format
);
2030 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
2032 /* Adjust size of surface if and only if the block width or
2033 * height is changed. */
2034 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
2035 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
2036 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
2037 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
2039 width
= nblks_x
* templ_desc
->block
.width
;
2040 height
= nblks_y
* templ_desc
->block
.height
;
2042 width0
= util_format_get_nblocksx(tex
->format
, width0
);
2043 height0
= util_format_get_nblocksy(tex
->format
, height0
);
2047 return si_create_surface_custom(pipe
, tex
, templ
,
2052 static void r600_surface_destroy(struct pipe_context
*pipe
,
2053 struct pipe_surface
*surface
)
2055 pipe_resource_reference(&surface
->texture
, NULL
);
2059 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
2061 const struct util_format_description
*desc
= util_format_description(format
);
2063 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
2065 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2066 return V_028C70_SWAP_STD
;
2068 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
2071 switch (desc
->nr_channels
) {
2073 if (HAS_SWIZZLE(0,X
))
2074 return V_028C70_SWAP_STD
; /* X___ */
2075 else if (HAS_SWIZZLE(3,X
))
2076 return V_028C70_SWAP_ALT_REV
; /* ___X */
2079 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
2080 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
2081 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
2082 return V_028C70_SWAP_STD
; /* XY__ */
2083 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
2084 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
2085 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
2087 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2088 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
2089 return V_028C70_SWAP_ALT
; /* X__Y */
2090 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
2091 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2094 if (HAS_SWIZZLE(0,X
))
2095 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2096 else if (HAS_SWIZZLE(0,Z
))
2097 return V_028C70_SWAP_STD_REV
; /* ZYX */
2100 /* check the middle channels, the 1st and 4th channel can be NONE */
2101 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
2102 return V_028C70_SWAP_STD
; /* XYZW */
2103 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
2104 return V_028C70_SWAP_STD_REV
; /* WZYX */
2105 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
2106 return V_028C70_SWAP_ALT
; /* ZYXW */
2107 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2110 return V_028C70_SWAP_ALT_REV
;
2112 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2119 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2121 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
,
2126 if (sctx
->b
.dcc_stats
[slot
].query_active
)
2127 vi_separate_dcc_stop_query(&sctx
->b
.b
,
2128 sctx
->b
.dcc_stats
[slot
].tex
);
2130 for (i
= 0; i
< ARRAY_SIZE(sctx
->b
.dcc_stats
[slot
].ps_stats
); i
++)
2131 if (sctx
->b
.dcc_stats
[slot
].ps_stats
[i
]) {
2132 sctx
->b
.b
.destroy_query(&sctx
->b
.b
,
2133 sctx
->b
.dcc_stats
[slot
].ps_stats
[i
]);
2134 sctx
->b
.dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2137 r600_texture_reference(&sctx
->b
.dcc_stats
[slot
].tex
, NULL
);
2141 * Return the per-context slot where DCC statistics queries for the texture live.
2143 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
,
2144 struct r600_texture
*tex
)
2146 int i
, empty_slot
= -1;
2148 /* Remove zombie textures (textures kept alive by this array only). */
2149 for (i
= 0; i
< ARRAY_SIZE(sctx
->b
.dcc_stats
); i
++)
2150 if (sctx
->b
.dcc_stats
[i
].tex
&&
2151 sctx
->b
.dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2152 vi_dcc_clean_up_context_slot(sctx
, i
);
2154 /* Find the texture. */
2155 for (i
= 0; i
< ARRAY_SIZE(sctx
->b
.dcc_stats
); i
++) {
2156 /* Return if found. */
2157 if (sctx
->b
.dcc_stats
[i
].tex
== tex
) {
2158 sctx
->b
.dcc_stats
[i
].last_use_timestamp
= os_time_get();
2162 /* Record the first seen empty slot. */
2163 if (empty_slot
== -1 && !sctx
->b
.dcc_stats
[i
].tex
)
2167 /* Not found. Remove the oldest member to make space in the array. */
2168 if (empty_slot
== -1) {
2169 int oldest_slot
= 0;
2171 /* Find the oldest slot. */
2172 for (i
= 1; i
< ARRAY_SIZE(sctx
->b
.dcc_stats
); i
++)
2173 if (sctx
->b
.dcc_stats
[oldest_slot
].last_use_timestamp
>
2174 sctx
->b
.dcc_stats
[i
].last_use_timestamp
)
2177 /* Clean up the oldest slot. */
2178 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2179 empty_slot
= oldest_slot
;
2182 /* Add the texture to the new slot. */
2183 r600_texture_reference(&sctx
->b
.dcc_stats
[empty_slot
].tex
, tex
);
2184 sctx
->b
.dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2188 static struct pipe_query
*
2189 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2191 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2192 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2194 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2195 return (struct pipe_query
*)query
;
2199 * Called when binding a color buffer.
2201 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2202 struct r600_texture
*tex
)
2204 struct si_context
*sctx
= (struct si_context
*)ctx
;
2205 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2207 assert(!sctx
->b
.dcc_stats
[i
].query_active
);
2209 if (!sctx
->b
.dcc_stats
[i
].ps_stats
[0])
2210 sctx
->b
.dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2212 /* begin or resume the query */
2213 ctx
->begin_query(ctx
, sctx
->b
.dcc_stats
[i
].ps_stats
[0]);
2214 sctx
->b
.dcc_stats
[i
].query_active
= true;
2218 * Called when unbinding a color buffer.
2220 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2221 struct r600_texture
*tex
)
2223 struct si_context
*sctx
= (struct si_context
*)ctx
;
2224 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2226 assert(sctx
->b
.dcc_stats
[i
].query_active
);
2227 assert(sctx
->b
.dcc_stats
[i
].ps_stats
[0]);
2229 /* pause or end the query */
2230 ctx
->end_query(ctx
, sctx
->b
.dcc_stats
[i
].ps_stats
[0]);
2231 sctx
->b
.dcc_stats
[i
].query_active
= false;
2234 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2236 /* The minimum number of fullscreen draws per frame that is required
2238 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2241 /* Called by fast clear. */
2242 void vi_separate_dcc_try_enable(struct si_context
*sctx
,
2243 struct r600_texture
*tex
)
2245 /* The intent is to use this with shared displayable back buffers,
2246 * but it's not strictly limited only to them.
2248 if (!tex
->resource
.b
.is_shared
||
2249 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2250 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2251 tex
->resource
.b
.b
.last_level
> 0 ||
2252 !tex
->surface
.dcc_size
)
2255 if (tex
->dcc_offset
)
2256 return; /* already enabled */
2258 /* Enable the DCC stat gathering. */
2259 if (!tex
->dcc_gather_statistics
) {
2260 tex
->dcc_gather_statistics
= true;
2261 vi_separate_dcc_start_query(&sctx
->b
.b
, tex
);
2264 if (!vi_should_enable_separate_dcc(tex
))
2265 return; /* stats show that DCC decompression is too expensive */
2267 assert(tex
->surface
.num_dcc_levels
);
2268 assert(!tex
->dcc_separate_buffer
);
2270 si_texture_discard_cmask(sctx
->screen
, tex
);
2272 /* Get a DCC buffer. */
2273 if (tex
->last_dcc_separate_buffer
) {
2274 assert(tex
->dcc_gather_statistics
);
2275 assert(!tex
->dcc_separate_buffer
);
2276 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2277 tex
->last_dcc_separate_buffer
= NULL
;
2279 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2280 si_aligned_buffer_create(sctx
->b
.b
.screen
,
2281 R600_RESOURCE_FLAG_UNMAPPABLE
,
2283 tex
->surface
.dcc_size
,
2284 tex
->surface
.dcc_alignment
);
2285 if (!tex
->dcc_separate_buffer
)
2289 /* dcc_offset is the absolute GPUVM address. */
2290 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2292 /* no need to flag anything since this is called by fast clear that
2293 * flags framebuffer state
2298 * Called by pipe_context::flush_resource, the place where DCC decompression
2301 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2302 struct r600_texture
*tex
)
2304 struct si_context
*sctx
= (struct si_context
*)ctx
;
2305 struct pipe_query
*tmp
;
2306 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2307 bool query_active
= sctx
->b
.dcc_stats
[i
].query_active
;
2308 bool disable
= false;
2310 if (sctx
->b
.dcc_stats
[i
].ps_stats
[2]) {
2311 union pipe_query_result result
;
2313 /* Read the results. */
2314 ctx
->get_query_result(ctx
, sctx
->b
.dcc_stats
[i
].ps_stats
[2],
2316 si_query_hw_reset_buffers(sctx
,
2317 (struct r600_query_hw
*)
2318 sctx
->b
.dcc_stats
[i
].ps_stats
[2]);
2320 /* Compute the approximate number of fullscreen draws. */
2321 tex
->ps_draw_ratio
=
2322 result
.pipeline_statistics
.ps_invocations
/
2323 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2324 sctx
->b
.last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2326 disable
= tex
->dcc_separate_buffer
&&
2327 !vi_should_enable_separate_dcc(tex
);
2330 tex
->num_slow_clears
= 0;
2332 /* stop the statistics query for ps_stats[0] */
2334 vi_separate_dcc_stop_query(ctx
, tex
);
2336 /* Move the queries in the queue by one. */
2337 tmp
= sctx
->b
.dcc_stats
[i
].ps_stats
[2];
2338 sctx
->b
.dcc_stats
[i
].ps_stats
[2] = sctx
->b
.dcc_stats
[i
].ps_stats
[1];
2339 sctx
->b
.dcc_stats
[i
].ps_stats
[1] = sctx
->b
.dcc_stats
[i
].ps_stats
[0];
2340 sctx
->b
.dcc_stats
[i
].ps_stats
[0] = tmp
;
2342 /* create and start a new query as ps_stats[0] */
2344 vi_separate_dcc_start_query(ctx
, tex
);
2347 assert(!tex
->last_dcc_separate_buffer
);
2348 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2349 tex
->dcc_separate_buffer
= NULL
;
2350 tex
->dcc_offset
= 0;
2351 /* no need to flag anything since this is called after
2352 * decompression that re-sets framebuffer state
2357 static struct pipe_memory_object
*
2358 r600_memobj_from_handle(struct pipe_screen
*screen
,
2359 struct winsys_handle
*whandle
,
2362 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2363 struct r600_memory_object
*memobj
= CALLOC_STRUCT(r600_memory_object
);
2364 struct pb_buffer
*buf
= NULL
;
2365 uint32_t stride
, offset
;
2370 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
,
2377 memobj
->b
.dedicated
= dedicated
;
2379 memobj
->stride
= stride
;
2380 memobj
->offset
= offset
;
2382 return (struct pipe_memory_object
*)memobj
;
2387 r600_memobj_destroy(struct pipe_screen
*screen
,
2388 struct pipe_memory_object
*_memobj
)
2390 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2392 pb_reference(&memobj
->buf
, NULL
);
2396 static struct pipe_resource
*
2397 r600_texture_from_memobj(struct pipe_screen
*screen
,
2398 const struct pipe_resource
*templ
,
2399 struct pipe_memory_object
*_memobj
,
2403 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2404 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
2405 struct r600_texture
*rtex
;
2406 struct radeon_surf surface
= {};
2407 struct radeon_bo_metadata metadata
= {};
2408 enum radeon_surf_mode array_mode
;
2410 struct pb_buffer
*buf
= NULL
;
2412 if (memobj
->b
.dedicated
) {
2413 sscreen
->ws
->buffer_get_metadata(memobj
->buf
, &metadata
);
2414 r600_surface_import_metadata(sscreen
, &surface
, &metadata
,
2415 &array_mode
, &is_scanout
);
2418 * The bo metadata is unset for un-dedicated images. So we fall
2419 * back to linear. See answer to question 5 of the
2420 * VK_KHX_external_memory spec for some details.
2422 * It is possible that this case isn't going to work if the
2423 * surface pitch isn't correctly aligned by default.
2425 * In order to support it correctly we require multi-image
2426 * metadata to be syncrhonized between radv and radeonsi. The
2427 * semantics of associating multiple image metadata to a memory
2428 * object on the vulkan export side are not concretely defined
2431 * All the use cases we are aware of at the moment for memory
2432 * objects use dedicated allocations. So lets keep the initial
2433 * implementation simple.
2435 * A possible alternative is to attempt to reconstruct the
2436 * tiling information when the TexParameter TEXTURE_TILING_EXT
2439 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
2444 r
= r600_init_surface(sscreen
, &surface
, templ
,
2445 array_mode
, memobj
->stride
,
2446 offset
, true, is_scanout
,
2451 rtex
= r600_texture_create_object(screen
, templ
, memobj
->buf
, &surface
);
2455 /* r600_texture_create_object doesn't increment refcount of
2456 * memobj->buf, so increment it here.
2458 pb_reference(&buf
, memobj
->buf
);
2460 rtex
->resource
.b
.is_shared
= true;
2461 rtex
->resource
.external_usage
= PIPE_HANDLE_USAGE_READ_WRITE
;
2463 si_apply_opaque_metadata(sscreen
, rtex
, &metadata
);
2465 return &rtex
->resource
.b
.b
;
2468 static bool si_check_resource_capability(struct pipe_screen
*screen
,
2469 struct pipe_resource
*resource
,
2472 struct r600_texture
*tex
= (struct r600_texture
*)resource
;
2474 /* Buffers only support the linear flag. */
2475 if (resource
->target
== PIPE_BUFFER
)
2476 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2478 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2481 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2484 /* TODO: PIPE_BIND_CURSOR - do we care? */
2488 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2490 sscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2491 sscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2492 sscreen
->b
.resource_from_memobj
= r600_texture_from_memobj
;
2493 sscreen
->b
.memobj_create_from_handle
= r600_memobj_from_handle
;
2494 sscreen
->b
.memobj_destroy
= r600_memobj_destroy
;
2495 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2498 void si_init_context_texture_functions(struct si_context
*sctx
)
2500 sctx
->b
.b
.create_surface
= r600_create_surface
;
2501 sctx
->b
.b
.surface_destroy
= r600_surface_destroy
;