2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
35 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
36 struct r600_texture
*rtex
);
37 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
38 const struct pipe_resource
*templ
);
41 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
42 struct r600_texture
*rdst
,
43 unsigned dst_level
, unsigned dstx
,
44 unsigned dsty
, unsigned dstz
,
45 struct r600_texture
*rsrc
,
47 const struct pipe_box
*src_box
)
52 if (util_format_get_blocksizebits(rdst
->resource
.b
.b
.format
) !=
53 util_format_get_blocksizebits(rsrc
->resource
.b
.b
.format
))
56 /* MSAA: Blits don't exist in the real world. */
57 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
58 rdst
->resource
.b
.b
.nr_samples
> 1)
61 /* Depth-stencil surfaces:
62 * When dst is linear, the DB->CB copy preserves HTILE.
63 * When dst is tiled, the 3D path must be used to update HTILE.
65 if (rsrc
->is_depth
|| rdst
->is_depth
)
69 * src: Use the 3D path. DCC decompression is expensive.
70 * dst: Use the 3D path to compress the pixels with DCC.
72 if ((rsrc
->dcc_offset
&& rsrc
->surface
.level
[src_level
].dcc_enabled
) ||
73 (rdst
->dcc_offset
&& rdst
->surface
.level
[dst_level
].dcc_enabled
))
77 * src: Both texture and SDMA paths need decompression. Use SDMA.
78 * dst: If overwriting the whole texture, discard CMASK and use
79 * SDMA. Otherwise, use the 3D path.
81 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
82 /* The CMASK clear is only enabled for the first level. */
83 assert(dst_level
== 0);
84 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
85 dstx
, dsty
, dstz
, src_box
->width
,
86 src_box
->height
, src_box
->depth
))
89 r600_texture_discard_cmask(rctx
->screen
, rdst
);
92 /* All requirements are met. Prepare textures for SDMA. */
93 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
94 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
96 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
97 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
102 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
103 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
104 struct pipe_resource
*dst
,
106 unsigned dstx
, unsigned dsty
, unsigned dstz
,
107 struct pipe_resource
*src
,
109 const struct pipe_box
*src_box
)
111 struct pipe_blit_info blit
;
113 memset(&blit
, 0, sizeof(blit
));
114 blit
.src
.resource
= src
;
115 blit
.src
.format
= src
->format
;
116 blit
.src
.level
= src_level
;
117 blit
.src
.box
= *src_box
;
118 blit
.dst
.resource
= dst
;
119 blit
.dst
.format
= dst
->format
;
120 blit
.dst
.level
= dst_level
;
121 blit
.dst
.box
.x
= dstx
;
122 blit
.dst
.box
.y
= dsty
;
123 blit
.dst
.box
.z
= dstz
;
124 blit
.dst
.box
.width
= src_box
->width
;
125 blit
.dst
.box
.height
= src_box
->height
;
126 blit
.dst
.box
.depth
= src_box
->depth
;
127 blit
.mask
= util_format_get_mask(src
->format
) &
128 util_format_get_mask(dst
->format
);
129 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
132 pipe
->blit(pipe
, &blit
);
136 /* Copy from a full GPU texture to a transfer's staging one. */
137 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
139 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
140 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
141 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
142 struct pipe_resource
*src
= transfer
->resource
;
144 if (src
->nr_samples
> 1) {
145 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
146 src
, transfer
->level
, &transfer
->box
);
150 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
154 /* Copy from a transfer's staging texture to a full GPU one. */
155 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
157 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
158 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
159 struct pipe_resource
*dst
= transfer
->resource
;
160 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
161 struct pipe_box sbox
;
163 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
165 if (dst
->nr_samples
> 1) {
166 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
167 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
172 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
173 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
177 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
178 const struct pipe_box
*box
)
180 enum pipe_format format
= rtex
->resource
.b
.b
.format
;
182 return rtex
->surface
.level
[level
].offset
+
183 box
->z
* rtex
->surface
.level
[level
].slice_size
+
184 box
->y
/ util_format_get_blockheight(format
) * rtex
->surface
.level
[level
].pitch_bytes
+
185 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
188 static int r600_init_surface(struct r600_common_screen
*rscreen
,
189 struct radeon_surf
*surface
,
190 const struct pipe_resource
*ptex
,
192 bool is_flushed_depth
)
194 const struct util_format_description
*desc
=
195 util_format_description(ptex
->format
);
196 bool is_depth
, is_stencil
;
198 is_depth
= util_format_has_depth(desc
);
199 is_stencil
= util_format_has_stencil(desc
);
201 surface
->npix_x
= ptex
->width0
;
202 surface
->npix_y
= ptex
->height0
;
203 surface
->npix_z
= ptex
->depth0
;
204 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
205 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
207 surface
->array_size
= 1;
208 surface
->last_level
= ptex
->last_level
;
210 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
211 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
212 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
214 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
215 /* align byte per element on dword */
216 if (surface
->bpe
== 3) {
221 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
222 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
224 switch (ptex
->target
) {
225 case PIPE_TEXTURE_1D
:
226 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
228 case PIPE_TEXTURE_RECT
:
229 case PIPE_TEXTURE_2D
:
230 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
232 case PIPE_TEXTURE_3D
:
233 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
235 case PIPE_TEXTURE_1D_ARRAY
:
236 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
237 surface
->array_size
= ptex
->array_size
;
239 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d array */
240 assert(ptex
->array_size
% 6 == 0);
241 case PIPE_TEXTURE_2D_ARRAY
:
242 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
243 surface
->array_size
= ptex
->array_size
;
245 case PIPE_TEXTURE_CUBE
:
246 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
253 if (!is_flushed_depth
&& is_depth
) {
254 surface
->flags
|= RADEON_SURF_ZBUFFER
;
257 surface
->flags
|= RADEON_SURF_SBUFFER
|
258 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
261 if (rscreen
->chip_class
>= SI
) {
262 surface
->flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
265 if (rscreen
->chip_class
>= VI
&&
266 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
267 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
268 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
270 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
271 /* This should catch bugs in gallium users setting incorrect flags. */
272 assert(surface
->nsamples
== 1 &&
273 surface
->array_size
== 1 &&
274 surface
->npix_z
== 1 &&
275 surface
->last_level
== 0 &&
276 !(surface
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
278 surface
->flags
|= RADEON_SURF_SCANOUT
;
283 static int r600_setup_surface(struct pipe_screen
*screen
,
284 struct r600_texture
*rtex
,
285 unsigned pitch_in_bytes_override
,
288 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
292 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
297 rtex
->size
= rtex
->surface
.bo_size
;
299 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
300 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
303 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
304 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
305 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
309 for (i
= 0; i
< ARRAY_SIZE(rtex
->surface
.level
); ++i
)
310 rtex
->surface
.level
[i
].offset
+= offset
;
315 static void r600_texture_init_metadata(struct r600_texture
*rtex
,
316 struct radeon_bo_metadata
*metadata
)
318 struct radeon_surf
*surface
= &rtex
->surface
;
320 memset(metadata
, 0, sizeof(*metadata
));
321 metadata
->microtile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
322 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
323 metadata
->macrotile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
324 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
325 metadata
->pipe_config
= surface
->pipe_config
;
326 metadata
->bankw
= surface
->bankw
;
327 metadata
->bankh
= surface
->bankh
;
328 metadata
->tile_split
= surface
->tile_split
;
329 metadata
->mtilea
= surface
->mtilea
;
330 metadata
->num_banks
= surface
->num_banks
;
331 metadata
->stride
= surface
->level
[0].pitch_bytes
;
332 metadata
->scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
335 static void r600_dirty_all_framebuffer_states(struct r600_common_screen
*rscreen
)
337 p_atomic_inc(&rscreen
->dirty_fb_counter
);
340 static void r600_eliminate_fast_color_clear(struct r600_common_screen
*rscreen
,
341 struct r600_texture
*rtex
)
343 struct pipe_context
*ctx
= rscreen
->aux_context
;
345 pipe_mutex_lock(rscreen
->aux_context_lock
);
346 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
347 ctx
->flush(ctx
, NULL
, 0);
348 pipe_mutex_unlock(rscreen
->aux_context_lock
);
351 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
352 struct r600_texture
*rtex
)
354 if (!rtex
->cmask
.size
)
357 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
360 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
361 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
363 if (rscreen
->chip_class
>= SI
)
364 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
366 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
368 if (rtex
->cmask_buffer
!= &rtex
->resource
)
369 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
371 /* Notify all contexts about the change. */
372 r600_dirty_all_framebuffer_states(rscreen
);
373 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
376 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
378 /* We can't disable DCC if it can be written by another process. */
379 return rtex
->dcc_offset
&&
380 (!rtex
->resource
.is_shared
||
381 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
384 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
385 struct r600_texture
*rtex
)
387 if (!r600_can_disable_dcc(rtex
))
390 assert(rtex
->dcc_separate_buffer
== NULL
);
393 rtex
->dcc_offset
= 0;
395 /* Notify all contexts about the change. */
396 r600_dirty_all_framebuffer_states(rscreen
);
400 bool r600_texture_disable_dcc(struct r600_common_screen
*rscreen
,
401 struct r600_texture
*rtex
)
403 struct r600_common_context
*rctx
=
404 (struct r600_common_context
*)rscreen
->aux_context
;
406 if (!r600_can_disable_dcc(rtex
))
409 /* Decompress DCC. */
410 pipe_mutex_lock(rscreen
->aux_context_lock
);
411 rctx
->decompress_dcc(&rctx
->b
, rtex
);
412 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
413 pipe_mutex_unlock(rscreen
->aux_context_lock
);
415 return r600_texture_discard_dcc(rscreen
, rtex
);
418 static void r600_degrade_tile_mode_to_linear(struct r600_common_context
*rctx
,
419 struct r600_texture
*rtex
,
420 bool invalidate_storage
)
422 struct pipe_screen
*screen
= rctx
->b
.screen
;
423 struct r600_texture
*new_tex
;
424 struct pipe_resource templ
= rtex
->resource
.b
.b
;
427 templ
.bind
|= PIPE_BIND_LINEAR
;
429 /* r600g doesn't react to dirty_tex_descriptor_counter */
430 if (rctx
->chip_class
< SI
)
433 if (rtex
->resource
.is_shared
||
434 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
)
437 /* This fails with MSAA, depth, and compressed textures. */
438 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
439 RADEON_SURF_MODE_LINEAR_ALIGNED
)
442 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
446 /* Copy the pixels to the new texture. */
447 if (!invalidate_storage
) {
448 for (i
= 0; i
<= templ
.last_level
; i
++) {
452 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
453 util_max_layer(&templ
, i
) + 1, &box
);
455 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
456 &rtex
->resource
.b
.b
, i
, &box
);
460 r600_texture_discard_cmask(rctx
->screen
, rtex
);
461 r600_texture_discard_dcc(rctx
->screen
, rtex
);
463 /* Replace the structure fields of rtex. */
464 rtex
->resource
.b
.b
.bind
= templ
.bind
;
465 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
466 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
467 rtex
->resource
.domains
= new_tex
->resource
.domains
;
468 rtex
->size
= new_tex
->size
;
469 rtex
->surface
= new_tex
->surface
;
470 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
471 rtex
->cb_color_info
= new_tex
->cb_color_info
;
472 rtex
->cmask
= new_tex
->cmask
; /* needed even without CMASK */
474 assert(!rtex
->htile_buffer
);
475 assert(!rtex
->cmask
.size
);
476 assert(!rtex
->fmask
.size
);
477 assert(!rtex
->dcc_offset
);
478 assert(!rtex
->is_depth
);
480 pipe_resource_reference((struct pipe_resource
**)&new_tex
, NULL
);
482 r600_dirty_all_framebuffer_states(rctx
->screen
);
483 p_atomic_inc(&rctx
->screen
->dirty_tex_descriptor_counter
);
486 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
487 struct pipe_resource
*resource
,
488 struct winsys_handle
*whandle
,
491 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
492 struct r600_resource
*res
= (struct r600_resource
*)resource
;
493 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
494 struct radeon_bo_metadata metadata
;
495 bool update_metadata
= false;
497 /* This is not supported now, but it might be required for OpenCL
498 * interop in the future.
500 if (resource
->target
!= PIPE_BUFFER
&&
501 (resource
->nr_samples
> 1 || rtex
->is_depth
))
504 if (resource
->target
!= PIPE_BUFFER
) {
505 /* Since shader image stores don't support DCC on VI,
506 * disable it for external clients that want write
509 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
510 if (r600_texture_disable_dcc(rscreen
, rtex
))
511 update_metadata
= true;
514 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
516 /* Eliminate fast clear (both CMASK and DCC) */
517 r600_eliminate_fast_color_clear(rscreen
, rtex
);
519 /* Disable CMASK if flush_resource isn't going
522 r600_texture_discard_cmask(rscreen
, rtex
);
526 if (!res
->is_shared
|| update_metadata
) {
527 r600_texture_init_metadata(rtex
, &metadata
);
528 if (rscreen
->query_opaque_metadata
)
529 rscreen
->query_opaque_metadata(rscreen
, rtex
,
532 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
536 if (res
->is_shared
) {
537 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
540 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
541 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
542 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
544 res
->is_shared
= true;
545 res
->external_usage
= usage
;
548 return rscreen
->ws
->buffer_get_handle(res
->buf
,
549 rtex
->surface
.level
[0].pitch_bytes
,
550 rtex
->surface
.level
[0].offset
,
551 rtex
->surface
.level
[0].slice_size
,
555 static void r600_texture_destroy(struct pipe_screen
*screen
,
556 struct pipe_resource
*ptex
)
558 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
559 struct r600_resource
*resource
= &rtex
->resource
;
561 if (rtex
->flushed_depth_texture
)
562 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
564 r600_resource_reference(&rtex
->htile_buffer
, NULL
);
565 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
566 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
568 pb_reference(&resource
->buf
, NULL
);
569 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
573 static const struct u_resource_vtbl r600_texture_vtbl
;
575 /* The number of samples can be specified independently of the texture. */
576 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
577 struct r600_texture
*rtex
,
579 struct r600_fmask_info
*out
)
581 /* FMASK is allocated like an ordinary texture. */
582 struct radeon_surf fmask
= rtex
->surface
;
584 memset(out
, 0, sizeof(*out
));
586 fmask
.bo_alignment
= 0;
589 fmask
.flags
|= RADEON_SURF_FMASK
;
591 /* Force 2D tiling if it wasn't set. This may occur when creating
592 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
593 * destination buffer must have an FMASK too. */
594 fmask
.flags
= RADEON_SURF_CLR(fmask
.flags
, MODE
);
595 fmask
.flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
597 if (rscreen
->chip_class
>= SI
) {
598 fmask
.flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
601 switch (nr_samples
) {
605 if (rscreen
->chip_class
<= CAYMAN
) {
613 R600_ERR("Invalid sample count for FMASK allocation.\n");
617 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
618 * This can be fixed by writing a separate FMASK allocator specifically
619 * for R600-R700 asics. */
620 if (rscreen
->chip_class
<= R700
) {
624 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
625 R600_ERR("Got error in surface_init while allocating FMASK.\n");
629 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
631 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
632 if (out
->slice_tile_max
)
633 out
->slice_tile_max
-= 1;
635 out
->tile_mode_index
= fmask
.tiling_index
[0];
636 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
637 out
->bank_height
= fmask
.bankh
;
638 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
639 out
->size
= fmask
.bo_size
;
642 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
643 struct r600_texture
*rtex
)
645 r600_texture_get_fmask_info(rscreen
, rtex
,
646 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
648 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
649 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
652 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
653 struct r600_texture
*rtex
,
654 struct r600_cmask_info
*out
)
656 unsigned cmask_tile_width
= 8;
657 unsigned cmask_tile_height
= 8;
658 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
659 unsigned element_bits
= 4;
660 unsigned cmask_cache_bits
= 1024;
661 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
662 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
664 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
665 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
666 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
667 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
668 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
670 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
671 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
673 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
674 unsigned slice_bytes
=
675 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
677 assert(macro_tile_width
% 128 == 0);
678 assert(macro_tile_height
% 128 == 0);
680 out
->pitch
= pitch_elements
;
681 out
->height
= height
;
682 out
->xalign
= macro_tile_width
;
683 out
->yalign
= macro_tile_height
;
684 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
685 out
->alignment
= MAX2(256, base_align
);
686 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
687 align(slice_bytes
, base_align
);
690 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
691 struct r600_texture
*rtex
,
692 struct r600_cmask_info
*out
)
694 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
695 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
696 unsigned cl_width
, cl_height
;
711 case 16: /* Hawaii */
720 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
722 unsigned width
= align(rtex
->surface
.npix_x
, cl_width
*8);
723 unsigned height
= align(rtex
->surface
.npix_y
, cl_height
*8);
724 unsigned slice_elements
= (width
* height
) / (8*8);
726 /* Each element of CMASK is a nibble. */
727 unsigned slice_bytes
= slice_elements
/ 2;
730 out
->height
= height
;
731 out
->xalign
= cl_width
* 8;
732 out
->yalign
= cl_height
* 8;
733 out
->slice_tile_max
= (width
* height
) / (128*128);
734 if (out
->slice_tile_max
)
735 out
->slice_tile_max
-= 1;
737 out
->alignment
= MAX2(256, base_align
);
738 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
739 align(slice_bytes
, base_align
);
742 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
743 struct r600_texture
*rtex
)
745 if (rscreen
->chip_class
>= SI
) {
746 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
748 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
751 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
752 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
754 if (rscreen
->chip_class
>= SI
)
755 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
757 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
760 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
761 struct r600_texture
*rtex
)
763 if (rtex
->cmask_buffer
)
766 assert(rtex
->cmask
.size
== 0);
768 if (rscreen
->chip_class
>= SI
) {
769 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
771 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
774 rtex
->cmask_buffer
= (struct r600_resource
*)
775 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
776 PIPE_USAGE_DEFAULT
, rtex
->cmask
.size
);
777 if (rtex
->cmask_buffer
== NULL
) {
778 rtex
->cmask
.size
= 0;
782 /* update colorbuffer state bits */
783 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
785 if (rscreen
->chip_class
>= SI
)
786 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
788 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
790 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
793 static unsigned r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
794 struct r600_texture
*rtex
)
796 unsigned cl_width
, cl_height
, width
, height
;
797 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
798 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
800 if (rscreen
->chip_class
<= EVERGREEN
&&
801 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
804 /* HW bug on R6xx. */
805 if (rscreen
->chip_class
== R600
&&
806 (rtex
->surface
.level
[0].npix_x
> 7680 ||
807 rtex
->surface
.level
[0].npix_y
> 7680))
810 /* HTILE is broken with 1D tiling on old kernels and CIK. */
811 if (rscreen
->chip_class
>= CIK
&&
812 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
813 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
816 /* Overalign HTILE on P2 configs to work around GPU hangs in
817 * piglit/depthstencil-render-miplevels 585.
819 * This has been confirmed to help Kabini & Stoney, where the hangs
820 * are always reproducible. I think I have seen the test hang
821 * on Carrizo too, though it was very rare there.
823 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
852 width
= align(rtex
->surface
.npix_x
, cl_width
* 8);
853 height
= align(rtex
->surface
.npix_y
, cl_height
* 8);
855 slice_elements
= (width
* height
) / (8 * 8);
856 slice_bytes
= slice_elements
* 4;
858 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
859 base_align
= num_pipes
* pipe_interleave_bytes
;
861 rtex
->htile
.pitch
= width
;
862 rtex
->htile
.height
= height
;
863 rtex
->htile
.xalign
= cl_width
* 8;
864 rtex
->htile
.yalign
= cl_height
* 8;
866 return (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
867 align(slice_bytes
, base_align
);
870 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
871 struct r600_texture
*rtex
)
873 unsigned htile_size
= r600_texture_get_htile_size(rscreen
, rtex
);
878 rtex
->htile_buffer
= (struct r600_resource
*)
879 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
880 PIPE_USAGE_DEFAULT
, htile_size
);
881 if (rtex
->htile_buffer
== NULL
) {
882 /* this is not a fatal error as we can still keep rendering
883 * without htile buffer */
884 R600_ERR("Failed to create buffer object for htile buffer.\n");
886 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
, 0,
887 htile_size
, 0, R600_COHERENCY_NONE
);
891 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
)
895 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
896 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
897 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
898 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
899 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
900 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
901 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
902 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
903 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
905 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%"PRIu64
", bankw=%u, "
906 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
907 rtex
->surface
.bo_size
, rtex
->surface
.bo_alignment
, rtex
->surface
.bankw
,
908 rtex
->surface
.bankh
, rtex
->surface
.num_banks
, rtex
->surface
.mtilea
,
909 rtex
->surface
.tile_split
, rtex
->surface
.pipe_config
,
910 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
912 if (rtex
->fmask
.size
)
913 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
914 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
915 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
916 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
917 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
919 if (rtex
->cmask
.size
)
920 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch=%u, "
921 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
922 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
923 rtex
->cmask
.pitch
, rtex
->cmask
.height
, rtex
->cmask
.xalign
,
924 rtex
->cmask
.yalign
, rtex
->cmask
.slice_tile_max
);
926 if (rtex
->htile_buffer
)
927 fprintf(f
, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
928 "xalign=%u, yalign=%u\n",
929 rtex
->htile_buffer
->b
.b
.width0
,
930 rtex
->htile_buffer
->buf
->alignment
, rtex
->htile
.pitch
,
931 rtex
->htile
.height
, rtex
->htile
.xalign
, rtex
->htile
.yalign
);
933 if (rtex
->dcc_offset
) {
934 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%"PRIu64
"\n",
935 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
936 rtex
->surface
.dcc_alignment
);
937 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
938 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
939 "fast_clear_size=%"PRIu64
"\n",
940 i
, rtex
->surface
.level
[i
].dcc_enabled
,
941 rtex
->surface
.level
[i
].dcc_offset
,
942 rtex
->surface
.level
[i
].dcc_fast_clear_size
);
945 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
946 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
947 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
948 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
949 i
, rtex
->surface
.level
[i
].offset
,
950 rtex
->surface
.level
[i
].slice_size
,
951 u_minify(rtex
->resource
.b
.b
.width0
, i
),
952 u_minify(rtex
->resource
.b
.b
.height0
, i
),
953 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
954 rtex
->surface
.level
[i
].nblk_x
,
955 rtex
->surface
.level
[i
].nblk_y
,
956 rtex
->surface
.level
[i
].nblk_z
,
957 rtex
->surface
.level
[i
].pitch_bytes
,
958 rtex
->surface
.level
[i
].mode
);
960 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
961 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
962 fprintf(f
, " StencilLayout: tilesplit=%u\n",
963 rtex
->surface
.stencil_tile_split
);
964 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
965 "slice_size=%"PRIu64
", npix_x=%u, "
966 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
967 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
968 i
, rtex
->surface
.stencil_level
[i
].offset
,
969 rtex
->surface
.stencil_level
[i
].slice_size
,
970 u_minify(rtex
->resource
.b
.b
.width0
, i
),
971 u_minify(rtex
->resource
.b
.b
.height0
, i
),
972 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
973 rtex
->surface
.stencil_level
[i
].nblk_x
,
974 rtex
->surface
.stencil_level
[i
].nblk_y
,
975 rtex
->surface
.stencil_level
[i
].nblk_z
,
976 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
977 rtex
->surface
.stencil_level
[i
].mode
);
982 /* Common processing for r600_texture_create and r600_texture_from_handle */
983 static struct r600_texture
*
984 r600_texture_create_object(struct pipe_screen
*screen
,
985 const struct pipe_resource
*base
,
986 unsigned pitch_in_bytes_override
,
988 struct pb_buffer
*buf
,
989 struct radeon_surf
*surface
)
991 struct r600_texture
*rtex
;
992 struct r600_resource
*resource
;
993 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
995 rtex
= CALLOC_STRUCT(r600_texture
);
999 resource
= &rtex
->resource
;
1000 resource
->b
.b
= *base
;
1001 resource
->b
.vtbl
= &r600_texture_vtbl
;
1002 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1003 resource
->b
.b
.screen
= screen
;
1005 /* don't include stencil-only formats which we don't support for rendering */
1006 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1008 rtex
->surface
= *surface
;
1009 if (r600_setup_surface(screen
, rtex
, pitch_in_bytes_override
, offset
)) {
1014 /* Tiled depth textures utilize the non-displayable tile order.
1015 * This must be done after r600_setup_surface.
1016 * Applies to R600-Cayman. */
1017 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1018 /* Applies to GCN. */
1019 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1021 if (rtex
->is_depth
) {
1022 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1023 R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) &&
1024 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
)) {
1026 r600_texture_allocate_htile(rscreen
, rtex
);
1029 if (base
->nr_samples
> 1) {
1031 r600_texture_allocate_fmask(rscreen
, rtex
);
1032 r600_texture_allocate_cmask(rscreen
, rtex
);
1033 rtex
->cmask_buffer
= &rtex
->resource
;
1035 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1041 /* Shared textures must always set up DCC here.
1042 * If it's not present, it will be disabled by
1043 * apply_opaque_metadata later.
1045 if (rtex
->surface
.dcc_size
&&
1046 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1047 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1048 /* Reserve space for the DCC buffer. */
1049 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1050 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1054 /* Now create the backing buffer. */
1056 if (!r600_init_resource(rscreen
, resource
, rtex
->size
,
1057 rtex
->surface
.bo_alignment
)) {
1062 resource
->buf
= buf
;
1063 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1064 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1067 if (rtex
->cmask
.size
) {
1068 /* Initialize the cmask to 0xCC (= compressed state). */
1069 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1070 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1071 0xCCCCCCCC, R600_COHERENCY_NONE
);
1074 /* Initialize DCC only if the texture is not being imported. */
1075 if (!buf
&& rtex
->dcc_offset
) {
1076 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1078 rtex
->surface
.dcc_size
,
1079 0xFFFFFFFF, R600_COHERENCY_NONE
);
1082 /* Initialize the CMASK base register value. */
1083 rtex
->cmask
.base_address_reg
=
1084 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1086 if (rscreen
->debug_flags
& DBG_VM
) {
1087 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1088 rtex
->resource
.gpu_address
,
1089 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1090 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1091 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1094 if (rscreen
->debug_flags
& DBG_TEX
) {
1096 r600_print_texture_info(rtex
, stdout
);
1102 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
1103 const struct pipe_resource
*templ
)
1105 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1106 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1108 /* MSAA resources must be 2D tiled. */
1109 if (templ
->nr_samples
> 1)
1110 return RADEON_SURF_MODE_2D
;
1112 /* Transfer resources should be linear. */
1113 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1114 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1116 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1117 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1118 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1119 (templ
->target
== PIPE_TEXTURE_2D
||
1120 templ
->target
== PIPE_TEXTURE_3D
))
1121 force_tiling
= true;
1123 /* Handle common candidates for the linear mode.
1124 * Compressed textures and DB surfaces must always be tiled.
1126 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
1127 (!util_format_is_depth_or_stencil(templ
->format
) ||
1128 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
1129 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1130 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1132 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1133 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1134 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1136 /* Cursors are linear on SI.
1137 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1138 if (rscreen
->chip_class
>= SI
&&
1139 (templ
->bind
& PIPE_BIND_CURSOR
))
1140 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1142 if (templ
->bind
& PIPE_BIND_LINEAR
)
1143 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1145 /* Textures with a very small height are recommended to be linear. */
1146 if (templ
->target
== PIPE_TEXTURE_1D
||
1147 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1148 templ
->height0
<= 4)
1149 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1151 /* Textures likely to be mapped often. */
1152 if (templ
->usage
== PIPE_USAGE_STAGING
||
1153 templ
->usage
== PIPE_USAGE_STREAM
)
1154 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1157 /* Make small textures 1D tiled. */
1158 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1159 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1160 return RADEON_SURF_MODE_1D
;
1162 /* The allocator will switch to 1D if needed. */
1163 return RADEON_SURF_MODE_2D
;
1166 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1167 const struct pipe_resource
*templ
)
1169 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1170 struct radeon_surf surface
= {0};
1173 r
= r600_init_surface(rscreen
, &surface
, templ
,
1174 r600_choose_tiling(rscreen
, templ
),
1175 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1179 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
1183 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, 0,
1187 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1188 const struct pipe_resource
*templ
,
1189 struct winsys_handle
*whandle
,
1192 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1193 struct pb_buffer
*buf
= NULL
;
1194 unsigned stride
= 0, offset
= 0;
1195 unsigned array_mode
;
1196 struct radeon_surf surface
;
1198 struct radeon_bo_metadata metadata
= {};
1199 struct r600_texture
*rtex
;
1201 /* Support only 2D textures without mipmaps */
1202 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1203 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1206 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1210 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1212 surface
.pipe_config
= metadata
.pipe_config
;
1213 surface
.bankw
= metadata
.bankw
;
1214 surface
.bankh
= metadata
.bankh
;
1215 surface
.tile_split
= metadata
.tile_split
;
1216 surface
.mtilea
= metadata
.mtilea
;
1217 surface
.num_banks
= metadata
.num_banks
;
1219 if (metadata
.macrotile
== RADEON_LAYOUT_TILED
)
1220 array_mode
= RADEON_SURF_MODE_2D
;
1221 else if (metadata
.microtile
== RADEON_LAYOUT_TILED
)
1222 array_mode
= RADEON_SURF_MODE_1D
;
1224 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1226 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, false);
1231 if (metadata
.scanout
)
1232 surface
.flags
|= RADEON_SURF_SCANOUT
;
1234 rtex
= r600_texture_create_object(screen
, templ
, stride
,
1235 offset
, buf
, &surface
);
1239 rtex
->resource
.is_shared
= true;
1240 rtex
->resource
.external_usage
= usage
;
1242 if (rscreen
->apply_opaque_metadata
)
1243 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1245 return &rtex
->resource
.b
.b
;
1248 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1249 struct pipe_resource
*texture
,
1250 struct r600_texture
**staging
)
1252 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1253 struct pipe_resource resource
;
1254 struct r600_texture
**flushed_depth_texture
= staging
?
1255 staging
: &rtex
->flushed_depth_texture
;
1257 if (!staging
&& rtex
->flushed_depth_texture
)
1258 return true; /* it's ready */
1260 resource
.target
= texture
->target
;
1261 resource
.format
= texture
->format
;
1262 resource
.width0
= texture
->width0
;
1263 resource
.height0
= texture
->height0
;
1264 resource
.depth0
= texture
->depth0
;
1265 resource
.array_size
= texture
->array_size
;
1266 resource
.last_level
= texture
->last_level
;
1267 resource
.nr_samples
= texture
->nr_samples
;
1268 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1269 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1270 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1273 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1275 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1276 if (*flushed_depth_texture
== NULL
) {
1277 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1281 (*flushed_depth_texture
)->is_flushing_texture
= true;
1282 (*flushed_depth_texture
)->non_disp_tiling
= false;
1287 * Initialize the pipe_resource descriptor to be of the same size as the box,
1288 * which is supposed to hold a subregion of the texture "orig" at the given
1291 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1292 struct pipe_resource
*orig
,
1293 const struct pipe_box
*box
,
1294 unsigned level
, unsigned flags
)
1296 memset(res
, 0, sizeof(*res
));
1297 res
->format
= orig
->format
;
1298 res
->width0
= box
->width
;
1299 res
->height0
= box
->height
;
1301 res
->array_size
= 1;
1302 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1305 /* We must set the correct texture target and dimensions for a 3D box. */
1306 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1307 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1308 res
->array_size
= box
->depth
;
1310 res
->target
= PIPE_TEXTURE_2D
;
1314 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1315 struct r600_texture
*rtex
,
1316 unsigned transfer_usage
,
1317 const struct pipe_box
*box
)
1319 /* r600g doesn't react to dirty_tex_descriptor_counter */
1320 return rscreen
->chip_class
>= SI
&&
1321 !rtex
->resource
.is_shared
&&
1322 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1323 rtex
->resource
.b
.b
.last_level
== 0 &&
1324 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1325 box
->x
, box
->y
, box
->z
,
1326 box
->width
, box
->height
,
1330 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1331 struct r600_texture
*rtex
)
1333 struct r600_common_screen
*rscreen
= rctx
->screen
;
1335 /* There is no point in discarding depth and tiled buffers. */
1336 assert(!rtex
->is_depth
);
1337 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
);
1339 /* Reallocate the buffer in the same pipe_resource. */
1340 r600_init_resource(rscreen
, &rtex
->resource
, rtex
->size
,
1341 rtex
->surface
.bo_alignment
);
1343 /* Initialize the CMASK base address (needed even without CMASK). */
1344 rtex
->cmask
.base_address_reg
=
1345 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1347 r600_dirty_all_framebuffer_states(rscreen
);
1348 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
1350 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1353 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1354 struct pipe_resource
*texture
,
1357 const struct pipe_box
*box
,
1358 struct pipe_transfer
**ptransfer
)
1360 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1361 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1362 struct r600_transfer
*trans
;
1363 struct r600_resource
*buf
;
1364 unsigned offset
= 0;
1366 bool use_staging_texture
= false;
1368 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1370 /* Depth textures use staging unconditionally. */
1371 if (!rtex
->is_depth
) {
1372 /* Degrade the tile mode if we get too many transfers on APUs.
1373 * On dGPUs, the staging texture is always faster.
1374 * Only count uploads that are at least 4x4 pixels large.
1376 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1378 box
->width
>= 4 && box
->height
>= 4 &&
1379 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1380 bool can_invalidate
=
1381 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1384 r600_degrade_tile_mode_to_linear(rctx
, rtex
,
1388 /* Tiled textures need to be converted into a linear texture for CPU
1389 * access. The staging texture is always linear and is placed in GART.
1391 * Reading from VRAM is slow, always use the staging texture in
1394 * Use the staging texture for uploads if the underlying BO
1397 if (rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
)
1398 use_staging_texture
= true;
1399 else if (usage
& PIPE_TRANSFER_READ
)
1400 use_staging_texture
= (rtex
->resource
.domains
&
1401 RADEON_DOMAIN_VRAM
) != 0;
1402 /* Write & linear only: */
1403 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1404 RADEON_USAGE_READWRITE
) ||
1405 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1406 RADEON_USAGE_READWRITE
)) {
1408 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1410 r600_texture_invalidate_storage(rctx
, rtex
);
1412 use_staging_texture
= true;
1416 trans
= CALLOC_STRUCT(r600_transfer
);
1419 trans
->transfer
.resource
= texture
;
1420 trans
->transfer
.level
= level
;
1421 trans
->transfer
.usage
= usage
;
1422 trans
->transfer
.box
= *box
;
1424 if (rtex
->is_depth
) {
1425 struct r600_texture
*staging_depth
;
1427 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1428 /* MSAA depth buffers need to be converted to single sample buffers.
1430 * Mapping MSAA depth buffers can occur if ReadPixels is called
1431 * with a multisample GLX visual.
1433 * First downsample the depth buffer to a temporary texture,
1434 * then decompress the temporary one to staging.
1436 * Only the region being mapped is transfered.
1438 struct pipe_resource resource
;
1440 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1442 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1443 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1448 if (usage
& PIPE_TRANSFER_READ
) {
1449 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1451 R600_ERR("failed to create a temporary depth texture\n");
1456 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1457 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1458 0, 0, 0, box
->depth
, 0, 0);
1459 pipe_resource_reference(&temp
, NULL
);
1463 /* XXX: only readback the rectangle which is being mapped? */
1464 /* XXX: when discard is true, no need to read back from depth texture */
1465 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1466 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1471 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1473 box
->z
, box
->z
+ box
->depth
- 1,
1476 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1479 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
1480 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
1481 trans
->staging
= (struct r600_resource
*)staging_depth
;
1482 buf
= trans
->staging
;
1483 } else if (use_staging_texture
) {
1484 struct pipe_resource resource
;
1485 struct r600_texture
*staging
;
1487 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1488 R600_RESOURCE_FLAG_TRANSFER
);
1489 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1490 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1492 /* Create the temporary texture. */
1493 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1495 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1499 trans
->staging
= &staging
->resource
;
1500 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
1501 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1503 if (usage
& PIPE_TRANSFER_READ
)
1504 r600_copy_to_staging_texture(ctx
, trans
);
1506 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1508 buf
= trans
->staging
;
1510 /* the resource is mapped directly */
1511 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
1512 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1513 offset
= r600_texture_get_offset(rtex
, level
, box
);
1514 buf
= &rtex
->resource
;
1517 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1518 r600_resource_reference(&trans
->staging
, NULL
);
1523 *ptransfer
= &trans
->transfer
;
1524 return map
+ offset
;
1527 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1528 struct pipe_transfer
* transfer
)
1530 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1531 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1532 struct pipe_resource
*texture
= transfer
->resource
;
1533 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1535 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1536 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1537 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1538 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1539 &rtransfer
->staging
->b
.b
, transfer
->level
,
1542 r600_copy_from_staging_texture(ctx
, rtransfer
);
1546 if (rtransfer
->staging
) {
1547 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1548 r600_resource_reference(&rtransfer
->staging
, NULL
);
1551 /* Heuristic for {upload, draw, upload, draw, ..}:
1553 * Flush the gfx IB if we've allocated too much texture storage.
1555 * The idea is that we don't want to build IBs that use too much
1556 * memory and put pressure on the kernel memory manager and we also
1557 * want to make temporary and invalidated buffers go idle ASAP to
1558 * decrease the total memory usage or make them reusable. The memory
1559 * usage will be slightly higher than given here because of the buffer
1560 * cache in the winsys.
1562 * The result is that the kernel memory manager is never a bottleneck.
1564 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1565 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1566 rctx
->num_alloc_tex_transfer_bytes
= 0;
1572 static const struct u_resource_vtbl r600_texture_vtbl
=
1574 NULL
, /* get_handle */
1575 r600_texture_destroy
, /* resource_destroy */
1576 r600_texture_transfer_map
, /* transfer_map */
1577 u_default_transfer_flush_region
, /* transfer_flush_region */
1578 r600_texture_transfer_unmap
, /* transfer_unmap */
1579 NULL
/* transfer_inline_write */
1582 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1583 struct pipe_resource
*texture
,
1584 const struct pipe_surface
*templ
,
1585 unsigned width
, unsigned height
)
1587 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1588 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1593 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1594 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1596 pipe_reference_init(&surface
->base
.reference
, 1);
1597 pipe_resource_reference(&surface
->base
.texture
, texture
);
1598 surface
->base
.context
= pipe
;
1599 surface
->base
.format
= templ
->format
;
1600 surface
->base
.width
= width
;
1601 surface
->base
.height
= height
;
1602 surface
->base
.u
= templ
->u
;
1603 surface
->level_info
= &rtex
->surface
.level
[templ
->u
.tex
.level
];
1604 return &surface
->base
;
1607 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1608 struct pipe_resource
*tex
,
1609 const struct pipe_surface
*templ
)
1611 unsigned level
= templ
->u
.tex
.level
;
1612 unsigned width
= u_minify(tex
->width0
, level
);
1613 unsigned height
= u_minify(tex
->height0
, level
);
1615 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1616 const struct util_format_description
*tex_desc
1617 = util_format_description(tex
->format
);
1618 const struct util_format_description
*templ_desc
1619 = util_format_description(templ
->format
);
1621 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1623 /* Adjust size of surface if and only if the block width or
1624 * height is changed. */
1625 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1626 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1627 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1628 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1630 width
= nblks_x
* templ_desc
->block
.width
;
1631 height
= nblks_y
* templ_desc
->block
.height
;
1635 return r600_create_surface_custom(pipe
, tex
, templ
, width
, height
);
1638 static void r600_surface_destroy(struct pipe_context
*pipe
,
1639 struct pipe_surface
*surface
)
1641 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1642 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1643 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1644 pipe_resource_reference(&surface
->texture
, NULL
);
1648 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1650 const struct util_format_description
*desc
= util_format_description(format
);
1652 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1654 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1655 return V_0280A0_SWAP_STD
;
1657 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1660 switch (desc
->nr_channels
) {
1662 if (HAS_SWIZZLE(0,X
))
1663 return V_0280A0_SWAP_STD
; /* X___ */
1664 else if (HAS_SWIZZLE(3,X
))
1665 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1668 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1669 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1670 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1671 return V_0280A0_SWAP_STD
; /* XY__ */
1672 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1673 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1674 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1676 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
1677 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1678 return V_0280A0_SWAP_ALT
; /* X__Y */
1679 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1680 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1683 if (HAS_SWIZZLE(0,X
))
1684 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
1685 else if (HAS_SWIZZLE(0,Z
))
1686 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1689 /* check the middle channels, the 1st and 4th channel can be NONE */
1690 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
1691 return V_0280A0_SWAP_STD
; /* XYZW */
1692 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
1693 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1694 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
1695 return V_0280A0_SWAP_ALT
; /* ZYXW */
1696 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
1699 return V_0280A0_SWAP_ALT_REV
;
1701 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
1708 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
1709 enum pipe_format surface_format
,
1710 const union pipe_color_union
*color
)
1712 union util_color uc
;
1714 memset(&uc
, 0, sizeof(uc
));
1716 if (util_format_is_pure_uint(surface_format
)) {
1717 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
1718 } else if (util_format_is_pure_sint(surface_format
)) {
1719 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
1721 util_pack_color(color
->f
, surface_format
, &uc
);
1724 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
1727 static void vi_get_fast_clear_parameters(enum pipe_format surface_format
,
1728 const union pipe_color_union
*color
,
1729 uint32_t* reset_value
,
1730 bool* clear_words_needed
)
1732 bool values
[4] = {};
1734 bool main_value
= false;
1735 bool extra_value
= false;
1737 const struct util_format_description
*desc
= util_format_description(surface_format
);
1739 *clear_words_needed
= true;
1740 *reset_value
= 0x20202020U
;
1742 /* If we want to clear without needing a fast clear eliminate step, we
1743 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1744 * have two sets of flags, one for the last or first channel(extra) and
1745 * one for the other channels(main).
1748 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
1749 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
1750 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
1752 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
1753 if(r600_translate_colorswap(surface_format
, false) <= 1)
1754 extra_channel
= desc
->nr_channels
- 1;
1760 for (i
= 0; i
< 4; ++i
) {
1761 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
1763 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
1764 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
1767 if (util_format_is_pure_sint(surface_format
)) {
1768 values
[i
] = color
->i
[i
] != 0;
1769 if (color
->i
[i
] != 0 && color
->i
[i
] != INT32_MAX
)
1771 } else if (util_format_is_pure_uint(surface_format
)) {
1772 values
[i
] = color
->ui
[i
] != 0U;
1773 if (color
->ui
[i
] != 0U && color
->ui
[i
] != UINT32_MAX
)
1776 values
[i
] = color
->f
[i
] != 0.0F
;
1777 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
1781 if (index
== extra_channel
)
1782 extra_value
= values
[i
];
1784 main_value
= values
[i
];
1787 for (int i
= 0; i
< 4; ++i
)
1788 if (values
[i
] != main_value
&&
1789 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
1790 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
1791 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
1794 *clear_words_needed
= false;
1796 *reset_value
|= 0x80808080U
;
1799 *reset_value
|= 0x40404040U
;
1802 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
1803 struct r600_texture
*rtex
,
1804 unsigned level
, unsigned clear_value
)
1806 struct pipe_resource
*dcc_buffer
;
1807 uint64_t dcc_offset
;
1809 assert(rtex
->dcc_offset
&& rtex
->surface
.level
[level
].dcc_enabled
);
1811 if (rtex
->dcc_separate_buffer
) {
1812 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
1815 dcc_buffer
= &rtex
->resource
.b
.b
;
1816 dcc_offset
= rtex
->dcc_offset
;
1819 dcc_offset
+= rtex
->surface
.level
[level
].dcc_offset
;
1821 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
,
1822 rtex
->surface
.level
[level
].dcc_fast_clear_size
,
1823 clear_value
, R600_COHERENCY_CB_META
);
1826 /* Set the same micro tile mode as the destination of the last MSAA resolve.
1827 * This allows hitting the MSAA resolve fast path, which requires that both
1828 * src and dst micro tile modes match.
1830 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
1831 struct r600_texture
*rtex
)
1833 if (rtex
->resource
.is_shared
||
1834 rtex
->surface
.nsamples
<= 1 ||
1835 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
1838 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_2D
);
1839 assert(rtex
->surface
.last_level
== 0);
1841 /* These magic numbers were copied from addrlib. It doesn't use any
1842 * definitions for them either. They are all 2D_TILED_THIN1 modes with
1843 * different bpp and micro tile mode.
1845 if (rscreen
->chip_class
>= CIK
) {
1846 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
1847 case 0: /* displayable */
1848 rtex
->surface
.tiling_index
[0] = 10;
1851 rtex
->surface
.tiling_index
[0] = 14;
1853 case 3: /* rotated */
1854 rtex
->surface
.tiling_index
[0] = 28;
1856 default: /* depth, thick */
1857 assert(!"unexpected micro mode");
1861 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
1862 case 0: /* displayable */
1863 switch (rtex
->surface
.bpe
) {
1865 rtex
->surface
.tiling_index
[0] = 10;
1868 rtex
->surface
.tiling_index
[0] = 11;
1870 default: /* 32, 64 */
1871 rtex
->surface
.tiling_index
[0] = 12;
1876 switch (rtex
->surface
.bpe
) {
1878 rtex
->surface
.tiling_index
[0] = 14;
1881 rtex
->surface
.tiling_index
[0] = 15;
1884 rtex
->surface
.tiling_index
[0] = 16;
1886 default: /* 64, 128 */
1887 rtex
->surface
.tiling_index
[0] = 17;
1891 default: /* depth, thick */
1892 assert(!"unexpected micro mode");
1897 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
1899 p_atomic_inc(&rscreen
->dirty_fb_counter
);
1900 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
1903 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
1904 struct pipe_framebuffer_state
*fb
,
1905 struct r600_atom
*fb_state
,
1906 unsigned *buffers
, unsigned *dirty_cbufs
,
1907 const union pipe_color_union
*color
)
1911 /* This function is broken in BE, so just disable this path for now */
1912 #ifdef PIPE_ARCH_BIG_ENDIAN
1916 if (rctx
->render_cond
)
1919 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
1920 struct r600_texture
*tex
;
1921 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
1926 /* if this colorbuffer is not being cleared */
1927 if (!(*buffers
& clear_bit
))
1930 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
1932 /* 128-bit formats are unusupported */
1933 if (util_format_get_blocksizebits(fb
->cbufs
[i
]->format
) > 64) {
1937 /* the clear is allowed if all layers are bound */
1938 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
1939 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
1943 /* cannot clear mipmapped textures */
1944 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
1948 /* only supported on tiled surfaces */
1949 if (tex
->surface
.level
[0].mode
< RADEON_SURF_MODE_1D
) {
1953 /* shared textures can't use fast clear without an explicit flush,
1954 * because there is no way to communicate the clear color among
1957 if (tex
->resource
.is_shared
&&
1958 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
1961 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1962 if (tex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
1963 rctx
->chip_class
>= CIK
&&
1964 rctx
->screen
->info
.drm_major
== 2 &&
1965 rctx
->screen
->info
.drm_minor
< 38) {
1969 if (tex
->dcc_offset
&& tex
->surface
.level
[0].dcc_enabled
) {
1970 uint32_t reset_value
;
1971 bool clear_words_needed
;
1973 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
1976 /* We can change the micro tile mode before a full clear. */
1977 if (rctx
->screen
->chip_class
>= SI
)
1978 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
1980 vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
, color
, &reset_value
, &clear_words_needed
);
1981 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
1983 if (clear_words_needed
)
1984 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
1986 /* Stoney/RB+ doesn't work with CMASK fast clear. */
1987 if (rctx
->family
== CHIP_STONEY
)
1990 /* ensure CMASK is enabled */
1991 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
1992 if (tex
->cmask
.size
== 0) {
1996 /* We can change the micro tile mode before a full clear. */
1997 if (rctx
->screen
->chip_class
>= SI
)
1998 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2000 /* Do the fast clear. */
2001 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2002 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2003 R600_COHERENCY_CB_META
);
2005 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2008 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2011 *dirty_cbufs
|= 1 << i
;
2012 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2013 *buffers
&= ~clear_bit
;
2017 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2019 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2020 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2023 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2025 rctx
->b
.create_surface
= r600_create_surface
;
2026 rctx
->b
.surface_destroy
= r600_surface_destroy
;