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c573b438b01d6e36b94cd10e028318d54ebfd761
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include <errno.h>
33 #include <inttypes.h>
34
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context *pipe,
37 struct pipe_resource *dst,
38 unsigned dst_level,
39 unsigned dstx, unsigned dsty, unsigned dstz,
40 struct pipe_resource *src,
41 unsigned src_level,
42 const struct pipe_box *src_box)
43 {
44 struct pipe_blit_info blit;
45
46 memset(&blit, 0, sizeof(blit));
47 blit.src.resource = src;
48 blit.src.format = src->format;
49 blit.src.level = src_level;
50 blit.src.box = *src_box;
51 blit.dst.resource = dst;
52 blit.dst.format = dst->format;
53 blit.dst.level = dst_level;
54 blit.dst.box.x = dstx;
55 blit.dst.box.y = dsty;
56 blit.dst.box.z = dstz;
57 blit.dst.box.width = src_box->width;
58 blit.dst.box.height = src_box->height;
59 blit.dst.box.depth = src_box->depth;
60 blit.mask = util_format_get_mask(src->format) &
61 util_format_get_mask(dst->format);
62 blit.filter = PIPE_TEX_FILTER_NEAREST;
63
64 if (blit.mask) {
65 pipe->blit(pipe, &blit);
66 }
67 }
68
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
71 {
72 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
73 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
74 struct pipe_resource *dst = &rtransfer->staging->b.b;
75 struct pipe_resource *src = transfer->resource;
76
77 if (src->nr_samples > 1) {
78 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
79 src, transfer->level, &transfer->box);
80 return;
81 }
82
83 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
84 &transfer->box);
85 }
86
87 /* Copy from a transfer's staging texture to a full GPU one. */
88 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
89 {
90 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
91 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
92 struct pipe_resource *dst = transfer->resource;
93 struct pipe_resource *src = &rtransfer->staging->b.b;
94 struct pipe_box sbox;
95
96 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
97
98 if (dst->nr_samples > 1) {
99 r600_copy_region_with_blit(ctx, dst, transfer->level,
100 transfer->box.x, transfer->box.y, transfer->box.z,
101 src, 0, &sbox);
102 return;
103 }
104
105 rctx->dma_copy(ctx, dst, transfer->level,
106 transfer->box.x, transfer->box.y, transfer->box.z,
107 src, 0, &sbox);
108 }
109
110 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
111 const struct pipe_box *box)
112 {
113 enum pipe_format format = rtex->resource.b.b.format;
114
115 return rtex->surface.level[level].offset +
116 box->z * rtex->surface.level[level].slice_size +
117 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
118 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
119 }
120
121 static int r600_init_surface(struct r600_common_screen *rscreen,
122 struct radeon_surf *surface,
123 const struct pipe_resource *ptex,
124 unsigned array_mode,
125 bool is_flushed_depth)
126 {
127 const struct util_format_description *desc =
128 util_format_description(ptex->format);
129 bool is_depth, is_stencil;
130
131 is_depth = util_format_has_depth(desc);
132 is_stencil = util_format_has_stencil(desc);
133
134 surface->npix_x = ptex->width0;
135 surface->npix_y = ptex->height0;
136 surface->npix_z = ptex->depth0;
137 surface->blk_w = util_format_get_blockwidth(ptex->format);
138 surface->blk_h = util_format_get_blockheight(ptex->format);
139 surface->blk_d = 1;
140 surface->array_size = 1;
141 surface->last_level = ptex->last_level;
142
143 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
144 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
145 surface->bpe = 4; /* stencil is allocated separately on evergreen */
146 } else {
147 surface->bpe = util_format_get_blocksize(ptex->format);
148 /* align byte per element on dword */
149 if (surface->bpe == 3) {
150 surface->bpe = 4;
151 }
152 }
153
154 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
155 surface->flags = RADEON_SURF_SET(array_mode, MODE);
156
157 switch (ptex->target) {
158 case PIPE_TEXTURE_1D:
159 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
160 break;
161 case PIPE_TEXTURE_RECT:
162 case PIPE_TEXTURE_2D:
163 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
164 break;
165 case PIPE_TEXTURE_3D:
166 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
167 break;
168 case PIPE_TEXTURE_1D_ARRAY:
169 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
170 surface->array_size = ptex->array_size;
171 break;
172 case PIPE_TEXTURE_2D_ARRAY:
173 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
175 surface->array_size = ptex->array_size;
176 break;
177 case PIPE_TEXTURE_CUBE:
178 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
179 break;
180 case PIPE_BUFFER:
181 default:
182 return -EINVAL;
183 }
184 if (ptex->bind & PIPE_BIND_SCANOUT) {
185 surface->flags |= RADEON_SURF_SCANOUT;
186 }
187
188 if (!is_flushed_depth && is_depth) {
189 surface->flags |= RADEON_SURF_ZBUFFER;
190
191 if (is_stencil) {
192 surface->flags |= RADEON_SURF_SBUFFER |
193 RADEON_SURF_HAS_SBUFFER_MIPTREE;
194 }
195 }
196 if (rscreen->chip_class >= SI) {
197 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
198 }
199 return 0;
200 }
201
202 static int r600_setup_surface(struct pipe_screen *screen,
203 struct r600_texture *rtex,
204 unsigned pitch_in_bytes_override,
205 unsigned offset)
206 {
207 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
208 unsigned i;
209 int r;
210
211 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
212 if (r) {
213 return r;
214 }
215
216 rtex->size = rtex->surface.bo_size;
217
218 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
219 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
220 * for those
221 */
222 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
223 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
224 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
225 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
226 rtex->surface.stencil_offset =
227 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
228 }
229 }
230
231 if (offset) {
232 for (i = 0; i < Elements(rtex->surface.level); ++i)
233 rtex->surface.level[i].offset += offset;
234 }
235 return 0;
236 }
237
238 static void r600_texture_init_metadata(struct r600_texture *rtex,
239 struct radeon_bo_metadata *metadata)
240 {
241 struct radeon_surf *surface = &rtex->surface;
242
243 memset(metadata, 0, sizeof(*metadata));
244 metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
245 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
246 metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
247 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
248 metadata->pipe_config = surface->pipe_config;
249 metadata->bankw = surface->bankw;
250 metadata->bankh = surface->bankh;
251 metadata->tile_split = surface->tile_split;
252 metadata->stencil_tile_split = surface->stencil_tile_split;
253 metadata->mtilea = surface->mtilea;
254 metadata->num_banks = surface->num_banks;
255 metadata->stride = surface->level[0].pitch_bytes;
256 metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
257 }
258
259 static void r600_dirty_all_framebuffer_states(struct r600_common_screen *rscreen)
260 {
261 p_atomic_inc(&rscreen->dirty_fb_counter);
262 }
263
264 static void r600_eliminate_fast_color_clear(struct r600_common_screen *rscreen,
265 struct r600_texture *rtex)
266 {
267 struct pipe_context *ctx = rscreen->aux_context;
268
269 pipe_mutex_lock(rscreen->aux_context_lock);
270 ctx->flush_resource(ctx, &rtex->resource.b.b);
271 ctx->flush(ctx, NULL, 0);
272 pipe_mutex_unlock(rscreen->aux_context_lock);
273 }
274
275 static void r600_texture_disable_cmask(struct r600_common_screen *rscreen,
276 struct r600_texture *rtex)
277 {
278 if (!rtex->cmask.size)
279 return;
280
281 assert(rtex->resource.b.b.nr_samples <= 1);
282
283 /* Disable CMASK. */
284 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
285 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
286
287 if (rscreen->chip_class >= SI)
288 rtex->cb_color_info &= ~SI_S_028C70_FAST_CLEAR(1);
289 else
290 rtex->cb_color_info &= ~EG_S_028C70_FAST_CLEAR(1);
291
292 if (rtex->cmask_buffer != &rtex->resource)
293 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
294
295 /* Notify all contexts about the change. */
296 r600_dirty_all_framebuffer_states(rscreen);
297 p_atomic_inc(&rscreen->compressed_colortex_counter);
298 }
299
300 static void r600_texture_disable_dcc(struct r600_common_screen *rscreen,
301 struct r600_texture *rtex)
302 {
303 struct r600_common_context *rctx =
304 (struct r600_common_context *)rscreen->aux_context;
305
306 if (!rtex->dcc_offset)
307 return;
308
309 /* Decompress DCC. */
310 pipe_mutex_lock(rscreen->aux_context_lock);
311 rctx->decompress_dcc(&rctx->b, rtex);
312 rctx->b.flush(&rctx->b, NULL, 0);
313 pipe_mutex_unlock(rscreen->aux_context_lock);
314
315 /* Disable DCC. */
316 rtex->dcc_offset = 0;
317 rtex->cb_color_info &= ~VI_S_028C70_DCC_ENABLE(1);
318
319 /* Notify all contexts about the change. */
320 r600_dirty_all_framebuffer_states(rscreen);
321 }
322
323 static boolean r600_texture_get_handle(struct pipe_screen* screen,
324 struct pipe_resource *resource,
325 struct winsys_handle *whandle,
326 unsigned usage)
327 {
328 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
329 struct r600_resource *res = (struct r600_resource*)resource;
330 struct r600_texture *rtex = (struct r600_texture*)resource;
331 struct radeon_bo_metadata metadata;
332
333 /* This is not supported now, but it might be required for OpenCL
334 * interop in the future.
335 */
336 if (resource->target != PIPE_BUFFER &&
337 (resource->nr_samples > 1 || rtex->is_depth))
338 return NULL;
339
340 if (!res->is_shared) {
341 res->is_shared = true;
342 res->external_usage = usage;
343
344 if (resource->target != PIPE_BUFFER) {
345 /* Since shader image stores don't support DCC on VI,
346 * disable it for external clients that want write
347 * access.
348 */
349 if (usage & PIPE_HANDLE_USAGE_WRITE)
350 r600_texture_disable_dcc(rscreen, rtex);
351
352 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) {
353 /* Eliminate fast clear (both CMASK and DCC) */
354 r600_eliminate_fast_color_clear(rscreen, rtex);
355
356 /* Disable CMASK if flush_resource isn't going
357 * to be called.
358 */
359 r600_texture_disable_cmask(rscreen, rtex);
360 }
361
362 /* Set metadata. */
363 r600_texture_init_metadata(rtex, &metadata);
364 if (rscreen->query_opaque_metadata)
365 rscreen->query_opaque_metadata(rscreen, rtex,
366 &metadata);
367
368 rscreen->ws->buffer_set_metadata(res->buf, &metadata);
369 }
370 } else {
371 assert(res->external_usage == usage);
372 }
373
374 return rscreen->ws->buffer_get_handle(res->buf,
375 rtex->surface.level[0].pitch_bytes,
376 rtex->surface.level[0].offset,
377 rtex->surface.level[0].slice_size,
378 whandle);
379 }
380
381 static void r600_texture_destroy(struct pipe_screen *screen,
382 struct pipe_resource *ptex)
383 {
384 struct r600_texture *rtex = (struct r600_texture*)ptex;
385 struct r600_resource *resource = &rtex->resource;
386
387 if (rtex->flushed_depth_texture)
388 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
389
390 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
391 if (rtex->cmask_buffer != &rtex->resource) {
392 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
393 }
394 pb_reference(&resource->buf, NULL);
395 FREE(rtex);
396 }
397
398 static const struct u_resource_vtbl r600_texture_vtbl;
399
400 /* The number of samples can be specified independently of the texture. */
401 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
402 struct r600_texture *rtex,
403 unsigned nr_samples,
404 struct r600_fmask_info *out)
405 {
406 /* FMASK is allocated like an ordinary texture. */
407 struct radeon_surf fmask = rtex->surface;
408
409 memset(out, 0, sizeof(*out));
410
411 fmask.bo_alignment = 0;
412 fmask.bo_size = 0;
413 fmask.nsamples = 1;
414 fmask.flags |= RADEON_SURF_FMASK;
415
416 /* Force 2D tiling if it wasn't set. This may occur when creating
417 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
418 * destination buffer must have an FMASK too. */
419 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
420 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
421
422 if (rscreen->chip_class >= SI) {
423 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
424 }
425
426 switch (nr_samples) {
427 case 2:
428 case 4:
429 fmask.bpe = 1;
430 if (rscreen->chip_class <= CAYMAN) {
431 fmask.bankh = 4;
432 }
433 break;
434 case 8:
435 fmask.bpe = 4;
436 break;
437 default:
438 R600_ERR("Invalid sample count for FMASK allocation.\n");
439 return;
440 }
441
442 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
443 * This can be fixed by writing a separate FMASK allocator specifically
444 * for R600-R700 asics. */
445 if (rscreen->chip_class <= R700) {
446 fmask.bpe *= 2;
447 }
448
449 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
450 R600_ERR("Got error in surface_init while allocating FMASK.\n");
451 return;
452 }
453
454 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
455
456 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
457 if (out->slice_tile_max)
458 out->slice_tile_max -= 1;
459
460 out->tile_mode_index = fmask.tiling_index[0];
461 out->pitch_in_pixels = fmask.level[0].nblk_x;
462 out->bank_height = fmask.bankh;
463 out->alignment = MAX2(256, fmask.bo_alignment);
464 out->size = fmask.bo_size;
465 }
466
467 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
468 struct r600_texture *rtex)
469 {
470 r600_texture_get_fmask_info(rscreen, rtex,
471 rtex->resource.b.b.nr_samples, &rtex->fmask);
472
473 rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
474 rtex->size = rtex->fmask.offset + rtex->fmask.size;
475 }
476
477 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
478 struct r600_texture *rtex,
479 struct r600_cmask_info *out)
480 {
481 unsigned cmask_tile_width = 8;
482 unsigned cmask_tile_height = 8;
483 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
484 unsigned element_bits = 4;
485 unsigned cmask_cache_bits = 1024;
486 unsigned num_pipes = rscreen->info.num_tile_pipes;
487 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
488
489 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
490 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
491 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
492 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
493 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
494
495 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
496 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
497
498 unsigned base_align = num_pipes * pipe_interleave_bytes;
499 unsigned slice_bytes =
500 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
501
502 assert(macro_tile_width % 128 == 0);
503 assert(macro_tile_height % 128 == 0);
504
505 out->pitch = pitch_elements;
506 out->height = height;
507 out->xalign = macro_tile_width;
508 out->yalign = macro_tile_height;
509 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
510 out->alignment = MAX2(256, base_align);
511 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
512 align(slice_bytes, base_align);
513 }
514
515 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
516 struct r600_texture *rtex,
517 struct r600_cmask_info *out)
518 {
519 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
520 unsigned num_pipes = rscreen->info.num_tile_pipes;
521 unsigned cl_width, cl_height;
522
523 switch (num_pipes) {
524 case 2:
525 cl_width = 32;
526 cl_height = 16;
527 break;
528 case 4:
529 cl_width = 32;
530 cl_height = 32;
531 break;
532 case 8:
533 cl_width = 64;
534 cl_height = 32;
535 break;
536 case 16: /* Hawaii */
537 cl_width = 64;
538 cl_height = 64;
539 break;
540 default:
541 assert(0);
542 return;
543 }
544
545 unsigned base_align = num_pipes * pipe_interleave_bytes;
546
547 unsigned width = align(rtex->surface.npix_x, cl_width*8);
548 unsigned height = align(rtex->surface.npix_y, cl_height*8);
549 unsigned slice_elements = (width * height) / (8*8);
550
551 /* Each element of CMASK is a nibble. */
552 unsigned slice_bytes = slice_elements / 2;
553
554 out->pitch = width;
555 out->height = height;
556 out->xalign = cl_width * 8;
557 out->yalign = cl_height * 8;
558 out->slice_tile_max = (width * height) / (128*128);
559 if (out->slice_tile_max)
560 out->slice_tile_max -= 1;
561
562 out->alignment = MAX2(256, base_align);
563 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
564 align(slice_bytes, base_align);
565 }
566
567 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
568 struct r600_texture *rtex)
569 {
570 if (rscreen->chip_class >= SI) {
571 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
572 } else {
573 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
574 }
575
576 rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
577 rtex->size = rtex->cmask.offset + rtex->cmask.size;
578
579 if (rscreen->chip_class >= SI)
580 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
581 else
582 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
583 }
584
585 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
586 struct r600_texture *rtex)
587 {
588 if (rtex->cmask_buffer)
589 return;
590
591 assert(rtex->cmask.size == 0);
592
593 if (rscreen->chip_class >= SI) {
594 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
595 } else {
596 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
597 }
598
599 rtex->cmask_buffer = (struct r600_resource *)
600 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
601 PIPE_USAGE_DEFAULT, rtex->cmask.size);
602 if (rtex->cmask_buffer == NULL) {
603 rtex->cmask.size = 0;
604 return;
605 }
606
607 /* update colorbuffer state bits */
608 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
609
610 if (rscreen->chip_class >= SI)
611 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
612 else
613 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
614
615 p_atomic_inc(&rscreen->compressed_colortex_counter);
616 }
617
618 static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
619 struct r600_texture *rtex)
620 {
621 unsigned cl_width, cl_height, width, height;
622 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
623 unsigned num_pipes = rscreen->info.num_tile_pipes;
624
625 if (rscreen->chip_class <= EVERGREEN &&
626 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
627 return 0;
628
629 /* HW bug on R6xx. */
630 if (rscreen->chip_class == R600 &&
631 (rtex->surface.level[0].npix_x > 7680 ||
632 rtex->surface.level[0].npix_y > 7680))
633 return 0;
634
635 /* HTILE is broken with 1D tiling on old kernels and CIK. */
636 if (rscreen->chip_class >= CIK &&
637 rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
638 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
639 return 0;
640
641 /* Overalign HTILE on P2 configs to work around GPU hangs in
642 * piglit/depthstencil-render-miplevels 585.
643 *
644 * This has been confirmed to help Kabini & Stoney, where the hangs
645 * are always reproducible. I think I have seen the test hang
646 * on Carrizo too, though it was very rare there.
647 */
648 if (rscreen->chip_class >= CIK && num_pipes < 4)
649 num_pipes = 4;
650
651 switch (num_pipes) {
652 case 1:
653 cl_width = 32;
654 cl_height = 16;
655 break;
656 case 2:
657 cl_width = 32;
658 cl_height = 32;
659 break;
660 case 4:
661 cl_width = 64;
662 cl_height = 32;
663 break;
664 case 8:
665 cl_width = 64;
666 cl_height = 64;
667 break;
668 case 16:
669 cl_width = 128;
670 cl_height = 64;
671 break;
672 default:
673 assert(0);
674 return 0;
675 }
676
677 width = align(rtex->surface.npix_x, cl_width * 8);
678 height = align(rtex->surface.npix_y, cl_height * 8);
679
680 slice_elements = (width * height) / (8 * 8);
681 slice_bytes = slice_elements * 4;
682
683 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
684 base_align = num_pipes * pipe_interleave_bytes;
685
686 rtex->htile.pitch = width;
687 rtex->htile.height = height;
688 rtex->htile.xalign = cl_width * 8;
689 rtex->htile.yalign = cl_height * 8;
690
691 return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
692 align(slice_bytes, base_align);
693 }
694
695 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
696 struct r600_texture *rtex)
697 {
698 unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex);
699
700 if (!htile_size)
701 return;
702
703 rtex->htile_buffer = (struct r600_resource*)
704 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
705 PIPE_USAGE_DEFAULT, htile_size);
706 if (rtex->htile_buffer == NULL) {
707 /* this is not a fatal error as we can still keep rendering
708 * without htile buffer */
709 R600_ERR("Failed to create buffer object for htile buffer.\n");
710 } else {
711 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0,
712 htile_size, 0, true);
713 }
714 }
715
716 void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
717 {
718 int i;
719
720 fprintf(f, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
721 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
722 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
723 rtex->surface.npix_x, rtex->surface.npix_y,
724 rtex->surface.npix_z, rtex->surface.blk_w,
725 rtex->surface.blk_h, rtex->surface.blk_d,
726 rtex->surface.array_size, rtex->surface.last_level,
727 rtex->surface.bpe, rtex->surface.nsamples,
728 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
729
730 fprintf(f, " Layout: size=%"PRIu64", alignment=%"PRIu64", bankw=%u, "
731 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
732 rtex->surface.bo_size, rtex->surface.bo_alignment, rtex->surface.bankw,
733 rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
734 rtex->surface.tile_split, rtex->surface.pipe_config,
735 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
736
737 if (rtex->fmask.size)
738 fprintf(f, " FMask: offset=%u, size=%u, alignment=%u, pitch_in_pixels=%u, "
739 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
740 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
741 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
742 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
743
744 if (rtex->cmask.size)
745 fprintf(f, " CMask: offset=%u, size=%u, alignment=%u, pitch=%u, "
746 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
747 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
748 rtex->cmask.pitch, rtex->cmask.height, rtex->cmask.xalign,
749 rtex->cmask.yalign, rtex->cmask.slice_tile_max);
750
751 if (rtex->htile_buffer)
752 fprintf(f, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
753 "xalign=%u, yalign=%u\n",
754 rtex->htile_buffer->b.b.width0,
755 rtex->htile_buffer->buf->alignment, rtex->htile.pitch,
756 rtex->htile.height, rtex->htile.xalign, rtex->htile.yalign);
757
758 if (rtex->dcc_offset) {
759 fprintf(f, " DCC: offset=%u, size=%"PRIu64", alignment=%"PRIu64"\n",
760 rtex->dcc_offset, rtex->surface.dcc_size,
761 rtex->surface.dcc_alignment);
762 for (i = 0; i <= rtex->surface.last_level; i++)
763 fprintf(f, " DCCLevel[%i]: offset=%"PRIu64"\n",
764 i, rtex->surface.level[i].dcc_offset);
765 }
766
767 for (i = 0; i <= rtex->surface.last_level; i++)
768 fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
769 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
770 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
771 i, rtex->surface.level[i].offset,
772 rtex->surface.level[i].slice_size,
773 u_minify(rtex->resource.b.b.width0, i),
774 u_minify(rtex->resource.b.b.height0, i),
775 u_minify(rtex->resource.b.b.depth0, i),
776 rtex->surface.level[i].nblk_x,
777 rtex->surface.level[i].nblk_y,
778 rtex->surface.level[i].nblk_z,
779 rtex->surface.level[i].pitch_bytes,
780 rtex->surface.level[i].mode);
781
782 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
783 for (i = 0; i <= rtex->surface.last_level; i++) {
784 fprintf(f, " StencilLayout: tilesplit=%u\n",
785 rtex->surface.stencil_tile_split);
786 fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
787 "slice_size=%"PRIu64", npix_x=%u, "
788 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
789 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
790 i, rtex->surface.stencil_level[i].offset,
791 rtex->surface.stencil_level[i].slice_size,
792 u_minify(rtex->resource.b.b.width0, i),
793 u_minify(rtex->resource.b.b.height0, i),
794 u_minify(rtex->resource.b.b.depth0, i),
795 rtex->surface.stencil_level[i].nblk_x,
796 rtex->surface.stencil_level[i].nblk_y,
797 rtex->surface.stencil_level[i].nblk_z,
798 rtex->surface.stencil_level[i].pitch_bytes,
799 rtex->surface.stencil_level[i].mode);
800 }
801 }
802 }
803
804 /* Common processing for r600_texture_create and r600_texture_from_handle */
805 static struct r600_texture *
806 r600_texture_create_object(struct pipe_screen *screen,
807 const struct pipe_resource *base,
808 unsigned pitch_in_bytes_override,
809 unsigned offset,
810 struct pb_buffer *buf,
811 struct radeon_surf *surface)
812 {
813 struct r600_texture *rtex;
814 struct r600_resource *resource;
815 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
816
817 rtex = CALLOC_STRUCT(r600_texture);
818 if (!rtex)
819 return NULL;
820
821 resource = &rtex->resource;
822 resource->b.b = *base;
823 resource->b.vtbl = &r600_texture_vtbl;
824 pipe_reference_init(&resource->b.b.reference, 1);
825 resource->b.b.screen = screen;
826
827 /* don't include stencil-only formats which we don't support for rendering */
828 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
829
830 rtex->surface = *surface;
831 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override, offset)) {
832 FREE(rtex);
833 return NULL;
834 }
835
836 /* Tiled depth textures utilize the non-displayable tile order.
837 * This must be done after r600_setup_surface.
838 * Applies to R600-Cayman. */
839 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
840
841 if (rtex->is_depth) {
842 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
843 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
844 !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
845
846 r600_texture_allocate_htile(rscreen, rtex);
847 }
848 } else {
849 if (base->nr_samples > 1) {
850 if (!buf) {
851 r600_texture_allocate_fmask(rscreen, rtex);
852 r600_texture_allocate_cmask(rscreen, rtex);
853 rtex->cmask_buffer = &rtex->resource;
854 }
855 if (!rtex->fmask.size || !rtex->cmask.size) {
856 FREE(rtex);
857 return NULL;
858 }
859 }
860
861 if (!buf && rtex->surface.dcc_size &&
862 !(rscreen->debug_flags & DBG_NO_DCC)) {
863 /* Reserve space for the DCC buffer. */
864 rtex->dcc_offset = align(rtex->size, rtex->surface.dcc_alignment);
865 rtex->size = rtex->dcc_offset + rtex->surface.dcc_size;
866 rtex->cb_color_info |= VI_S_028C70_DCC_ENABLE(1);
867 }
868 }
869
870 /* Now create the backing buffer. */
871 if (!buf) {
872 if (!r600_init_resource(rscreen, resource, rtex->size,
873 rtex->surface.bo_alignment, TRUE)) {
874 FREE(rtex);
875 return NULL;
876 }
877 } else {
878 resource->buf = buf;
879 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
880 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
881 }
882
883 if (rtex->cmask.size) {
884 /* Initialize the cmask to 0xCC (= compressed state). */
885 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
886 rtex->cmask.offset, rtex->cmask.size,
887 0xCCCCCCCC, true);
888 }
889 if (rtex->dcc_offset) {
890 r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
891 rtex->dcc_offset,
892 rtex->surface.dcc_size,
893 0xFFFFFFFF, true);
894 }
895
896 /* Initialize the CMASK base register value. */
897 rtex->cmask.base_address_reg =
898 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
899
900 if (rscreen->debug_flags & DBG_VM) {
901 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
902 rtex->resource.gpu_address,
903 rtex->resource.gpu_address + rtex->resource.buf->size,
904 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
905 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
906 }
907
908 if (rscreen->debug_flags & DBG_TEX) {
909 puts("Texture:");
910 r600_print_texture_info(rtex, stdout);
911 }
912
913 return rtex;
914 }
915
916 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
917 const struct pipe_resource *templ)
918 {
919 const struct util_format_description *desc = util_format_description(templ->format);
920 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
921
922 /* MSAA resources must be 2D tiled. */
923 if (templ->nr_samples > 1)
924 return RADEON_SURF_MODE_2D;
925
926 /* Transfer resources should be linear. */
927 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
928 return RADEON_SURF_MODE_LINEAR_ALIGNED;
929
930 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
931 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
932 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
933 (templ->target == PIPE_TEXTURE_2D ||
934 templ->target == PIPE_TEXTURE_3D))
935 force_tiling = true;
936
937 /* Handle common candidates for the linear mode.
938 * Compressed textures must always be tiled. */
939 if (!force_tiling && !util_format_is_compressed(templ->format)) {
940 /* Not everything can be linear, so we cannot enforce it
941 * for all textures. */
942 if ((rscreen->debug_flags & DBG_NO_TILING) &&
943 (!util_format_is_depth_or_stencil(templ->format) ||
944 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH)))
945 return RADEON_SURF_MODE_LINEAR_ALIGNED;
946
947 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
948 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
949 return RADEON_SURF_MODE_LINEAR_ALIGNED;
950
951 /* Cursors are linear on SI.
952 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
953 if (rscreen->chip_class >= SI &&
954 (templ->bind & PIPE_BIND_CURSOR))
955 return RADEON_SURF_MODE_LINEAR_ALIGNED;
956
957 if (templ->bind & PIPE_BIND_LINEAR)
958 return RADEON_SURF_MODE_LINEAR_ALIGNED;
959
960 /* Textures with a very small height are recommended to be linear. */
961 if (templ->target == PIPE_TEXTURE_1D ||
962 templ->target == PIPE_TEXTURE_1D_ARRAY ||
963 templ->height0 <= 4)
964 return RADEON_SURF_MODE_LINEAR_ALIGNED;
965
966 /* Textures likely to be mapped often. */
967 if (templ->usage == PIPE_USAGE_STAGING ||
968 templ->usage == PIPE_USAGE_STREAM)
969 return RADEON_SURF_MODE_LINEAR_ALIGNED;
970 }
971
972 /* Make small textures 1D tiled. */
973 if (templ->width0 <= 16 || templ->height0 <= 16 ||
974 (rscreen->debug_flags & DBG_NO_2D_TILING))
975 return RADEON_SURF_MODE_1D;
976
977 /* The allocator will switch to 1D if needed. */
978 return RADEON_SURF_MODE_2D;
979 }
980
981 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
982 const struct pipe_resource *templ)
983 {
984 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
985 struct radeon_surf surface = {0};
986 int r;
987
988 r = r600_init_surface(rscreen, &surface, templ,
989 r600_choose_tiling(rscreen, templ),
990 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
991 if (r) {
992 return NULL;
993 }
994 r = rscreen->ws->surface_best(rscreen->ws, &surface);
995 if (r) {
996 return NULL;
997 }
998 return (struct pipe_resource *)r600_texture_create_object(screen, templ, 0,
999 0, NULL, &surface);
1000 }
1001
1002 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
1003 const struct pipe_resource *templ,
1004 struct winsys_handle *whandle,
1005 unsigned usage)
1006 {
1007 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1008 struct pb_buffer *buf = NULL;
1009 unsigned stride = 0, offset = 0;
1010 unsigned array_mode;
1011 struct radeon_surf surface;
1012 int r;
1013 struct radeon_bo_metadata metadata = {};
1014 struct r600_texture *rtex;
1015
1016 /* Support only 2D textures without mipmaps */
1017 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
1018 templ->depth0 != 1 || templ->last_level != 0)
1019 return NULL;
1020
1021 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride, &offset);
1022 if (!buf)
1023 return NULL;
1024
1025 rscreen->ws->buffer_get_metadata(buf, &metadata);
1026
1027 surface.bankw = metadata.bankw;
1028 surface.bankh = metadata.bankh;
1029 surface.tile_split = metadata.tile_split;
1030 surface.stencil_tile_split = metadata.stencil_tile_split;
1031 surface.mtilea = metadata.mtilea;
1032
1033 if (metadata.macrotile == RADEON_LAYOUT_TILED)
1034 array_mode = RADEON_SURF_MODE_2D;
1035 else if (metadata.microtile == RADEON_LAYOUT_TILED)
1036 array_mode = RADEON_SURF_MODE_1D;
1037 else
1038 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1039
1040 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
1041 if (r) {
1042 return NULL;
1043 }
1044
1045 if (metadata.scanout)
1046 surface.flags |= RADEON_SURF_SCANOUT;
1047
1048 rtex = r600_texture_create_object(screen, templ, stride,
1049 offset, buf, &surface);
1050 if (!rtex)
1051 return NULL;
1052
1053 rtex->resource.is_shared = true;
1054 rtex->resource.external_usage = usage;
1055 return &rtex->resource.b.b;
1056 }
1057
1058 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
1059 struct pipe_resource *texture,
1060 struct r600_texture **staging)
1061 {
1062 struct r600_texture *rtex = (struct r600_texture*)texture;
1063 struct pipe_resource resource;
1064 struct r600_texture **flushed_depth_texture = staging ?
1065 staging : &rtex->flushed_depth_texture;
1066
1067 if (!staging && rtex->flushed_depth_texture)
1068 return true; /* it's ready */
1069
1070 resource.target = texture->target;
1071 resource.format = texture->format;
1072 resource.width0 = texture->width0;
1073 resource.height0 = texture->height0;
1074 resource.depth0 = texture->depth0;
1075 resource.array_size = texture->array_size;
1076 resource.last_level = texture->last_level;
1077 resource.nr_samples = texture->nr_samples;
1078 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1079 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
1080 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1081
1082 if (staging)
1083 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
1084
1085 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
1086 if (*flushed_depth_texture == NULL) {
1087 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1088 return false;
1089 }
1090
1091 (*flushed_depth_texture)->is_flushing_texture = TRUE;
1092 (*flushed_depth_texture)->non_disp_tiling = false;
1093 return true;
1094 }
1095
1096 /**
1097 * Initialize the pipe_resource descriptor to be of the same size as the box,
1098 * which is supposed to hold a subregion of the texture "orig" at the given
1099 * mipmap level.
1100 */
1101 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
1102 struct pipe_resource *orig,
1103 const struct pipe_box *box,
1104 unsigned level, unsigned flags)
1105 {
1106 memset(res, 0, sizeof(*res));
1107 res->format = orig->format;
1108 res->width0 = box->width;
1109 res->height0 = box->height;
1110 res->depth0 = 1;
1111 res->array_size = 1;
1112 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1113 res->flags = flags;
1114
1115 /* We must set the correct texture target and dimensions for a 3D box. */
1116 if (box->depth > 1 && util_max_layer(orig, level) > 0)
1117 res->target = orig->target;
1118 else
1119 res->target = PIPE_TEXTURE_2D;
1120
1121 switch (res->target) {
1122 case PIPE_TEXTURE_1D_ARRAY:
1123 case PIPE_TEXTURE_2D_ARRAY:
1124 case PIPE_TEXTURE_CUBE_ARRAY:
1125 res->array_size = box->depth;
1126 break;
1127 case PIPE_TEXTURE_3D:
1128 res->depth0 = box->depth;
1129 break;
1130 default:;
1131 }
1132 }
1133
1134 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1135 struct pipe_resource *texture,
1136 unsigned level,
1137 unsigned usage,
1138 const struct pipe_box *box,
1139 struct pipe_transfer **ptransfer)
1140 {
1141 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1142 struct r600_texture *rtex = (struct r600_texture*)texture;
1143 struct r600_transfer *trans;
1144 boolean use_staging_texture = FALSE;
1145 struct r600_resource *buf;
1146 unsigned offset = 0;
1147 char *map;
1148
1149 /* We cannot map a tiled texture directly because the data is
1150 * in a different order, therefore we do detiling using a blit.
1151 *
1152 * Also, use a temporary in GTT memory for read transfers, as
1153 * the CPU is much happier reading out of cached system memory
1154 * than uncached VRAM.
1155 */
1156 if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
1157 use_staging_texture = TRUE;
1158 } else if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
1159 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
1160 /* Untiled buffers in VRAM, which is slow for CPU reads */
1161 use_staging_texture = TRUE;
1162 } else if (!(usage & PIPE_TRANSFER_READ) &&
1163 (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf, RADEON_USAGE_READWRITE) ||
1164 !rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) {
1165 /* Use a staging texture for uploads if the underlying BO is busy. */
1166 use_staging_texture = TRUE;
1167 }
1168
1169 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
1170 use_staging_texture = FALSE;
1171 }
1172
1173 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
1174 return NULL;
1175 }
1176
1177 trans = CALLOC_STRUCT(r600_transfer);
1178 if (!trans)
1179 return NULL;
1180 trans->transfer.resource = texture;
1181 trans->transfer.level = level;
1182 trans->transfer.usage = usage;
1183 trans->transfer.box = *box;
1184
1185 if (rtex->is_depth) {
1186 struct r600_texture *staging_depth;
1187
1188 if (rtex->resource.b.b.nr_samples > 1) {
1189 /* MSAA depth buffers need to be converted to single sample buffers.
1190 *
1191 * Mapping MSAA depth buffers can occur if ReadPixels is called
1192 * with a multisample GLX visual.
1193 *
1194 * First downsample the depth buffer to a temporary texture,
1195 * then decompress the temporary one to staging.
1196 *
1197 * Only the region being mapped is transfered.
1198 */
1199 struct pipe_resource resource;
1200
1201 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1202
1203 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1204 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1205 FREE(trans);
1206 return NULL;
1207 }
1208
1209 if (usage & PIPE_TRANSFER_READ) {
1210 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1211 if (!temp) {
1212 R600_ERR("failed to create a temporary depth texture\n");
1213 FREE(trans);
1214 return NULL;
1215 }
1216
1217 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1218 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1219 0, 0, 0, box->depth, 0, 0);
1220 pipe_resource_reference(&temp, NULL);
1221 }
1222 }
1223 else {
1224 /* XXX: only readback the rectangle which is being mapped? */
1225 /* XXX: when discard is true, no need to read back from depth texture */
1226 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1227 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1228 FREE(trans);
1229 return NULL;
1230 }
1231
1232 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1233 level, level,
1234 box->z, box->z + box->depth - 1,
1235 0, 0);
1236
1237 offset = r600_texture_get_offset(staging_depth, level, box);
1238 }
1239
1240 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
1241 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1242 trans->staging = (struct r600_resource*)staging_depth;
1243 } else if (use_staging_texture) {
1244 struct pipe_resource resource;
1245 struct r600_texture *staging;
1246
1247 r600_init_temp_resource_from_box(&resource, texture, box, level,
1248 R600_RESOURCE_FLAG_TRANSFER);
1249 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1250 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1251
1252 /* Create the temporary texture. */
1253 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1254 if (!staging) {
1255 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1256 FREE(trans);
1257 return NULL;
1258 }
1259 trans->staging = &staging->resource;
1260 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1261 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1262 if (usage & PIPE_TRANSFER_READ) {
1263 r600_copy_to_staging_texture(ctx, trans);
1264 }
1265 } else {
1266 /* the resource is mapped directly */
1267 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1268 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1269 offset = r600_texture_get_offset(rtex, level, box);
1270 }
1271
1272 if (trans->staging) {
1273 buf = trans->staging;
1274 if (!rtex->is_depth && !(usage & PIPE_TRANSFER_READ))
1275 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1276 } else {
1277 buf = &rtex->resource;
1278 }
1279
1280 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1281 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1282 FREE(trans);
1283 return NULL;
1284 }
1285
1286 *ptransfer = &trans->transfer;
1287 return map + offset;
1288 }
1289
1290 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1291 struct pipe_transfer* transfer)
1292 {
1293 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1294 struct pipe_resource *texture = transfer->resource;
1295 struct r600_texture *rtex = (struct r600_texture*)texture;
1296
1297 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1298 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1299 ctx->resource_copy_region(ctx, texture, transfer->level,
1300 transfer->box.x, transfer->box.y, transfer->box.z,
1301 &rtransfer->staging->b.b, transfer->level,
1302 &transfer->box);
1303 } else {
1304 r600_copy_from_staging_texture(ctx, rtransfer);
1305 }
1306 }
1307
1308 if (rtransfer->staging)
1309 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1310
1311 FREE(transfer);
1312 }
1313
1314 static const struct u_resource_vtbl r600_texture_vtbl =
1315 {
1316 NULL, /* get_handle */
1317 r600_texture_destroy, /* resource_destroy */
1318 r600_texture_transfer_map, /* transfer_map */
1319 u_default_transfer_flush_region, /* transfer_flush_region */
1320 r600_texture_transfer_unmap, /* transfer_unmap */
1321 NULL /* transfer_inline_write */
1322 };
1323
1324 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1325 struct pipe_resource *texture,
1326 const struct pipe_surface *templ,
1327 unsigned width, unsigned height)
1328 {
1329 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1330
1331 if (!surface)
1332 return NULL;
1333
1334 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1335 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1336
1337 pipe_reference_init(&surface->base.reference, 1);
1338 pipe_resource_reference(&surface->base.texture, texture);
1339 surface->base.context = pipe;
1340 surface->base.format = templ->format;
1341 surface->base.width = width;
1342 surface->base.height = height;
1343 surface->base.u = templ->u;
1344 return &surface->base;
1345 }
1346
1347 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1348 struct pipe_resource *tex,
1349 const struct pipe_surface *templ)
1350 {
1351 unsigned level = templ->u.tex.level;
1352 unsigned width = u_minify(tex->width0, level);
1353 unsigned height = u_minify(tex->height0, level);
1354
1355 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1356 const struct util_format_description *tex_desc
1357 = util_format_description(tex->format);
1358 const struct util_format_description *templ_desc
1359 = util_format_description(templ->format);
1360
1361 assert(tex_desc->block.bits == templ_desc->block.bits);
1362
1363 /* Adjust size of surface if and only if the block width or
1364 * height is changed. */
1365 if (tex_desc->block.width != templ_desc->block.width ||
1366 tex_desc->block.height != templ_desc->block.height) {
1367 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1368 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1369
1370 width = nblks_x * templ_desc->block.width;
1371 height = nblks_y * templ_desc->block.height;
1372 }
1373 }
1374
1375 return r600_create_surface_custom(pipe, tex, templ, width, height);
1376 }
1377
1378 static void r600_surface_destroy(struct pipe_context *pipe,
1379 struct pipe_surface *surface)
1380 {
1381 struct r600_surface *surf = (struct r600_surface*)surface;
1382 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1383 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1384 pipe_resource_reference(&surface->texture, NULL);
1385 FREE(surface);
1386 }
1387
1388 unsigned r600_translate_colorswap(enum pipe_format format)
1389 {
1390 const struct util_format_description *desc = util_format_description(format);
1391
1392 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1393
1394 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1395 return V_0280A0_SWAP_STD;
1396
1397 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1398 return ~0U;
1399
1400 switch (desc->nr_channels) {
1401 case 1:
1402 if (HAS_SWIZZLE(0,X))
1403 return V_0280A0_SWAP_STD; /* X___ */
1404 else if (HAS_SWIZZLE(3,X))
1405 return V_0280A0_SWAP_ALT_REV; /* ___X */
1406 break;
1407 case 2:
1408 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1409 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1410 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1411 return V_0280A0_SWAP_STD; /* XY__ */
1412 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1413 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1414 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1415 return V_0280A0_SWAP_STD_REV; /* YX__ */
1416 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1417 return V_0280A0_SWAP_ALT; /* X__Y */
1418 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1419 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1420 break;
1421 case 3:
1422 if (HAS_SWIZZLE(0,X))
1423 return V_0280A0_SWAP_STD; /* XYZ */
1424 else if (HAS_SWIZZLE(0,Z))
1425 return V_0280A0_SWAP_STD_REV; /* ZYX */
1426 break;
1427 case 4:
1428 /* check the middle channels, the 1st and 4th channel can be NONE */
1429 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
1430 return V_0280A0_SWAP_STD; /* XYZW */
1431 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
1432 return V_0280A0_SWAP_STD_REV; /* WZYX */
1433 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
1434 return V_0280A0_SWAP_ALT; /* ZYXW */
1435 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W))
1436 return V_0280A0_SWAP_ALT_REV; /* YZWX */
1437 break;
1438 }
1439 return ~0U;
1440 }
1441
1442 static void evergreen_set_clear_color(struct r600_texture *rtex,
1443 enum pipe_format surface_format,
1444 const union pipe_color_union *color)
1445 {
1446 union util_color uc;
1447
1448 memset(&uc, 0, sizeof(uc));
1449
1450 if (util_format_is_pure_uint(surface_format)) {
1451 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1452 } else if (util_format_is_pure_sint(surface_format)) {
1453 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1454 } else {
1455 util_pack_color(color->f, surface_format, &uc);
1456 }
1457
1458 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1459 }
1460
1461 static void vi_get_fast_clear_parameters(enum pipe_format surface_format,
1462 const union pipe_color_union *color,
1463 uint32_t* reset_value,
1464 bool* clear_words_needed)
1465 {
1466 bool values[4] = {};
1467 int i;
1468 bool main_value = false;
1469 bool extra_value = false;
1470 int extra_channel;
1471 const struct util_format_description *desc = util_format_description(surface_format);
1472
1473 *clear_words_needed = true;
1474 *reset_value = 0x20202020U;
1475
1476 /* If we want to clear without needing a fast clear eliminate step, we
1477 * can set each channel to 0 or 1 (or 0/max for integer formats). We
1478 * have two sets of flags, one for the last or first channel(extra) and
1479 * one for the other channels(main).
1480 */
1481
1482 if (surface_format == PIPE_FORMAT_R11G11B10_FLOAT ||
1483 surface_format == PIPE_FORMAT_B5G6R5_UNORM ||
1484 surface_format == PIPE_FORMAT_B5G6R5_SRGB) {
1485 extra_channel = -1;
1486 } else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
1487 if(r600_translate_colorswap(surface_format) <= 1)
1488 extra_channel = desc->nr_channels - 1;
1489 else
1490 extra_channel = 0;
1491 } else
1492 return;
1493
1494 for (i = 0; i < 4; ++i) {
1495 int index = desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X;
1496
1497 if (desc->swizzle[i] < UTIL_FORMAT_SWIZZLE_X ||
1498 desc->swizzle[i] > UTIL_FORMAT_SWIZZLE_W)
1499 continue;
1500
1501 if (util_format_is_pure_sint(surface_format)) {
1502 values[i] = color->i[i] != 0;
1503 if (color->i[i] != 0 && color->i[i] != INT32_MAX)
1504 return;
1505 } else if (util_format_is_pure_uint(surface_format)) {
1506 values[i] = color->ui[i] != 0U;
1507 if (color->ui[i] != 0U && color->ui[i] != UINT32_MAX)
1508 return;
1509 } else {
1510 values[i] = color->f[i] != 0.0F;
1511 if (color->f[i] != 0.0F && color->f[i] != 1.0F)
1512 return;
1513 }
1514
1515 if (index == extra_channel)
1516 extra_value = values[i];
1517 else
1518 main_value = values[i];
1519 }
1520
1521 for (int i = 0; i < 4; ++i)
1522 if (values[i] != main_value &&
1523 desc->swizzle[i] - UTIL_FORMAT_SWIZZLE_X != extra_channel &&
1524 desc->swizzle[i] >= UTIL_FORMAT_SWIZZLE_X &&
1525 desc->swizzle[i] <= UTIL_FORMAT_SWIZZLE_W)
1526 return;
1527
1528 *clear_words_needed = false;
1529 if (main_value)
1530 *reset_value |= 0x80808080U;
1531
1532 if (extra_value)
1533 *reset_value |= 0x40404040U;
1534 }
1535
1536 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1537 struct pipe_framebuffer_state *fb,
1538 struct r600_atom *fb_state,
1539 unsigned *buffers, unsigned *dirty_cbufs,
1540 const union pipe_color_union *color)
1541 {
1542 int i;
1543
1544 /* This function is broken in BE, so just disable this path for now */
1545 #ifdef PIPE_ARCH_BIG_ENDIAN
1546 return;
1547 #endif
1548
1549 if (rctx->render_cond)
1550 return;
1551
1552 for (i = 0; i < fb->nr_cbufs; i++) {
1553 struct r600_texture *tex;
1554 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1555
1556 if (!fb->cbufs[i])
1557 continue;
1558
1559 /* if this colorbuffer is not being cleared */
1560 if (!(*buffers & clear_bit))
1561 continue;
1562
1563 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1564
1565 /* 128-bit formats are unusupported */
1566 if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
1567 continue;
1568 }
1569
1570 /* the clear is allowed if all layers are bound */
1571 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1572 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1573 continue;
1574 }
1575
1576 /* cannot clear mipmapped textures */
1577 if (fb->cbufs[i]->texture->last_level != 0) {
1578 continue;
1579 }
1580
1581 /* only supported on tiled surfaces */
1582 if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
1583 continue;
1584 }
1585
1586 /* shared textures can't use fast clear without an explicit flush,
1587 * because there is no way to communicate the clear color among
1588 * all clients
1589 */
1590 if (tex->resource.is_shared &&
1591 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
1592 continue;
1593
1594 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
1595 if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
1596 rctx->chip_class >= CIK &&
1597 rctx->screen->info.drm_major == 2 &&
1598 rctx->screen->info.drm_minor < 38) {
1599 continue;
1600 }
1601
1602 if (tex->dcc_offset) {
1603 uint32_t reset_value;
1604 bool clear_words_needed;
1605
1606 if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
1607 continue;
1608
1609 vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed);
1610
1611 rctx->clear_buffer(&rctx->b, &tex->resource.b.b,
1612 tex->dcc_offset, tex->surface.dcc_size,
1613 reset_value, true);
1614
1615 if (clear_words_needed)
1616 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1617 } else {
1618 /* Stoney/RB+ doesn't work with CMASK fast clear. */
1619 if (rctx->family == CHIP_STONEY)
1620 continue;
1621
1622 /* ensure CMASK is enabled */
1623 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1624 if (tex->cmask.size == 0) {
1625 continue;
1626 }
1627
1628 /* Do the fast clear. */
1629 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1630 tex->cmask.offset, tex->cmask.size, 0, true);
1631
1632 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1633 }
1634
1635 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1636
1637 if (dirty_cbufs)
1638 *dirty_cbufs |= 1 << i;
1639 rctx->set_atom_dirty(rctx, fb_state, true);
1640 *buffers &= ~clear_bit;
1641 }
1642 }
1643
1644 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1645 {
1646 rscreen->b.resource_from_handle = r600_texture_from_handle;
1647 rscreen->b.resource_get_handle = r600_texture_get_handle;
1648 }
1649
1650 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1651 {
1652 rctx->b.create_surface = r600_create_surface;
1653 rctx->b.surface_destroy = r600_surface_destroy;
1654 }