2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "os/os_time.h"
37 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
38 struct r600_texture
*rtex
);
39 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
40 const struct pipe_resource
*templ
);
43 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
44 struct r600_texture
*rdst
,
45 unsigned dst_level
, unsigned dstx
,
46 unsigned dsty
, unsigned dstz
,
47 struct r600_texture
*rsrc
,
49 const struct pipe_box
*src_box
)
54 if (util_format_get_blocksizebits(rdst
->resource
.b
.b
.format
) !=
55 util_format_get_blocksizebits(rsrc
->resource
.b
.b
.format
))
58 /* MSAA: Blits don't exist in the real world. */
59 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
60 rdst
->resource
.b
.b
.nr_samples
> 1)
63 /* Depth-stencil surfaces:
64 * When dst is linear, the DB->CB copy preserves HTILE.
65 * When dst is tiled, the 3D path must be used to update HTILE.
67 if (rsrc
->is_depth
|| rdst
->is_depth
)
71 * src: Use the 3D path. DCC decompression is expensive.
72 * dst: Use the 3D path to compress the pixels with DCC.
74 if ((rsrc
->dcc_offset
&& rsrc
->surface
.level
[src_level
].dcc_enabled
) ||
75 (rdst
->dcc_offset
&& rdst
->surface
.level
[dst_level
].dcc_enabled
))
79 * src: Both texture and SDMA paths need decompression. Use SDMA.
80 * dst: If overwriting the whole texture, discard CMASK and use
81 * SDMA. Otherwise, use the 3D path.
83 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
84 /* The CMASK clear is only enabled for the first level. */
85 assert(dst_level
== 0);
86 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
87 dstx
, dsty
, dstz
, src_box
->width
,
88 src_box
->height
, src_box
->depth
))
91 r600_texture_discard_cmask(rctx
->screen
, rdst
);
94 /* All requirements are met. Prepare textures for SDMA. */
95 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
96 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
98 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
99 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
104 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
105 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
106 struct pipe_resource
*dst
,
108 unsigned dstx
, unsigned dsty
, unsigned dstz
,
109 struct pipe_resource
*src
,
111 const struct pipe_box
*src_box
)
113 struct pipe_blit_info blit
;
115 memset(&blit
, 0, sizeof(blit
));
116 blit
.src
.resource
= src
;
117 blit
.src
.format
= src
->format
;
118 blit
.src
.level
= src_level
;
119 blit
.src
.box
= *src_box
;
120 blit
.dst
.resource
= dst
;
121 blit
.dst
.format
= dst
->format
;
122 blit
.dst
.level
= dst_level
;
123 blit
.dst
.box
.x
= dstx
;
124 blit
.dst
.box
.y
= dsty
;
125 blit
.dst
.box
.z
= dstz
;
126 blit
.dst
.box
.width
= src_box
->width
;
127 blit
.dst
.box
.height
= src_box
->height
;
128 blit
.dst
.box
.depth
= src_box
->depth
;
129 blit
.mask
= util_format_get_mask(src
->format
) &
130 util_format_get_mask(dst
->format
);
131 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
134 pipe
->blit(pipe
, &blit
);
138 /* Copy from a full GPU texture to a transfer's staging one. */
139 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
141 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
142 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
143 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
144 struct pipe_resource
*src
= transfer
->resource
;
146 if (src
->nr_samples
> 1) {
147 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
148 src
, transfer
->level
, &transfer
->box
);
152 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
156 /* Copy from a transfer's staging texture to a full GPU one. */
157 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
159 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
160 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
161 struct pipe_resource
*dst
= transfer
->resource
;
162 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
163 struct pipe_box sbox
;
165 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
167 if (dst
->nr_samples
> 1) {
168 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
169 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
174 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
175 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
179 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
180 const struct pipe_box
*box
)
182 enum pipe_format format
= rtex
->resource
.b
.b
.format
;
184 return rtex
->surface
.level
[level
].offset
+
185 box
->z
* rtex
->surface
.level
[level
].slice_size
+
186 box
->y
/ util_format_get_blockheight(format
) * rtex
->surface
.level
[level
].pitch_bytes
+
187 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
190 static int r600_init_surface(struct r600_common_screen
*rscreen
,
191 struct radeon_surf
*surface
,
192 const struct pipe_resource
*ptex
,
194 bool is_flushed_depth
)
196 const struct util_format_description
*desc
=
197 util_format_description(ptex
->format
);
198 bool is_depth
, is_stencil
;
200 is_depth
= util_format_has_depth(desc
);
201 is_stencil
= util_format_has_stencil(desc
);
203 surface
->npix_x
= ptex
->width0
;
204 surface
->npix_y
= ptex
->height0
;
205 surface
->npix_z
= ptex
->depth0
;
206 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
207 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
209 surface
->array_size
= 1;
210 surface
->last_level
= ptex
->last_level
;
212 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
213 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
214 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
216 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
217 /* align byte per element on dword */
218 if (surface
->bpe
== 3) {
223 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
224 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
226 switch (ptex
->target
) {
227 case PIPE_TEXTURE_1D
:
228 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
230 case PIPE_TEXTURE_RECT
:
231 case PIPE_TEXTURE_2D
:
232 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
234 case PIPE_TEXTURE_3D
:
235 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
237 case PIPE_TEXTURE_1D_ARRAY
:
238 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
239 surface
->array_size
= ptex
->array_size
;
241 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d array */
242 assert(ptex
->array_size
% 6 == 0);
243 case PIPE_TEXTURE_2D_ARRAY
:
244 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
245 surface
->array_size
= ptex
->array_size
;
247 case PIPE_TEXTURE_CUBE
:
248 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
255 if (!is_flushed_depth
&& is_depth
) {
256 surface
->flags
|= RADEON_SURF_ZBUFFER
;
259 surface
->flags
|= RADEON_SURF_SBUFFER
|
260 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
263 if (rscreen
->chip_class
>= SI
) {
264 surface
->flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
267 if (rscreen
->chip_class
>= VI
&&
268 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
269 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
270 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
272 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
273 /* This should catch bugs in gallium users setting incorrect flags. */
274 assert(surface
->nsamples
== 1 &&
275 surface
->array_size
== 1 &&
276 surface
->npix_z
== 1 &&
277 surface
->last_level
== 0 &&
278 !(surface
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
280 surface
->flags
|= RADEON_SURF_SCANOUT
;
285 static int r600_setup_surface(struct pipe_screen
*screen
,
286 struct r600_texture
*rtex
,
287 unsigned pitch_in_bytes_override
,
290 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
294 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
299 rtex
->size
= rtex
->surface
.bo_size
;
301 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
302 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
305 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
306 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
307 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
311 for (i
= 0; i
< ARRAY_SIZE(rtex
->surface
.level
); ++i
)
312 rtex
->surface
.level
[i
].offset
+= offset
;
317 static void r600_texture_init_metadata(struct r600_texture
*rtex
,
318 struct radeon_bo_metadata
*metadata
)
320 struct radeon_surf
*surface
= &rtex
->surface
;
322 memset(metadata
, 0, sizeof(*metadata
));
323 metadata
->microtile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
324 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
325 metadata
->macrotile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
326 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
327 metadata
->pipe_config
= surface
->pipe_config
;
328 metadata
->bankw
= surface
->bankw
;
329 metadata
->bankh
= surface
->bankh
;
330 metadata
->tile_split
= surface
->tile_split
;
331 metadata
->mtilea
= surface
->mtilea
;
332 metadata
->num_banks
= surface
->num_banks
;
333 metadata
->stride
= surface
->level
[0].pitch_bytes
;
334 metadata
->scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
337 static void r600_dirty_all_framebuffer_states(struct r600_common_screen
*rscreen
)
339 p_atomic_inc(&rscreen
->dirty_fb_counter
);
342 static void r600_eliminate_fast_color_clear(struct r600_common_screen
*rscreen
,
343 struct r600_texture
*rtex
)
345 struct pipe_context
*ctx
= rscreen
->aux_context
;
347 pipe_mutex_lock(rscreen
->aux_context_lock
);
348 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
349 ctx
->flush(ctx
, NULL
, 0);
350 pipe_mutex_unlock(rscreen
->aux_context_lock
);
353 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
354 struct r600_texture
*rtex
)
356 if (!rtex
->cmask
.size
)
359 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
362 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
363 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
365 if (rscreen
->chip_class
>= SI
)
366 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
368 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
370 if (rtex
->cmask_buffer
!= &rtex
->resource
)
371 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
373 /* Notify all contexts about the change. */
374 r600_dirty_all_framebuffer_states(rscreen
);
375 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
378 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
380 /* We can't disable DCC if it can be written by another process. */
381 return rtex
->dcc_offset
&&
382 (!rtex
->resource
.is_shared
||
383 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
386 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
387 struct r600_texture
*rtex
)
389 if (!r600_can_disable_dcc(rtex
))
392 assert(rtex
->dcc_separate_buffer
== NULL
);
395 rtex
->dcc_offset
= 0;
397 /* Notify all contexts about the change. */
398 r600_dirty_all_framebuffer_states(rscreen
);
402 bool r600_texture_disable_dcc(struct r600_common_screen
*rscreen
,
403 struct r600_texture
*rtex
)
405 struct r600_common_context
*rctx
=
406 (struct r600_common_context
*)rscreen
->aux_context
;
408 if (!r600_can_disable_dcc(rtex
))
411 /* Decompress DCC. */
412 pipe_mutex_lock(rscreen
->aux_context_lock
);
413 rctx
->decompress_dcc(&rctx
->b
, rtex
);
414 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
415 pipe_mutex_unlock(rscreen
->aux_context_lock
);
417 return r600_texture_discard_dcc(rscreen
, rtex
);
420 static void r600_degrade_tile_mode_to_linear(struct r600_common_context
*rctx
,
421 struct r600_texture
*rtex
,
422 bool invalidate_storage
)
424 struct pipe_screen
*screen
= rctx
->b
.screen
;
425 struct r600_texture
*new_tex
;
426 struct pipe_resource templ
= rtex
->resource
.b
.b
;
429 templ
.bind
|= PIPE_BIND_LINEAR
;
431 /* r600g doesn't react to dirty_tex_descriptor_counter */
432 if (rctx
->chip_class
< SI
)
435 if (rtex
->resource
.is_shared
||
436 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
)
439 /* This fails with MSAA, depth, and compressed textures. */
440 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
441 RADEON_SURF_MODE_LINEAR_ALIGNED
)
444 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
448 /* Copy the pixels to the new texture. */
449 if (!invalidate_storage
) {
450 for (i
= 0; i
<= templ
.last_level
; i
++) {
454 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
455 util_max_layer(&templ
, i
) + 1, &box
);
457 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
458 &rtex
->resource
.b
.b
, i
, &box
);
462 r600_texture_discard_cmask(rctx
->screen
, rtex
);
463 r600_texture_discard_dcc(rctx
->screen
, rtex
);
465 /* Replace the structure fields of rtex. */
466 rtex
->resource
.b
.b
.bind
= templ
.bind
;
467 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
468 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
469 rtex
->resource
.domains
= new_tex
->resource
.domains
;
470 rtex
->size
= new_tex
->size
;
471 rtex
->surface
= new_tex
->surface
;
472 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
473 rtex
->cb_color_info
= new_tex
->cb_color_info
;
474 rtex
->cmask
= new_tex
->cmask
; /* needed even without CMASK */
476 assert(!rtex
->htile_buffer
);
477 assert(!rtex
->cmask
.size
);
478 assert(!rtex
->fmask
.size
);
479 assert(!rtex
->dcc_offset
);
480 assert(!rtex
->is_depth
);
482 r600_texture_reference(&new_tex
, NULL
);
484 r600_dirty_all_framebuffer_states(rctx
->screen
);
485 p_atomic_inc(&rctx
->screen
->dirty_tex_descriptor_counter
);
488 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
489 struct pipe_resource
*resource
,
490 struct winsys_handle
*whandle
,
493 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
494 struct r600_resource
*res
= (struct r600_resource
*)resource
;
495 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
496 struct radeon_bo_metadata metadata
;
497 bool update_metadata
= false;
499 /* This is not supported now, but it might be required for OpenCL
500 * interop in the future.
502 if (resource
->target
!= PIPE_BUFFER
&&
503 (resource
->nr_samples
> 1 || rtex
->is_depth
))
506 if (resource
->target
!= PIPE_BUFFER
) {
507 /* Since shader image stores don't support DCC on VI,
508 * disable it for external clients that want write
511 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
512 if (r600_texture_disable_dcc(rscreen
, rtex
))
513 update_metadata
= true;
516 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
518 /* Eliminate fast clear (both CMASK and DCC) */
519 r600_eliminate_fast_color_clear(rscreen
, rtex
);
521 /* Disable CMASK if flush_resource isn't going
524 r600_texture_discard_cmask(rscreen
, rtex
);
528 if (!res
->is_shared
|| update_metadata
) {
529 r600_texture_init_metadata(rtex
, &metadata
);
530 if (rscreen
->query_opaque_metadata
)
531 rscreen
->query_opaque_metadata(rscreen
, rtex
,
534 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
538 if (res
->is_shared
) {
539 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
542 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
543 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
544 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
546 res
->is_shared
= true;
547 res
->external_usage
= usage
;
550 return rscreen
->ws
->buffer_get_handle(res
->buf
,
551 rtex
->surface
.level
[0].pitch_bytes
,
552 rtex
->surface
.level
[0].offset
,
553 rtex
->surface
.level
[0].slice_size
,
557 static void r600_texture_destroy(struct pipe_screen
*screen
,
558 struct pipe_resource
*ptex
)
560 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
561 struct r600_resource
*resource
= &rtex
->resource
;
563 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
565 r600_resource_reference(&rtex
->htile_buffer
, NULL
);
566 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
567 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
569 pb_reference(&resource
->buf
, NULL
);
570 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
571 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
575 static const struct u_resource_vtbl r600_texture_vtbl
;
577 /* The number of samples can be specified independently of the texture. */
578 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
579 struct r600_texture
*rtex
,
581 struct r600_fmask_info
*out
)
583 /* FMASK is allocated like an ordinary texture. */
584 struct radeon_surf fmask
= rtex
->surface
;
586 memset(out
, 0, sizeof(*out
));
588 fmask
.bo_alignment
= 0;
591 fmask
.flags
|= RADEON_SURF_FMASK
;
593 /* Force 2D tiling if it wasn't set. This may occur when creating
594 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
595 * destination buffer must have an FMASK too. */
596 fmask
.flags
= RADEON_SURF_CLR(fmask
.flags
, MODE
);
597 fmask
.flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
599 if (rscreen
->chip_class
>= SI
) {
600 fmask
.flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
603 switch (nr_samples
) {
607 if (rscreen
->chip_class
<= CAYMAN
) {
615 R600_ERR("Invalid sample count for FMASK allocation.\n");
619 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
620 * This can be fixed by writing a separate FMASK allocator specifically
621 * for R600-R700 asics. */
622 if (rscreen
->chip_class
<= R700
) {
626 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
627 R600_ERR("Got error in surface_init while allocating FMASK.\n");
631 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
633 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
634 if (out
->slice_tile_max
)
635 out
->slice_tile_max
-= 1;
637 out
->tile_mode_index
= fmask
.tiling_index
[0];
638 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
639 out
->bank_height
= fmask
.bankh
;
640 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
641 out
->size
= fmask
.bo_size
;
644 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
645 struct r600_texture
*rtex
)
647 r600_texture_get_fmask_info(rscreen
, rtex
,
648 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
650 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
651 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
654 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
655 struct r600_texture
*rtex
,
656 struct r600_cmask_info
*out
)
658 unsigned cmask_tile_width
= 8;
659 unsigned cmask_tile_height
= 8;
660 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
661 unsigned element_bits
= 4;
662 unsigned cmask_cache_bits
= 1024;
663 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
664 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
666 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
667 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
668 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
669 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
670 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
672 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
673 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
675 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
676 unsigned slice_bytes
=
677 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
679 assert(macro_tile_width
% 128 == 0);
680 assert(macro_tile_height
% 128 == 0);
682 out
->pitch
= pitch_elements
;
683 out
->height
= height
;
684 out
->xalign
= macro_tile_width
;
685 out
->yalign
= macro_tile_height
;
686 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
687 out
->alignment
= MAX2(256, base_align
);
688 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
689 align(slice_bytes
, base_align
);
692 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
693 struct r600_texture
*rtex
,
694 struct r600_cmask_info
*out
)
696 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
697 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
698 unsigned cl_width
, cl_height
;
713 case 16: /* Hawaii */
722 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
724 unsigned width
= align(rtex
->surface
.npix_x
, cl_width
*8);
725 unsigned height
= align(rtex
->surface
.npix_y
, cl_height
*8);
726 unsigned slice_elements
= (width
* height
) / (8*8);
728 /* Each element of CMASK is a nibble. */
729 unsigned slice_bytes
= slice_elements
/ 2;
732 out
->height
= height
;
733 out
->xalign
= cl_width
* 8;
734 out
->yalign
= cl_height
* 8;
735 out
->slice_tile_max
= (width
* height
) / (128*128);
736 if (out
->slice_tile_max
)
737 out
->slice_tile_max
-= 1;
739 out
->alignment
= MAX2(256, base_align
);
740 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
741 align(slice_bytes
, base_align
);
744 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
745 struct r600_texture
*rtex
)
747 if (rscreen
->chip_class
>= SI
) {
748 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
750 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
753 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
754 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
756 if (rscreen
->chip_class
>= SI
)
757 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
759 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
762 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
763 struct r600_texture
*rtex
)
765 if (rtex
->cmask_buffer
)
768 assert(rtex
->cmask
.size
== 0);
770 if (rscreen
->chip_class
>= SI
) {
771 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
773 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
776 rtex
->cmask_buffer
= (struct r600_resource
*)
777 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
778 PIPE_USAGE_DEFAULT
, rtex
->cmask
.size
);
779 if (rtex
->cmask_buffer
== NULL
) {
780 rtex
->cmask
.size
= 0;
784 /* update colorbuffer state bits */
785 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
787 if (rscreen
->chip_class
>= SI
)
788 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
790 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
792 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
795 static unsigned r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
796 struct r600_texture
*rtex
)
798 unsigned cl_width
, cl_height
, width
, height
;
799 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
800 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
802 if (rscreen
->chip_class
<= EVERGREEN
&&
803 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
806 /* HW bug on R6xx. */
807 if (rscreen
->chip_class
== R600
&&
808 (rtex
->surface
.level
[0].npix_x
> 7680 ||
809 rtex
->surface
.level
[0].npix_y
> 7680))
812 /* HTILE is broken with 1D tiling on old kernels and CIK. */
813 if (rscreen
->chip_class
>= CIK
&&
814 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
815 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
818 /* Overalign HTILE on P2 configs to work around GPU hangs in
819 * piglit/depthstencil-render-miplevels 585.
821 * This has been confirmed to help Kabini & Stoney, where the hangs
822 * are always reproducible. I think I have seen the test hang
823 * on Carrizo too, though it was very rare there.
825 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
854 width
= align(rtex
->surface
.npix_x
, cl_width
* 8);
855 height
= align(rtex
->surface
.npix_y
, cl_height
* 8);
857 slice_elements
= (width
* height
) / (8 * 8);
858 slice_bytes
= slice_elements
* 4;
860 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
861 base_align
= num_pipes
* pipe_interleave_bytes
;
863 rtex
->htile
.pitch
= width
;
864 rtex
->htile
.height
= height
;
865 rtex
->htile
.xalign
= cl_width
* 8;
866 rtex
->htile
.yalign
= cl_height
* 8;
868 return (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
869 align(slice_bytes
, base_align
);
872 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
873 struct r600_texture
*rtex
)
875 unsigned htile_size
= r600_texture_get_htile_size(rscreen
, rtex
);
880 rtex
->htile_buffer
= (struct r600_resource
*)
881 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
882 PIPE_USAGE_DEFAULT
, htile_size
);
883 if (rtex
->htile_buffer
== NULL
) {
884 /* this is not a fatal error as we can still keep rendering
885 * without htile buffer */
886 R600_ERR("Failed to create buffer object for htile buffer.\n");
888 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
, 0,
889 htile_size
, 0, R600_COHERENCY_NONE
);
893 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
)
897 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
898 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
899 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
900 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
901 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
902 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
903 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
904 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
905 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
907 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%"PRIu64
", bankw=%u, "
908 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
909 rtex
->surface
.bo_size
, rtex
->surface
.bo_alignment
, rtex
->surface
.bankw
,
910 rtex
->surface
.bankh
, rtex
->surface
.num_banks
, rtex
->surface
.mtilea
,
911 rtex
->surface
.tile_split
, rtex
->surface
.pipe_config
,
912 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
914 if (rtex
->fmask
.size
)
915 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
916 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
917 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
918 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
919 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
921 if (rtex
->cmask
.size
)
922 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch=%u, "
923 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
924 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
925 rtex
->cmask
.pitch
, rtex
->cmask
.height
, rtex
->cmask
.xalign
,
926 rtex
->cmask
.yalign
, rtex
->cmask
.slice_tile_max
);
928 if (rtex
->htile_buffer
)
929 fprintf(f
, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
930 "xalign=%u, yalign=%u\n",
931 rtex
->htile_buffer
->b
.b
.width0
,
932 rtex
->htile_buffer
->buf
->alignment
, rtex
->htile
.pitch
,
933 rtex
->htile
.height
, rtex
->htile
.xalign
, rtex
->htile
.yalign
);
935 if (rtex
->dcc_offset
) {
936 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%"PRIu64
"\n",
937 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
938 rtex
->surface
.dcc_alignment
);
939 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
940 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
941 "fast_clear_size=%"PRIu64
"\n",
942 i
, rtex
->surface
.level
[i
].dcc_enabled
,
943 rtex
->surface
.level
[i
].dcc_offset
,
944 rtex
->surface
.level
[i
].dcc_fast_clear_size
);
947 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
948 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
949 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
950 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
951 i
, rtex
->surface
.level
[i
].offset
,
952 rtex
->surface
.level
[i
].slice_size
,
953 u_minify(rtex
->resource
.b
.b
.width0
, i
),
954 u_minify(rtex
->resource
.b
.b
.height0
, i
),
955 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
956 rtex
->surface
.level
[i
].nblk_x
,
957 rtex
->surface
.level
[i
].nblk_y
,
958 rtex
->surface
.level
[i
].nblk_z
,
959 rtex
->surface
.level
[i
].pitch_bytes
,
960 rtex
->surface
.level
[i
].mode
);
962 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
963 fprintf(f
, " StencilLayout: tilesplit=%u\n",
964 rtex
->surface
.stencil_tile_split
);
965 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
966 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
967 "slice_size=%"PRIu64
", npix_x=%u, "
968 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
969 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
970 i
, rtex
->surface
.stencil_level
[i
].offset
,
971 rtex
->surface
.stencil_level
[i
].slice_size
,
972 u_minify(rtex
->resource
.b
.b
.width0
, i
),
973 u_minify(rtex
->resource
.b
.b
.height0
, i
),
974 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
975 rtex
->surface
.stencil_level
[i
].nblk_x
,
976 rtex
->surface
.stencil_level
[i
].nblk_y
,
977 rtex
->surface
.stencil_level
[i
].nblk_z
,
978 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
979 rtex
->surface
.stencil_level
[i
].mode
);
984 /* Common processing for r600_texture_create and r600_texture_from_handle */
985 static struct r600_texture
*
986 r600_texture_create_object(struct pipe_screen
*screen
,
987 const struct pipe_resource
*base
,
988 unsigned pitch_in_bytes_override
,
990 struct pb_buffer
*buf
,
991 struct radeon_surf
*surface
)
993 struct r600_texture
*rtex
;
994 struct r600_resource
*resource
;
995 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
997 rtex
= CALLOC_STRUCT(r600_texture
);
1001 resource
= &rtex
->resource
;
1002 resource
->b
.b
= *base
;
1003 resource
->b
.vtbl
= &r600_texture_vtbl
;
1004 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1005 resource
->b
.b
.screen
= screen
;
1007 /* don't include stencil-only formats which we don't support for rendering */
1008 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1010 rtex
->surface
= *surface
;
1011 if (r600_setup_surface(screen
, rtex
, pitch_in_bytes_override
, offset
)) {
1016 /* Tiled depth textures utilize the non-displayable tile order.
1017 * This must be done after r600_setup_surface.
1018 * Applies to R600-Cayman. */
1019 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1020 /* Applies to GCN. */
1021 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1023 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1024 * between frames, so the only thing that can enable separate DCC
1025 * with DRI2 is multiple slow clears within a frame.
1027 rtex
->ps_draw_ratio
= 0;
1029 if (rtex
->is_depth
) {
1030 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1031 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1032 rscreen
->chip_class
>= EVERGREEN
) {
1033 rtex
->can_sample_z
= !rtex
->surface
.depth_adjusted
;
1034 rtex
->can_sample_s
= !rtex
->surface
.stencil_adjusted
;
1036 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1037 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1038 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1039 rtex
->can_sample_z
= true;
1042 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1043 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1044 rtex
->db_compatible
= true;
1046 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1047 r600_texture_allocate_htile(rscreen
, rtex
);
1050 if (base
->nr_samples
> 1) {
1052 r600_texture_allocate_fmask(rscreen
, rtex
);
1053 r600_texture_allocate_cmask(rscreen
, rtex
);
1054 rtex
->cmask_buffer
= &rtex
->resource
;
1056 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1062 /* Shared textures must always set up DCC here.
1063 * If it's not present, it will be disabled by
1064 * apply_opaque_metadata later.
1066 if (rtex
->surface
.dcc_size
&&
1067 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1068 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1069 /* Reserve space for the DCC buffer. */
1070 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1071 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1075 /* Now create the backing buffer. */
1077 if (!r600_init_resource(rscreen
, resource
, rtex
->size
,
1078 rtex
->surface
.bo_alignment
)) {
1083 resource
->buf
= buf
;
1084 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1085 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1088 if (rtex
->cmask
.size
) {
1089 /* Initialize the cmask to 0xCC (= compressed state). */
1090 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1091 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1092 0xCCCCCCCC, R600_COHERENCY_NONE
);
1095 /* Initialize DCC only if the texture is not being imported. */
1096 if (!buf
&& rtex
->dcc_offset
) {
1097 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1099 rtex
->surface
.dcc_size
,
1100 0xFFFFFFFF, R600_COHERENCY_NONE
);
1103 /* Initialize the CMASK base register value. */
1104 rtex
->cmask
.base_address_reg
=
1105 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1107 if (rscreen
->debug_flags
& DBG_VM
) {
1108 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1109 rtex
->resource
.gpu_address
,
1110 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1111 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1112 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1115 if (rscreen
->debug_flags
& DBG_TEX
) {
1117 r600_print_texture_info(rtex
, stdout
);
1124 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
1125 const struct pipe_resource
*templ
)
1127 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1128 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1130 /* MSAA resources must be 2D tiled. */
1131 if (templ
->nr_samples
> 1)
1132 return RADEON_SURF_MODE_2D
;
1134 /* Transfer resources should be linear. */
1135 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1136 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1138 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1139 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1140 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1141 (templ
->target
== PIPE_TEXTURE_2D
||
1142 templ
->target
== PIPE_TEXTURE_3D
))
1143 force_tiling
= true;
1145 /* Handle common candidates for the linear mode.
1146 * Compressed textures and DB surfaces must always be tiled.
1148 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
1149 (!util_format_is_depth_or_stencil(templ
->format
) ||
1150 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
1151 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1152 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1154 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1155 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1156 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1158 /* Cursors are linear on SI.
1159 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1160 if (rscreen
->chip_class
>= SI
&&
1161 (templ
->bind
& PIPE_BIND_CURSOR
))
1162 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1164 if (templ
->bind
& PIPE_BIND_LINEAR
)
1165 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1167 /* Textures with a very small height are recommended to be linear. */
1168 if (templ
->target
== PIPE_TEXTURE_1D
||
1169 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1170 templ
->height0
<= 4)
1171 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1173 /* Textures likely to be mapped often. */
1174 if (templ
->usage
== PIPE_USAGE_STAGING
||
1175 templ
->usage
== PIPE_USAGE_STREAM
)
1176 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1179 /* Make small textures 1D tiled. */
1180 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1181 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1182 return RADEON_SURF_MODE_1D
;
1184 /* The allocator will switch to 1D if needed. */
1185 return RADEON_SURF_MODE_2D
;
1188 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1189 const struct pipe_resource
*templ
)
1191 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1192 struct radeon_surf surface
= {0};
1195 r
= r600_init_surface(rscreen
, &surface
, templ
,
1196 r600_choose_tiling(rscreen
, templ
),
1197 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1201 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
1205 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, 0,
1209 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1210 const struct pipe_resource
*templ
,
1211 struct winsys_handle
*whandle
,
1214 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1215 struct pb_buffer
*buf
= NULL
;
1216 unsigned stride
= 0, offset
= 0;
1217 unsigned array_mode
;
1218 struct radeon_surf surface
;
1220 struct radeon_bo_metadata metadata
= {};
1221 struct r600_texture
*rtex
;
1223 /* Support only 2D textures without mipmaps */
1224 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1225 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1228 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1232 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1234 surface
.pipe_config
= metadata
.pipe_config
;
1235 surface
.bankw
= metadata
.bankw
;
1236 surface
.bankh
= metadata
.bankh
;
1237 surface
.tile_split
= metadata
.tile_split
;
1238 surface
.mtilea
= metadata
.mtilea
;
1239 surface
.num_banks
= metadata
.num_banks
;
1241 if (metadata
.macrotile
== RADEON_LAYOUT_TILED
)
1242 array_mode
= RADEON_SURF_MODE_2D
;
1243 else if (metadata
.microtile
== RADEON_LAYOUT_TILED
)
1244 array_mode
= RADEON_SURF_MODE_1D
;
1246 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1248 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, false);
1253 if (metadata
.scanout
)
1254 surface
.flags
|= RADEON_SURF_SCANOUT
;
1256 rtex
= r600_texture_create_object(screen
, templ
, stride
,
1257 offset
, buf
, &surface
);
1261 rtex
->resource
.is_shared
= true;
1262 rtex
->resource
.external_usage
= usage
;
1264 if (rscreen
->apply_opaque_metadata
)
1265 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1267 return &rtex
->resource
.b
.b
;
1270 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1271 struct pipe_resource
*texture
,
1272 struct r600_texture
**staging
)
1274 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1275 struct pipe_resource resource
;
1276 struct r600_texture
**flushed_depth_texture
= staging
?
1277 staging
: &rtex
->flushed_depth_texture
;
1278 enum pipe_format pipe_format
= texture
->format
;
1281 if (rtex
->flushed_depth_texture
)
1282 return true; /* it's ready */
1284 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1285 switch (pipe_format
) {
1286 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1287 /* Save memory by not allocating the S plane. */
1288 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1290 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1291 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1292 /* Save memory bandwidth by not copying the
1293 * stencil part during flush.
1295 * This potentially increases memory bandwidth
1296 * if an application uses both Z and S texturing
1297 * simultaneously (a flushed Z24S8 texture
1298 * would be stored compactly), but how often
1299 * does that really happen?
1301 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1305 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1306 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1308 /* DB->CB copies to an 8bpp surface don't work. */
1309 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1313 resource
.target
= texture
->target
;
1314 resource
.format
= pipe_format
;
1315 resource
.width0
= texture
->width0
;
1316 resource
.height0
= texture
->height0
;
1317 resource
.depth0
= texture
->depth0
;
1318 resource
.array_size
= texture
->array_size
;
1319 resource
.last_level
= texture
->last_level
;
1320 resource
.nr_samples
= texture
->nr_samples
;
1321 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1322 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1323 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1326 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1328 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1329 if (*flushed_depth_texture
== NULL
) {
1330 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1334 (*flushed_depth_texture
)->non_disp_tiling
= false;
1339 * Initialize the pipe_resource descriptor to be of the same size as the box,
1340 * which is supposed to hold a subregion of the texture "orig" at the given
1343 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1344 struct pipe_resource
*orig
,
1345 const struct pipe_box
*box
,
1346 unsigned level
, unsigned flags
)
1348 memset(res
, 0, sizeof(*res
));
1349 res
->format
= orig
->format
;
1350 res
->width0
= box
->width
;
1351 res
->height0
= box
->height
;
1353 res
->array_size
= 1;
1354 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1357 /* We must set the correct texture target and dimensions for a 3D box. */
1358 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1359 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1360 res
->array_size
= box
->depth
;
1362 res
->target
= PIPE_TEXTURE_2D
;
1366 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1367 struct r600_texture
*rtex
,
1368 unsigned transfer_usage
,
1369 const struct pipe_box
*box
)
1371 /* r600g doesn't react to dirty_tex_descriptor_counter */
1372 return rscreen
->chip_class
>= SI
&&
1373 !rtex
->resource
.is_shared
&&
1374 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1375 rtex
->resource
.b
.b
.last_level
== 0 &&
1376 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1377 box
->x
, box
->y
, box
->z
,
1378 box
->width
, box
->height
,
1382 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1383 struct r600_texture
*rtex
)
1385 struct r600_common_screen
*rscreen
= rctx
->screen
;
1387 /* There is no point in discarding depth and tiled buffers. */
1388 assert(!rtex
->is_depth
);
1389 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
);
1391 /* Reallocate the buffer in the same pipe_resource. */
1392 r600_init_resource(rscreen
, &rtex
->resource
, rtex
->size
,
1393 rtex
->surface
.bo_alignment
);
1395 /* Initialize the CMASK base address (needed even without CMASK). */
1396 rtex
->cmask
.base_address_reg
=
1397 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1399 r600_dirty_all_framebuffer_states(rscreen
);
1400 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
1402 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1405 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1406 struct pipe_resource
*texture
,
1409 const struct pipe_box
*box
,
1410 struct pipe_transfer
**ptransfer
)
1412 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1413 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1414 struct r600_transfer
*trans
;
1415 struct r600_resource
*buf
;
1416 unsigned offset
= 0;
1418 bool use_staging_texture
= false;
1420 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1422 /* Depth textures use staging unconditionally. */
1423 if (!rtex
->is_depth
) {
1424 /* Degrade the tile mode if we get too many transfers on APUs.
1425 * On dGPUs, the staging texture is always faster.
1426 * Only count uploads that are at least 4x4 pixels large.
1428 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1430 box
->width
>= 4 && box
->height
>= 4 &&
1431 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1432 bool can_invalidate
=
1433 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1436 r600_degrade_tile_mode_to_linear(rctx
, rtex
,
1440 /* Tiled textures need to be converted into a linear texture for CPU
1441 * access. The staging texture is always linear and is placed in GART.
1443 * Reading from VRAM is slow, always use the staging texture in
1446 * Use the staging texture for uploads if the underlying BO
1449 if (rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
)
1450 use_staging_texture
= true;
1451 else if (usage
& PIPE_TRANSFER_READ
)
1452 use_staging_texture
= (rtex
->resource
.domains
&
1453 RADEON_DOMAIN_VRAM
) != 0;
1454 /* Write & linear only: */
1455 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1456 RADEON_USAGE_READWRITE
) ||
1457 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1458 RADEON_USAGE_READWRITE
)) {
1460 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1462 r600_texture_invalidate_storage(rctx
, rtex
);
1464 use_staging_texture
= true;
1468 trans
= CALLOC_STRUCT(r600_transfer
);
1471 trans
->transfer
.resource
= texture
;
1472 trans
->transfer
.level
= level
;
1473 trans
->transfer
.usage
= usage
;
1474 trans
->transfer
.box
= *box
;
1476 if (rtex
->is_depth
) {
1477 struct r600_texture
*staging_depth
;
1479 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1480 /* MSAA depth buffers need to be converted to single sample buffers.
1482 * Mapping MSAA depth buffers can occur if ReadPixels is called
1483 * with a multisample GLX visual.
1485 * First downsample the depth buffer to a temporary texture,
1486 * then decompress the temporary one to staging.
1488 * Only the region being mapped is transfered.
1490 struct pipe_resource resource
;
1492 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1494 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1495 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1500 if (usage
& PIPE_TRANSFER_READ
) {
1501 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1503 R600_ERR("failed to create a temporary depth texture\n");
1508 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1509 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1510 0, 0, 0, box
->depth
, 0, 0);
1511 pipe_resource_reference(&temp
, NULL
);
1515 /* XXX: only readback the rectangle which is being mapped? */
1516 /* XXX: when discard is true, no need to read back from depth texture */
1517 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1518 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1523 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1525 box
->z
, box
->z
+ box
->depth
- 1,
1528 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1531 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
1532 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
1533 trans
->staging
= (struct r600_resource
*)staging_depth
;
1534 buf
= trans
->staging
;
1535 } else if (use_staging_texture
) {
1536 struct pipe_resource resource
;
1537 struct r600_texture
*staging
;
1539 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1540 R600_RESOURCE_FLAG_TRANSFER
);
1541 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1542 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1544 /* Create the temporary texture. */
1545 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1547 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1551 trans
->staging
= &staging
->resource
;
1552 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
1553 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1555 if (usage
& PIPE_TRANSFER_READ
)
1556 r600_copy_to_staging_texture(ctx
, trans
);
1558 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1560 buf
= trans
->staging
;
1562 /* the resource is mapped directly */
1563 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
1564 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1565 offset
= r600_texture_get_offset(rtex
, level
, box
);
1566 buf
= &rtex
->resource
;
1569 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1570 r600_resource_reference(&trans
->staging
, NULL
);
1575 *ptransfer
= &trans
->transfer
;
1576 return map
+ offset
;
1579 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1580 struct pipe_transfer
* transfer
)
1582 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1583 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1584 struct pipe_resource
*texture
= transfer
->resource
;
1585 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1587 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1588 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1589 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1590 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1591 &rtransfer
->staging
->b
.b
, transfer
->level
,
1594 r600_copy_from_staging_texture(ctx
, rtransfer
);
1598 if (rtransfer
->staging
) {
1599 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1600 r600_resource_reference(&rtransfer
->staging
, NULL
);
1603 /* Heuristic for {upload, draw, upload, draw, ..}:
1605 * Flush the gfx IB if we've allocated too much texture storage.
1607 * The idea is that we don't want to build IBs that use too much
1608 * memory and put pressure on the kernel memory manager and we also
1609 * want to make temporary and invalidated buffers go idle ASAP to
1610 * decrease the total memory usage or make them reusable. The memory
1611 * usage will be slightly higher than given here because of the buffer
1612 * cache in the winsys.
1614 * The result is that the kernel memory manager is never a bottleneck.
1616 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1617 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1618 rctx
->num_alloc_tex_transfer_bytes
= 0;
1624 static const struct u_resource_vtbl r600_texture_vtbl
=
1626 NULL
, /* get_handle */
1627 r600_texture_destroy
, /* resource_destroy */
1628 r600_texture_transfer_map
, /* transfer_map */
1629 u_default_transfer_flush_region
, /* transfer_flush_region */
1630 r600_texture_transfer_unmap
, /* transfer_unmap */
1633 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1634 struct pipe_resource
*texture
,
1635 const struct pipe_surface
*templ
,
1636 unsigned width
, unsigned height
)
1638 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1639 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1644 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1645 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1647 pipe_reference_init(&surface
->base
.reference
, 1);
1648 pipe_resource_reference(&surface
->base
.texture
, texture
);
1649 surface
->base
.context
= pipe
;
1650 surface
->base
.format
= templ
->format
;
1651 surface
->base
.width
= width
;
1652 surface
->base
.height
= height
;
1653 surface
->base
.u
= templ
->u
;
1654 surface
->level_info
= &rtex
->surface
.level
[templ
->u
.tex
.level
];
1655 return &surface
->base
;
1658 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1659 struct pipe_resource
*tex
,
1660 const struct pipe_surface
*templ
)
1662 unsigned level
= templ
->u
.tex
.level
;
1663 unsigned width
= u_minify(tex
->width0
, level
);
1664 unsigned height
= u_minify(tex
->height0
, level
);
1666 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1667 const struct util_format_description
*tex_desc
1668 = util_format_description(tex
->format
);
1669 const struct util_format_description
*templ_desc
1670 = util_format_description(templ
->format
);
1672 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1674 /* Adjust size of surface if and only if the block width or
1675 * height is changed. */
1676 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1677 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1678 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1679 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1681 width
= nblks_x
* templ_desc
->block
.width
;
1682 height
= nblks_y
* templ_desc
->block
.height
;
1686 return r600_create_surface_custom(pipe
, tex
, templ
, width
, height
);
1689 static void r600_surface_destroy(struct pipe_context
*pipe
,
1690 struct pipe_surface
*surface
)
1692 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1693 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1694 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1695 pipe_resource_reference(&surface
->texture
, NULL
);
1699 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1701 const struct util_format_description
*desc
= util_format_description(format
);
1703 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1705 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1706 return V_0280A0_SWAP_STD
;
1708 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1711 switch (desc
->nr_channels
) {
1713 if (HAS_SWIZZLE(0,X
))
1714 return V_0280A0_SWAP_STD
; /* X___ */
1715 else if (HAS_SWIZZLE(3,X
))
1716 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1719 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1720 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1721 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1722 return V_0280A0_SWAP_STD
; /* XY__ */
1723 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1724 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1725 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1727 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
1728 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1729 return V_0280A0_SWAP_ALT
; /* X__Y */
1730 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1731 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1734 if (HAS_SWIZZLE(0,X
))
1735 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
1736 else if (HAS_SWIZZLE(0,Z
))
1737 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1740 /* check the middle channels, the 1st and 4th channel can be NONE */
1741 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
1742 return V_0280A0_SWAP_STD
; /* XYZW */
1743 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
1744 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1745 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
1746 return V_0280A0_SWAP_ALT
; /* ZYXW */
1747 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
1750 return V_0280A0_SWAP_ALT_REV
;
1752 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
1759 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
1761 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
1766 if (rctx
->dcc_stats
[slot
].query_active
)
1767 vi_separate_dcc_stop_query(&rctx
->b
,
1768 rctx
->dcc_stats
[slot
].tex
);
1770 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
1771 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
1772 rctx
->b
.destroy_query(&rctx
->b
,
1773 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
1774 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
1777 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
1781 * Return the per-context slot where DCC statistics queries for the texture live.
1783 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
1784 struct r600_texture
*tex
)
1786 int i
, empty_slot
= -1;
1788 /* Remove zombie textures (textures kept alive by this array only). */
1789 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
1790 if (rctx
->dcc_stats
[i
].tex
&&
1791 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
1792 vi_dcc_clean_up_context_slot(rctx
, i
);
1794 /* Find the texture. */
1795 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
1796 /* Return if found. */
1797 if (rctx
->dcc_stats
[i
].tex
== tex
) {
1798 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
1802 /* Record the first seen empty slot. */
1803 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
1807 /* Not found. Remove the oldest member to make space in the array. */
1808 if (empty_slot
== -1) {
1809 int oldest_slot
= 0;
1811 /* Find the oldest slot. */
1812 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
1813 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
1814 rctx
->dcc_stats
[i
].last_use_timestamp
)
1817 /* Clean up the oldest slot. */
1818 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
1819 empty_slot
= oldest_slot
;
1822 /* Add the texture to the new slot. */
1823 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
1824 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
1828 static struct pipe_query
*
1829 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
1831 struct r600_query_hw
*query
= (struct r600_query_hw
*)
1832 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
1834 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
1835 return (struct pipe_query
*)query
;
1839 * Called when binding a color buffer.
1841 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
1842 struct r600_texture
*tex
)
1844 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1845 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
1847 assert(!rctx
->dcc_stats
[i
].query_active
);
1849 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
1850 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
1852 /* begin or resume the query */
1853 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
1854 rctx
->dcc_stats
[i
].query_active
= true;
1858 * Called when unbinding a color buffer.
1860 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
1861 struct r600_texture
*tex
)
1863 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1864 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
1866 assert(rctx
->dcc_stats
[i
].query_active
);
1867 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
1869 /* pause or end the query */
1870 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
1871 rctx
->dcc_stats
[i
].query_active
= false;
1874 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
1876 /* The minimum number of fullscreen draws per frame that is required
1878 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
1881 /* Called by fast clear. */
1882 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
1883 struct r600_texture
*tex
)
1885 /* The intent is to use this with shared displayable back buffers,
1886 * but it's not strictly limited only to them.
1888 if (!tex
->resource
.is_shared
||
1889 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
1890 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
1891 tex
->surface
.last_level
> 0 ||
1892 !tex
->surface
.dcc_size
)
1895 if (tex
->dcc_offset
)
1896 return; /* already enabled */
1898 /* Enable the DCC stat gathering. */
1899 if (!tex
->dcc_gather_statistics
) {
1900 tex
->dcc_gather_statistics
= true;
1901 vi_separate_dcc_start_query(&rctx
->b
, tex
);
1904 if (!vi_should_enable_separate_dcc(tex
))
1905 return; /* stats show that DCC decompression is too expensive */
1907 assert(tex
->surface
.level
[0].dcc_enabled
);
1908 assert(!tex
->dcc_separate_buffer
);
1910 r600_texture_discard_cmask(rctx
->screen
, tex
);
1912 /* Get a DCC buffer. */
1913 if (tex
->last_dcc_separate_buffer
) {
1914 assert(tex
->dcc_gather_statistics
);
1915 assert(!tex
->dcc_separate_buffer
);
1916 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
1917 tex
->last_dcc_separate_buffer
= NULL
;
1919 tex
->dcc_separate_buffer
= (struct r600_resource
*)
1920 r600_aligned_buffer_create(rctx
->b
.screen
, 0,
1922 tex
->surface
.dcc_size
,
1923 tex
->surface
.dcc_alignment
);
1924 if (!tex
->dcc_separate_buffer
)
1928 /* dcc_offset is the absolute GPUVM address. */
1929 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
1931 /* no need to flag anything since this is called by fast clear that
1932 * flags framebuffer state
1937 * Called by pipe_context::flush_resource, the place where DCC decompression
1940 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
1941 struct r600_texture
*tex
)
1943 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1944 struct pipe_query
*tmp
;
1945 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
1946 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
1947 bool disable
= false;
1949 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
1950 union pipe_query_result result
;
1952 /* Read the results. */
1953 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
1955 r600_query_hw_reset_buffers(rctx
,
1956 (struct r600_query_hw
*)
1957 rctx
->dcc_stats
[i
].ps_stats
[2]);
1959 /* Compute the approximate number of fullscreen draws. */
1960 tex
->ps_draw_ratio
=
1961 result
.pipeline_statistics
.ps_invocations
/
1962 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
1963 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
1965 disable
= tex
->dcc_separate_buffer
&&
1966 !vi_should_enable_separate_dcc(tex
);
1969 tex
->num_slow_clears
= 0;
1971 /* stop the statistics query for ps_stats[0] */
1973 vi_separate_dcc_stop_query(ctx
, tex
);
1975 /* Move the queries in the queue by one. */
1976 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
1977 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
1978 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
1979 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
1981 /* create and start a new query as ps_stats[0] */
1983 vi_separate_dcc_start_query(ctx
, tex
);
1986 assert(!tex
->last_dcc_separate_buffer
);
1987 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
1988 tex
->dcc_separate_buffer
= NULL
;
1989 tex
->dcc_offset
= 0;
1990 /* no need to flag anything since this is called after
1991 * decompression that re-sets framebuffer state
1996 /* FAST COLOR CLEAR */
1998 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
1999 enum pipe_format surface_format
,
2000 const union pipe_color_union
*color
)
2002 union util_color uc
;
2004 memset(&uc
, 0, sizeof(uc
));
2006 if (util_format_is_pure_uint(surface_format
)) {
2007 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2008 } else if (util_format_is_pure_sint(surface_format
)) {
2009 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2011 util_pack_color(color
->f
, surface_format
, &uc
);
2014 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2017 static void vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2018 const union pipe_color_union
*color
,
2019 uint32_t* reset_value
,
2020 bool* clear_words_needed
)
2022 bool values
[4] = {};
2024 bool main_value
= false;
2025 bool extra_value
= false;
2027 const struct util_format_description
*desc
= util_format_description(surface_format
);
2029 *clear_words_needed
= true;
2030 *reset_value
= 0x20202020U
;
2032 /* If we want to clear without needing a fast clear eliminate step, we
2033 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2034 * have two sets of flags, one for the last or first channel(extra) and
2035 * one for the other channels(main).
2038 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2039 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2040 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
2042 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2043 if(r600_translate_colorswap(surface_format
, false) <= 1)
2044 extra_channel
= desc
->nr_channels
- 1;
2050 for (i
= 0; i
< 4; ++i
) {
2051 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2053 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2054 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2057 if (util_format_is_pure_sint(surface_format
)) {
2058 values
[i
] = color
->i
[i
] != 0;
2059 if (color
->i
[i
] != 0 && color
->i
[i
] != INT32_MAX
)
2061 } else if (util_format_is_pure_uint(surface_format
)) {
2062 values
[i
] = color
->ui
[i
] != 0U;
2063 if (color
->ui
[i
] != 0U && color
->ui
[i
] != UINT32_MAX
)
2066 values
[i
] = color
->f
[i
] != 0.0F
;
2067 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2071 if (index
== extra_channel
)
2072 extra_value
= values
[i
];
2074 main_value
= values
[i
];
2077 for (int i
= 0; i
< 4; ++i
)
2078 if (values
[i
] != main_value
&&
2079 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2080 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2081 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2084 *clear_words_needed
= false;
2086 *reset_value
|= 0x80808080U
;
2089 *reset_value
|= 0x40404040U
;
2092 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2093 struct r600_texture
*rtex
,
2094 unsigned level
, unsigned clear_value
)
2096 struct pipe_resource
*dcc_buffer
;
2097 uint64_t dcc_offset
;
2099 assert(rtex
->dcc_offset
&& rtex
->surface
.level
[level
].dcc_enabled
);
2101 if (rtex
->dcc_separate_buffer
) {
2102 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2105 dcc_buffer
= &rtex
->resource
.b
.b
;
2106 dcc_offset
= rtex
->dcc_offset
;
2109 dcc_offset
+= rtex
->surface
.level
[level
].dcc_offset
;
2111 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
,
2112 rtex
->surface
.level
[level
].dcc_fast_clear_size
,
2113 clear_value
, R600_COHERENCY_CB_META
);
2116 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2117 * This allows hitting the MSAA resolve fast path, which requires that both
2118 * src and dst micro tile modes match.
2120 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2121 struct r600_texture
*rtex
)
2123 if (rtex
->resource
.is_shared
||
2124 rtex
->surface
.nsamples
<= 1 ||
2125 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2128 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2129 assert(rtex
->surface
.last_level
== 0);
2131 /* These magic numbers were copied from addrlib. It doesn't use any
2132 * definitions for them either. They are all 2D_TILED_THIN1 modes with
2133 * different bpp and micro tile mode.
2135 if (rscreen
->chip_class
>= CIK
) {
2136 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2137 case 0: /* displayable */
2138 rtex
->surface
.tiling_index
[0] = 10;
2141 rtex
->surface
.tiling_index
[0] = 14;
2143 case 3: /* rotated */
2144 rtex
->surface
.tiling_index
[0] = 28;
2146 default: /* depth, thick */
2147 assert(!"unexpected micro mode");
2151 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2152 case 0: /* displayable */
2153 switch (rtex
->surface
.bpe
) {
2155 rtex
->surface
.tiling_index
[0] = 10;
2158 rtex
->surface
.tiling_index
[0] = 11;
2160 default: /* 32, 64 */
2161 rtex
->surface
.tiling_index
[0] = 12;
2166 switch (rtex
->surface
.bpe
) {
2168 rtex
->surface
.tiling_index
[0] = 14;
2171 rtex
->surface
.tiling_index
[0] = 15;
2174 rtex
->surface
.tiling_index
[0] = 16;
2176 default: /* 64, 128 */
2177 rtex
->surface
.tiling_index
[0] = 17;
2181 default: /* depth, thick */
2182 assert(!"unexpected micro mode");
2187 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2189 p_atomic_inc(&rscreen
->dirty_fb_counter
);
2190 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
2193 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2194 struct pipe_framebuffer_state
*fb
,
2195 struct r600_atom
*fb_state
,
2196 unsigned *buffers
, unsigned *dirty_cbufs
,
2197 const union pipe_color_union
*color
)
2201 /* This function is broken in BE, so just disable this path for now */
2202 #ifdef PIPE_ARCH_BIG_ENDIAN
2206 if (rctx
->render_cond
)
2209 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2210 struct r600_texture
*tex
;
2211 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2216 /* if this colorbuffer is not being cleared */
2217 if (!(*buffers
& clear_bit
))
2220 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2222 /* 128-bit formats are unusupported */
2223 if (util_format_get_blocksizebits(fb
->cbufs
[i
]->format
) > 64) {
2227 /* the clear is allowed if all layers are bound */
2228 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2229 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2233 /* cannot clear mipmapped textures */
2234 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2238 /* only supported on tiled surfaces */
2239 if (tex
->surface
.level
[0].mode
< RADEON_SURF_MODE_1D
) {
2243 /* shared textures can't use fast clear without an explicit flush,
2244 * because there is no way to communicate the clear color among
2247 if (tex
->resource
.is_shared
&&
2248 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2251 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2252 if (tex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2253 rctx
->chip_class
>= CIK
&&
2254 rctx
->screen
->info
.drm_major
== 2 &&
2255 rctx
->screen
->info
.drm_minor
< 38) {
2259 /* Fast clear is the most appropriate place to enable DCC for
2260 * displayable surfaces.
2262 if (rctx
->chip_class
>= VI
&&
2263 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2264 vi_separate_dcc_try_enable(rctx
, tex
);
2266 /* Stoney can't do a CMASK-based clear, so all clears are
2267 * considered to be hypothetically slow clears, which
2268 * is weighed when determining to enable separate DCC.
2270 if (tex
->dcc_gather_statistics
&&
2271 rctx
->family
== CHIP_STONEY
)
2272 tex
->num_slow_clears
++;
2275 /* Try to clear DCC first, otherwise try CMASK. */
2276 if (tex
->dcc_offset
&& tex
->surface
.level
[0].dcc_enabled
) {
2277 uint32_t reset_value
;
2278 bool clear_words_needed
;
2280 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2283 /* We can change the micro tile mode before a full clear. */
2284 if (rctx
->screen
->chip_class
>= SI
)
2285 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2287 vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
, color
, &reset_value
, &clear_words_needed
);
2288 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2290 if (clear_words_needed
)
2291 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2292 tex
->separate_dcc_dirty
= true;
2294 /* Stoney/RB+ doesn't work with CMASK fast clear. */
2295 if (rctx
->family
== CHIP_STONEY
)
2298 /* ensure CMASK is enabled */
2299 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2300 if (tex
->cmask
.size
== 0) {
2304 /* We can change the micro tile mode before a full clear. */
2305 if (rctx
->screen
->chip_class
>= SI
)
2306 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2308 /* Do the fast clear. */
2309 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2310 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2311 R600_COHERENCY_CB_META
);
2313 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2316 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2319 *dirty_cbufs
|= 1 << i
;
2320 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2321 *buffers
&= ~clear_bit
;
2325 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2327 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2328 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2331 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2333 rctx
->b
.create_surface
= r600_create_surface
;
2334 rctx
->b
.surface_destroy
= r600_surface_destroy
;