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radeonsi: disable fast color clear for 1D-tiled surfaces on CIK
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
32 #include <errno.h>
33 #include <inttypes.h>
34
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context *pipe,
37 struct pipe_resource *dst,
38 unsigned dst_level,
39 unsigned dstx, unsigned dsty, unsigned dstz,
40 struct pipe_resource *src,
41 unsigned src_level,
42 const struct pipe_box *src_box)
43 {
44 struct pipe_blit_info blit;
45
46 memset(&blit, 0, sizeof(blit));
47 blit.src.resource = src;
48 blit.src.format = src->format;
49 blit.src.level = src_level;
50 blit.src.box = *src_box;
51 blit.dst.resource = dst;
52 blit.dst.format = dst->format;
53 blit.dst.level = dst_level;
54 blit.dst.box.x = dstx;
55 blit.dst.box.y = dsty;
56 blit.dst.box.z = dstz;
57 blit.dst.box.width = src_box->width;
58 blit.dst.box.height = src_box->height;
59 blit.dst.box.depth = src_box->depth;
60 blit.mask = util_format_get_mask(src->format) &
61 util_format_get_mask(dst->format);
62 blit.filter = PIPE_TEX_FILTER_NEAREST;
63
64 if (blit.mask) {
65 pipe->blit(pipe, &blit);
66 }
67 }
68
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
71 {
72 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
73 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
74 struct pipe_resource *dst = &rtransfer->staging->b.b;
75 struct pipe_resource *src = transfer->resource;
76
77 if (src->nr_samples > 1) {
78 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
79 src, transfer->level, &transfer->box);
80 return;
81 }
82
83 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
84 &transfer->box);
85 }
86
87 /* Copy from a transfer's staging texture to a full GPU one. */
88 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
89 {
90 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
91 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
92 struct pipe_resource *dst = transfer->resource;
93 struct pipe_resource *src = &rtransfer->staging->b.b;
94 struct pipe_box sbox;
95
96 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
97
98 if (dst->nr_samples > 1) {
99 r600_copy_region_with_blit(ctx, dst, transfer->level,
100 transfer->box.x, transfer->box.y, transfer->box.z,
101 src, 0, &sbox);
102 return;
103 }
104
105 rctx->dma_copy(ctx, dst, transfer->level,
106 transfer->box.x, transfer->box.y, transfer->box.z,
107 src, 0, &sbox);
108 }
109
110 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
111 const struct pipe_box *box)
112 {
113 enum pipe_format format = rtex->resource.b.b.format;
114
115 return rtex->surface.level[level].offset +
116 box->z * rtex->surface.level[level].slice_size +
117 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
118 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
119 }
120
121 static int r600_init_surface(struct r600_common_screen *rscreen,
122 struct radeon_surface *surface,
123 const struct pipe_resource *ptex,
124 unsigned array_mode,
125 bool is_flushed_depth)
126 {
127 const struct util_format_description *desc =
128 util_format_description(ptex->format);
129 bool is_depth, is_stencil;
130
131 is_depth = util_format_has_depth(desc);
132 is_stencil = util_format_has_stencil(desc);
133
134 surface->npix_x = ptex->width0;
135 surface->npix_y = ptex->height0;
136 surface->npix_z = ptex->depth0;
137 surface->blk_w = util_format_get_blockwidth(ptex->format);
138 surface->blk_h = util_format_get_blockheight(ptex->format);
139 surface->blk_d = 1;
140 surface->array_size = 1;
141 surface->last_level = ptex->last_level;
142
143 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
144 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
145 surface->bpe = 4; /* stencil is allocated separately on evergreen */
146 } else {
147 surface->bpe = util_format_get_blocksize(ptex->format);
148 /* align byte per element on dword */
149 if (surface->bpe == 3) {
150 surface->bpe = 4;
151 }
152 }
153
154 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
155 surface->flags = RADEON_SURF_SET(array_mode, MODE);
156
157 switch (ptex->target) {
158 case PIPE_TEXTURE_1D:
159 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
160 break;
161 case PIPE_TEXTURE_RECT:
162 case PIPE_TEXTURE_2D:
163 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
164 break;
165 case PIPE_TEXTURE_3D:
166 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
167 break;
168 case PIPE_TEXTURE_1D_ARRAY:
169 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
170 surface->array_size = ptex->array_size;
171 break;
172 case PIPE_TEXTURE_2D_ARRAY:
173 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
174 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
175 surface->array_size = ptex->array_size;
176 break;
177 case PIPE_TEXTURE_CUBE:
178 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
179 break;
180 case PIPE_BUFFER:
181 default:
182 return -EINVAL;
183 }
184 if (ptex->bind & PIPE_BIND_SCANOUT) {
185 surface->flags |= RADEON_SURF_SCANOUT;
186 }
187
188 if (!is_flushed_depth && is_depth) {
189 surface->flags |= RADEON_SURF_ZBUFFER;
190
191 if (is_stencil) {
192 surface->flags |= RADEON_SURF_SBUFFER |
193 RADEON_SURF_HAS_SBUFFER_MIPTREE;
194 }
195 }
196 if (rscreen->chip_class >= SI) {
197 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
198 }
199 return 0;
200 }
201
202 static int r600_setup_surface(struct pipe_screen *screen,
203 struct r600_texture *rtex,
204 unsigned pitch_in_bytes_override)
205 {
206 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
207 int r;
208
209 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
210 if (r) {
211 return r;
212 }
213
214 rtex->size = rtex->surface.bo_size;
215
216 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
217 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
218 * for those
219 */
220 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
221 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
222 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
223 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
224 rtex->surface.stencil_offset =
225 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
226 }
227 }
228 return 0;
229 }
230
231 static boolean r600_texture_get_handle(struct pipe_screen* screen,
232 struct pipe_resource *ptex,
233 struct winsys_handle *whandle)
234 {
235 struct r600_texture *rtex = (struct r600_texture*)ptex;
236 struct r600_resource *resource = &rtex->resource;
237 struct radeon_surface *surface = &rtex->surface;
238 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
239
240 rscreen->ws->buffer_set_tiling(resource->buf,
241 NULL,
242 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
243 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
244 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
245 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
246 surface->bankw, surface->bankh,
247 surface->tile_split,
248 surface->stencil_tile_split,
249 surface->mtilea,
250 surface->level[0].pitch_bytes,
251 (surface->flags & RADEON_SURF_SCANOUT) != 0);
252
253 return rscreen->ws->buffer_get_handle(resource->buf,
254 surface->level[0].pitch_bytes, whandle);
255 }
256
257 static void r600_texture_destroy(struct pipe_screen *screen,
258 struct pipe_resource *ptex)
259 {
260 struct r600_texture *rtex = (struct r600_texture*)ptex;
261 struct r600_resource *resource = &rtex->resource;
262
263 if (rtex->flushed_depth_texture)
264 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
265
266 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
267 if (rtex->cmask_buffer != &rtex->resource) {
268 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
269 }
270 pb_reference(&resource->buf, NULL);
271 FREE(rtex);
272 }
273
274 static const struct u_resource_vtbl r600_texture_vtbl;
275
276 /* The number of samples can be specified independently of the texture. */
277 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
278 struct r600_texture *rtex,
279 unsigned nr_samples,
280 struct r600_fmask_info *out)
281 {
282 /* FMASK is allocated like an ordinary texture. */
283 struct radeon_surface fmask = rtex->surface;
284
285 memset(out, 0, sizeof(*out));
286
287 fmask.bo_alignment = 0;
288 fmask.bo_size = 0;
289 fmask.nsamples = 1;
290 fmask.flags |= RADEON_SURF_FMASK;
291
292 if (rscreen->chip_class >= SI) {
293 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
294 }
295
296 switch (nr_samples) {
297 case 2:
298 case 4:
299 fmask.bpe = 1;
300 if (rscreen->chip_class <= CAYMAN) {
301 fmask.bankh = 4;
302 }
303 break;
304 case 8:
305 fmask.bpe = 4;
306 break;
307 default:
308 R600_ERR("Invalid sample count for FMASK allocation.\n");
309 return;
310 }
311
312 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
313 * This can be fixed by writing a separate FMASK allocator specifically
314 * for R600-R700 asics. */
315 if (rscreen->chip_class <= R700) {
316 fmask.bpe *= 2;
317 }
318
319 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
320 R600_ERR("Got error in surface_init while allocating FMASK.\n");
321 return;
322 }
323
324 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
325
326 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
327 if (out->slice_tile_max)
328 out->slice_tile_max -= 1;
329
330 out->tile_mode_index = fmask.tiling_index[0];
331 out->pitch = fmask.level[0].nblk_x;
332 out->bank_height = fmask.bankh;
333 out->alignment = MAX2(256, fmask.bo_alignment);
334 out->size = fmask.bo_size;
335 }
336
337 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
338 struct r600_texture *rtex)
339 {
340 r600_texture_get_fmask_info(rscreen, rtex,
341 rtex->resource.b.b.nr_samples, &rtex->fmask);
342
343 rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
344 rtex->size = rtex->fmask.offset + rtex->fmask.size;
345 }
346
347 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
348 struct r600_texture *rtex,
349 struct r600_cmask_info *out)
350 {
351 unsigned cmask_tile_width = 8;
352 unsigned cmask_tile_height = 8;
353 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
354 unsigned element_bits = 4;
355 unsigned cmask_cache_bits = 1024;
356 unsigned num_pipes = rscreen->tiling_info.num_channels;
357 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
358
359 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
360 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
361 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
362 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
363 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
364
365 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
366 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
367
368 unsigned base_align = num_pipes * pipe_interleave_bytes;
369 unsigned slice_bytes =
370 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
371
372 assert(macro_tile_width % 128 == 0);
373 assert(macro_tile_height % 128 == 0);
374
375 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
376 out->alignment = MAX2(256, base_align);
377 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
378 }
379
380 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
381 struct r600_texture *rtex,
382 struct r600_cmask_info *out)
383 {
384 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
385 unsigned num_pipes = rscreen->tiling_info.num_channels;
386 unsigned cl_width, cl_height;
387
388 switch (num_pipes) {
389 case 2:
390 cl_width = 32;
391 cl_height = 16;
392 break;
393 case 4:
394 cl_width = 32;
395 cl_height = 32;
396 break;
397 case 8:
398 cl_width = 64;
399 cl_height = 32;
400 break;
401 case 16: /* Hawaii */
402 cl_width = 64;
403 cl_height = 64;
404 break;
405 default:
406 assert(0);
407 return;
408 }
409
410 unsigned base_align = num_pipes * pipe_interleave_bytes;
411
412 unsigned width = align(rtex->surface.npix_x, cl_width*8);
413 unsigned height = align(rtex->surface.npix_y, cl_height*8);
414 unsigned slice_elements = (width * height) / (8*8);
415
416 /* Each element of CMASK is a nibble. */
417 unsigned slice_bytes = slice_elements / 2;
418
419 out->slice_tile_max = (width * height) / (128*128);
420 if (out->slice_tile_max)
421 out->slice_tile_max -= 1;
422
423 out->alignment = MAX2(256, base_align);
424 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
425 }
426
427 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
428 struct r600_texture *rtex)
429 {
430 if (rscreen->chip_class >= SI) {
431 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
432 } else {
433 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
434 }
435
436 rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
437 rtex->size = rtex->cmask.offset + rtex->cmask.size;
438
439 if (rscreen->chip_class >= SI)
440 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
441 else
442 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
443 }
444
445 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
446 struct r600_texture *rtex)
447 {
448 if (rtex->cmask_buffer)
449 return;
450
451 assert(rtex->cmask.size == 0);
452
453 if (rscreen->chip_class >= SI) {
454 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
455 } else {
456 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
457 }
458
459 rtex->cmask_buffer = (struct r600_resource *)
460 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
461 PIPE_USAGE_DEFAULT, rtex->cmask.size);
462 if (rtex->cmask_buffer == NULL) {
463 rtex->cmask.size = 0;
464 return;
465 }
466
467 /* update colorbuffer state bits */
468 rtex->cmask.base_address_reg =
469 r600_resource_va(&rscreen->b, &rtex->cmask_buffer->b.b) >> 8;
470
471 if (rscreen->chip_class >= SI)
472 rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
473 else
474 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
475 }
476
477 static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen,
478 struct r600_texture *rtex)
479 {
480 unsigned cl_width, cl_height, width, height;
481 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
482 unsigned num_pipes = rscreen->tiling_info.num_channels;
483
484 /* HTILE doesn't work with 1D tiling (there's massive corruption
485 * in glxgears). */
486 if (rtex->surface.level[0].mode != RADEON_SURF_MODE_2D)
487 return 0;
488
489 switch (num_pipes) {
490 case 2:
491 cl_width = 32;
492 cl_height = 32;
493 break;
494 case 4:
495 cl_width = 64;
496 cl_height = 32;
497 break;
498 case 8:
499 cl_width = 64;
500 cl_height = 64;
501 break;
502 case 16:
503 cl_width = 128;
504 cl_height = 64;
505 break;
506 default:
507 assert(0);
508 return 0;
509 }
510
511 width = align(rtex->surface.npix_x, cl_width * 8);
512 height = align(rtex->surface.npix_y, cl_height * 8);
513
514 slice_elements = (width * height) / (8 * 8);
515 slice_bytes = slice_elements * 4;
516
517 pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
518 base_align = num_pipes * pipe_interleave_bytes;
519
520 return rtex->surface.array_size * align(slice_bytes, base_align);
521 }
522
523 static unsigned r600_texture_htile_alloc_size(struct r600_common_screen *rscreen,
524 struct r600_texture *rtex)
525 {
526 unsigned sw = rtex->surface.level[0].nblk_x * rtex->surface.blk_w;
527 unsigned sh = rtex->surface.level[0].nblk_y * rtex->surface.blk_h;
528 unsigned npipes = rscreen->info.r600_num_tile_pipes;
529 unsigned htile_size;
530
531 /* XXX also use it for other texture targets */
532 if (rscreen->info.drm_minor < 26 ||
533 rtex->resource.b.b.target != PIPE_TEXTURE_2D ||
534 rtex->surface.level[0].nblk_x < 32 ||
535 rtex->surface.level[0].nblk_y < 32) {
536 return 0;
537 }
538
539 /* this alignment and htile size only apply to linear htile buffer */
540 sw = align(sw, 16 << 3);
541 sh = align(sh, npipes << 3);
542 htile_size = (sw >> 3) * (sh >> 3) * 4;
543 /* must be aligned with 2K * npipes */
544 htile_size = align(htile_size, (2 << 10) * npipes);
545 return htile_size;
546 }
547
548 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
549 struct r600_texture *rtex)
550 {
551 unsigned htile_size;
552 if (rscreen->chip_class >= SI) {
553 htile_size = si_texture_htile_alloc_size(rscreen, rtex);
554 } else {
555 htile_size = r600_texture_htile_alloc_size(rscreen, rtex);
556 }
557
558 if (!htile_size)
559 return;
560
561 /* XXX don't allocate it separately */
562 rtex->htile_buffer = (struct r600_resource*)
563 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
564 PIPE_USAGE_DEFAULT, htile_size);
565 if (rtex->htile_buffer == NULL) {
566 /* this is not a fatal error as we can still keep rendering
567 * without htile buffer */
568 R600_ERR("Failed to create buffer object for htile buffer.\n");
569 } else {
570 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0, htile_size, 0);
571 }
572 }
573
574 /* Common processing for r600_texture_create and r600_texture_from_handle */
575 static struct r600_texture *
576 r600_texture_create_object(struct pipe_screen *screen,
577 const struct pipe_resource *base,
578 unsigned pitch_in_bytes_override,
579 struct pb_buffer *buf,
580 struct radeon_surface *surface)
581 {
582 struct r600_texture *rtex;
583 struct r600_resource *resource;
584 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
585 uint64_t va;
586
587 rtex = CALLOC_STRUCT(r600_texture);
588 if (rtex == NULL)
589 return NULL;
590
591 resource = &rtex->resource;
592 resource->b.b = *base;
593 resource->b.vtbl = &r600_texture_vtbl;
594 pipe_reference_init(&resource->b.b.reference, 1);
595 resource->b.b.screen = screen;
596 rtex->pitch_override = pitch_in_bytes_override;
597
598 /* don't include stencil-only formats which we don't support for rendering */
599 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
600
601 rtex->surface = *surface;
602 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override)) {
603 FREE(rtex);
604 return NULL;
605 }
606
607 /* Tiled depth textures utilize the non-displayable tile order.
608 * This must be done after r600_setup_surface.
609 * Applies to R600-Cayman. */
610 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
611
612 if (rtex->is_depth) {
613 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
614 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
615 (rscreen->debug_flags & DBG_HYPERZ)) {
616
617 r600_texture_allocate_htile(rscreen, rtex);
618 }
619 } else {
620 if (base->nr_samples > 1) {
621 if (!buf) {
622 r600_texture_allocate_fmask(rscreen, rtex);
623 r600_texture_allocate_cmask(rscreen, rtex);
624 rtex->cmask_buffer = &rtex->resource;
625 }
626 if (!rtex->fmask.size || !rtex->cmask.size) {
627 FREE(rtex);
628 return NULL;
629 }
630 }
631 }
632
633 /* Now create the backing buffer. */
634 if (!buf) {
635 if (!r600_init_resource(rscreen, resource, rtex->size,
636 rtex->surface.bo_alignment, FALSE)) {
637 FREE(rtex);
638 return NULL;
639 }
640 } else {
641 resource->buf = buf;
642 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
643 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
644 }
645
646 if (rtex->cmask.size) {
647 /* Initialize the cmask to 0xCC (= compressed state). */
648 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
649 rtex->cmask.offset, rtex->cmask.size, 0xCCCCCCCC);
650 }
651
652 /* Initialize the CMASK base register value. */
653 va = r600_resource_va(&rscreen->b, &rtex->resource.b.b);
654 rtex->cmask.base_address_reg = (va + rtex->cmask.offset) >> 8;
655
656 if (rscreen->debug_flags & DBG_VM) {
657 fprintf(stderr, "VM start=0x%"PRIu64" end=0x%"PRIu64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
658 r600_resource_va(screen, &rtex->resource.b.b),
659 r600_resource_va(screen, &rtex->resource.b.b) + rtex->resource.buf->size,
660 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
661 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
662 }
663
664 if (rscreen->debug_flags & DBG_TEX ||
665 (rtex->resource.b.b.last_level > 0 && rscreen->debug_flags & DBG_TEXMIP)) {
666 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
667 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
668 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
669 rtex->surface.npix_x, rtex->surface.npix_y,
670 rtex->surface.npix_z, rtex->surface.blk_w,
671 rtex->surface.blk_h, rtex->surface.blk_d,
672 rtex->surface.array_size, rtex->surface.last_level,
673 rtex->surface.bpe, rtex->surface.nsamples,
674 rtex->surface.flags, util_format_short_name(base->format));
675 for (int i = 0; i <= rtex->surface.last_level; i++) {
676 printf(" L %i: offset=%"PRIu64", slice_size=%"PRIu64", npix_x=%u, "
677 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
678 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
679 i, rtex->surface.level[i].offset,
680 rtex->surface.level[i].slice_size,
681 u_minify(rtex->resource.b.b.width0, i),
682 u_minify(rtex->resource.b.b.height0, i),
683 u_minify(rtex->resource.b.b.depth0, i),
684 rtex->surface.level[i].nblk_x,
685 rtex->surface.level[i].nblk_y,
686 rtex->surface.level[i].nblk_z,
687 rtex->surface.level[i].pitch_bytes,
688 rtex->surface.level[i].mode);
689 }
690 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
691 for (int i = 0; i <= rtex->surface.last_level; i++) {
692 printf(" S %i: offset=%"PRIu64", slice_size=%"PRIu64", npix_x=%u, "
693 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
694 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
695 i, rtex->surface.stencil_level[i].offset,
696 rtex->surface.stencil_level[i].slice_size,
697 u_minify(rtex->resource.b.b.width0, i),
698 u_minify(rtex->resource.b.b.height0, i),
699 u_minify(rtex->resource.b.b.depth0, i),
700 rtex->surface.stencil_level[i].nblk_x,
701 rtex->surface.stencil_level[i].nblk_y,
702 rtex->surface.stencil_level[i].nblk_z,
703 rtex->surface.stencil_level[i].pitch_bytes,
704 rtex->surface.stencil_level[i].mode);
705 }
706 }
707 }
708 return rtex;
709 }
710
711 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
712 const struct pipe_resource *templ)
713 {
714 const struct util_format_description *desc = util_format_description(templ->format);
715
716 /* MSAA resources must be 2D tiled. */
717 if (templ->nr_samples > 1)
718 return RADEON_SURF_MODE_2D;
719
720 /* Transfer resources should be linear. */
721 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
722 return RADEON_SURF_MODE_LINEAR_ALIGNED;
723
724 /* Handle common candidates for the linear mode.
725 * Compressed textures must always be tiled. */
726 if (!(templ->flags & R600_RESOURCE_FLAG_FORCE_TILING) &&
727 !util_format_is_compressed(templ->format)) {
728 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600-Cayman. */
729 if (rscreen->chip_class <= CAYMAN &&
730 desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
731 return RADEON_SURF_MODE_LINEAR_ALIGNED;
732
733 /* Cursors are linear on SI.
734 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
735 if (rscreen->chip_class >= SI &&
736 (templ->bind & PIPE_BIND_CURSOR))
737 return RADEON_SURF_MODE_LINEAR_ALIGNED;
738
739 if (templ->bind & PIPE_BIND_LINEAR)
740 return RADEON_SURF_MODE_LINEAR_ALIGNED;
741
742 /* Textures with a very small height are recommended to be linear. */
743 if (templ->target == PIPE_TEXTURE_1D ||
744 templ->target == PIPE_TEXTURE_1D_ARRAY ||
745 templ->height0 <= 4)
746 return RADEON_SURF_MODE_LINEAR_ALIGNED;
747
748 /* Textures likely to be mapped often. */
749 if (templ->usage == PIPE_USAGE_STAGING ||
750 templ->usage == PIPE_USAGE_STREAM)
751 return RADEON_SURF_MODE_LINEAR_ALIGNED;
752 }
753
754 /* Make small textures 1D tiled. */
755 if (templ->width0 <= 16 || templ->height0 <= 16)
756 return RADEON_SURF_MODE_1D;
757
758 /* The allocator will switch to 1D if needed. */
759 return RADEON_SURF_MODE_2D;
760 }
761
762 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
763 const struct pipe_resource *templ)
764 {
765 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
766 struct radeon_surface surface = {0};
767 int r;
768
769 r = r600_init_surface(rscreen, &surface, templ,
770 r600_choose_tiling(rscreen, templ),
771 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
772 if (r) {
773 return NULL;
774 }
775 r = rscreen->ws->surface_best(rscreen->ws, &surface);
776 if (r) {
777 return NULL;
778 }
779 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
780 0, NULL, &surface);
781 }
782
783 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
784 const struct pipe_resource *templ,
785 struct winsys_handle *whandle)
786 {
787 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
788 struct pb_buffer *buf = NULL;
789 unsigned stride = 0;
790 unsigned array_mode;
791 enum radeon_bo_layout micro, macro;
792 struct radeon_surface surface;
793 bool scanout;
794 int r;
795
796 /* Support only 2D textures without mipmaps */
797 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
798 templ->depth0 != 1 || templ->last_level != 0)
799 return NULL;
800
801 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
802 if (!buf)
803 return NULL;
804
805 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
806 &surface.bankw, &surface.bankh,
807 &surface.tile_split,
808 &surface.stencil_tile_split,
809 &surface.mtilea, &scanout);
810
811 if (macro == RADEON_LAYOUT_TILED)
812 array_mode = RADEON_SURF_MODE_2D;
813 else if (micro == RADEON_LAYOUT_TILED)
814 array_mode = RADEON_SURF_MODE_1D;
815 else
816 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
817
818 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
819 if (r) {
820 return NULL;
821 }
822
823 if (scanout)
824 surface.flags |= RADEON_SURF_SCANOUT;
825
826 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
827 stride, buf, &surface);
828 }
829
830 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
831 struct pipe_resource *texture,
832 struct r600_texture **staging)
833 {
834 struct r600_texture *rtex = (struct r600_texture*)texture;
835 struct pipe_resource resource;
836 struct r600_texture **flushed_depth_texture = staging ?
837 staging : &rtex->flushed_depth_texture;
838
839 if (!staging && rtex->flushed_depth_texture)
840 return true; /* it's ready */
841
842 resource.target = texture->target;
843 resource.format = texture->format;
844 resource.width0 = texture->width0;
845 resource.height0 = texture->height0;
846 resource.depth0 = texture->depth0;
847 resource.array_size = texture->array_size;
848 resource.last_level = texture->last_level;
849 resource.nr_samples = texture->nr_samples;
850 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
851 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
852 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
853
854 if (staging)
855 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
856
857 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
858 if (*flushed_depth_texture == NULL) {
859 R600_ERR("failed to create temporary texture to hold flushed depth\n");
860 return false;
861 }
862
863 (*flushed_depth_texture)->is_flushing_texture = TRUE;
864 (*flushed_depth_texture)->non_disp_tiling = false;
865 return true;
866 }
867
868 /**
869 * Initialize the pipe_resource descriptor to be of the same size as the box,
870 * which is supposed to hold a subregion of the texture "orig" at the given
871 * mipmap level.
872 */
873 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
874 struct pipe_resource *orig,
875 const struct pipe_box *box,
876 unsigned level, unsigned flags)
877 {
878 memset(res, 0, sizeof(*res));
879 res->format = orig->format;
880 res->width0 = box->width;
881 res->height0 = box->height;
882 res->depth0 = 1;
883 res->array_size = 1;
884 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
885 res->flags = flags;
886
887 /* We must set the correct texture target and dimensions for a 3D box. */
888 if (box->depth > 1 && util_max_layer(orig, level) > 0)
889 res->target = orig->target;
890 else
891 res->target = PIPE_TEXTURE_2D;
892
893 switch (res->target) {
894 case PIPE_TEXTURE_1D_ARRAY:
895 case PIPE_TEXTURE_2D_ARRAY:
896 case PIPE_TEXTURE_CUBE_ARRAY:
897 res->array_size = box->depth;
898 break;
899 case PIPE_TEXTURE_3D:
900 res->depth0 = box->depth;
901 break;
902 default:;
903 }
904 }
905
906 static void *r600_texture_transfer_map(struct pipe_context *ctx,
907 struct pipe_resource *texture,
908 unsigned level,
909 unsigned usage,
910 const struct pipe_box *box,
911 struct pipe_transfer **ptransfer)
912 {
913 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
914 struct r600_texture *rtex = (struct r600_texture*)texture;
915 struct r600_transfer *trans;
916 boolean use_staging_texture = FALSE;
917 struct r600_resource *buf;
918 unsigned offset = 0;
919 char *map;
920
921 /* We cannot map a tiled texture directly because the data is
922 * in a different order, therefore we do detiling using a blit.
923 *
924 * Also, use a temporary in GTT memory for read transfers, as
925 * the CPU is much happier reading out of cached system memory
926 * than uncached VRAM.
927 */
928 if (rtex->surface.level[level].mode >= RADEON_SURF_MODE_1D)
929 use_staging_texture = TRUE;
930
931 /* Untiled buffers in VRAM, which is slow for CPU reads and writes */
932 if (!(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
933 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
934 use_staging_texture = TRUE;
935 }
936
937 /* Use a staging texture for uploads if the underlying BO is busy. */
938 if (!(usage & PIPE_TRANSFER_READ) &&
939 (r600_rings_is_buffer_referenced(rctx, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
940 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
941 use_staging_texture = TRUE;
942 }
943
944 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
945 use_staging_texture = FALSE;
946 }
947
948 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
949 return NULL;
950 }
951
952 trans = CALLOC_STRUCT(r600_transfer);
953 if (trans == NULL)
954 return NULL;
955 trans->transfer.resource = texture;
956 trans->transfer.level = level;
957 trans->transfer.usage = usage;
958 trans->transfer.box = *box;
959
960 if (rtex->is_depth) {
961 struct r600_texture *staging_depth;
962
963 if (rtex->resource.b.b.nr_samples > 1) {
964 /* MSAA depth buffers need to be converted to single sample buffers.
965 *
966 * Mapping MSAA depth buffers can occur if ReadPixels is called
967 * with a multisample GLX visual.
968 *
969 * First downsample the depth buffer to a temporary texture,
970 * then decompress the temporary one to staging.
971 *
972 * Only the region being mapped is transfered.
973 */
974 struct pipe_resource resource;
975
976 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
977
978 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
979 R600_ERR("failed to create temporary texture to hold untiled copy\n");
980 FREE(trans);
981 return NULL;
982 }
983
984 if (usage & PIPE_TRANSFER_READ) {
985 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
986
987 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
988 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
989 0, 0, 0, box->depth, 0, 0);
990 pipe_resource_reference((struct pipe_resource**)&temp, NULL);
991 }
992 }
993 else {
994 /* XXX: only readback the rectangle which is being mapped? */
995 /* XXX: when discard is true, no need to read back from depth texture */
996 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
997 R600_ERR("failed to create temporary texture to hold untiled copy\n");
998 FREE(trans);
999 return NULL;
1000 }
1001
1002 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1003 level, level,
1004 box->z, box->z + box->depth - 1,
1005 0, 0);
1006
1007 offset = r600_texture_get_offset(staging_depth, level, box);
1008 }
1009
1010 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
1011 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
1012 trans->staging = (struct r600_resource*)staging_depth;
1013 } else if (use_staging_texture) {
1014 struct pipe_resource resource;
1015 struct r600_texture *staging;
1016
1017 r600_init_temp_resource_from_box(&resource, texture, box, level,
1018 R600_RESOURCE_FLAG_TRANSFER);
1019
1020 /* Create the temporary texture. */
1021 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1022 if (staging == NULL) {
1023 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1024 FREE(trans);
1025 return NULL;
1026 }
1027 trans->staging = &staging->resource;
1028 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1029 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1030 if (usage & PIPE_TRANSFER_READ) {
1031 r600_copy_to_staging_texture(ctx, trans);
1032 }
1033 } else {
1034 /* the resource is mapped directly */
1035 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1036 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1037 offset = r600_texture_get_offset(rtex, level, box);
1038 }
1039
1040 if (trans->staging) {
1041 buf = trans->staging;
1042 } else {
1043 buf = &rtex->resource;
1044 }
1045
1046 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1047 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1048 FREE(trans);
1049 return NULL;
1050 }
1051
1052 *ptransfer = &trans->transfer;
1053 return map + offset;
1054 }
1055
1056 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1057 struct pipe_transfer* transfer)
1058 {
1059 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1060 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1061 struct radeon_winsys_cs_handle *buf;
1062 struct pipe_resource *texture = transfer->resource;
1063 struct r600_texture *rtex = (struct r600_texture*)texture;
1064
1065 if (rtransfer->staging) {
1066 buf = rtransfer->staging->cs_buf;
1067 } else {
1068 buf = r600_resource(transfer->resource)->cs_buf;
1069 }
1070 rctx->ws->buffer_unmap(buf);
1071
1072 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1073 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1074 ctx->resource_copy_region(ctx, texture, transfer->level,
1075 transfer->box.x, transfer->box.y, transfer->box.z,
1076 &rtransfer->staging->b.b, transfer->level,
1077 &transfer->box);
1078 } else {
1079 r600_copy_from_staging_texture(ctx, rtransfer);
1080 }
1081 }
1082
1083 if (rtransfer->staging)
1084 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1085
1086 FREE(transfer);
1087 }
1088
1089 static const struct u_resource_vtbl r600_texture_vtbl =
1090 {
1091 NULL, /* get_handle */
1092 r600_texture_destroy, /* resource_destroy */
1093 r600_texture_transfer_map, /* transfer_map */
1094 NULL, /* transfer_flush_region */
1095 r600_texture_transfer_unmap, /* transfer_unmap */
1096 NULL /* transfer_inline_write */
1097 };
1098
1099 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1100 struct pipe_resource *texture,
1101 const struct pipe_surface *templ,
1102 unsigned width, unsigned height)
1103 {
1104 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1105
1106 if (surface == NULL)
1107 return NULL;
1108
1109 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1110 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1111
1112 pipe_reference_init(&surface->base.reference, 1);
1113 pipe_resource_reference(&surface->base.texture, texture);
1114 surface->base.context = pipe;
1115 surface->base.format = templ->format;
1116 surface->base.width = width;
1117 surface->base.height = height;
1118 surface->base.u = templ->u;
1119 return &surface->base;
1120 }
1121
1122 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1123 struct pipe_resource *tex,
1124 const struct pipe_surface *templ)
1125 {
1126 unsigned level = templ->u.tex.level;
1127
1128 return r600_create_surface_custom(pipe, tex, templ,
1129 u_minify(tex->width0, level),
1130 u_minify(tex->height0, level));
1131 }
1132
1133 static void r600_surface_destroy(struct pipe_context *pipe,
1134 struct pipe_surface *surface)
1135 {
1136 struct r600_surface *surf = (struct r600_surface*)surface;
1137 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1138 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1139 pipe_resource_reference(&surface->texture, NULL);
1140 FREE(surface);
1141 }
1142
1143 unsigned r600_translate_colorswap(enum pipe_format format)
1144 {
1145 const struct util_format_description *desc = util_format_description(format);
1146
1147 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1148
1149 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1150 return V_0280A0_SWAP_STD;
1151
1152 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1153 return ~0U;
1154
1155 switch (desc->nr_channels) {
1156 case 1:
1157 if (HAS_SWIZZLE(0,X))
1158 return V_0280A0_SWAP_STD; /* X___ */
1159 else if (HAS_SWIZZLE(3,X))
1160 return V_0280A0_SWAP_ALT_REV; /* ___X */
1161 break;
1162 case 2:
1163 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1164 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1165 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1166 return V_0280A0_SWAP_STD; /* XY__ */
1167 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1168 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1169 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1170 return V_0280A0_SWAP_STD_REV; /* YX__ */
1171 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1172 return V_0280A0_SWAP_ALT; /* X__Y */
1173 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1174 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1175 break;
1176 case 3:
1177 if (HAS_SWIZZLE(0,X))
1178 return V_0280A0_SWAP_STD; /* XYZ */
1179 else if (HAS_SWIZZLE(0,Z))
1180 return V_0280A0_SWAP_STD_REV; /* ZYX */
1181 break;
1182 case 4:
1183 /* check the middle channels, the 1st and 4th channel can be NONE */
1184 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
1185 return V_0280A0_SWAP_STD; /* XYZW */
1186 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
1187 return V_0280A0_SWAP_STD_REV; /* WZYX */
1188 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
1189 return V_0280A0_SWAP_ALT; /* ZYXW */
1190 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
1191 return V_0280A0_SWAP_ALT_REV; /* WXYZ */
1192 break;
1193 }
1194 return ~0U;
1195 }
1196
1197 static void evergreen_set_clear_color(struct r600_texture *rtex,
1198 enum pipe_format surface_format,
1199 const union pipe_color_union *color)
1200 {
1201 union util_color uc;
1202
1203 memset(&uc, 0, sizeof(uc));
1204
1205 if (util_format_is_pure_uint(surface_format)) {
1206 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1207 } else if (util_format_is_pure_sint(surface_format)) {
1208 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1209 } else {
1210 util_pack_color(color->f, surface_format, &uc);
1211 }
1212
1213 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1214 }
1215
1216 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1217 struct pipe_framebuffer_state *fb,
1218 struct r600_atom *fb_state,
1219 unsigned *buffers,
1220 const union pipe_color_union *color)
1221 {
1222 int i;
1223
1224 for (i = 0; i < fb->nr_cbufs; i++) {
1225 struct r600_texture *tex;
1226 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1227
1228 if (!fb->cbufs[i])
1229 continue;
1230
1231 /* if this colorbuffer is not being cleared */
1232 if (!(*buffers & clear_bit))
1233 continue;
1234
1235 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1236
1237 /* 128-bit formats are unusupported */
1238 if (util_format_get_blocksizebits(fb->cbufs[i]->format) > 64) {
1239 continue;
1240 }
1241
1242 /* the clear is allowed if all layers are bound */
1243 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1244 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1245 continue;
1246 }
1247
1248 /* cannot clear mipmapped textures */
1249 if (fb->cbufs[i]->texture->last_level != 0) {
1250 continue;
1251 }
1252
1253 /* only supported on tiled surfaces */
1254 if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
1255 continue;
1256 }
1257
1258 /* fast color clear with 1D tiling doesn't work on CIK */
1259 if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
1260 rctx->chip_class >= CIK) {
1261 continue;
1262 }
1263
1264 /* ensure CMASK is enabled */
1265 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1266 if (tex->cmask.size == 0) {
1267 continue;
1268 }
1269
1270 /* Do the fast clear. */
1271 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1272 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1273 tex->cmask.offset, tex->cmask.size, 0);
1274
1275 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1276 fb_state->dirty = true;
1277 *buffers &= ~clear_bit;
1278 }
1279 }
1280
1281 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1282 {
1283 rscreen->b.resource_from_handle = r600_texture_from_handle;
1284 rscreen->b.resource_get_handle = r600_texture_get_handle;
1285 }
1286
1287 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1288 {
1289 rctx->b.create_surface = r600_create_surface;
1290 rctx->b.surface_destroy = r600_surface_destroy;
1291 }