2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
41 const struct pipe_resource
*templ
);
44 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
45 struct r600_texture
*rdst
,
46 unsigned dst_level
, unsigned dstx
,
47 unsigned dsty
, unsigned dstz
,
48 struct r600_texture
*rsrc
,
50 const struct pipe_box
*src_box
)
55 if (util_format_get_blocksizebits(rdst
->resource
.b
.b
.format
) !=
56 util_format_get_blocksizebits(rsrc
->resource
.b
.b
.format
))
59 /* MSAA: Blits don't exist in the real world. */
60 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
61 rdst
->resource
.b
.b
.nr_samples
> 1)
64 /* Depth-stencil surfaces:
65 * When dst is linear, the DB->CB copy preserves HTILE.
66 * When dst is tiled, the 3D path must be used to update HTILE.
68 if (rsrc
->is_depth
|| rdst
->is_depth
)
72 * src: Use the 3D path. DCC decompression is expensive.
73 * dst: Use the 3D path to compress the pixels with DCC.
75 if ((rsrc
->dcc_offset
&& rsrc
->surface
.level
[src_level
].dcc_enabled
) ||
76 (rdst
->dcc_offset
&& rdst
->surface
.level
[dst_level
].dcc_enabled
))
80 * src: Both texture and SDMA paths need decompression. Use SDMA.
81 * dst: If overwriting the whole texture, discard CMASK and use
82 * SDMA. Otherwise, use the 3D path.
84 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
85 /* The CMASK clear is only enabled for the first level. */
86 assert(dst_level
== 0);
87 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
88 dstx
, dsty
, dstz
, src_box
->width
,
89 src_box
->height
, src_box
->depth
))
92 r600_texture_discard_cmask(rctx
->screen
, rdst
);
95 /* All requirements are met. Prepare textures for SDMA. */
96 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
97 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
99 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
100 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
105 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
106 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
107 struct pipe_resource
*dst
,
109 unsigned dstx
, unsigned dsty
, unsigned dstz
,
110 struct pipe_resource
*src
,
112 const struct pipe_box
*src_box
)
114 struct pipe_blit_info blit
;
116 memset(&blit
, 0, sizeof(blit
));
117 blit
.src
.resource
= src
;
118 blit
.src
.format
= src
->format
;
119 blit
.src
.level
= src_level
;
120 blit
.src
.box
= *src_box
;
121 blit
.dst
.resource
= dst
;
122 blit
.dst
.format
= dst
->format
;
123 blit
.dst
.level
= dst_level
;
124 blit
.dst
.box
.x
= dstx
;
125 blit
.dst
.box
.y
= dsty
;
126 blit
.dst
.box
.z
= dstz
;
127 blit
.dst
.box
.width
= src_box
->width
;
128 blit
.dst
.box
.height
= src_box
->height
;
129 blit
.dst
.box
.depth
= src_box
->depth
;
130 blit
.mask
= util_format_get_mask(src
->format
) &
131 util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
142 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
144 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1) {
148 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
160 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1) {
169 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
176 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
180 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
181 const struct pipe_box
*box
)
183 enum pipe_format format
= rtex
->resource
.b
.b
.format
;
185 return rtex
->surface
.level
[level
].offset
+
186 box
->z
* rtex
->surface
.level
[level
].slice_size
+
187 box
->y
/ util_format_get_blockheight(format
) * rtex
->surface
.level
[level
].pitch_bytes
+
188 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
191 static int r600_init_surface(struct r600_common_screen
*rscreen
,
192 struct radeon_surf
*surface
,
193 const struct pipe_resource
*ptex
,
195 bool is_flushed_depth
)
197 const struct util_format_description
*desc
=
198 util_format_description(ptex
->format
);
199 bool is_depth
, is_stencil
;
201 is_depth
= util_format_has_depth(desc
);
202 is_stencil
= util_format_has_stencil(desc
);
204 surface
->npix_x
= ptex
->width0
;
205 surface
->npix_y
= ptex
->height0
;
206 surface
->npix_z
= ptex
->depth0
;
207 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
208 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
210 surface
->array_size
= 1;
211 surface
->last_level
= ptex
->last_level
;
213 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
214 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
215 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
217 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
218 /* align byte per element on dword */
219 if (surface
->bpe
== 3) {
224 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
225 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
227 switch (ptex
->target
) {
228 case PIPE_TEXTURE_1D
:
229 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
231 case PIPE_TEXTURE_RECT
:
232 case PIPE_TEXTURE_2D
:
233 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
235 case PIPE_TEXTURE_3D
:
236 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
238 case PIPE_TEXTURE_1D_ARRAY
:
239 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
240 surface
->array_size
= ptex
->array_size
;
242 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d array */
243 assert(ptex
->array_size
% 6 == 0);
244 case PIPE_TEXTURE_2D_ARRAY
:
245 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
246 surface
->array_size
= ptex
->array_size
;
248 case PIPE_TEXTURE_CUBE
:
249 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
256 if (!is_flushed_depth
&& is_depth
) {
257 surface
->flags
|= RADEON_SURF_ZBUFFER
;
260 surface
->flags
|= RADEON_SURF_SBUFFER
|
261 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
264 if (rscreen
->chip_class
>= SI
) {
265 surface
->flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
268 if (rscreen
->chip_class
>= VI
&&
269 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
270 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
271 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
273 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
274 /* This should catch bugs in gallium users setting incorrect flags. */
275 assert(surface
->nsamples
== 1 &&
276 surface
->array_size
== 1 &&
277 surface
->npix_z
== 1 &&
278 surface
->last_level
== 0 &&
279 !(surface
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
281 surface
->flags
|= RADEON_SURF_SCANOUT
;
286 static int r600_setup_surface(struct pipe_screen
*screen
,
287 struct r600_texture
*rtex
,
288 unsigned pitch_in_bytes_override
,
291 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
295 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
300 rtex
->size
= rtex
->surface
.bo_size
;
302 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
303 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
306 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
307 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
308 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
312 for (i
= 0; i
< ARRAY_SIZE(rtex
->surface
.level
); ++i
)
313 rtex
->surface
.level
[i
].offset
+= offset
;
318 static void r600_texture_init_metadata(struct r600_texture
*rtex
,
319 struct radeon_bo_metadata
*metadata
)
321 struct radeon_surf
*surface
= &rtex
->surface
;
323 memset(metadata
, 0, sizeof(*metadata
));
324 metadata
->microtile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
325 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
326 metadata
->macrotile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
327 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
328 metadata
->pipe_config
= surface
->pipe_config
;
329 metadata
->bankw
= surface
->bankw
;
330 metadata
->bankh
= surface
->bankh
;
331 metadata
->tile_split
= surface
->tile_split
;
332 metadata
->mtilea
= surface
->mtilea
;
333 metadata
->num_banks
= surface
->num_banks
;
334 metadata
->stride
= surface
->level
[0].pitch_bytes
;
335 metadata
->scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
338 static void r600_dirty_all_framebuffer_states(struct r600_common_screen
*rscreen
)
340 p_atomic_inc(&rscreen
->dirty_fb_counter
);
343 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
344 struct r600_texture
*rtex
)
346 struct r600_common_screen
*rscreen
= rctx
->screen
;
347 struct pipe_context
*ctx
= &rctx
->b
;
349 if (ctx
== rscreen
->aux_context
)
350 pipe_mutex_lock(rscreen
->aux_context_lock
);
352 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
353 ctx
->flush(ctx
, NULL
, 0);
355 if (ctx
== rscreen
->aux_context
)
356 pipe_mutex_unlock(rscreen
->aux_context_lock
);
359 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
360 struct r600_texture
*rtex
)
362 if (!rtex
->cmask
.size
)
365 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
368 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
369 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
370 rtex
->dirty_level_mask
= 0;
372 if (rscreen
->chip_class
>= SI
)
373 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
375 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
377 if (rtex
->cmask_buffer
!= &rtex
->resource
)
378 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
380 /* Notify all contexts about the change. */
381 r600_dirty_all_framebuffer_states(rscreen
);
382 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
385 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
387 /* We can't disable DCC if it can be written by another process. */
388 return rtex
->dcc_offset
&&
389 (!rtex
->resource
.is_shared
||
390 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
393 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
394 struct r600_texture
*rtex
)
396 if (!r600_can_disable_dcc(rtex
))
399 assert(rtex
->dcc_separate_buffer
== NULL
);
402 rtex
->dcc_offset
= 0;
404 /* Notify all contexts about the change. */
405 r600_dirty_all_framebuffer_states(rscreen
);
410 * Disable DCC for the texture. (first decompress, then discard metadata).
412 * There is unresolved multi-context synchronization issue between
413 * screen::aux_context and the current context. If applications do this with
414 * multiple contexts, it's already undefined behavior for them and we don't
415 * have to worry about that. The scenario is:
417 * If context 1 disables DCC and context 2 has queued commands that write
418 * to the texture via CB with DCC enabled, and the order of operations is
420 * context 2 queues draw calls rendering to the texture, but doesn't flush
421 * context 1 disables DCC and flushes
422 * context 1 & 2 reset descriptors and FB state
423 * context 2 flushes (new compressed tiles written by the draw calls)
424 * context 1 & 2 read garbage, because DCC is disabled, yet there are
427 * \param rctx the current context if you have one, or rscreen->aux_context
430 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
431 struct r600_texture
*rtex
)
433 struct r600_common_screen
*rscreen
= rctx
->screen
;
435 if (!r600_can_disable_dcc(rtex
))
438 if (&rctx
->b
== rscreen
->aux_context
)
439 pipe_mutex_lock(rscreen
->aux_context_lock
);
441 /* Decompress DCC. */
442 rctx
->decompress_dcc(&rctx
->b
, rtex
);
443 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
445 if (&rctx
->b
== rscreen
->aux_context
)
446 pipe_mutex_unlock(rscreen
->aux_context_lock
);
448 return r600_texture_discard_dcc(rscreen
, rtex
);
451 static void r600_degrade_tile_mode_to_linear(struct r600_common_context
*rctx
,
452 struct r600_texture
*rtex
,
453 bool invalidate_storage
)
455 struct pipe_screen
*screen
= rctx
->b
.screen
;
456 struct r600_texture
*new_tex
;
457 struct pipe_resource templ
= rtex
->resource
.b
.b
;
460 templ
.bind
|= PIPE_BIND_LINEAR
;
462 /* r600g doesn't react to dirty_tex_descriptor_counter */
463 if (rctx
->chip_class
< SI
)
466 if (rtex
->resource
.is_shared
||
467 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
)
470 /* This fails with MSAA, depth, and compressed textures. */
471 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
472 RADEON_SURF_MODE_LINEAR_ALIGNED
)
475 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
479 /* Copy the pixels to the new texture. */
480 if (!invalidate_storage
) {
481 for (i
= 0; i
<= templ
.last_level
; i
++) {
485 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
486 util_max_layer(&templ
, i
) + 1, &box
);
488 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
489 &rtex
->resource
.b
.b
, i
, &box
);
493 r600_texture_discard_cmask(rctx
->screen
, rtex
);
494 r600_texture_discard_dcc(rctx
->screen
, rtex
);
496 /* Replace the structure fields of rtex. */
497 rtex
->resource
.b
.b
.bind
= templ
.bind
;
498 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
499 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
500 rtex
->resource
.domains
= new_tex
->resource
.domains
;
501 rtex
->size
= new_tex
->size
;
502 rtex
->surface
= new_tex
->surface
;
503 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
504 rtex
->cb_color_info
= new_tex
->cb_color_info
;
505 rtex
->cmask
= new_tex
->cmask
; /* needed even without CMASK */
507 assert(!rtex
->htile_buffer
);
508 assert(!rtex
->cmask
.size
);
509 assert(!rtex
->fmask
.size
);
510 assert(!rtex
->dcc_offset
);
511 assert(!rtex
->is_depth
);
513 r600_texture_reference(&new_tex
, NULL
);
515 r600_dirty_all_framebuffer_states(rctx
->screen
);
516 p_atomic_inc(&rctx
->screen
->dirty_tex_descriptor_counter
);
519 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
520 struct pipe_context
*ctx
,
521 struct pipe_resource
*resource
,
522 struct winsys_handle
*whandle
,
525 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
526 struct r600_common_context
*rctx
= (struct r600_common_context
*)
527 (ctx
? ctx
: rscreen
->aux_context
);
528 struct r600_resource
*res
= (struct r600_resource
*)resource
;
529 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
530 struct radeon_bo_metadata metadata
;
531 bool update_metadata
= false;
533 /* This is not supported now, but it might be required for OpenCL
534 * interop in the future.
536 if (resource
->target
!= PIPE_BUFFER
&&
537 (resource
->nr_samples
> 1 || rtex
->is_depth
))
540 if (resource
->target
!= PIPE_BUFFER
) {
541 /* Since shader image stores don't support DCC on VI,
542 * disable it for external clients that want write
545 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
546 if (r600_texture_disable_dcc(rctx
, rtex
))
547 update_metadata
= true;
550 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
551 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
552 /* Eliminate fast clear (both CMASK and DCC) */
553 r600_eliminate_fast_color_clear(rctx
, rtex
);
555 /* Disable CMASK if flush_resource isn't going
558 if (rtex
->cmask
.size
)
559 r600_texture_discard_cmask(rscreen
, rtex
);
563 if (!res
->is_shared
|| update_metadata
) {
564 r600_texture_init_metadata(rtex
, &metadata
);
565 if (rscreen
->query_opaque_metadata
)
566 rscreen
->query_opaque_metadata(rscreen
, rtex
,
569 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
573 if (res
->is_shared
) {
574 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
577 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
578 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
579 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
581 res
->is_shared
= true;
582 res
->external_usage
= usage
;
585 return rscreen
->ws
->buffer_get_handle(res
->buf
,
586 rtex
->surface
.level
[0].pitch_bytes
,
587 rtex
->surface
.level
[0].offset
,
588 rtex
->surface
.level
[0].slice_size
,
592 static void r600_texture_destroy(struct pipe_screen
*screen
,
593 struct pipe_resource
*ptex
)
595 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
596 struct r600_resource
*resource
= &rtex
->resource
;
598 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
600 r600_resource_reference(&rtex
->htile_buffer
, NULL
);
601 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
602 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
604 pb_reference(&resource
->buf
, NULL
);
605 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
606 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
610 static const struct u_resource_vtbl r600_texture_vtbl
;
612 /* The number of samples can be specified independently of the texture. */
613 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
614 struct r600_texture
*rtex
,
616 struct r600_fmask_info
*out
)
618 /* FMASK is allocated like an ordinary texture. */
619 struct radeon_surf fmask
= rtex
->surface
;
621 memset(out
, 0, sizeof(*out
));
623 fmask
.bo_alignment
= 0;
626 fmask
.flags
|= RADEON_SURF_FMASK
;
628 /* Force 2D tiling if it wasn't set. This may occur when creating
629 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
630 * destination buffer must have an FMASK too. */
631 fmask
.flags
= RADEON_SURF_CLR(fmask
.flags
, MODE
);
632 fmask
.flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
634 if (rscreen
->chip_class
>= SI
) {
635 fmask
.flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
638 switch (nr_samples
) {
642 if (rscreen
->chip_class
<= CAYMAN
) {
650 R600_ERR("Invalid sample count for FMASK allocation.\n");
654 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
655 * This can be fixed by writing a separate FMASK allocator specifically
656 * for R600-R700 asics. */
657 if (rscreen
->chip_class
<= R700
) {
661 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
662 R600_ERR("Got error in surface_init while allocating FMASK.\n");
666 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
668 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
669 if (out
->slice_tile_max
)
670 out
->slice_tile_max
-= 1;
672 out
->tile_mode_index
= fmask
.tiling_index
[0];
673 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
674 out
->bank_height
= fmask
.bankh
;
675 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
676 out
->size
= fmask
.bo_size
;
679 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
680 struct r600_texture
*rtex
)
682 r600_texture_get_fmask_info(rscreen
, rtex
,
683 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
685 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
686 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
689 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
690 struct r600_texture
*rtex
,
691 struct r600_cmask_info
*out
)
693 unsigned cmask_tile_width
= 8;
694 unsigned cmask_tile_height
= 8;
695 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
696 unsigned element_bits
= 4;
697 unsigned cmask_cache_bits
= 1024;
698 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
699 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
701 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
702 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
703 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
704 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
705 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
707 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
708 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
710 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
711 unsigned slice_bytes
=
712 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
714 assert(macro_tile_width
% 128 == 0);
715 assert(macro_tile_height
% 128 == 0);
717 out
->pitch
= pitch_elements
;
718 out
->height
= height
;
719 out
->xalign
= macro_tile_width
;
720 out
->yalign
= macro_tile_height
;
721 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
722 out
->alignment
= MAX2(256, base_align
);
723 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
724 align(slice_bytes
, base_align
);
727 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
728 struct r600_texture
*rtex
,
729 struct r600_cmask_info
*out
)
731 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
732 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
733 unsigned cl_width
, cl_height
;
748 case 16: /* Hawaii */
757 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
759 unsigned width
= align(rtex
->surface
.npix_x
, cl_width
*8);
760 unsigned height
= align(rtex
->surface
.npix_y
, cl_height
*8);
761 unsigned slice_elements
= (width
* height
) / (8*8);
763 /* Each element of CMASK is a nibble. */
764 unsigned slice_bytes
= slice_elements
/ 2;
767 out
->height
= height
;
768 out
->xalign
= cl_width
* 8;
769 out
->yalign
= cl_height
* 8;
770 out
->slice_tile_max
= (width
* height
) / (128*128);
771 if (out
->slice_tile_max
)
772 out
->slice_tile_max
-= 1;
774 out
->alignment
= MAX2(256, base_align
);
775 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
776 align(slice_bytes
, base_align
);
779 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
780 struct r600_texture
*rtex
)
782 if (rscreen
->chip_class
>= SI
) {
783 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
785 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
788 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
789 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
791 if (rscreen
->chip_class
>= SI
)
792 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
794 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
797 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
798 struct r600_texture
*rtex
)
800 if (rtex
->cmask_buffer
)
803 assert(rtex
->cmask
.size
== 0);
805 if (rscreen
->chip_class
>= SI
) {
806 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
808 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
811 rtex
->cmask_buffer
= (struct r600_resource
*)
812 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
813 PIPE_USAGE_DEFAULT
, rtex
->cmask
.size
);
814 if (rtex
->cmask_buffer
== NULL
) {
815 rtex
->cmask
.size
= 0;
819 /* update colorbuffer state bits */
820 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
822 if (rscreen
->chip_class
>= SI
)
823 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
825 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
827 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
830 static unsigned r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
831 struct r600_texture
*rtex
)
833 unsigned cl_width
, cl_height
, width
, height
;
834 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
835 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
837 if (rscreen
->chip_class
<= EVERGREEN
&&
838 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
841 /* HW bug on R6xx. */
842 if (rscreen
->chip_class
== R600
&&
843 (rtex
->surface
.level
[0].npix_x
> 7680 ||
844 rtex
->surface
.level
[0].npix_y
> 7680))
847 /* HTILE is broken with 1D tiling on old kernels and CIK. */
848 if (rscreen
->chip_class
>= CIK
&&
849 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
850 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
853 /* Overalign HTILE on P2 configs to work around GPU hangs in
854 * piglit/depthstencil-render-miplevels 585.
856 * This has been confirmed to help Kabini & Stoney, where the hangs
857 * are always reproducible. I think I have seen the test hang
858 * on Carrizo too, though it was very rare there.
860 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
889 width
= align(rtex
->surface
.npix_x
, cl_width
* 8);
890 height
= align(rtex
->surface
.npix_y
, cl_height
* 8);
892 slice_elements
= (width
* height
) / (8 * 8);
893 slice_bytes
= slice_elements
* 4;
895 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
896 base_align
= num_pipes
* pipe_interleave_bytes
;
898 rtex
->htile
.pitch
= width
;
899 rtex
->htile
.height
= height
;
900 rtex
->htile
.xalign
= cl_width
* 8;
901 rtex
->htile
.yalign
= cl_height
* 8;
903 return (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
904 align(slice_bytes
, base_align
);
907 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
908 struct r600_texture
*rtex
)
910 unsigned htile_size
= r600_texture_get_htile_size(rscreen
, rtex
);
915 rtex
->htile_buffer
= (struct r600_resource
*)
916 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
917 PIPE_USAGE_DEFAULT
, htile_size
);
918 if (rtex
->htile_buffer
== NULL
) {
919 /* this is not a fatal error as we can still keep rendering
920 * without htile buffer */
921 R600_ERR("Failed to create buffer object for htile buffer.\n");
923 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
, 0,
924 htile_size
, 0, R600_COHERENCY_NONE
);
928 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
)
932 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
933 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
934 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
935 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
936 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
937 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
938 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
939 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
940 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
942 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%"PRIu64
", bankw=%u, "
943 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
944 rtex
->surface
.bo_size
, rtex
->surface
.bo_alignment
, rtex
->surface
.bankw
,
945 rtex
->surface
.bankh
, rtex
->surface
.num_banks
, rtex
->surface
.mtilea
,
946 rtex
->surface
.tile_split
, rtex
->surface
.pipe_config
,
947 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
949 if (rtex
->fmask
.size
)
950 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
951 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
952 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
953 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
954 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
956 if (rtex
->cmask
.size
)
957 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch=%u, "
958 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
959 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
960 rtex
->cmask
.pitch
, rtex
->cmask
.height
, rtex
->cmask
.xalign
,
961 rtex
->cmask
.yalign
, rtex
->cmask
.slice_tile_max
);
963 if (rtex
->htile_buffer
)
964 fprintf(f
, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
965 "xalign=%u, yalign=%u\n",
966 rtex
->htile_buffer
->b
.b
.width0
,
967 rtex
->htile_buffer
->buf
->alignment
, rtex
->htile
.pitch
,
968 rtex
->htile
.height
, rtex
->htile
.xalign
, rtex
->htile
.yalign
);
970 if (rtex
->dcc_offset
) {
971 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%"PRIu64
"\n",
972 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
973 rtex
->surface
.dcc_alignment
);
974 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
975 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
976 "fast_clear_size=%"PRIu64
"\n",
977 i
, rtex
->surface
.level
[i
].dcc_enabled
,
978 rtex
->surface
.level
[i
].dcc_offset
,
979 rtex
->surface
.level
[i
].dcc_fast_clear_size
);
982 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
983 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
984 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
985 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
986 i
, rtex
->surface
.level
[i
].offset
,
987 rtex
->surface
.level
[i
].slice_size
,
988 u_minify(rtex
->resource
.b
.b
.width0
, i
),
989 u_minify(rtex
->resource
.b
.b
.height0
, i
),
990 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
991 rtex
->surface
.level
[i
].nblk_x
,
992 rtex
->surface
.level
[i
].nblk_y
,
993 rtex
->surface
.level
[i
].nblk_z
,
994 rtex
->surface
.level
[i
].pitch_bytes
,
995 rtex
->surface
.level
[i
].mode
);
997 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
998 fprintf(f
, " StencilLayout: tilesplit=%u\n",
999 rtex
->surface
.stencil_tile_split
);
1000 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
1001 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
1002 "slice_size=%"PRIu64
", npix_x=%u, "
1003 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1004 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
1005 i
, rtex
->surface
.stencil_level
[i
].offset
,
1006 rtex
->surface
.stencil_level
[i
].slice_size
,
1007 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1008 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1009 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1010 rtex
->surface
.stencil_level
[i
].nblk_x
,
1011 rtex
->surface
.stencil_level
[i
].nblk_y
,
1012 rtex
->surface
.stencil_level
[i
].nblk_z
,
1013 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
1014 rtex
->surface
.stencil_level
[i
].mode
);
1019 /* Common processing for r600_texture_create and r600_texture_from_handle */
1020 static struct r600_texture
*
1021 r600_texture_create_object(struct pipe_screen
*screen
,
1022 const struct pipe_resource
*base
,
1023 unsigned pitch_in_bytes_override
,
1025 struct pb_buffer
*buf
,
1026 struct radeon_surf
*surface
)
1028 struct r600_texture
*rtex
;
1029 struct r600_resource
*resource
;
1030 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1032 rtex
= CALLOC_STRUCT(r600_texture
);
1036 resource
= &rtex
->resource
;
1037 resource
->b
.b
= *base
;
1038 resource
->b
.vtbl
= &r600_texture_vtbl
;
1039 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1040 resource
->b
.b
.screen
= screen
;
1042 /* don't include stencil-only formats which we don't support for rendering */
1043 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1045 rtex
->surface
= *surface
;
1046 if (r600_setup_surface(screen
, rtex
, pitch_in_bytes_override
, offset
)) {
1051 /* Tiled depth textures utilize the non-displayable tile order.
1052 * This must be done after r600_setup_surface.
1053 * Applies to R600-Cayman. */
1054 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1055 /* Applies to GCN. */
1056 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1058 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1059 * between frames, so the only thing that can enable separate DCC
1060 * with DRI2 is multiple slow clears within a frame.
1062 rtex
->ps_draw_ratio
= 0;
1064 if (rtex
->is_depth
) {
1065 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1066 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1067 rscreen
->chip_class
>= EVERGREEN
) {
1068 rtex
->can_sample_z
= !rtex
->surface
.depth_adjusted
;
1069 rtex
->can_sample_s
= !rtex
->surface
.stencil_adjusted
;
1071 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1072 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1073 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1074 rtex
->can_sample_z
= true;
1077 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1078 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1079 rtex
->db_compatible
= true;
1081 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1082 r600_texture_allocate_htile(rscreen
, rtex
);
1085 if (base
->nr_samples
> 1) {
1087 r600_texture_allocate_fmask(rscreen
, rtex
);
1088 r600_texture_allocate_cmask(rscreen
, rtex
);
1089 rtex
->cmask_buffer
= &rtex
->resource
;
1091 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1097 /* Shared textures must always set up DCC here.
1098 * If it's not present, it will be disabled by
1099 * apply_opaque_metadata later.
1101 if (rtex
->surface
.dcc_size
&&
1102 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1103 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1104 /* Reserve space for the DCC buffer. */
1105 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1106 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1110 /* Now create the backing buffer. */
1112 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
1113 rtex
->surface
.bo_alignment
);
1115 if (!r600_alloc_resource(rscreen
, resource
)) {
1120 resource
->buf
= buf
;
1121 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1122 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1125 if (rtex
->cmask
.size
) {
1126 /* Initialize the cmask to 0xCC (= compressed state). */
1127 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1128 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1129 0xCCCCCCCC, R600_COHERENCY_NONE
);
1132 /* Initialize DCC only if the texture is not being imported. */
1133 if (!buf
&& rtex
->dcc_offset
) {
1134 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1136 rtex
->surface
.dcc_size
,
1137 0xFFFFFFFF, R600_COHERENCY_NONE
);
1140 /* Initialize the CMASK base register value. */
1141 rtex
->cmask
.base_address_reg
=
1142 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1144 if (rscreen
->debug_flags
& DBG_VM
) {
1145 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1146 rtex
->resource
.gpu_address
,
1147 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1148 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1149 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1152 if (rscreen
->debug_flags
& DBG_TEX
) {
1154 r600_print_texture_info(rtex
, stdout
);
1161 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
1162 const struct pipe_resource
*templ
)
1164 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1165 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1167 /* MSAA resources must be 2D tiled. */
1168 if (templ
->nr_samples
> 1)
1169 return RADEON_SURF_MODE_2D
;
1171 /* Transfer resources should be linear. */
1172 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1173 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1175 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1176 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1177 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1178 (templ
->target
== PIPE_TEXTURE_2D
||
1179 templ
->target
== PIPE_TEXTURE_3D
))
1180 force_tiling
= true;
1182 /* Handle common candidates for the linear mode.
1183 * Compressed textures and DB surfaces must always be tiled.
1185 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
1186 (!util_format_is_depth_or_stencil(templ
->format
) ||
1187 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
1188 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1189 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1191 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1192 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1193 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1195 /* Cursors are linear on SI.
1196 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1197 if (rscreen
->chip_class
>= SI
&&
1198 (templ
->bind
& PIPE_BIND_CURSOR
))
1199 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1201 if (templ
->bind
& PIPE_BIND_LINEAR
)
1202 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1204 /* Textures with a very small height are recommended to be linear. */
1205 if (templ
->target
== PIPE_TEXTURE_1D
||
1206 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1207 templ
->height0
<= 4)
1208 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1210 /* Textures likely to be mapped often. */
1211 if (templ
->usage
== PIPE_USAGE_STAGING
||
1212 templ
->usage
== PIPE_USAGE_STREAM
)
1213 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1216 /* Make small textures 1D tiled. */
1217 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1218 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1219 return RADEON_SURF_MODE_1D
;
1221 /* The allocator will switch to 1D if needed. */
1222 return RADEON_SURF_MODE_2D
;
1225 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1226 const struct pipe_resource
*templ
)
1228 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1229 struct radeon_surf surface
= {0};
1232 r
= r600_init_surface(rscreen
, &surface
, templ
,
1233 r600_choose_tiling(rscreen
, templ
),
1234 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1238 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
1242 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
, 0,
1246 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1247 const struct pipe_resource
*templ
,
1248 struct winsys_handle
*whandle
,
1251 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1252 struct pb_buffer
*buf
= NULL
;
1253 unsigned stride
= 0, offset
= 0;
1254 unsigned array_mode
;
1255 struct radeon_surf surface
;
1257 struct radeon_bo_metadata metadata
= {};
1258 struct r600_texture
*rtex
;
1260 /* Support only 2D textures without mipmaps */
1261 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1262 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1265 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1269 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1271 surface
.pipe_config
= metadata
.pipe_config
;
1272 surface
.bankw
= metadata
.bankw
;
1273 surface
.bankh
= metadata
.bankh
;
1274 surface
.tile_split
= metadata
.tile_split
;
1275 surface
.mtilea
= metadata
.mtilea
;
1276 surface
.num_banks
= metadata
.num_banks
;
1278 if (metadata
.macrotile
== RADEON_LAYOUT_TILED
)
1279 array_mode
= RADEON_SURF_MODE_2D
;
1280 else if (metadata
.microtile
== RADEON_LAYOUT_TILED
)
1281 array_mode
= RADEON_SURF_MODE_1D
;
1283 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1285 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, false);
1290 if (metadata
.scanout
)
1291 surface
.flags
|= RADEON_SURF_SCANOUT
;
1293 rtex
= r600_texture_create_object(screen
, templ
, stride
,
1294 offset
, buf
, &surface
);
1298 rtex
->resource
.is_shared
= true;
1299 rtex
->resource
.external_usage
= usage
;
1301 if (rscreen
->apply_opaque_metadata
)
1302 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1304 return &rtex
->resource
.b
.b
;
1307 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1308 struct pipe_resource
*texture
,
1309 struct r600_texture
**staging
)
1311 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1312 struct pipe_resource resource
;
1313 struct r600_texture
**flushed_depth_texture
= staging
?
1314 staging
: &rtex
->flushed_depth_texture
;
1315 enum pipe_format pipe_format
= texture
->format
;
1318 if (rtex
->flushed_depth_texture
)
1319 return true; /* it's ready */
1321 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1322 switch (pipe_format
) {
1323 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1324 /* Save memory by not allocating the S plane. */
1325 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1327 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1328 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1329 /* Save memory bandwidth by not copying the
1330 * stencil part during flush.
1332 * This potentially increases memory bandwidth
1333 * if an application uses both Z and S texturing
1334 * simultaneously (a flushed Z24S8 texture
1335 * would be stored compactly), but how often
1336 * does that really happen?
1338 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1342 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1343 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1345 /* DB->CB copies to an 8bpp surface don't work. */
1346 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1350 resource
.target
= texture
->target
;
1351 resource
.format
= pipe_format
;
1352 resource
.width0
= texture
->width0
;
1353 resource
.height0
= texture
->height0
;
1354 resource
.depth0
= texture
->depth0
;
1355 resource
.array_size
= texture
->array_size
;
1356 resource
.last_level
= texture
->last_level
;
1357 resource
.nr_samples
= texture
->nr_samples
;
1358 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1359 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1360 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1363 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1365 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1366 if (*flushed_depth_texture
== NULL
) {
1367 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1371 (*flushed_depth_texture
)->non_disp_tiling
= false;
1376 * Initialize the pipe_resource descriptor to be of the same size as the box,
1377 * which is supposed to hold a subregion of the texture "orig" at the given
1380 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1381 struct pipe_resource
*orig
,
1382 const struct pipe_box
*box
,
1383 unsigned level
, unsigned flags
)
1385 memset(res
, 0, sizeof(*res
));
1386 res
->format
= orig
->format
;
1387 res
->width0
= box
->width
;
1388 res
->height0
= box
->height
;
1390 res
->array_size
= 1;
1391 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1394 /* We must set the correct texture target and dimensions for a 3D box. */
1395 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1396 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1397 res
->array_size
= box
->depth
;
1399 res
->target
= PIPE_TEXTURE_2D
;
1403 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1404 struct r600_texture
*rtex
,
1405 unsigned transfer_usage
,
1406 const struct pipe_box
*box
)
1408 /* r600g doesn't react to dirty_tex_descriptor_counter */
1409 return rscreen
->chip_class
>= SI
&&
1410 !rtex
->resource
.is_shared
&&
1411 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1412 rtex
->resource
.b
.b
.last_level
== 0 &&
1413 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1414 box
->x
, box
->y
, box
->z
,
1415 box
->width
, box
->height
,
1419 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1420 struct r600_texture
*rtex
)
1422 struct r600_common_screen
*rscreen
= rctx
->screen
;
1424 /* There is no point in discarding depth and tiled buffers. */
1425 assert(!rtex
->is_depth
);
1426 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
);
1428 /* Reallocate the buffer in the same pipe_resource. */
1429 r600_alloc_resource(rscreen
, &rtex
->resource
);
1431 /* Initialize the CMASK base address (needed even without CMASK). */
1432 rtex
->cmask
.base_address_reg
=
1433 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1435 r600_dirty_all_framebuffer_states(rscreen
);
1436 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
1438 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1441 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1442 struct pipe_resource
*texture
,
1445 const struct pipe_box
*box
,
1446 struct pipe_transfer
**ptransfer
)
1448 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1449 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1450 struct r600_transfer
*trans
;
1451 struct r600_resource
*buf
;
1452 unsigned offset
= 0;
1454 bool use_staging_texture
= false;
1456 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1458 /* Depth textures use staging unconditionally. */
1459 if (!rtex
->is_depth
) {
1460 /* Degrade the tile mode if we get too many transfers on APUs.
1461 * On dGPUs, the staging texture is always faster.
1462 * Only count uploads that are at least 4x4 pixels large.
1464 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1466 box
->width
>= 4 && box
->height
>= 4 &&
1467 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1468 bool can_invalidate
=
1469 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1472 r600_degrade_tile_mode_to_linear(rctx
, rtex
,
1476 /* Tiled textures need to be converted into a linear texture for CPU
1477 * access. The staging texture is always linear and is placed in GART.
1479 * Reading from VRAM is slow, always use the staging texture in
1482 * Use the staging texture for uploads if the underlying BO
1485 if (rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
)
1486 use_staging_texture
= true;
1487 else if (usage
& PIPE_TRANSFER_READ
)
1488 use_staging_texture
= (rtex
->resource
.domains
&
1489 RADEON_DOMAIN_VRAM
) != 0;
1490 /* Write & linear only: */
1491 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1492 RADEON_USAGE_READWRITE
) ||
1493 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1494 RADEON_USAGE_READWRITE
)) {
1496 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1498 r600_texture_invalidate_storage(rctx
, rtex
);
1500 use_staging_texture
= true;
1504 trans
= CALLOC_STRUCT(r600_transfer
);
1507 trans
->transfer
.resource
= texture
;
1508 trans
->transfer
.level
= level
;
1509 trans
->transfer
.usage
= usage
;
1510 trans
->transfer
.box
= *box
;
1512 if (rtex
->is_depth
) {
1513 struct r600_texture
*staging_depth
;
1515 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1516 /* MSAA depth buffers need to be converted to single sample buffers.
1518 * Mapping MSAA depth buffers can occur if ReadPixels is called
1519 * with a multisample GLX visual.
1521 * First downsample the depth buffer to a temporary texture,
1522 * then decompress the temporary one to staging.
1524 * Only the region being mapped is transfered.
1526 struct pipe_resource resource
;
1528 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1530 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1531 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1536 if (usage
& PIPE_TRANSFER_READ
) {
1537 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1539 R600_ERR("failed to create a temporary depth texture\n");
1544 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1545 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1546 0, 0, 0, box
->depth
, 0, 0);
1547 pipe_resource_reference(&temp
, NULL
);
1551 /* XXX: only readback the rectangle which is being mapped? */
1552 /* XXX: when discard is true, no need to read back from depth texture */
1553 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1554 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1559 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1561 box
->z
, box
->z
+ box
->depth
- 1,
1564 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1567 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
1568 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
1569 trans
->staging
= (struct r600_resource
*)staging_depth
;
1570 buf
= trans
->staging
;
1571 } else if (use_staging_texture
) {
1572 struct pipe_resource resource
;
1573 struct r600_texture
*staging
;
1575 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1576 R600_RESOURCE_FLAG_TRANSFER
);
1577 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1578 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1580 /* Create the temporary texture. */
1581 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1583 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1587 trans
->staging
= &staging
->resource
;
1588 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
1589 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1591 if (usage
& PIPE_TRANSFER_READ
)
1592 r600_copy_to_staging_texture(ctx
, trans
);
1594 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1596 buf
= trans
->staging
;
1598 /* the resource is mapped directly */
1599 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
1600 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1601 offset
= r600_texture_get_offset(rtex
, level
, box
);
1602 buf
= &rtex
->resource
;
1605 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1606 r600_resource_reference(&trans
->staging
, NULL
);
1611 *ptransfer
= &trans
->transfer
;
1612 return map
+ offset
;
1615 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1616 struct pipe_transfer
* transfer
)
1618 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1619 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1620 struct pipe_resource
*texture
= transfer
->resource
;
1621 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1623 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1624 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1625 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1626 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1627 &rtransfer
->staging
->b
.b
, transfer
->level
,
1630 r600_copy_from_staging_texture(ctx
, rtransfer
);
1634 if (rtransfer
->staging
) {
1635 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1636 r600_resource_reference(&rtransfer
->staging
, NULL
);
1639 /* Heuristic for {upload, draw, upload, draw, ..}:
1641 * Flush the gfx IB if we've allocated too much texture storage.
1643 * The idea is that we don't want to build IBs that use too much
1644 * memory and put pressure on the kernel memory manager and we also
1645 * want to make temporary and invalidated buffers go idle ASAP to
1646 * decrease the total memory usage or make them reusable. The memory
1647 * usage will be slightly higher than given here because of the buffer
1648 * cache in the winsys.
1650 * The result is that the kernel memory manager is never a bottleneck.
1652 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1653 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1654 rctx
->num_alloc_tex_transfer_bytes
= 0;
1660 static const struct u_resource_vtbl r600_texture_vtbl
=
1662 NULL
, /* get_handle */
1663 r600_texture_destroy
, /* resource_destroy */
1664 r600_texture_transfer_map
, /* transfer_map */
1665 u_default_transfer_flush_region
, /* transfer_flush_region */
1666 r600_texture_transfer_unmap
, /* transfer_unmap */
1669 /* DCC channel type categories within which formats can be reinterpreted
1670 * while keeping the same DCC encoding. The swizzle must also match. */
1671 enum dcc_channel_type
{
1672 dcc_channel_float32
,
1675 dcc_channel_float16
,
1678 dcc_channel_uint_10_10_10_2
,
1681 dcc_channel_incompatible
,
1684 /* Return the type of DCC encoding. */
1685 static enum dcc_channel_type
1686 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1690 /* Find the first non-void channel. */
1691 for (i
= 0; i
< desc
->nr_channels
; i
++)
1692 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1694 if (i
== desc
->nr_channels
)
1695 return dcc_channel_incompatible
;
1697 switch (desc
->channel
[i
].size
) {
1699 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1700 return dcc_channel_float32
;
1701 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1702 return dcc_channel_uint32
;
1703 return dcc_channel_sint32
;
1705 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1706 return dcc_channel_float16
;
1707 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1708 return dcc_channel_uint16
;
1709 return dcc_channel_sint16
;
1711 return dcc_channel_uint_10_10_10_2
;
1713 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1714 return dcc_channel_uint8
;
1715 return dcc_channel_sint8
;
1717 return dcc_channel_incompatible
;
1721 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1722 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1723 enum pipe_format format2
)
1725 const struct util_format_description
*desc1
, *desc2
;
1726 enum dcc_channel_type type1
, type2
;
1729 if (format1
== format2
)
1732 desc1
= util_format_description(format1
);
1733 desc2
= util_format_description(format2
);
1735 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1738 /* Swizzles must be the same. */
1739 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1740 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1741 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1742 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1745 type1
= vi_get_dcc_channel_type(desc1
);
1746 type2
= vi_get_dcc_channel_type(desc2
);
1748 return type1
!= dcc_channel_incompatible
&&
1749 type2
!= dcc_channel_incompatible
&&
1753 void vi_dcc_disable_if_incompatible_format(struct r600_common_context
*rctx
,
1754 struct pipe_resource
*tex
,
1756 enum pipe_format view_format
)
1758 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1760 if (rtex
->dcc_offset
&&
1761 rtex
->surface
.level
[level
].dcc_enabled
&&
1762 !vi_dcc_formats_compatible(tex
->format
, view_format
))
1763 if (!r600_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1764 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1767 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1768 struct pipe_resource
*texture
,
1769 const struct pipe_surface
*templ
,
1770 unsigned width
, unsigned height
)
1772 struct r600_common_context
*rctx
= (struct r600_common_context
*)pipe
;
1773 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1774 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1779 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1780 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1782 pipe_reference_init(&surface
->base
.reference
, 1);
1783 pipe_resource_reference(&surface
->base
.texture
, texture
);
1784 surface
->base
.context
= pipe
;
1785 surface
->base
.format
= templ
->format
;
1786 surface
->base
.width
= width
;
1787 surface
->base
.height
= height
;
1788 surface
->base
.u
= templ
->u
;
1789 surface
->level_info
= &rtex
->surface
.level
[templ
->u
.tex
.level
];
1791 vi_dcc_disable_if_incompatible_format(rctx
, texture
,
1795 return &surface
->base
;
1798 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1799 struct pipe_resource
*tex
,
1800 const struct pipe_surface
*templ
)
1802 unsigned level
= templ
->u
.tex
.level
;
1803 unsigned width
= u_minify(tex
->width0
, level
);
1804 unsigned height
= u_minify(tex
->height0
, level
);
1806 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1807 const struct util_format_description
*tex_desc
1808 = util_format_description(tex
->format
);
1809 const struct util_format_description
*templ_desc
1810 = util_format_description(templ
->format
);
1812 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1814 /* Adjust size of surface if and only if the block width or
1815 * height is changed. */
1816 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1817 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1818 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1819 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1821 width
= nblks_x
* templ_desc
->block
.width
;
1822 height
= nblks_y
* templ_desc
->block
.height
;
1826 return r600_create_surface_custom(pipe
, tex
, templ
, width
, height
);
1829 static void r600_surface_destroy(struct pipe_context
*pipe
,
1830 struct pipe_surface
*surface
)
1832 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1833 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1834 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1835 pipe_resource_reference(&surface
->texture
, NULL
);
1839 static void r600_clear_texture(struct pipe_context
*pipe
,
1840 struct pipe_resource
*tex
,
1842 const struct pipe_box
*box
,
1845 struct pipe_screen
*screen
= pipe
->screen
;
1846 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1847 struct pipe_surface tmpl
= {{0}};
1848 struct pipe_surface
*sf
;
1849 const struct util_format_description
*desc
=
1850 util_format_description(tex
->format
);
1852 tmpl
.format
= tex
->format
;
1853 tmpl
.u
.tex
.first_layer
= box
->z
;
1854 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
1855 tmpl
.u
.tex
.level
= level
;
1856 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
1860 if (rtex
->is_depth
) {
1863 uint8_t stencil
= 0;
1865 /* Depth is always present. */
1866 clear
= PIPE_CLEAR_DEPTH
;
1867 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
1869 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1870 clear
|= PIPE_CLEAR_STENCIL
;
1871 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
1874 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
1876 box
->width
, box
->height
, false);
1878 union pipe_color_union color
;
1880 /* pipe_color_union requires the full vec4 representation. */
1881 if (util_format_is_pure_uint(tex
->format
))
1882 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
1883 else if (util_format_is_pure_sint(tex
->format
))
1884 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
1886 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
1888 if (screen
->is_format_supported(screen
, tex
->format
,
1890 PIPE_BIND_RENDER_TARGET
)) {
1891 pipe
->clear_render_target(pipe
, sf
, &color
,
1893 box
->width
, box
->height
, false);
1895 /* Software fallback - just for R9G9B9E5_FLOAT */
1896 util_clear_render_target(pipe
, sf
, &color
,
1898 box
->width
, box
->height
);
1901 pipe_surface_reference(&sf
, NULL
);
1904 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1906 const struct util_format_description
*desc
= util_format_description(format
);
1908 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1910 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1911 return V_0280A0_SWAP_STD
;
1913 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1916 switch (desc
->nr_channels
) {
1918 if (HAS_SWIZZLE(0,X
))
1919 return V_0280A0_SWAP_STD
; /* X___ */
1920 else if (HAS_SWIZZLE(3,X
))
1921 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1924 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1925 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1926 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1927 return V_0280A0_SWAP_STD
; /* XY__ */
1928 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1929 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1930 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1932 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
1933 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1934 return V_0280A0_SWAP_ALT
; /* X__Y */
1935 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1936 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1939 if (HAS_SWIZZLE(0,X
))
1940 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
1941 else if (HAS_SWIZZLE(0,Z
))
1942 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1945 /* check the middle channels, the 1st and 4th channel can be NONE */
1946 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
1947 return V_0280A0_SWAP_STD
; /* XYZW */
1948 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
1949 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1950 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
1951 return V_0280A0_SWAP_ALT
; /* ZYXW */
1952 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
1955 return V_0280A0_SWAP_ALT_REV
;
1957 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
1964 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
1966 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
1971 if (rctx
->dcc_stats
[slot
].query_active
)
1972 vi_separate_dcc_stop_query(&rctx
->b
,
1973 rctx
->dcc_stats
[slot
].tex
);
1975 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
1976 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
1977 rctx
->b
.destroy_query(&rctx
->b
,
1978 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
1979 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
1982 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
1986 * Return the per-context slot where DCC statistics queries for the texture live.
1988 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
1989 struct r600_texture
*tex
)
1991 int i
, empty_slot
= -1;
1993 /* Remove zombie textures (textures kept alive by this array only). */
1994 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
1995 if (rctx
->dcc_stats
[i
].tex
&&
1996 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
1997 vi_dcc_clean_up_context_slot(rctx
, i
);
1999 /* Find the texture. */
2000 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2001 /* Return if found. */
2002 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2003 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2007 /* Record the first seen empty slot. */
2008 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2012 /* Not found. Remove the oldest member to make space in the array. */
2013 if (empty_slot
== -1) {
2014 int oldest_slot
= 0;
2016 /* Find the oldest slot. */
2017 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2018 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2019 rctx
->dcc_stats
[i
].last_use_timestamp
)
2022 /* Clean up the oldest slot. */
2023 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2024 empty_slot
= oldest_slot
;
2027 /* Add the texture to the new slot. */
2028 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2029 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2033 static struct pipe_query
*
2034 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2036 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2037 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2039 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2040 return (struct pipe_query
*)query
;
2044 * Called when binding a color buffer.
2046 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2047 struct r600_texture
*tex
)
2049 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2050 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2052 assert(!rctx
->dcc_stats
[i
].query_active
);
2054 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2055 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2057 /* begin or resume the query */
2058 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2059 rctx
->dcc_stats
[i
].query_active
= true;
2063 * Called when unbinding a color buffer.
2065 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2066 struct r600_texture
*tex
)
2068 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2069 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2071 assert(rctx
->dcc_stats
[i
].query_active
);
2072 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2074 /* pause or end the query */
2075 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2076 rctx
->dcc_stats
[i
].query_active
= false;
2079 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2081 /* The minimum number of fullscreen draws per frame that is required
2083 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2086 /* Called by fast clear. */
2087 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2088 struct r600_texture
*tex
)
2090 /* The intent is to use this with shared displayable back buffers,
2091 * but it's not strictly limited only to them.
2093 if (!tex
->resource
.is_shared
||
2094 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2095 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2096 tex
->surface
.last_level
> 0 ||
2097 !tex
->surface
.dcc_size
)
2100 if (tex
->dcc_offset
)
2101 return; /* already enabled */
2103 /* Enable the DCC stat gathering. */
2104 if (!tex
->dcc_gather_statistics
) {
2105 tex
->dcc_gather_statistics
= true;
2106 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2109 if (!vi_should_enable_separate_dcc(tex
))
2110 return; /* stats show that DCC decompression is too expensive */
2112 assert(tex
->surface
.level
[0].dcc_enabled
);
2113 assert(!tex
->dcc_separate_buffer
);
2115 r600_texture_discard_cmask(rctx
->screen
, tex
);
2117 /* Get a DCC buffer. */
2118 if (tex
->last_dcc_separate_buffer
) {
2119 assert(tex
->dcc_gather_statistics
);
2120 assert(!tex
->dcc_separate_buffer
);
2121 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2122 tex
->last_dcc_separate_buffer
= NULL
;
2124 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2125 r600_aligned_buffer_create(rctx
->b
.screen
, 0,
2127 tex
->surface
.dcc_size
,
2128 tex
->surface
.dcc_alignment
);
2129 if (!tex
->dcc_separate_buffer
)
2133 /* dcc_offset is the absolute GPUVM address. */
2134 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2136 /* no need to flag anything since this is called by fast clear that
2137 * flags framebuffer state
2142 * Called by pipe_context::flush_resource, the place where DCC decompression
2145 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2146 struct r600_texture
*tex
)
2148 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2149 struct pipe_query
*tmp
;
2150 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2151 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2152 bool disable
= false;
2154 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2155 union pipe_query_result result
;
2157 /* Read the results. */
2158 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2160 r600_query_hw_reset_buffers(rctx
,
2161 (struct r600_query_hw
*)
2162 rctx
->dcc_stats
[i
].ps_stats
[2]);
2164 /* Compute the approximate number of fullscreen draws. */
2165 tex
->ps_draw_ratio
=
2166 result
.pipeline_statistics
.ps_invocations
/
2167 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2168 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2170 disable
= tex
->dcc_separate_buffer
&&
2171 !vi_should_enable_separate_dcc(tex
);
2174 tex
->num_slow_clears
= 0;
2176 /* stop the statistics query for ps_stats[0] */
2178 vi_separate_dcc_stop_query(ctx
, tex
);
2180 /* Move the queries in the queue by one. */
2181 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2182 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2183 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2184 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2186 /* create and start a new query as ps_stats[0] */
2188 vi_separate_dcc_start_query(ctx
, tex
);
2191 assert(!tex
->last_dcc_separate_buffer
);
2192 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2193 tex
->dcc_separate_buffer
= NULL
;
2194 tex
->dcc_offset
= 0;
2195 /* no need to flag anything since this is called after
2196 * decompression that re-sets framebuffer state
2201 /* FAST COLOR CLEAR */
2203 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2204 enum pipe_format surface_format
,
2205 const union pipe_color_union
*color
)
2207 union util_color uc
;
2209 memset(&uc
, 0, sizeof(uc
));
2211 if (util_format_get_blocksizebits(surface_format
) == 128) {
2212 /* DCC fast clear only:
2213 * CLEAR_WORD0 = R = G = B
2216 assert(color
->ui
[0] == color
->ui
[1] &&
2217 color
->ui
[0] == color
->ui
[2]);
2218 uc
.ui
[0] = color
->ui
[0];
2219 uc
.ui
[1] = color
->ui
[3];
2220 } else if (util_format_is_pure_uint(surface_format
)) {
2221 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2222 } else if (util_format_is_pure_sint(surface_format
)) {
2223 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2225 util_pack_color(color
->f
, surface_format
, &uc
);
2228 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2231 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2232 const union pipe_color_union
*color
,
2233 uint32_t* reset_value
,
2234 bool* clear_words_needed
)
2236 bool values
[4] = {};
2238 bool main_value
= false;
2239 bool extra_value
= false;
2241 const struct util_format_description
*desc
= util_format_description(surface_format
);
2243 if (desc
->block
.bits
== 128 &&
2244 (color
->ui
[0] != color
->ui
[1] ||
2245 color
->ui
[0] != color
->ui
[2]))
2248 *clear_words_needed
= true;
2249 *reset_value
= 0x20202020U
;
2251 /* If we want to clear without needing a fast clear eliminate step, we
2252 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2253 * have two sets of flags, one for the last or first channel(extra) and
2254 * one for the other channels(main).
2257 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2258 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2259 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
2261 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2262 if(r600_translate_colorswap(surface_format
, false) <= 1)
2263 extra_channel
= desc
->nr_channels
- 1;
2269 for (i
= 0; i
< 4; ++i
) {
2270 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2272 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2273 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2276 if (desc
->channel
[i
].pure_integer
&&
2277 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2278 /* Use the maximum value for clamping the clear color. */
2279 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2281 values
[i
] = color
->i
[i
] != 0;
2282 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2284 } else if (desc
->channel
[i
].pure_integer
&&
2285 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2286 /* Use the maximum value for clamping the clear color. */
2287 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2289 values
[i
] = color
->ui
[i
] != 0U;
2290 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2293 values
[i
] = color
->f
[i
] != 0.0F
;
2294 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2298 if (index
== extra_channel
)
2299 extra_value
= values
[i
];
2301 main_value
= values
[i
];
2304 for (int i
= 0; i
< 4; ++i
)
2305 if (values
[i
] != main_value
&&
2306 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2307 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2308 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2311 *clear_words_needed
= false;
2313 *reset_value
|= 0x80808080U
;
2316 *reset_value
|= 0x40404040U
;
2320 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2321 struct r600_texture
*rtex
,
2322 unsigned level
, unsigned clear_value
)
2324 struct pipe_resource
*dcc_buffer
;
2325 uint64_t dcc_offset
;
2327 assert(rtex
->dcc_offset
&& rtex
->surface
.level
[level
].dcc_enabled
);
2329 if (rtex
->dcc_separate_buffer
) {
2330 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2333 dcc_buffer
= &rtex
->resource
.b
.b
;
2334 dcc_offset
= rtex
->dcc_offset
;
2337 dcc_offset
+= rtex
->surface
.level
[level
].dcc_offset
;
2339 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
,
2340 rtex
->surface
.level
[level
].dcc_fast_clear_size
,
2341 clear_value
, R600_COHERENCY_CB_META
);
2344 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2345 * This allows hitting the MSAA resolve fast path, which requires that both
2346 * src and dst micro tile modes match.
2348 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2349 struct r600_texture
*rtex
)
2351 if (rtex
->resource
.is_shared
||
2352 rtex
->surface
.nsamples
<= 1 ||
2353 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2356 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2357 assert(rtex
->surface
.last_level
== 0);
2359 /* These magic numbers were copied from addrlib. It doesn't use any
2360 * definitions for them either. They are all 2D_TILED_THIN1 modes with
2361 * different bpp and micro tile mode.
2363 if (rscreen
->chip_class
>= CIK
) {
2364 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2365 case 0: /* displayable */
2366 rtex
->surface
.tiling_index
[0] = 10;
2369 rtex
->surface
.tiling_index
[0] = 14;
2371 case 3: /* rotated */
2372 rtex
->surface
.tiling_index
[0] = 28;
2374 default: /* depth, thick */
2375 assert(!"unexpected micro mode");
2379 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2380 case 0: /* displayable */
2381 switch (rtex
->surface
.bpe
) {
2383 rtex
->surface
.tiling_index
[0] = 10;
2386 rtex
->surface
.tiling_index
[0] = 11;
2388 default: /* 32, 64 */
2389 rtex
->surface
.tiling_index
[0] = 12;
2394 switch (rtex
->surface
.bpe
) {
2396 rtex
->surface
.tiling_index
[0] = 14;
2399 rtex
->surface
.tiling_index
[0] = 15;
2402 rtex
->surface
.tiling_index
[0] = 16;
2404 default: /* 64, 128 */
2405 rtex
->surface
.tiling_index
[0] = 17;
2409 default: /* depth, thick */
2410 assert(!"unexpected micro mode");
2415 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2417 p_atomic_inc(&rscreen
->dirty_fb_counter
);
2418 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
2421 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2422 struct pipe_framebuffer_state
*fb
,
2423 struct r600_atom
*fb_state
,
2424 unsigned *buffers
, unsigned *dirty_cbufs
,
2425 const union pipe_color_union
*color
)
2429 /* This function is broken in BE, so just disable this path for now */
2430 #ifdef PIPE_ARCH_BIG_ENDIAN
2434 if (rctx
->render_cond
)
2437 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2438 struct r600_texture
*tex
;
2439 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2444 /* if this colorbuffer is not being cleared */
2445 if (!(*buffers
& clear_bit
))
2448 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2450 /* the clear is allowed if all layers are bound */
2451 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2452 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2456 /* cannot clear mipmapped textures */
2457 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2461 /* only supported on tiled surfaces */
2462 if (tex
->surface
.level
[0].mode
< RADEON_SURF_MODE_1D
) {
2466 /* shared textures can't use fast clear without an explicit flush,
2467 * because there is no way to communicate the clear color among
2470 if (tex
->resource
.is_shared
&&
2471 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2474 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2475 if (tex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2476 rctx
->chip_class
>= CIK
&&
2477 rctx
->screen
->info
.drm_major
== 2 &&
2478 rctx
->screen
->info
.drm_minor
< 38) {
2482 /* Fast clear is the most appropriate place to enable DCC for
2483 * displayable surfaces.
2485 if (rctx
->chip_class
>= VI
&&
2486 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2487 vi_separate_dcc_try_enable(rctx
, tex
);
2489 /* Stoney can't do a CMASK-based clear, so all clears are
2490 * considered to be hypothetically slow clears, which
2491 * is weighed when determining to enable separate DCC.
2493 if (tex
->dcc_gather_statistics
&&
2494 rctx
->family
== CHIP_STONEY
)
2495 tex
->num_slow_clears
++;
2498 /* Try to clear DCC first, otherwise try CMASK. */
2499 if (tex
->dcc_offset
&& tex
->surface
.level
[0].dcc_enabled
) {
2500 uint32_t reset_value
;
2501 bool clear_words_needed
;
2503 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2506 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2507 color
, &reset_value
,
2508 &clear_words_needed
))
2511 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2513 if (clear_words_needed
)
2514 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2515 tex
->separate_dcc_dirty
= true;
2517 /* 128-bit formats are unusupported */
2518 if (util_format_get_blocksizebits(fb
->cbufs
[i
]->format
) > 64) {
2522 /* Stoney/RB+ doesn't work with CMASK fast clear. */
2523 if (rctx
->family
== CHIP_STONEY
)
2526 /* ensure CMASK is enabled */
2527 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2528 if (tex
->cmask
.size
== 0) {
2532 /* Do the fast clear. */
2533 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2534 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2535 R600_COHERENCY_CB_META
);
2537 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2540 /* We can change the micro tile mode before a full clear. */
2541 if (rctx
->screen
->chip_class
>= SI
)
2542 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2544 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2547 *dirty_cbufs
|= 1 << i
;
2548 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2549 *buffers
&= ~clear_bit
;
2553 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2555 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2556 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2559 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2561 rctx
->b
.create_surface
= r600_create_surface
;
2562 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2563 rctx
->b
.clear_texture
= r600_clear_texture
;