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radeonsi: disable HTILE for 1D-tiled depth-stencil buffers
[mesa.git] / src / gallium / drivers / radeon / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include <errno.h>
32 #include <inttypes.h>
33
34 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
35 static void r600_copy_region_with_blit(struct pipe_context *pipe,
36 struct pipe_resource *dst,
37 unsigned dst_level,
38 unsigned dstx, unsigned dsty, unsigned dstz,
39 struct pipe_resource *src,
40 unsigned src_level,
41 const struct pipe_box *src_box)
42 {
43 struct pipe_blit_info blit;
44
45 memset(&blit, 0, sizeof(blit));
46 blit.src.resource = src;
47 blit.src.format = src->format;
48 blit.src.level = src_level;
49 blit.src.box = *src_box;
50 blit.dst.resource = dst;
51 blit.dst.format = dst->format;
52 blit.dst.level = dst_level;
53 blit.dst.box.x = dstx;
54 blit.dst.box.y = dsty;
55 blit.dst.box.z = dstz;
56 blit.dst.box.width = src_box->width;
57 blit.dst.box.height = src_box->height;
58 blit.dst.box.depth = src_box->depth;
59 blit.mask = util_format_get_mask(src->format) &
60 util_format_get_mask(dst->format);
61 blit.filter = PIPE_TEX_FILTER_NEAREST;
62
63 if (blit.mask) {
64 pipe->blit(pipe, &blit);
65 }
66 }
67
68 /* Copy from a full GPU texture to a transfer's staging one. */
69 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
70 {
71 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
72 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
73 struct pipe_resource *dst = &rtransfer->staging->b.b;
74 struct pipe_resource *src = transfer->resource;
75
76 if (src->nr_samples > 1) {
77 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
78 src, transfer->level, &transfer->box);
79 return;
80 }
81
82 if (!rctx->dma_copy(ctx, dst, 0, 0, 0, 0,
83 src, transfer->level,
84 &transfer->box)) {
85 ctx->resource_copy_region(ctx, dst, 0, 0, 0, 0,
86 src, transfer->level, &transfer->box);
87 }
88 }
89
90 /* Copy from a transfer's staging texture to a full GPU one. */
91 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
92 {
93 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
94 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
95 struct pipe_resource *dst = transfer->resource;
96 struct pipe_resource *src = &rtransfer->staging->b.b;
97 struct pipe_box sbox;
98
99 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
100
101 if (dst->nr_samples > 1) {
102 r600_copy_region_with_blit(ctx, dst, transfer->level,
103 transfer->box.x, transfer->box.y, transfer->box.z,
104 src, 0, &sbox);
105 return;
106 }
107
108 if (!rctx->dma_copy(ctx, dst, transfer->level,
109 transfer->box.x, transfer->box.y, transfer->box.z,
110 src, 0, &sbox)) {
111 ctx->resource_copy_region(ctx, dst, transfer->level,
112 transfer->box.x, transfer->box.y, transfer->box.z,
113 src, 0, &sbox);
114 }
115 }
116
117 static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
118 const struct pipe_box *box)
119 {
120 enum pipe_format format = rtex->resource.b.b.format;
121
122 return rtex->surface.level[level].offset +
123 box->z * rtex->surface.level[level].slice_size +
124 box->y / util_format_get_blockheight(format) * rtex->surface.level[level].pitch_bytes +
125 box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
126 }
127
128 static int r600_init_surface(struct r600_common_screen *rscreen,
129 struct radeon_surface *surface,
130 const struct pipe_resource *ptex,
131 unsigned array_mode,
132 bool is_flushed_depth)
133 {
134 const struct util_format_description *desc =
135 util_format_description(ptex->format);
136 bool is_depth, is_stencil;
137
138 is_depth = util_format_has_depth(desc);
139 is_stencil = util_format_has_stencil(desc);
140
141 surface->npix_x = ptex->width0;
142 surface->npix_y = ptex->height0;
143 surface->npix_z = ptex->depth0;
144 surface->blk_w = util_format_get_blockwidth(ptex->format);
145 surface->blk_h = util_format_get_blockheight(ptex->format);
146 surface->blk_d = 1;
147 surface->array_size = 1;
148 surface->last_level = ptex->last_level;
149
150 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
151 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
152 surface->bpe = 4; /* stencil is allocated separately on evergreen */
153 } else {
154 surface->bpe = util_format_get_blocksize(ptex->format);
155 /* align byte per element on dword */
156 if (surface->bpe == 3) {
157 surface->bpe = 4;
158 }
159 }
160
161 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
162 surface->flags = RADEON_SURF_SET(array_mode, MODE);
163
164 switch (ptex->target) {
165 case PIPE_TEXTURE_1D:
166 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
167 break;
168 case PIPE_TEXTURE_RECT:
169 case PIPE_TEXTURE_2D:
170 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
171 break;
172 case PIPE_TEXTURE_3D:
173 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
174 break;
175 case PIPE_TEXTURE_1D_ARRAY:
176 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
177 surface->array_size = ptex->array_size;
178 break;
179 case PIPE_TEXTURE_2D_ARRAY:
180 case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
181 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
182 surface->array_size = ptex->array_size;
183 break;
184 case PIPE_TEXTURE_CUBE:
185 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
186 break;
187 case PIPE_BUFFER:
188 default:
189 return -EINVAL;
190 }
191 if (ptex->bind & PIPE_BIND_SCANOUT) {
192 surface->flags |= RADEON_SURF_SCANOUT;
193 }
194
195 if (!is_flushed_depth && is_depth) {
196 surface->flags |= RADEON_SURF_ZBUFFER;
197
198 if (is_stencil) {
199 surface->flags |= RADEON_SURF_SBUFFER |
200 RADEON_SURF_HAS_SBUFFER_MIPTREE;
201 }
202 }
203 if (rscreen->chip_class >= SI) {
204 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
205 }
206 return 0;
207 }
208
209 static int r600_setup_surface(struct pipe_screen *screen,
210 struct r600_texture *rtex,
211 unsigned pitch_in_bytes_override)
212 {
213 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
214 int r;
215
216 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
217 if (r) {
218 return r;
219 }
220
221 rtex->size = rtex->surface.bo_size;
222
223 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
224 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
225 * for those
226 */
227 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
228 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
229 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
230 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
231 rtex->surface.stencil_offset =
232 rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
233 }
234 }
235 return 0;
236 }
237
238 static boolean r600_texture_get_handle(struct pipe_screen* screen,
239 struct pipe_resource *ptex,
240 struct winsys_handle *whandle)
241 {
242 struct r600_texture *rtex = (struct r600_texture*)ptex;
243 struct r600_resource *resource = &rtex->resource;
244 struct radeon_surface *surface = &rtex->surface;
245 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
246
247 rscreen->ws->buffer_set_tiling(resource->buf,
248 NULL,
249 surface->level[0].mode >= RADEON_SURF_MODE_1D ?
250 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
251 surface->level[0].mode >= RADEON_SURF_MODE_2D ?
252 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
253 surface->bankw, surface->bankh,
254 surface->tile_split,
255 surface->stencil_tile_split,
256 surface->mtilea,
257 surface->level[0].pitch_bytes,
258 (surface->flags & RADEON_SURF_SCANOUT) != 0);
259
260 return rscreen->ws->buffer_get_handle(resource->buf,
261 surface->level[0].pitch_bytes, whandle);
262 }
263
264 static void r600_texture_destroy(struct pipe_screen *screen,
265 struct pipe_resource *ptex)
266 {
267 struct r600_texture *rtex = (struct r600_texture*)ptex;
268 struct r600_resource *resource = &rtex->resource;
269
270 if (rtex->flushed_depth_texture)
271 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
272
273 pipe_resource_reference((struct pipe_resource**)&rtex->htile_buffer, NULL);
274 if (rtex->cmask_buffer != &rtex->resource) {
275 pipe_resource_reference((struct pipe_resource**)&rtex->cmask_buffer, NULL);
276 }
277 pb_reference(&resource->buf, NULL);
278 FREE(rtex);
279 }
280
281 static const struct u_resource_vtbl r600_texture_vtbl;
282
283 /* The number of samples can be specified independently of the texture. */
284 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
285 struct r600_texture *rtex,
286 unsigned nr_samples,
287 struct r600_fmask_info *out)
288 {
289 /* FMASK is allocated like an ordinary texture. */
290 struct radeon_surface fmask = rtex->surface;
291
292 memset(out, 0, sizeof(*out));
293
294 fmask.bo_alignment = 0;
295 fmask.bo_size = 0;
296 fmask.nsamples = 1;
297 fmask.flags |= RADEON_SURF_FMASK;
298
299 if (rscreen->chip_class >= SI) {
300 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
301 }
302
303 switch (nr_samples) {
304 case 2:
305 case 4:
306 fmask.bpe = 1;
307 if (rscreen->chip_class <= CAYMAN) {
308 fmask.bankh = 4;
309 }
310 break;
311 case 8:
312 fmask.bpe = 4;
313 break;
314 default:
315 R600_ERR("Invalid sample count for FMASK allocation.\n");
316 return;
317 }
318
319 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
320 * This can be fixed by writing a separate FMASK allocator specifically
321 * for R600-R700 asics. */
322 if (rscreen->chip_class <= R700) {
323 fmask.bpe *= 2;
324 }
325
326 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
327 R600_ERR("Got error in surface_init while allocating FMASK.\n");
328 return;
329 }
330
331 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
332
333 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
334 if (out->slice_tile_max)
335 out->slice_tile_max -= 1;
336
337 out->tile_mode_index = fmask.tiling_index[0];
338 out->pitch = fmask.level[0].nblk_x;
339 out->bank_height = fmask.bankh;
340 out->alignment = MAX2(256, fmask.bo_alignment);
341 out->size = fmask.bo_size;
342 }
343
344 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
345 struct r600_texture *rtex)
346 {
347 r600_texture_get_fmask_info(rscreen, rtex,
348 rtex->resource.b.b.nr_samples, &rtex->fmask);
349
350 rtex->fmask.offset = align(rtex->size, rtex->fmask.alignment);
351 rtex->size = rtex->fmask.offset + rtex->fmask.size;
352 }
353
354 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
355 struct r600_texture *rtex,
356 struct r600_cmask_info *out)
357 {
358 unsigned cmask_tile_width = 8;
359 unsigned cmask_tile_height = 8;
360 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
361 unsigned element_bits = 4;
362 unsigned cmask_cache_bits = 1024;
363 unsigned num_pipes = rscreen->tiling_info.num_channels;
364 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
365
366 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
367 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
368 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
369 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
370 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
371
372 unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
373 unsigned height = align(rtex->surface.npix_y, macro_tile_height);
374
375 unsigned base_align = num_pipes * pipe_interleave_bytes;
376 unsigned slice_bytes =
377 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
378
379 assert(macro_tile_width % 128 == 0);
380 assert(macro_tile_height % 128 == 0);
381
382 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
383 out->alignment = MAX2(256, base_align);
384 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
385 }
386
387 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
388 struct r600_texture *rtex,
389 struct r600_cmask_info *out)
390 {
391 unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
392 unsigned num_pipes = rscreen->tiling_info.num_channels;
393 unsigned cl_width, cl_height;
394
395 switch (num_pipes) {
396 case 2:
397 cl_width = 32;
398 cl_height = 16;
399 break;
400 case 4:
401 cl_width = 32;
402 cl_height = 32;
403 break;
404 case 8:
405 cl_width = 64;
406 cl_height = 32;
407 break;
408 case 16: /* Hawaii */
409 cl_width = 64;
410 cl_height = 64;
411 break;
412 default:
413 assert(0);
414 return;
415 }
416
417 unsigned base_align = num_pipes * pipe_interleave_bytes;
418
419 unsigned width = align(rtex->surface.npix_x, cl_width*8);
420 unsigned height = align(rtex->surface.npix_y, cl_height*8);
421 unsigned slice_elements = (width * height) / (8*8);
422
423 /* Each element of CMASK is a nibble. */
424 unsigned slice_bytes = slice_elements / 2;
425
426 out->slice_tile_max = (width * height) / (128*128);
427 if (out->slice_tile_max)
428 out->slice_tile_max -= 1;
429
430 out->alignment = MAX2(256, base_align);
431 out->size = rtex->surface.array_size * align(slice_bytes, base_align);
432 }
433
434 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
435 struct r600_texture *rtex)
436 {
437 if (rscreen->chip_class >= SI) {
438 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
439 } else {
440 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
441 }
442
443 rtex->cmask.offset = align(rtex->size, rtex->cmask.alignment);
444 rtex->size = rtex->cmask.offset + rtex->cmask.size;
445 }
446
447 void r600_texture_init_cmask(struct r600_common_screen *rscreen,
448 struct r600_texture *rtex)
449 {
450 assert(rtex->cmask.size == 0);
451
452 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
453
454 rtex->cmask_buffer = (struct r600_resource *)
455 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
456 PIPE_USAGE_STATIC, rtex->cmask.size);
457 if (rtex->cmask_buffer == NULL) {
458 rtex->cmask.size = 0;
459 }
460 }
461
462 static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen,
463 struct r600_texture *rtex)
464 {
465 unsigned cl_width, cl_height, width, height;
466 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
467 unsigned num_pipes = rscreen->tiling_info.num_channels;
468
469 /* HTILE doesn't work with 1D tiling (there's massive corruption
470 * in glxgears). */
471 if (rtex->surface.level[0].mode != RADEON_SURF_MODE_2D)
472 return 0;
473
474 switch (num_pipes) {
475 case 2:
476 cl_width = 32;
477 cl_height = 32;
478 break;
479 case 4:
480 cl_width = 64;
481 cl_height = 32;
482 break;
483 case 8:
484 cl_width = 64;
485 cl_height = 64;
486 break;
487 case 16:
488 cl_width = 128;
489 cl_height = 64;
490 break;
491 default:
492 assert(0);
493 return 0;
494 }
495
496 width = align(rtex->surface.npix_x, cl_width * 8);
497 height = align(rtex->surface.npix_y, cl_height * 8);
498
499 slice_elements = (width * height) / (8 * 8);
500 slice_bytes = slice_elements * 4;
501
502 pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
503 base_align = num_pipes * pipe_interleave_bytes;
504
505 return rtex->surface.array_size * align(slice_bytes, base_align);
506 }
507
508 static unsigned r600_texture_htile_alloc_size(struct r600_common_screen *rscreen,
509 struct r600_texture *rtex)
510 {
511 unsigned sw = rtex->surface.level[0].nblk_x * rtex->surface.blk_w;
512 unsigned sh = rtex->surface.level[0].nblk_y * rtex->surface.blk_h;
513 unsigned npipes = rscreen->info.r600_num_tile_pipes;
514 unsigned htile_size;
515
516 /* XXX also use it for other texture targets */
517 if (rscreen->info.drm_minor < 26 ||
518 rtex->resource.b.b.target != PIPE_TEXTURE_2D ||
519 rtex->surface.level[0].nblk_x < 32 ||
520 rtex->surface.level[0].nblk_y < 32) {
521 return 0;
522 }
523
524 /* this alignment and htile size only apply to linear htile buffer */
525 sw = align(sw, 16 << 3);
526 sh = align(sh, npipes << 3);
527 htile_size = (sw >> 3) * (sh >> 3) * 4;
528 /* must be aligned with 2K * npipes */
529 htile_size = align(htile_size, (2 << 10) * npipes);
530 return htile_size;
531 }
532
533 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
534 struct r600_texture *rtex)
535 {
536 unsigned htile_size;
537 if (rscreen->chip_class >= SI) {
538 htile_size = si_texture_htile_alloc_size(rscreen, rtex);
539 } else {
540 htile_size = r600_texture_htile_alloc_size(rscreen, rtex);
541 }
542
543 if (!htile_size)
544 return;
545
546 /* XXX don't allocate it separately */
547 rtex->htile_buffer = (struct r600_resource*)
548 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
549 PIPE_USAGE_STATIC, htile_size);
550 if (rtex->htile_buffer == NULL) {
551 /* this is not a fatal error as we can still keep rendering
552 * without htile buffer */
553 R600_ERR("Failed to create buffer object for htile buffer.\n");
554 } else {
555 r600_screen_clear_buffer(rscreen, &rtex->htile_buffer->b.b, 0, htile_size, 0);
556 }
557 }
558
559 /* Common processing for r600_texture_create and r600_texture_from_handle */
560 static struct r600_texture *
561 r600_texture_create_object(struct pipe_screen *screen,
562 const struct pipe_resource *base,
563 unsigned pitch_in_bytes_override,
564 struct pb_buffer *buf,
565 struct radeon_surface *surface)
566 {
567 struct r600_texture *rtex;
568 struct r600_resource *resource;
569 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
570
571 rtex = CALLOC_STRUCT(r600_texture);
572 if (rtex == NULL)
573 return NULL;
574
575 resource = &rtex->resource;
576 resource->b.b = *base;
577 resource->b.vtbl = &r600_texture_vtbl;
578 pipe_reference_init(&resource->b.b.reference, 1);
579 resource->b.b.screen = screen;
580 rtex->pitch_override = pitch_in_bytes_override;
581
582 /* don't include stencil-only formats which we don't support for rendering */
583 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
584
585 rtex->surface = *surface;
586 if (r600_setup_surface(screen, rtex, pitch_in_bytes_override)) {
587 FREE(rtex);
588 return NULL;
589 }
590
591 /* Tiled depth textures utilize the non-displayable tile order.
592 * This must be done after r600_setup_surface.
593 * Applies to R600-Cayman. */
594 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
595
596 if (rtex->is_depth) {
597 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
598 R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
599 !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
600
601 r600_texture_allocate_htile(rscreen, rtex);
602 }
603 } else {
604 if (base->nr_samples > 1) {
605 if (!buf) {
606 r600_texture_allocate_fmask(rscreen, rtex);
607 r600_texture_allocate_cmask(rscreen, rtex);
608 rtex->cmask_buffer = &rtex->resource;
609 }
610 if (!rtex->fmask.size || !rtex->cmask.size) {
611 FREE(rtex);
612 return NULL;
613 }
614 }
615 }
616
617 /* Now create the backing buffer. */
618 if (!buf) {
619 unsigned base_align = rtex->surface.bo_alignment;
620 unsigned usage = rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D ?
621 PIPE_USAGE_STATIC : base->usage;
622
623 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, FALSE, usage)) {
624 FREE(rtex);
625 return NULL;
626 }
627 } else {
628 resource->buf = buf;
629 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
630 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
631 }
632
633 if (rtex->cmask.size) {
634 /* Initialize the cmask to 0xCC (= compressed state). */
635 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
636 rtex->cmask.offset, rtex->cmask.size, 0xCCCCCCCC);
637 }
638
639 if (rscreen->debug_flags & DBG_VM) {
640 fprintf(stderr, "VM start=0x%"PRIu64" end=0x%"PRIu64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
641 r600_resource_va(screen, &rtex->resource.b.b),
642 r600_resource_va(screen, &rtex->resource.b.b) + rtex->resource.buf->size,
643 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
644 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
645 }
646
647 if (rscreen->debug_flags & DBG_TEX ||
648 (rtex->resource.b.b.last_level > 0 && rscreen->debug_flags & DBG_TEXMIP)) {
649 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
650 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
651 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
652 rtex->surface.npix_x, rtex->surface.npix_y,
653 rtex->surface.npix_z, rtex->surface.blk_w,
654 rtex->surface.blk_h, rtex->surface.blk_d,
655 rtex->surface.array_size, rtex->surface.last_level,
656 rtex->surface.bpe, rtex->surface.nsamples,
657 rtex->surface.flags, util_format_short_name(base->format));
658 for (int i = 0; i <= rtex->surface.last_level; i++) {
659 printf(" L %i: offset=%"PRIu64", slice_size=%"PRIu64", npix_x=%u, "
660 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
661 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
662 i, rtex->surface.level[i].offset,
663 rtex->surface.level[i].slice_size,
664 u_minify(rtex->resource.b.b.width0, i),
665 u_minify(rtex->resource.b.b.height0, i),
666 u_minify(rtex->resource.b.b.depth0, i),
667 rtex->surface.level[i].nblk_x,
668 rtex->surface.level[i].nblk_y,
669 rtex->surface.level[i].nblk_z,
670 rtex->surface.level[i].pitch_bytes,
671 rtex->surface.level[i].mode);
672 }
673 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
674 for (int i = 0; i <= rtex->surface.last_level; i++) {
675 printf(" S %i: offset=%"PRIu64", slice_size=%"PRIu64", npix_x=%u, "
676 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
677 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
678 i, rtex->surface.stencil_level[i].offset,
679 rtex->surface.stencil_level[i].slice_size,
680 u_minify(rtex->resource.b.b.width0, i),
681 u_minify(rtex->resource.b.b.height0, i),
682 u_minify(rtex->resource.b.b.depth0, i),
683 rtex->surface.stencil_level[i].nblk_x,
684 rtex->surface.stencil_level[i].nblk_y,
685 rtex->surface.stencil_level[i].nblk_z,
686 rtex->surface.stencil_level[i].pitch_bytes,
687 rtex->surface.stencil_level[i].mode);
688 }
689 }
690 }
691 return rtex;
692 }
693
694 static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
695 const struct pipe_resource *templ)
696 {
697 const struct util_format_description *desc = util_format_description(templ->format);
698
699 /* MSAA resources must be 2D tiled. */
700 if (templ->nr_samples > 1)
701 return RADEON_SURF_MODE_2D;
702
703 /* Transfer resources should be linear. */
704 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
705 return RADEON_SURF_MODE_LINEAR_ALIGNED;
706
707 /* Handle common candidates for the linear mode.
708 * Compressed textures must always be tiled. */
709 if (!(templ->flags & R600_RESOURCE_FLAG_FORCE_TILING) &&
710 !util_format_is_compressed(templ->format)) {
711 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600-Cayman. */
712 if (rscreen->chip_class <= CAYMAN &&
713 desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
714 return RADEON_SURF_MODE_LINEAR_ALIGNED;
715
716 /* Cursors are linear on SI.
717 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
718 if (rscreen->chip_class >= SI &&
719 (templ->bind & PIPE_BIND_CURSOR))
720 return RADEON_SURF_MODE_LINEAR_ALIGNED;
721
722 if (templ->bind & PIPE_BIND_LINEAR)
723 return RADEON_SURF_MODE_LINEAR_ALIGNED;
724
725 /* Textures with a very small height are recommended to be linear. */
726 if (templ->target == PIPE_TEXTURE_1D ||
727 templ->target == PIPE_TEXTURE_1D_ARRAY ||
728 templ->height0 <= 4)
729 return RADEON_SURF_MODE_LINEAR_ALIGNED;
730
731 /* Textures likely to be mapped often. */
732 if (templ->usage == PIPE_USAGE_STAGING ||
733 templ->usage == PIPE_USAGE_STREAM)
734 return RADEON_SURF_MODE_LINEAR_ALIGNED;
735 }
736
737 /* Make small textures 1D tiled. */
738 if (templ->width0 <= 16 || templ->height0 <= 16)
739 return RADEON_SURF_MODE_1D;
740
741 /* The allocator will switch to 1D if needed. */
742 return RADEON_SURF_MODE_2D;
743 }
744
745 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
746 const struct pipe_resource *templ)
747 {
748 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
749 struct radeon_surface surface = {0};
750 int r;
751
752 r = r600_init_surface(rscreen, &surface, templ,
753 r600_choose_tiling(rscreen, templ),
754 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
755 if (r) {
756 return NULL;
757 }
758 r = rscreen->ws->surface_best(rscreen->ws, &surface);
759 if (r) {
760 return NULL;
761 }
762 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
763 0, NULL, &surface);
764 }
765
766 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
767 const struct pipe_resource *templ,
768 struct winsys_handle *whandle)
769 {
770 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
771 struct pb_buffer *buf = NULL;
772 unsigned stride = 0;
773 unsigned array_mode;
774 enum radeon_bo_layout micro, macro;
775 struct radeon_surface surface;
776 bool scanout;
777 int r;
778
779 /* Support only 2D textures without mipmaps */
780 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
781 templ->depth0 != 1 || templ->last_level != 0)
782 return NULL;
783
784 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
785 if (!buf)
786 return NULL;
787
788 rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
789 &surface.bankw, &surface.bankh,
790 &surface.tile_split,
791 &surface.stencil_tile_split,
792 &surface.mtilea, &scanout);
793
794 if (macro == RADEON_LAYOUT_TILED)
795 array_mode = RADEON_SURF_MODE_2D;
796 else if (micro == RADEON_LAYOUT_TILED)
797 array_mode = RADEON_SURF_MODE_1D;
798 else
799 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
800
801 r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
802 if (r) {
803 return NULL;
804 }
805
806 if (scanout)
807 surface.flags |= RADEON_SURF_SCANOUT;
808
809 return (struct pipe_resource *)r600_texture_create_object(screen, templ,
810 stride, buf, &surface);
811 }
812
813 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
814 struct pipe_resource *texture,
815 struct r600_texture **staging)
816 {
817 struct r600_texture *rtex = (struct r600_texture*)texture;
818 struct pipe_resource resource;
819 struct r600_texture **flushed_depth_texture = staging ?
820 staging : &rtex->flushed_depth_texture;
821
822 if (!staging && rtex->flushed_depth_texture)
823 return true; /* it's ready */
824
825 resource.target = texture->target;
826 resource.format = texture->format;
827 resource.width0 = texture->width0;
828 resource.height0 = texture->height0;
829 resource.depth0 = texture->depth0;
830 resource.array_size = texture->array_size;
831 resource.last_level = texture->last_level;
832 resource.nr_samples = texture->nr_samples;
833 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
834 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
835 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
836
837 if (staging)
838 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
839
840 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
841 if (*flushed_depth_texture == NULL) {
842 R600_ERR("failed to create temporary texture to hold flushed depth\n");
843 return false;
844 }
845
846 (*flushed_depth_texture)->is_flushing_texture = TRUE;
847 (*flushed_depth_texture)->non_disp_tiling = false;
848 return true;
849 }
850
851 /**
852 * Initialize the pipe_resource descriptor to be of the same size as the box,
853 * which is supposed to hold a subregion of the texture "orig" at the given
854 * mipmap level.
855 */
856 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
857 struct pipe_resource *orig,
858 const struct pipe_box *box,
859 unsigned level, unsigned flags)
860 {
861 memset(res, 0, sizeof(*res));
862 res->format = orig->format;
863 res->width0 = box->width;
864 res->height0 = box->height;
865 res->depth0 = 1;
866 res->array_size = 1;
867 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC;
868 res->flags = flags;
869
870 /* We must set the correct texture target and dimensions for a 3D box. */
871 if (box->depth > 1 && util_max_layer(orig, level) > 0)
872 res->target = orig->target;
873 else
874 res->target = PIPE_TEXTURE_2D;
875
876 switch (res->target) {
877 case PIPE_TEXTURE_1D_ARRAY:
878 case PIPE_TEXTURE_2D_ARRAY:
879 case PIPE_TEXTURE_CUBE_ARRAY:
880 res->array_size = box->depth;
881 break;
882 case PIPE_TEXTURE_3D:
883 res->depth0 = box->depth;
884 break;
885 default:;
886 }
887 }
888
889 static void *r600_texture_transfer_map(struct pipe_context *ctx,
890 struct pipe_resource *texture,
891 unsigned level,
892 unsigned usage,
893 const struct pipe_box *box,
894 struct pipe_transfer **ptransfer)
895 {
896 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
897 struct r600_texture *rtex = (struct r600_texture*)texture;
898 struct r600_transfer *trans;
899 boolean use_staging_texture = FALSE;
900 struct r600_resource *buf;
901 unsigned offset = 0;
902 char *map;
903
904 /* We cannot map a tiled texture directly because the data is
905 * in a different order, therefore we do detiling using a blit.
906 *
907 * Also, use a temporary in GTT memory for read transfers, as
908 * the CPU is much happier reading out of cached system memory
909 * than uncached VRAM.
910 */
911 if (rtex->surface.level[level].mode >= RADEON_SURF_MODE_1D)
912 use_staging_texture = TRUE;
913
914 /* Untiled buffers in VRAM, which is slow for CPU reads */
915 if ((usage & PIPE_TRANSFER_READ) && !(usage & PIPE_TRANSFER_MAP_DIRECTLY) &&
916 (rtex->resource.domains == RADEON_DOMAIN_VRAM)) {
917 use_staging_texture = TRUE;
918 }
919
920 /* Use a staging texture for uploads if the underlying BO is busy. */
921 if (!(usage & PIPE_TRANSFER_READ) &&
922 (r600_rings_is_buffer_referenced(rctx, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) ||
923 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) {
924 use_staging_texture = TRUE;
925 }
926
927 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) {
928 use_staging_texture = FALSE;
929 }
930
931 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
932 return NULL;
933 }
934
935 trans = CALLOC_STRUCT(r600_transfer);
936 if (trans == NULL)
937 return NULL;
938 trans->transfer.resource = texture;
939 trans->transfer.level = level;
940 trans->transfer.usage = usage;
941 trans->transfer.box = *box;
942
943 if (rtex->is_depth) {
944 struct r600_texture *staging_depth;
945
946 if (rtex->resource.b.b.nr_samples > 1) {
947 /* MSAA depth buffers need to be converted to single sample buffers.
948 *
949 * Mapping MSAA depth buffers can occur if ReadPixels is called
950 * with a multisample GLX visual.
951 *
952 * First downsample the depth buffer to a temporary texture,
953 * then decompress the temporary one to staging.
954 *
955 * Only the region being mapped is transfered.
956 */
957 struct pipe_resource resource;
958
959 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
960
961 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
962 R600_ERR("failed to create temporary texture to hold untiled copy\n");
963 FREE(trans);
964 return NULL;
965 }
966
967 if (usage & PIPE_TRANSFER_READ) {
968 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
969
970 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
971 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
972 0, 0, 0, box->depth, 0, 0);
973 pipe_resource_reference((struct pipe_resource**)&temp, NULL);
974 }
975 }
976 else {
977 /* XXX: only readback the rectangle which is being mapped? */
978 /* XXX: when discard is true, no need to read back from depth texture */
979 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
980 R600_ERR("failed to create temporary texture to hold untiled copy\n");
981 FREE(trans);
982 return NULL;
983 }
984
985 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
986 level, level,
987 box->z, box->z + box->depth - 1,
988 0, 0);
989
990 offset = r600_texture_get_offset(staging_depth, level, box);
991 }
992
993 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
994 trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
995 trans->staging = (struct r600_resource*)staging_depth;
996 } else if (use_staging_texture) {
997 struct pipe_resource resource;
998 struct r600_texture *staging;
999
1000 r600_init_temp_resource_from_box(&resource, texture, box, level,
1001 R600_RESOURCE_FLAG_TRANSFER);
1002
1003 /* Create the temporary texture. */
1004 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1005 if (staging == NULL) {
1006 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1007 FREE(trans);
1008 return NULL;
1009 }
1010 trans->staging = &staging->resource;
1011 trans->transfer.stride = staging->surface.level[0].pitch_bytes;
1012 trans->transfer.layer_stride = staging->surface.level[0].slice_size;
1013 if (usage & PIPE_TRANSFER_READ) {
1014 r600_copy_to_staging_texture(ctx, trans);
1015 }
1016 } else {
1017 /* the resource is mapped directly */
1018 trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
1019 trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
1020 offset = r600_texture_get_offset(rtex, level, box);
1021 }
1022
1023 if (trans->staging) {
1024 buf = trans->staging;
1025 } else {
1026 buf = &rtex->resource;
1027 }
1028
1029 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1030 pipe_resource_reference((struct pipe_resource**)&trans->staging, NULL);
1031 FREE(trans);
1032 return NULL;
1033 }
1034
1035 *ptransfer = &trans->transfer;
1036 return map + offset;
1037 }
1038
1039 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1040 struct pipe_transfer* transfer)
1041 {
1042 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1043 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1044 struct radeon_winsys_cs_handle *buf;
1045 struct pipe_resource *texture = transfer->resource;
1046 struct r600_texture *rtex = (struct r600_texture*)texture;
1047
1048 if (rtransfer->staging) {
1049 buf = rtransfer->staging->cs_buf;
1050 } else {
1051 buf = r600_resource(transfer->resource)->cs_buf;
1052 }
1053 rctx->ws->buffer_unmap(buf);
1054
1055 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1056 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1057 ctx->resource_copy_region(ctx, texture, transfer->level,
1058 transfer->box.x, transfer->box.y, transfer->box.z,
1059 &rtransfer->staging->b.b, transfer->level,
1060 &transfer->box);
1061 } else {
1062 r600_copy_from_staging_texture(ctx, rtransfer);
1063 }
1064 }
1065
1066 if (rtransfer->staging)
1067 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
1068
1069 FREE(transfer);
1070 }
1071
1072 static const struct u_resource_vtbl r600_texture_vtbl =
1073 {
1074 r600_texture_get_handle, /* get_handle */
1075 r600_texture_destroy, /* resource_destroy */
1076 r600_texture_transfer_map, /* transfer_map */
1077 NULL, /* transfer_flush_region */
1078 r600_texture_transfer_unmap, /* transfer_unmap */
1079 NULL /* transfer_inline_write */
1080 };