2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
41 const struct pipe_resource
*templ
);
44 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
45 struct r600_texture
*rdst
,
46 unsigned dst_level
, unsigned dstx
,
47 unsigned dsty
, unsigned dstz
,
48 struct r600_texture
*rsrc
,
50 const struct pipe_box
*src_box
)
55 if (util_format_get_blocksizebits(rdst
->resource
.b
.b
.format
) !=
56 util_format_get_blocksizebits(rsrc
->resource
.b
.b
.format
))
59 /* MSAA: Blits don't exist in the real world. */
60 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
61 rdst
->resource
.b
.b
.nr_samples
> 1)
64 /* Depth-stencil surfaces:
65 * When dst is linear, the DB->CB copy preserves HTILE.
66 * When dst is tiled, the 3D path must be used to update HTILE.
68 if (rsrc
->is_depth
|| rdst
->is_depth
)
72 * src: Use the 3D path. DCC decompression is expensive.
73 * dst: Use the 3D path to compress the pixels with DCC.
75 if ((rsrc
->dcc_offset
&& rsrc
->surface
.level
[src_level
].dcc_enabled
) ||
76 (rdst
->dcc_offset
&& rdst
->surface
.level
[dst_level
].dcc_enabled
))
80 * src: Both texture and SDMA paths need decompression. Use SDMA.
81 * dst: If overwriting the whole texture, discard CMASK and use
82 * SDMA. Otherwise, use the 3D path.
84 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
85 /* The CMASK clear is only enabled for the first level. */
86 assert(dst_level
== 0);
87 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
88 dstx
, dsty
, dstz
, src_box
->width
,
89 src_box
->height
, src_box
->depth
))
92 r600_texture_discard_cmask(rctx
->screen
, rdst
);
95 /* All requirements are met. Prepare textures for SDMA. */
96 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
97 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
99 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
100 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
105 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
106 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
107 struct pipe_resource
*dst
,
109 unsigned dstx
, unsigned dsty
, unsigned dstz
,
110 struct pipe_resource
*src
,
112 const struct pipe_box
*src_box
)
114 struct pipe_blit_info blit
;
116 memset(&blit
, 0, sizeof(blit
));
117 blit
.src
.resource
= src
;
118 blit
.src
.format
= src
->format
;
119 blit
.src
.level
= src_level
;
120 blit
.src
.box
= *src_box
;
121 blit
.dst
.resource
= dst
;
122 blit
.dst
.format
= dst
->format
;
123 blit
.dst
.level
= dst_level
;
124 blit
.dst
.box
.x
= dstx
;
125 blit
.dst
.box
.y
= dsty
;
126 blit
.dst
.box
.z
= dstz
;
127 blit
.dst
.box
.width
= src_box
->width
;
128 blit
.dst
.box
.height
= src_box
->height
;
129 blit
.dst
.box
.depth
= src_box
->depth
;
130 blit
.mask
= util_format_get_mask(src
->format
) &
131 util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
142 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
144 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1) {
148 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
149 src
, transfer
->level
, &transfer
->box
);
153 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
157 /* Copy from a transfer's staging texture to a full GPU one. */
158 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
160 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
161 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
162 struct pipe_resource
*dst
= transfer
->resource
;
163 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
164 struct pipe_box sbox
;
166 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
168 if (dst
->nr_samples
> 1) {
169 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
175 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
176 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
180 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
181 const struct pipe_box
*box
)
183 enum pipe_format format
= rtex
->resource
.b
.b
.format
;
185 return rtex
->surface
.level
[level
].offset
+
186 box
->z
* rtex
->surface
.level
[level
].slice_size
+
187 box
->y
/ util_format_get_blockheight(format
) * rtex
->surface
.level
[level
].pitch_bytes
+
188 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
191 static int r600_init_surface(struct r600_common_screen
*rscreen
,
192 struct radeon_surf
*surface
,
193 const struct pipe_resource
*ptex
,
195 unsigned pitch_in_bytes_override
,
199 bool is_flushed_depth
,
200 bool tc_compatible_htile
)
202 const struct util_format_description
*desc
=
203 util_format_description(ptex
->format
);
204 bool is_depth
, is_stencil
;
207 is_depth
= util_format_has_depth(desc
);
208 is_stencil
= util_format_has_stencil(desc
);
210 surface
->npix_x
= ptex
->width0
;
211 surface
->npix_y
= ptex
->height0
;
212 surface
->npix_z
= ptex
->depth0
;
213 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
214 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
216 surface
->array_size
= 1;
217 surface
->last_level
= ptex
->last_level
;
219 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
220 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
221 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
223 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
224 /* align byte per element on dword */
225 if (surface
->bpe
== 3) {
230 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
231 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
233 switch (ptex
->target
) {
234 case PIPE_TEXTURE_1D
:
235 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
237 case PIPE_TEXTURE_RECT
:
238 case PIPE_TEXTURE_2D
:
239 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
241 case PIPE_TEXTURE_3D
:
242 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
244 case PIPE_TEXTURE_1D_ARRAY
:
245 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
246 surface
->array_size
= ptex
->array_size
;
248 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d array */
249 assert(ptex
->array_size
% 6 == 0);
250 case PIPE_TEXTURE_2D_ARRAY
:
251 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
252 surface
->array_size
= ptex
->array_size
;
254 case PIPE_TEXTURE_CUBE
:
255 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
262 if (!is_flushed_depth
&& is_depth
) {
263 surface
->flags
|= RADEON_SURF_ZBUFFER
;
265 if (tc_compatible_htile
&&
266 array_mode
== RADEON_SURF_MODE_2D
) {
267 /* TC-compatible HTILE only supports Z32_FLOAT.
268 * Promote Z16 to Z32. DB->CB copies will convert
269 * the format for transfers.
272 surface
->flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
276 surface
->flags
|= RADEON_SURF_SBUFFER
|
277 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
281 if (rscreen
->chip_class
>= SI
) {
282 surface
->flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
285 if (rscreen
->chip_class
>= VI
&&
286 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
287 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
288 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
290 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
291 /* This should catch bugs in gallium users setting incorrect flags. */
292 assert(surface
->nsamples
== 1 &&
293 surface
->array_size
== 1 &&
294 surface
->npix_z
== 1 &&
295 surface
->last_level
== 0 &&
296 !(surface
->flags
& RADEON_SURF_Z_OR_SBUFFER
));
298 surface
->flags
|= RADEON_SURF_SCANOUT
;
302 surface
->flags
|= RADEON_SURF_IMPORTED
;
304 r
= rscreen
->ws
->surface_init(rscreen
->ws
, surface
);
309 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= surface
->level
[0].pitch_bytes
) {
310 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
313 surface
->level
[0].nblk_x
= pitch_in_bytes_override
/ surface
->bpe
;
314 surface
->level
[0].pitch_bytes
= pitch_in_bytes_override
;
315 surface
->level
[0].slice_size
= pitch_in_bytes_override
* surface
->level
[0].nblk_y
;
319 for (i
= 0; i
< ARRAY_SIZE(surface
->level
); ++i
)
320 surface
->level
[i
].offset
+= offset
;
325 static void r600_texture_init_metadata(struct r600_texture
*rtex
,
326 struct radeon_bo_metadata
*metadata
)
328 struct radeon_surf
*surface
= &rtex
->surface
;
330 memset(metadata
, 0, sizeof(*metadata
));
331 metadata
->microtile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
332 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
333 metadata
->macrotile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
334 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
335 metadata
->pipe_config
= surface
->pipe_config
;
336 metadata
->bankw
= surface
->bankw
;
337 metadata
->bankh
= surface
->bankh
;
338 metadata
->tile_split
= surface
->tile_split
;
339 metadata
->mtilea
= surface
->mtilea
;
340 metadata
->num_banks
= surface
->num_banks
;
341 metadata
->stride
= surface
->level
[0].pitch_bytes
;
342 metadata
->scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
345 static void r600_dirty_all_framebuffer_states(struct r600_common_screen
*rscreen
)
347 p_atomic_inc(&rscreen
->dirty_fb_counter
);
350 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
351 struct r600_texture
*rtex
)
353 struct r600_common_screen
*rscreen
= rctx
->screen
;
354 struct pipe_context
*ctx
= &rctx
->b
;
356 if (ctx
== rscreen
->aux_context
)
357 pipe_mutex_lock(rscreen
->aux_context_lock
);
359 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
360 ctx
->flush(ctx
, NULL
, 0);
362 if (ctx
== rscreen
->aux_context
)
363 pipe_mutex_unlock(rscreen
->aux_context_lock
);
366 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
367 struct r600_texture
*rtex
)
369 if (!rtex
->cmask
.size
)
372 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
375 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
376 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
377 rtex
->dirty_level_mask
= 0;
379 if (rscreen
->chip_class
>= SI
)
380 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
382 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
384 if (rtex
->cmask_buffer
!= &rtex
->resource
)
385 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
387 /* Notify all contexts about the change. */
388 r600_dirty_all_framebuffer_states(rscreen
);
389 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
392 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
394 /* We can't disable DCC if it can be written by another process. */
395 return rtex
->dcc_offset
&&
396 (!rtex
->resource
.is_shared
||
397 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
400 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
401 struct r600_texture
*rtex
)
403 if (!r600_can_disable_dcc(rtex
))
406 assert(rtex
->dcc_separate_buffer
== NULL
);
409 rtex
->dcc_offset
= 0;
411 /* Notify all contexts about the change. */
412 r600_dirty_all_framebuffer_states(rscreen
);
417 * Disable DCC for the texture. (first decompress, then discard metadata).
419 * There is unresolved multi-context synchronization issue between
420 * screen::aux_context and the current context. If applications do this with
421 * multiple contexts, it's already undefined behavior for them and we don't
422 * have to worry about that. The scenario is:
424 * If context 1 disables DCC and context 2 has queued commands that write
425 * to the texture via CB with DCC enabled, and the order of operations is
427 * context 2 queues draw calls rendering to the texture, but doesn't flush
428 * context 1 disables DCC and flushes
429 * context 1 & 2 reset descriptors and FB state
430 * context 2 flushes (new compressed tiles written by the draw calls)
431 * context 1 & 2 read garbage, because DCC is disabled, yet there are
434 * \param rctx the current context if you have one, or rscreen->aux_context
437 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
438 struct r600_texture
*rtex
)
440 struct r600_common_screen
*rscreen
= rctx
->screen
;
442 if (!r600_can_disable_dcc(rtex
))
445 if (&rctx
->b
== rscreen
->aux_context
)
446 pipe_mutex_lock(rscreen
->aux_context_lock
);
448 /* Decompress DCC. */
449 rctx
->decompress_dcc(&rctx
->b
, rtex
);
450 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
452 if (&rctx
->b
== rscreen
->aux_context
)
453 pipe_mutex_unlock(rscreen
->aux_context_lock
);
455 return r600_texture_discard_dcc(rscreen
, rtex
);
458 static void r600_degrade_tile_mode_to_linear(struct r600_common_context
*rctx
,
459 struct r600_texture
*rtex
,
460 bool invalidate_storage
)
462 struct pipe_screen
*screen
= rctx
->b
.screen
;
463 struct r600_texture
*new_tex
;
464 struct pipe_resource templ
= rtex
->resource
.b
.b
;
467 templ
.bind
|= PIPE_BIND_LINEAR
;
469 /* r600g doesn't react to dirty_tex_descriptor_counter */
470 if (rctx
->chip_class
< SI
)
473 if (rtex
->resource
.is_shared
||
474 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
)
477 /* This fails with MSAA, depth, and compressed textures. */
478 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
479 RADEON_SURF_MODE_LINEAR_ALIGNED
)
482 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
486 /* Copy the pixels to the new texture. */
487 if (!invalidate_storage
) {
488 for (i
= 0; i
<= templ
.last_level
; i
++) {
492 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
493 util_max_layer(&templ
, i
) + 1, &box
);
495 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
496 &rtex
->resource
.b
.b
, i
, &box
);
500 r600_texture_discard_cmask(rctx
->screen
, rtex
);
501 r600_texture_discard_dcc(rctx
->screen
, rtex
);
503 /* Replace the structure fields of rtex. */
504 rtex
->resource
.b
.b
.bind
= templ
.bind
;
505 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
506 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
507 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
508 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
509 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
510 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
511 rtex
->resource
.domains
= new_tex
->resource
.domains
;
512 rtex
->resource
.flags
= new_tex
->resource
.flags
;
513 rtex
->size
= new_tex
->size
;
514 rtex
->surface
= new_tex
->surface
;
515 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
516 rtex
->cb_color_info
= new_tex
->cb_color_info
;
517 rtex
->cmask
= new_tex
->cmask
; /* needed even without CMASK */
519 assert(!rtex
->htile_buffer
);
520 assert(!rtex
->cmask
.size
);
521 assert(!rtex
->fmask
.size
);
522 assert(!rtex
->dcc_offset
);
523 assert(!rtex
->is_depth
);
525 r600_texture_reference(&new_tex
, NULL
);
527 r600_dirty_all_framebuffer_states(rctx
->screen
);
528 p_atomic_inc(&rctx
->screen
->dirty_tex_descriptor_counter
);
531 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
532 struct pipe_context
*ctx
,
533 struct pipe_resource
*resource
,
534 struct winsys_handle
*whandle
,
537 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
538 struct r600_common_context
*rctx
= (struct r600_common_context
*)
539 (ctx
? ctx
: rscreen
->aux_context
);
540 struct r600_resource
*res
= (struct r600_resource
*)resource
;
541 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
542 struct radeon_bo_metadata metadata
;
543 bool update_metadata
= false;
545 /* This is not supported now, but it might be required for OpenCL
546 * interop in the future.
548 if (resource
->target
!= PIPE_BUFFER
&&
549 (resource
->nr_samples
> 1 || rtex
->is_depth
))
552 if (resource
->target
!= PIPE_BUFFER
) {
553 /* Since shader image stores don't support DCC on VI,
554 * disable it for external clients that want write
557 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
558 if (r600_texture_disable_dcc(rctx
, rtex
))
559 update_metadata
= true;
562 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
563 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
564 /* Eliminate fast clear (both CMASK and DCC) */
565 r600_eliminate_fast_color_clear(rctx
, rtex
);
567 /* Disable CMASK if flush_resource isn't going
570 if (rtex
->cmask
.size
)
571 r600_texture_discard_cmask(rscreen
, rtex
);
575 if (!res
->is_shared
|| update_metadata
) {
576 r600_texture_init_metadata(rtex
, &metadata
);
577 if (rscreen
->query_opaque_metadata
)
578 rscreen
->query_opaque_metadata(rscreen
, rtex
,
581 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
585 if (res
->is_shared
) {
586 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
589 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
590 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
591 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
593 res
->is_shared
= true;
594 res
->external_usage
= usage
;
597 return rscreen
->ws
->buffer_get_handle(res
->buf
,
598 rtex
->surface
.level
[0].pitch_bytes
,
599 rtex
->surface
.level
[0].offset
,
600 rtex
->surface
.level
[0].slice_size
,
604 static void r600_texture_destroy(struct pipe_screen
*screen
,
605 struct pipe_resource
*ptex
)
607 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
608 struct r600_resource
*resource
= &rtex
->resource
;
610 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
612 r600_resource_reference(&rtex
->htile_buffer
, NULL
);
613 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
614 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
616 pb_reference(&resource
->buf
, NULL
);
617 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
618 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
622 static const struct u_resource_vtbl r600_texture_vtbl
;
624 /* The number of samples can be specified independently of the texture. */
625 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
626 struct r600_texture
*rtex
,
628 struct r600_fmask_info
*out
)
630 /* FMASK is allocated like an ordinary texture. */
631 struct radeon_surf fmask
= rtex
->surface
;
633 memset(out
, 0, sizeof(*out
));
635 fmask
.bo_alignment
= 0;
638 fmask
.flags
|= RADEON_SURF_FMASK
;
640 /* Force 2D tiling if it wasn't set. This may occur when creating
641 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
642 * destination buffer must have an FMASK too. */
643 fmask
.flags
= RADEON_SURF_CLR(fmask
.flags
, MODE
);
644 fmask
.flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
646 if (rscreen
->chip_class
>= SI
) {
647 fmask
.flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
650 switch (nr_samples
) {
654 if (rscreen
->chip_class
<= CAYMAN
) {
662 R600_ERR("Invalid sample count for FMASK allocation.\n");
666 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
667 * This can be fixed by writing a separate FMASK allocator specifically
668 * for R600-R700 asics. */
669 if (rscreen
->chip_class
<= R700
) {
673 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
674 R600_ERR("Got error in surface_init while allocating FMASK.\n");
678 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
680 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
681 if (out
->slice_tile_max
)
682 out
->slice_tile_max
-= 1;
684 out
->tile_mode_index
= fmask
.tiling_index
[0];
685 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
686 out
->bank_height
= fmask
.bankh
;
687 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
688 out
->size
= fmask
.bo_size
;
691 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
692 struct r600_texture
*rtex
)
694 r600_texture_get_fmask_info(rscreen
, rtex
,
695 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
697 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
698 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
701 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
702 struct r600_texture
*rtex
,
703 struct r600_cmask_info
*out
)
705 unsigned cmask_tile_width
= 8;
706 unsigned cmask_tile_height
= 8;
707 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
708 unsigned element_bits
= 4;
709 unsigned cmask_cache_bits
= 1024;
710 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
711 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
713 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
714 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
715 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
716 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
717 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
719 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
720 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
722 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
723 unsigned slice_bytes
=
724 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
726 assert(macro_tile_width
% 128 == 0);
727 assert(macro_tile_height
% 128 == 0);
729 out
->pitch
= pitch_elements
;
730 out
->height
= height
;
731 out
->xalign
= macro_tile_width
;
732 out
->yalign
= macro_tile_height
;
733 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
734 out
->alignment
= MAX2(256, base_align
);
735 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
736 align(slice_bytes
, base_align
);
739 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
740 struct r600_texture
*rtex
,
741 struct r600_cmask_info
*out
)
743 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
744 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
745 unsigned cl_width
, cl_height
;
760 case 16: /* Hawaii */
769 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
771 unsigned width
= align(rtex
->surface
.npix_x
, cl_width
*8);
772 unsigned height
= align(rtex
->surface
.npix_y
, cl_height
*8);
773 unsigned slice_elements
= (width
* height
) / (8*8);
775 /* Each element of CMASK is a nibble. */
776 unsigned slice_bytes
= slice_elements
/ 2;
779 out
->height
= height
;
780 out
->xalign
= cl_width
* 8;
781 out
->yalign
= cl_height
* 8;
782 out
->slice_tile_max
= (width
* height
) / (128*128);
783 if (out
->slice_tile_max
)
784 out
->slice_tile_max
-= 1;
786 out
->alignment
= MAX2(256, base_align
);
787 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
788 align(slice_bytes
, base_align
);
791 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
792 struct r600_texture
*rtex
)
794 if (rscreen
->chip_class
>= SI
) {
795 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
797 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
800 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
801 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
803 if (rscreen
->chip_class
>= SI
)
804 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
806 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
809 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
810 struct r600_texture
*rtex
)
812 if (rtex
->cmask_buffer
)
815 assert(rtex
->cmask
.size
== 0);
817 if (rscreen
->chip_class
>= SI
) {
818 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
820 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
823 rtex
->cmask_buffer
= (struct r600_resource
*)
824 r600_aligned_buffer_create(&rscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
826 rtex
->cmask
.alignment
);
827 if (rtex
->cmask_buffer
== NULL
) {
828 rtex
->cmask
.size
= 0;
832 /* update colorbuffer state bits */
833 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
835 if (rscreen
->chip_class
>= SI
)
836 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
838 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
840 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
843 static unsigned r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
844 struct r600_texture
*rtex
)
846 unsigned cl_width
, cl_height
, width
, height
;
847 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
848 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
850 if (rscreen
->chip_class
<= EVERGREEN
&&
851 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
854 /* HW bug on R6xx. */
855 if (rscreen
->chip_class
== R600
&&
856 (rtex
->surface
.level
[0].npix_x
> 7680 ||
857 rtex
->surface
.level
[0].npix_y
> 7680))
860 /* HTILE is broken with 1D tiling on old kernels and CIK. */
861 if (rscreen
->chip_class
>= CIK
&&
862 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
863 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
866 /* Overalign HTILE on P2 configs to work around GPU hangs in
867 * piglit/depthstencil-render-miplevels 585.
869 * This has been confirmed to help Kabini & Stoney, where the hangs
870 * are always reproducible. I think I have seen the test hang
871 * on Carrizo too, though it was very rare there.
873 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
902 width
= align(rtex
->surface
.npix_x
, cl_width
* 8);
903 height
= align(rtex
->surface
.npix_y
, cl_height
* 8);
905 slice_elements
= (width
* height
) / (8 * 8);
906 slice_bytes
= slice_elements
* 4;
908 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
909 base_align
= num_pipes
* pipe_interleave_bytes
;
911 rtex
->htile
.pitch
= width
;
912 rtex
->htile
.height
= height
;
913 rtex
->htile
.xalign
= cl_width
* 8;
914 rtex
->htile
.yalign
= cl_height
* 8;
915 rtex
->htile
.alignment
= base_align
;
917 return (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
918 align(slice_bytes
, base_align
);
921 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
922 struct r600_texture
*rtex
)
924 uint64_t htile_size
, alignment
;
925 uint32_t clear_value
;
927 if (rtex
->tc_compatible_htile
) {
928 htile_size
= rtex
->surface
.htile_size
;
929 alignment
= rtex
->surface
.htile_alignment
;
930 clear_value
= 0x0000030F;
932 htile_size
= r600_texture_get_htile_size(rscreen
, rtex
);
933 alignment
= rtex
->htile
.alignment
;
940 rtex
->htile_buffer
= (struct r600_resource
*)
941 r600_aligned_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
943 htile_size
, alignment
);
944 if (rtex
->htile_buffer
== NULL
) {
945 /* this is not a fatal error as we can still keep rendering
946 * without htile buffer */
947 R600_ERR("Failed to create buffer object for htile buffer.\n");
949 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
,
950 0, htile_size
, clear_value
,
951 R600_COHERENCY_NONE
);
955 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
)
959 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
960 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
961 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
962 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
963 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
964 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
965 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
966 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
967 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
969 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%"PRIu64
", bankw=%u, "
970 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
971 rtex
->surface
.bo_size
, rtex
->surface
.bo_alignment
, rtex
->surface
.bankw
,
972 rtex
->surface
.bankh
, rtex
->surface
.num_banks
, rtex
->surface
.mtilea
,
973 rtex
->surface
.tile_split
, rtex
->surface
.pipe_config
,
974 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
976 if (rtex
->fmask
.size
)
977 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
978 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
979 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
980 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
981 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
983 if (rtex
->cmask
.size
)
984 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch=%u, "
985 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
986 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
987 rtex
->cmask
.pitch
, rtex
->cmask
.height
, rtex
->cmask
.xalign
,
988 rtex
->cmask
.yalign
, rtex
->cmask
.slice_tile_max
);
990 if (rtex
->htile_buffer
)
991 fprintf(f
, " HTile: size=%u, alignment=%u, pitch=%u, height=%u, "
992 "xalign=%u, yalign=%u, TC_compatible = %u\n",
993 rtex
->htile_buffer
->b
.b
.width0
,
994 rtex
->htile_buffer
->buf
->alignment
, rtex
->htile
.pitch
,
995 rtex
->htile
.height
, rtex
->htile
.xalign
, rtex
->htile
.yalign
,
996 rtex
->tc_compatible_htile
);
998 if (rtex
->dcc_offset
) {
999 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%"PRIu64
"\n",
1000 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
1001 rtex
->surface
.dcc_alignment
);
1002 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
1003 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
1004 "fast_clear_size=%"PRIu64
"\n",
1005 i
, rtex
->surface
.level
[i
].dcc_enabled
,
1006 rtex
->surface
.level
[i
].dcc_offset
,
1007 rtex
->surface
.level
[i
].dcc_fast_clear_size
);
1010 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++)
1011 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
1012 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1013 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
1014 i
, rtex
->surface
.level
[i
].offset
,
1015 rtex
->surface
.level
[i
].slice_size
,
1016 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1017 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1018 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1019 rtex
->surface
.level
[i
].nblk_x
,
1020 rtex
->surface
.level
[i
].nblk_y
,
1021 rtex
->surface
.level
[i
].nblk_z
,
1022 rtex
->surface
.level
[i
].pitch_bytes
,
1023 rtex
->surface
.level
[i
].mode
);
1025 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1026 fprintf(f
, " StencilLayout: tilesplit=%u\n",
1027 rtex
->surface
.stencil_tile_split
);
1028 for (i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
1029 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
1030 "slice_size=%"PRIu64
", npix_x=%u, "
1031 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
1032 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
1033 i
, rtex
->surface
.stencil_level
[i
].offset
,
1034 rtex
->surface
.stencil_level
[i
].slice_size
,
1035 u_minify(rtex
->resource
.b
.b
.width0
, i
),
1036 u_minify(rtex
->resource
.b
.b
.height0
, i
),
1037 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
1038 rtex
->surface
.stencil_level
[i
].nblk_x
,
1039 rtex
->surface
.stencil_level
[i
].nblk_y
,
1040 rtex
->surface
.stencil_level
[i
].nblk_z
,
1041 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
1042 rtex
->surface
.stencil_level
[i
].mode
);
1047 /* Common processing for r600_texture_create and r600_texture_from_handle */
1048 static struct r600_texture
*
1049 r600_texture_create_object(struct pipe_screen
*screen
,
1050 const struct pipe_resource
*base
,
1051 struct pb_buffer
*buf
,
1052 struct radeon_surf
*surface
)
1054 struct r600_texture
*rtex
;
1055 struct r600_resource
*resource
;
1056 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1058 rtex
= CALLOC_STRUCT(r600_texture
);
1062 resource
= &rtex
->resource
;
1063 resource
->b
.b
= *base
;
1064 resource
->b
.b
.next
= NULL
;
1065 resource
->b
.vtbl
= &r600_texture_vtbl
;
1066 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1067 resource
->b
.b
.screen
= screen
;
1069 /* don't include stencil-only formats which we don't support for rendering */
1070 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1072 rtex
->surface
= *surface
;
1073 rtex
->size
= rtex
->surface
.bo_size
;
1075 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0;
1076 assert(!!(rtex
->surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
) ==
1077 rtex
->tc_compatible_htile
);
1079 /* TC-compatible HTILE only supports Z32_FLOAT. */
1080 if (rtex
->tc_compatible_htile
)
1081 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1083 rtex
->db_render_format
= base
->format
;
1085 /* Tiled depth textures utilize the non-displayable tile order.
1086 * This must be done after r600_setup_surface.
1087 * Applies to R600-Cayman. */
1088 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1089 /* Applies to GCN. */
1090 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1092 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1093 * between frames, so the only thing that can enable separate DCC
1094 * with DRI2 is multiple slow clears within a frame.
1096 rtex
->ps_draw_ratio
= 0;
1098 if (rtex
->is_depth
) {
1099 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1100 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1101 rscreen
->chip_class
>= EVERGREEN
) {
1102 rtex
->can_sample_z
= !rtex
->surface
.depth_adjusted
;
1103 rtex
->can_sample_s
= !rtex
->surface
.stencil_adjusted
;
1105 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1106 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1107 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1108 rtex
->can_sample_z
= true;
1111 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1112 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1113 rtex
->db_compatible
= true;
1115 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1116 r600_texture_allocate_htile(rscreen
, rtex
);
1119 if (base
->nr_samples
> 1) {
1121 r600_texture_allocate_fmask(rscreen
, rtex
);
1122 r600_texture_allocate_cmask(rscreen
, rtex
);
1123 rtex
->cmask_buffer
= &rtex
->resource
;
1125 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1131 /* Shared textures must always set up DCC here.
1132 * If it's not present, it will be disabled by
1133 * apply_opaque_metadata later.
1135 if (rtex
->surface
.dcc_size
&&
1136 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1137 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1138 /* Reserve space for the DCC buffer. */
1139 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1140 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1144 /* Now create the backing buffer. */
1146 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
1147 rtex
->surface
.bo_alignment
);
1149 resource
->flags
|= RADEON_FLAG_HANDLE
;
1151 if (!r600_alloc_resource(rscreen
, resource
)) {
1156 resource
->buf
= buf
;
1157 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1158 resource
->bo_size
= buf
->size
;
1159 resource
->bo_alignment
= buf
->alignment
;
1160 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1161 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1162 resource
->vram_usage
= buf
->size
;
1163 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1164 resource
->gart_usage
= buf
->size
;
1167 if (rtex
->cmask
.size
) {
1168 /* Initialize the cmask to 0xCC (= compressed state). */
1169 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1170 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1171 0xCCCCCCCC, R600_COHERENCY_NONE
);
1174 /* Initialize DCC only if the texture is not being imported. */
1175 if (!buf
&& rtex
->dcc_offset
) {
1176 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1178 rtex
->surface
.dcc_size
,
1179 0xFFFFFFFF, R600_COHERENCY_NONE
);
1182 /* Initialize the CMASK base register value. */
1183 rtex
->cmask
.base_address_reg
=
1184 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1186 if (rscreen
->debug_flags
& DBG_VM
) {
1187 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1188 rtex
->resource
.gpu_address
,
1189 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1190 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1191 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1194 if (rscreen
->debug_flags
& DBG_TEX
) {
1196 r600_print_texture_info(rtex
, stdout
);
1203 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
1204 const struct pipe_resource
*templ
)
1206 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1207 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1209 /* MSAA resources must be 2D tiled. */
1210 if (templ
->nr_samples
> 1)
1211 return RADEON_SURF_MODE_2D
;
1213 /* Transfer resources should be linear. */
1214 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1215 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1217 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1218 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1219 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1220 (templ
->target
== PIPE_TEXTURE_2D
||
1221 templ
->target
== PIPE_TEXTURE_3D
))
1222 force_tiling
= true;
1224 /* Handle common candidates for the linear mode.
1225 * Compressed textures and DB surfaces must always be tiled.
1227 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
1228 (!util_format_is_depth_or_stencil(templ
->format
) ||
1229 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
1230 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1231 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1233 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1234 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1235 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1237 /* Cursors are linear on SI.
1238 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1239 if (rscreen
->chip_class
>= SI
&&
1240 (templ
->bind
& PIPE_BIND_CURSOR
))
1241 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1243 if (templ
->bind
& PIPE_BIND_LINEAR
)
1244 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1246 /* Textures with a very small height are recommended to be linear. */
1247 if (templ
->target
== PIPE_TEXTURE_1D
||
1248 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1249 templ
->height0
<= 4)
1250 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1252 /* Textures likely to be mapped often. */
1253 if (templ
->usage
== PIPE_USAGE_STAGING
||
1254 templ
->usage
== PIPE_USAGE_STREAM
)
1255 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1258 /* Make small textures 1D tiled. */
1259 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1260 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1261 return RADEON_SURF_MODE_1D
;
1263 /* The allocator will switch to 1D if needed. */
1264 return RADEON_SURF_MODE_2D
;
1267 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1268 const struct pipe_resource
*templ
)
1270 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1271 struct radeon_surf surface
= {0};
1272 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1273 bool tc_compatible_htile
=
1274 rscreen
->chip_class
>= VI
&&
1275 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1276 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
) &&
1277 !is_flushed_depth
&&
1278 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1279 util_format_is_depth_or_stencil(templ
->format
);
1283 r
= r600_init_surface(rscreen
, &surface
, templ
,
1284 r600_choose_tiling(rscreen
, templ
), 0, 0,
1285 false, false, is_flushed_depth
,
1286 tc_compatible_htile
);
1291 return (struct pipe_resource
*)
1292 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1295 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1296 const struct pipe_resource
*templ
,
1297 struct winsys_handle
*whandle
,
1300 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1301 struct pb_buffer
*buf
= NULL
;
1302 unsigned stride
= 0, offset
= 0;
1303 unsigned array_mode
;
1304 struct radeon_surf surface
;
1306 struct radeon_bo_metadata metadata
= {};
1307 struct r600_texture
*rtex
;
1309 /* Support only 2D textures without mipmaps */
1310 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1311 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1314 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1318 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1320 surface
.pipe_config
= metadata
.pipe_config
;
1321 surface
.bankw
= metadata
.bankw
;
1322 surface
.bankh
= metadata
.bankh
;
1323 surface
.tile_split
= metadata
.tile_split
;
1324 surface
.mtilea
= metadata
.mtilea
;
1325 surface
.num_banks
= metadata
.num_banks
;
1327 if (metadata
.macrotile
== RADEON_LAYOUT_TILED
)
1328 array_mode
= RADEON_SURF_MODE_2D
;
1329 else if (metadata
.microtile
== RADEON_LAYOUT_TILED
)
1330 array_mode
= RADEON_SURF_MODE_1D
;
1332 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1334 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1335 offset
, true, metadata
.scanout
, false, false);
1340 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1344 rtex
->resource
.is_shared
= true;
1345 rtex
->resource
.external_usage
= usage
;
1347 if (rscreen
->apply_opaque_metadata
)
1348 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1350 return &rtex
->resource
.b
.b
;
1353 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1354 struct pipe_resource
*texture
,
1355 struct r600_texture
**staging
)
1357 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1358 struct pipe_resource resource
;
1359 struct r600_texture
**flushed_depth_texture
= staging
?
1360 staging
: &rtex
->flushed_depth_texture
;
1361 enum pipe_format pipe_format
= texture
->format
;
1364 if (rtex
->flushed_depth_texture
)
1365 return true; /* it's ready */
1367 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1368 switch (pipe_format
) {
1369 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1370 /* Save memory by not allocating the S plane. */
1371 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1373 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1374 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1375 /* Save memory bandwidth by not copying the
1376 * stencil part during flush.
1378 * This potentially increases memory bandwidth
1379 * if an application uses both Z and S texturing
1380 * simultaneously (a flushed Z24S8 texture
1381 * would be stored compactly), but how often
1382 * does that really happen?
1384 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1388 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1389 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1391 /* DB->CB copies to an 8bpp surface don't work. */
1392 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1396 memset(&resource
, 0, sizeof(resource
));
1397 resource
.target
= texture
->target
;
1398 resource
.format
= pipe_format
;
1399 resource
.width0
= texture
->width0
;
1400 resource
.height0
= texture
->height0
;
1401 resource
.depth0
= texture
->depth0
;
1402 resource
.array_size
= texture
->array_size
;
1403 resource
.last_level
= texture
->last_level
;
1404 resource
.nr_samples
= texture
->nr_samples
;
1405 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1406 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1407 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1410 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1412 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1413 if (*flushed_depth_texture
== NULL
) {
1414 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1418 (*flushed_depth_texture
)->non_disp_tiling
= false;
1423 * Initialize the pipe_resource descriptor to be of the same size as the box,
1424 * which is supposed to hold a subregion of the texture "orig" at the given
1427 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1428 struct pipe_resource
*orig
,
1429 const struct pipe_box
*box
,
1430 unsigned level
, unsigned flags
)
1432 memset(res
, 0, sizeof(*res
));
1433 res
->format
= orig
->format
;
1434 res
->width0
= box
->width
;
1435 res
->height0
= box
->height
;
1437 res
->array_size
= 1;
1438 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1441 /* We must set the correct texture target and dimensions for a 3D box. */
1442 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1443 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1444 res
->array_size
= box
->depth
;
1446 res
->target
= PIPE_TEXTURE_2D
;
1450 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1451 struct r600_texture
*rtex
,
1452 unsigned transfer_usage
,
1453 const struct pipe_box
*box
)
1455 /* r600g doesn't react to dirty_tex_descriptor_counter */
1456 return rscreen
->chip_class
>= SI
&&
1457 !rtex
->resource
.is_shared
&&
1458 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1459 rtex
->resource
.b
.b
.last_level
== 0 &&
1460 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1461 box
->x
, box
->y
, box
->z
,
1462 box
->width
, box
->height
,
1466 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1467 struct r600_texture
*rtex
)
1469 struct r600_common_screen
*rscreen
= rctx
->screen
;
1471 /* There is no point in discarding depth and tiled buffers. */
1472 assert(!rtex
->is_depth
);
1473 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
);
1475 /* Reallocate the buffer in the same pipe_resource. */
1476 r600_alloc_resource(rscreen
, &rtex
->resource
);
1478 /* Initialize the CMASK base address (needed even without CMASK). */
1479 rtex
->cmask
.base_address_reg
=
1480 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1482 r600_dirty_all_framebuffer_states(rscreen
);
1483 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
1485 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1488 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1489 struct pipe_resource
*texture
,
1492 const struct pipe_box
*box
,
1493 struct pipe_transfer
**ptransfer
)
1495 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1496 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1497 struct r600_transfer
*trans
;
1498 struct r600_resource
*buf
;
1499 unsigned offset
= 0;
1501 bool use_staging_texture
= false;
1503 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1505 /* Depth textures use staging unconditionally. */
1506 if (!rtex
->is_depth
) {
1507 /* Degrade the tile mode if we get too many transfers on APUs.
1508 * On dGPUs, the staging texture is always faster.
1509 * Only count uploads that are at least 4x4 pixels large.
1511 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1513 box
->width
>= 4 && box
->height
>= 4 &&
1514 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1515 bool can_invalidate
=
1516 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1519 r600_degrade_tile_mode_to_linear(rctx
, rtex
,
1523 /* Tiled textures need to be converted into a linear texture for CPU
1524 * access. The staging texture is always linear and is placed in GART.
1526 * Reading from VRAM is slow, always use the staging texture in
1529 * Use the staging texture for uploads if the underlying BO
1532 if (rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
)
1533 use_staging_texture
= true;
1534 else if (usage
& PIPE_TRANSFER_READ
)
1535 use_staging_texture
= (rtex
->resource
.domains
&
1536 RADEON_DOMAIN_VRAM
) != 0;
1537 /* Write & linear only: */
1538 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1539 RADEON_USAGE_READWRITE
) ||
1540 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1541 RADEON_USAGE_READWRITE
)) {
1543 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1545 r600_texture_invalidate_storage(rctx
, rtex
);
1547 use_staging_texture
= true;
1551 trans
= CALLOC_STRUCT(r600_transfer
);
1554 trans
->transfer
.resource
= texture
;
1555 trans
->transfer
.level
= level
;
1556 trans
->transfer
.usage
= usage
;
1557 trans
->transfer
.box
= *box
;
1559 if (rtex
->is_depth
) {
1560 struct r600_texture
*staging_depth
;
1562 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1563 /* MSAA depth buffers need to be converted to single sample buffers.
1565 * Mapping MSAA depth buffers can occur if ReadPixels is called
1566 * with a multisample GLX visual.
1568 * First downsample the depth buffer to a temporary texture,
1569 * then decompress the temporary one to staging.
1571 * Only the region being mapped is transfered.
1573 struct pipe_resource resource
;
1575 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1577 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1578 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1583 if (usage
& PIPE_TRANSFER_READ
) {
1584 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1586 R600_ERR("failed to create a temporary depth texture\n");
1591 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1592 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1593 0, 0, 0, box
->depth
, 0, 0);
1594 pipe_resource_reference(&temp
, NULL
);
1598 /* XXX: only readback the rectangle which is being mapped? */
1599 /* XXX: when discard is true, no need to read back from depth texture */
1600 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1601 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1606 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1608 box
->z
, box
->z
+ box
->depth
- 1,
1611 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1614 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
1615 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
1616 trans
->staging
= (struct r600_resource
*)staging_depth
;
1617 buf
= trans
->staging
;
1618 } else if (use_staging_texture
) {
1619 struct pipe_resource resource
;
1620 struct r600_texture
*staging
;
1622 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1623 R600_RESOURCE_FLAG_TRANSFER
);
1624 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1625 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1627 /* Create the temporary texture. */
1628 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1630 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1634 trans
->staging
= &staging
->resource
;
1635 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
1636 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1638 if (usage
& PIPE_TRANSFER_READ
)
1639 r600_copy_to_staging_texture(ctx
, trans
);
1641 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1643 buf
= trans
->staging
;
1645 /* the resource is mapped directly */
1646 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
1647 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1648 offset
= r600_texture_get_offset(rtex
, level
, box
);
1649 buf
= &rtex
->resource
;
1652 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1653 r600_resource_reference(&trans
->staging
, NULL
);
1658 *ptransfer
= &trans
->transfer
;
1659 return map
+ offset
;
1662 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1663 struct pipe_transfer
* transfer
)
1665 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1666 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1667 struct pipe_resource
*texture
= transfer
->resource
;
1668 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1670 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1671 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1672 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1673 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1674 &rtransfer
->staging
->b
.b
, transfer
->level
,
1677 r600_copy_from_staging_texture(ctx
, rtransfer
);
1681 if (rtransfer
->staging
) {
1682 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1683 r600_resource_reference(&rtransfer
->staging
, NULL
);
1686 /* Heuristic for {upload, draw, upload, draw, ..}:
1688 * Flush the gfx IB if we've allocated too much texture storage.
1690 * The idea is that we don't want to build IBs that use too much
1691 * memory and put pressure on the kernel memory manager and we also
1692 * want to make temporary and invalidated buffers go idle ASAP to
1693 * decrease the total memory usage or make them reusable. The memory
1694 * usage will be slightly higher than given here because of the buffer
1695 * cache in the winsys.
1697 * The result is that the kernel memory manager is never a bottleneck.
1699 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1700 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1701 rctx
->num_alloc_tex_transfer_bytes
= 0;
1707 static const struct u_resource_vtbl r600_texture_vtbl
=
1709 NULL
, /* get_handle */
1710 r600_texture_destroy
, /* resource_destroy */
1711 r600_texture_transfer_map
, /* transfer_map */
1712 u_default_transfer_flush_region
, /* transfer_flush_region */
1713 r600_texture_transfer_unmap
, /* transfer_unmap */
1716 /* DCC channel type categories within which formats can be reinterpreted
1717 * while keeping the same DCC encoding. The swizzle must also match. */
1718 enum dcc_channel_type
{
1719 dcc_channel_float32
,
1722 dcc_channel_float16
,
1725 dcc_channel_uint_10_10_10_2
,
1728 dcc_channel_incompatible
,
1731 /* Return the type of DCC encoding. */
1732 static enum dcc_channel_type
1733 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1737 /* Find the first non-void channel. */
1738 for (i
= 0; i
< desc
->nr_channels
; i
++)
1739 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1741 if (i
== desc
->nr_channels
)
1742 return dcc_channel_incompatible
;
1744 switch (desc
->channel
[i
].size
) {
1746 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1747 return dcc_channel_float32
;
1748 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1749 return dcc_channel_uint32
;
1750 return dcc_channel_sint32
;
1752 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1753 return dcc_channel_float16
;
1754 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1755 return dcc_channel_uint16
;
1756 return dcc_channel_sint16
;
1758 return dcc_channel_uint_10_10_10_2
;
1760 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1761 return dcc_channel_uint8
;
1762 return dcc_channel_sint8
;
1764 return dcc_channel_incompatible
;
1768 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1769 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1770 enum pipe_format format2
)
1772 const struct util_format_description
*desc1
, *desc2
;
1773 enum dcc_channel_type type1
, type2
;
1776 if (format1
== format2
)
1779 desc1
= util_format_description(format1
);
1780 desc2
= util_format_description(format2
);
1782 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1785 /* Swizzles must be the same. */
1786 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1787 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1788 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1789 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1792 type1
= vi_get_dcc_channel_type(desc1
);
1793 type2
= vi_get_dcc_channel_type(desc2
);
1795 return type1
!= dcc_channel_incompatible
&&
1796 type2
!= dcc_channel_incompatible
&&
1800 void vi_dcc_disable_if_incompatible_format(struct r600_common_context
*rctx
,
1801 struct pipe_resource
*tex
,
1803 enum pipe_format view_format
)
1805 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1807 if (rtex
->dcc_offset
&&
1808 rtex
->surface
.level
[level
].dcc_enabled
&&
1809 !vi_dcc_formats_compatible(tex
->format
, view_format
))
1810 if (!r600_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1811 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1814 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1815 struct pipe_resource
*texture
,
1816 const struct pipe_surface
*templ
,
1817 unsigned width
, unsigned height
)
1819 struct r600_common_context
*rctx
= (struct r600_common_context
*)pipe
;
1820 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1821 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1826 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1827 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1829 pipe_reference_init(&surface
->base
.reference
, 1);
1830 pipe_resource_reference(&surface
->base
.texture
, texture
);
1831 surface
->base
.context
= pipe
;
1832 surface
->base
.format
= templ
->format
;
1833 surface
->base
.width
= width
;
1834 surface
->base
.height
= height
;
1835 surface
->base
.u
= templ
->u
;
1836 surface
->level_info
= &rtex
->surface
.level
[templ
->u
.tex
.level
];
1838 if (texture
->target
!= PIPE_BUFFER
)
1839 vi_dcc_disable_if_incompatible_format(rctx
, texture
,
1843 return &surface
->base
;
1846 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1847 struct pipe_resource
*tex
,
1848 const struct pipe_surface
*templ
)
1850 unsigned level
= templ
->u
.tex
.level
;
1851 unsigned width
= u_minify(tex
->width0
, level
);
1852 unsigned height
= u_minify(tex
->height0
, level
);
1854 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1855 const struct util_format_description
*tex_desc
1856 = util_format_description(tex
->format
);
1857 const struct util_format_description
*templ_desc
1858 = util_format_description(templ
->format
);
1860 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1862 /* Adjust size of surface if and only if the block width or
1863 * height is changed. */
1864 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1865 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1866 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1867 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1869 width
= nblks_x
* templ_desc
->block
.width
;
1870 height
= nblks_y
* templ_desc
->block
.height
;
1874 return r600_create_surface_custom(pipe
, tex
, templ
, width
, height
);
1877 static void r600_surface_destroy(struct pipe_context
*pipe
,
1878 struct pipe_surface
*surface
)
1880 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1881 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1882 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1883 pipe_resource_reference(&surface
->texture
, NULL
);
1887 static void r600_clear_texture(struct pipe_context
*pipe
,
1888 struct pipe_resource
*tex
,
1890 const struct pipe_box
*box
,
1893 struct pipe_screen
*screen
= pipe
->screen
;
1894 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1895 struct pipe_surface tmpl
= {{0}};
1896 struct pipe_surface
*sf
;
1897 const struct util_format_description
*desc
=
1898 util_format_description(tex
->format
);
1900 tmpl
.format
= tex
->format
;
1901 tmpl
.u
.tex
.first_layer
= box
->z
;
1902 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
1903 tmpl
.u
.tex
.level
= level
;
1904 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
1908 if (rtex
->is_depth
) {
1911 uint8_t stencil
= 0;
1913 /* Depth is always present. */
1914 clear
= PIPE_CLEAR_DEPTH
;
1915 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
1917 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1918 clear
|= PIPE_CLEAR_STENCIL
;
1919 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
1922 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
1924 box
->width
, box
->height
, false);
1926 union pipe_color_union color
;
1928 /* pipe_color_union requires the full vec4 representation. */
1929 if (util_format_is_pure_uint(tex
->format
))
1930 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
1931 else if (util_format_is_pure_sint(tex
->format
))
1932 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
1934 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
1936 if (screen
->is_format_supported(screen
, tex
->format
,
1938 PIPE_BIND_RENDER_TARGET
)) {
1939 pipe
->clear_render_target(pipe
, sf
, &color
,
1941 box
->width
, box
->height
, false);
1943 /* Software fallback - just for R9G9B9E5_FLOAT */
1944 util_clear_render_target(pipe
, sf
, &color
,
1946 box
->width
, box
->height
);
1949 pipe_surface_reference(&sf
, NULL
);
1952 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1954 const struct util_format_description
*desc
= util_format_description(format
);
1956 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1958 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1959 return V_0280A0_SWAP_STD
;
1961 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1964 switch (desc
->nr_channels
) {
1966 if (HAS_SWIZZLE(0,X
))
1967 return V_0280A0_SWAP_STD
; /* X___ */
1968 else if (HAS_SWIZZLE(3,X
))
1969 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1972 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1973 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1974 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1975 return V_0280A0_SWAP_STD
; /* XY__ */
1976 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1977 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1978 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1980 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
1981 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1982 return V_0280A0_SWAP_ALT
; /* X__Y */
1983 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1984 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1987 if (HAS_SWIZZLE(0,X
))
1988 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
1989 else if (HAS_SWIZZLE(0,Z
))
1990 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1993 /* check the middle channels, the 1st and 4th channel can be NONE */
1994 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
1995 return V_0280A0_SWAP_STD
; /* XYZW */
1996 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
1997 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1998 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
1999 return V_0280A0_SWAP_ALT
; /* ZYXW */
2000 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
2003 return V_0280A0_SWAP_ALT_REV
;
2005 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
2012 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2014 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
2019 if (rctx
->dcc_stats
[slot
].query_active
)
2020 vi_separate_dcc_stop_query(&rctx
->b
,
2021 rctx
->dcc_stats
[slot
].tex
);
2023 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
2024 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2025 rctx
->b
.destroy_query(&rctx
->b
,
2026 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
2027 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2030 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
2034 * Return the per-context slot where DCC statistics queries for the texture live.
2036 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
2037 struct r600_texture
*tex
)
2039 int i
, empty_slot
= -1;
2041 /* Remove zombie textures (textures kept alive by this array only). */
2042 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2043 if (rctx
->dcc_stats
[i
].tex
&&
2044 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
2045 vi_dcc_clean_up_context_slot(rctx
, i
);
2047 /* Find the texture. */
2048 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
2049 /* Return if found. */
2050 if (rctx
->dcc_stats
[i
].tex
== tex
) {
2051 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2055 /* Record the first seen empty slot. */
2056 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2060 /* Not found. Remove the oldest member to make space in the array. */
2061 if (empty_slot
== -1) {
2062 int oldest_slot
= 0;
2064 /* Find the oldest slot. */
2065 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2066 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2067 rctx
->dcc_stats
[i
].last_use_timestamp
)
2070 /* Clean up the oldest slot. */
2071 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2072 empty_slot
= oldest_slot
;
2075 /* Add the texture to the new slot. */
2076 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2077 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2081 static struct pipe_query
*
2082 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2084 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2085 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2087 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2088 return (struct pipe_query
*)query
;
2092 * Called when binding a color buffer.
2094 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2095 struct r600_texture
*tex
)
2097 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2098 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2100 assert(!rctx
->dcc_stats
[i
].query_active
);
2102 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2103 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2105 /* begin or resume the query */
2106 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2107 rctx
->dcc_stats
[i
].query_active
= true;
2111 * Called when unbinding a color buffer.
2113 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2114 struct r600_texture
*tex
)
2116 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2117 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2119 assert(rctx
->dcc_stats
[i
].query_active
);
2120 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2122 /* pause or end the query */
2123 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2124 rctx
->dcc_stats
[i
].query_active
= false;
2127 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2129 /* The minimum number of fullscreen draws per frame that is required
2131 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2134 /* Called by fast clear. */
2135 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2136 struct r600_texture
*tex
)
2138 /* The intent is to use this with shared displayable back buffers,
2139 * but it's not strictly limited only to them.
2141 if (!tex
->resource
.is_shared
||
2142 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2143 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2144 tex
->surface
.last_level
> 0 ||
2145 !tex
->surface
.dcc_size
)
2148 if (tex
->dcc_offset
)
2149 return; /* already enabled */
2151 /* Enable the DCC stat gathering. */
2152 if (!tex
->dcc_gather_statistics
) {
2153 tex
->dcc_gather_statistics
= true;
2154 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2157 if (!vi_should_enable_separate_dcc(tex
))
2158 return; /* stats show that DCC decompression is too expensive */
2160 assert(tex
->surface
.level
[0].dcc_enabled
);
2161 assert(!tex
->dcc_separate_buffer
);
2163 r600_texture_discard_cmask(rctx
->screen
, tex
);
2165 /* Get a DCC buffer. */
2166 if (tex
->last_dcc_separate_buffer
) {
2167 assert(tex
->dcc_gather_statistics
);
2168 assert(!tex
->dcc_separate_buffer
);
2169 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2170 tex
->last_dcc_separate_buffer
= NULL
;
2172 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2173 r600_aligned_buffer_create(rctx
->b
.screen
, 0,
2175 tex
->surface
.dcc_size
,
2176 tex
->surface
.dcc_alignment
);
2177 if (!tex
->dcc_separate_buffer
)
2181 /* dcc_offset is the absolute GPUVM address. */
2182 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2184 /* no need to flag anything since this is called by fast clear that
2185 * flags framebuffer state
2190 * Called by pipe_context::flush_resource, the place where DCC decompression
2193 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2194 struct r600_texture
*tex
)
2196 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2197 struct pipe_query
*tmp
;
2198 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2199 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2200 bool disable
= false;
2202 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2203 union pipe_query_result result
;
2205 /* Read the results. */
2206 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2208 r600_query_hw_reset_buffers(rctx
,
2209 (struct r600_query_hw
*)
2210 rctx
->dcc_stats
[i
].ps_stats
[2]);
2212 /* Compute the approximate number of fullscreen draws. */
2213 tex
->ps_draw_ratio
=
2214 result
.pipeline_statistics
.ps_invocations
/
2215 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2216 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2218 disable
= tex
->dcc_separate_buffer
&&
2219 !vi_should_enable_separate_dcc(tex
);
2222 tex
->num_slow_clears
= 0;
2224 /* stop the statistics query for ps_stats[0] */
2226 vi_separate_dcc_stop_query(ctx
, tex
);
2228 /* Move the queries in the queue by one. */
2229 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2230 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2231 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2232 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2234 /* create and start a new query as ps_stats[0] */
2236 vi_separate_dcc_start_query(ctx
, tex
);
2239 assert(!tex
->last_dcc_separate_buffer
);
2240 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2241 tex
->dcc_separate_buffer
= NULL
;
2242 tex
->dcc_offset
= 0;
2243 /* no need to flag anything since this is called after
2244 * decompression that re-sets framebuffer state
2249 /* FAST COLOR CLEAR */
2251 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2252 enum pipe_format surface_format
,
2253 const union pipe_color_union
*color
)
2255 union util_color uc
;
2257 memset(&uc
, 0, sizeof(uc
));
2259 if (util_format_get_blocksizebits(surface_format
) == 128) {
2260 /* DCC fast clear only:
2261 * CLEAR_WORD0 = R = G = B
2264 assert(color
->ui
[0] == color
->ui
[1] &&
2265 color
->ui
[0] == color
->ui
[2]);
2266 uc
.ui
[0] = color
->ui
[0];
2267 uc
.ui
[1] = color
->ui
[3];
2268 } else if (util_format_is_pure_uint(surface_format
)) {
2269 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2270 } else if (util_format_is_pure_sint(surface_format
)) {
2271 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2273 util_pack_color(color
->f
, surface_format
, &uc
);
2276 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2279 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2280 const union pipe_color_union
*color
,
2281 uint32_t* reset_value
,
2282 bool* clear_words_needed
)
2284 bool values
[4] = {};
2286 bool main_value
= false;
2287 bool extra_value
= false;
2289 const struct util_format_description
*desc
= util_format_description(surface_format
);
2291 if (desc
->block
.bits
== 128 &&
2292 (color
->ui
[0] != color
->ui
[1] ||
2293 color
->ui
[0] != color
->ui
[2]))
2296 *clear_words_needed
= true;
2297 *reset_value
= 0x20202020U
;
2299 /* If we want to clear without needing a fast clear eliminate step, we
2300 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2301 * have two sets of flags, one for the last or first channel(extra) and
2302 * one for the other channels(main).
2305 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2306 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2307 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
2309 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2310 if(r600_translate_colorswap(surface_format
, false) <= 1)
2311 extra_channel
= desc
->nr_channels
- 1;
2317 for (i
= 0; i
< 4; ++i
) {
2318 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2320 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2321 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2324 if (desc
->channel
[i
].pure_integer
&&
2325 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2326 /* Use the maximum value for clamping the clear color. */
2327 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2329 values
[i
] = color
->i
[i
] != 0;
2330 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2332 } else if (desc
->channel
[i
].pure_integer
&&
2333 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2334 /* Use the maximum value for clamping the clear color. */
2335 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2337 values
[i
] = color
->ui
[i
] != 0U;
2338 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2341 values
[i
] = color
->f
[i
] != 0.0F
;
2342 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2346 if (index
== extra_channel
)
2347 extra_value
= values
[i
];
2349 main_value
= values
[i
];
2352 for (int i
= 0; i
< 4; ++i
)
2353 if (values
[i
] != main_value
&&
2354 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2355 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2356 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2359 *clear_words_needed
= false;
2361 *reset_value
|= 0x80808080U
;
2364 *reset_value
|= 0x40404040U
;
2368 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2369 struct r600_texture
*rtex
,
2370 unsigned level
, unsigned clear_value
)
2372 struct pipe_resource
*dcc_buffer
;
2373 uint64_t dcc_offset
;
2375 assert(rtex
->dcc_offset
&& rtex
->surface
.level
[level
].dcc_enabled
);
2377 if (rtex
->dcc_separate_buffer
) {
2378 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2381 dcc_buffer
= &rtex
->resource
.b
.b
;
2382 dcc_offset
= rtex
->dcc_offset
;
2385 dcc_offset
+= rtex
->surface
.level
[level
].dcc_offset
;
2387 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
,
2388 rtex
->surface
.level
[level
].dcc_fast_clear_size
,
2389 clear_value
, R600_COHERENCY_CB_META
);
2392 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2393 * This allows hitting the MSAA resolve fast path, which requires that both
2394 * src and dst micro tile modes match.
2396 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2397 struct r600_texture
*rtex
)
2399 if (rtex
->resource
.is_shared
||
2400 rtex
->surface
.nsamples
<= 1 ||
2401 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2404 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2405 assert(rtex
->surface
.last_level
== 0);
2407 /* These magic numbers were copied from addrlib. It doesn't use any
2408 * definitions for them either. They are all 2D_TILED_THIN1 modes with
2409 * different bpp and micro tile mode.
2411 if (rscreen
->chip_class
>= CIK
) {
2412 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2413 case 0: /* displayable */
2414 rtex
->surface
.tiling_index
[0] = 10;
2417 rtex
->surface
.tiling_index
[0] = 14;
2419 case 3: /* rotated */
2420 rtex
->surface
.tiling_index
[0] = 28;
2422 default: /* depth, thick */
2423 assert(!"unexpected micro mode");
2427 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2428 case 0: /* displayable */
2429 switch (rtex
->surface
.bpe
) {
2431 rtex
->surface
.tiling_index
[0] = 10;
2434 rtex
->surface
.tiling_index
[0] = 11;
2437 rtex
->surface
.tiling_index
[0] = 12;
2442 switch (rtex
->surface
.bpe
) {
2444 rtex
->surface
.tiling_index
[0] = 14;
2447 rtex
->surface
.tiling_index
[0] = 15;
2450 rtex
->surface
.tiling_index
[0] = 16;
2452 default: /* 8, 16 */
2453 rtex
->surface
.tiling_index
[0] = 17;
2457 default: /* depth, thick */
2458 assert(!"unexpected micro mode");
2463 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2465 p_atomic_inc(&rscreen
->dirty_fb_counter
);
2466 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
2469 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2470 struct pipe_framebuffer_state
*fb
,
2471 struct r600_atom
*fb_state
,
2472 unsigned *buffers
, unsigned *dirty_cbufs
,
2473 const union pipe_color_union
*color
)
2477 /* This function is broken in BE, so just disable this path for now */
2478 #ifdef PIPE_ARCH_BIG_ENDIAN
2482 if (rctx
->render_cond
)
2485 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2486 struct r600_texture
*tex
;
2487 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2492 /* if this colorbuffer is not being cleared */
2493 if (!(*buffers
& clear_bit
))
2496 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2498 /* the clear is allowed if all layers are bound */
2499 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2500 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2504 /* cannot clear mipmapped textures */
2505 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2509 /* only supported on tiled surfaces */
2510 if (tex
->surface
.level
[0].mode
< RADEON_SURF_MODE_1D
) {
2514 /* shared textures can't use fast clear without an explicit flush,
2515 * because there is no way to communicate the clear color among
2518 if (tex
->resource
.is_shared
&&
2519 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2522 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2523 if (tex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2524 rctx
->chip_class
>= CIK
&&
2525 rctx
->screen
->info
.drm_major
== 2 &&
2526 rctx
->screen
->info
.drm_minor
< 38) {
2530 /* Fast clear is the most appropriate place to enable DCC for
2531 * displayable surfaces.
2533 if (rctx
->chip_class
>= VI
&&
2534 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2535 vi_separate_dcc_try_enable(rctx
, tex
);
2537 /* Stoney can't do a CMASK-based clear, so all clears are
2538 * considered to be hypothetically slow clears, which
2539 * is weighed when determining to enable separate DCC.
2541 if (tex
->dcc_gather_statistics
&&
2542 rctx
->family
== CHIP_STONEY
)
2543 tex
->num_slow_clears
++;
2546 /* Try to clear DCC first, otherwise try CMASK. */
2547 if (tex
->dcc_offset
&& tex
->surface
.level
[0].dcc_enabled
) {
2548 uint32_t reset_value
;
2549 bool clear_words_needed
;
2551 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2554 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2555 color
, &reset_value
,
2556 &clear_words_needed
))
2559 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2561 if (clear_words_needed
)
2562 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2563 tex
->separate_dcc_dirty
= true;
2565 /* 128-bit formats are unusupported */
2566 if (util_format_get_blocksizebits(fb
->cbufs
[i
]->format
) > 64) {
2570 /* Stoney/RB+ doesn't work with CMASK fast clear. */
2571 if (rctx
->family
== CHIP_STONEY
)
2574 /* ensure CMASK is enabled */
2575 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2576 if (tex
->cmask
.size
== 0) {
2580 /* Do the fast clear. */
2581 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2582 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2583 R600_COHERENCY_CB_META
);
2585 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2588 /* We can change the micro tile mode before a full clear. */
2589 if (rctx
->screen
->chip_class
>= SI
)
2590 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2592 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2595 *dirty_cbufs
|= 1 << i
;
2596 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2597 *buffers
&= ~clear_bit
;
2601 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2603 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2604 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2607 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2609 rctx
->b
.create_surface
= r600_create_surface
;
2610 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2611 rctx
->b
.clear_texture
= r600_clear_texture
;