2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "util/u_format.h"
30 #include "util/u_memory.h"
31 #include "util/u_pack_color.h"
35 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
36 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
37 struct pipe_resource
*dst
,
39 unsigned dstx
, unsigned dsty
, unsigned dstz
,
40 struct pipe_resource
*src
,
42 const struct pipe_box
*src_box
)
44 struct pipe_blit_info blit
;
46 memset(&blit
, 0, sizeof(blit
));
47 blit
.src
.resource
= src
;
48 blit
.src
.format
= src
->format
;
49 blit
.src
.level
= src_level
;
50 blit
.src
.box
= *src_box
;
51 blit
.dst
.resource
= dst
;
52 blit
.dst
.format
= dst
->format
;
53 blit
.dst
.level
= dst_level
;
54 blit
.dst
.box
.x
= dstx
;
55 blit
.dst
.box
.y
= dsty
;
56 blit
.dst
.box
.z
= dstz
;
57 blit
.dst
.box
.width
= src_box
->width
;
58 blit
.dst
.box
.height
= src_box
->height
;
59 blit
.dst
.box
.depth
= src_box
->depth
;
60 blit
.mask
= util_format_get_mask(src
->format
) &
61 util_format_get_mask(dst
->format
);
62 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
65 pipe
->blit(pipe
, &blit
);
69 /* Copy from a full GPU texture to a transfer's staging one. */
70 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
72 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
73 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
74 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
75 struct pipe_resource
*src
= transfer
->resource
;
77 if (src
->nr_samples
> 1) {
78 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
79 src
, transfer
->level
, &transfer
->box
);
83 if (!rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0,
86 ctx
->resource_copy_region(ctx
, dst
, 0, 0, 0, 0,
87 src
, transfer
->level
, &transfer
->box
);
91 /* Copy from a transfer's staging texture to a full GPU one. */
92 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
94 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
95 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
96 struct pipe_resource
*dst
= transfer
->resource
;
97 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
100 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
102 if (dst
->nr_samples
> 1) {
103 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
104 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
109 if (!rctx
->dma_copy(ctx
, dst
, transfer
->level
,
110 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
112 ctx
->resource_copy_region(ctx
, dst
, transfer
->level
,
113 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
118 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
119 const struct pipe_box
*box
)
121 enum pipe_format format
= rtex
->resource
.b
.b
.format
;
123 return rtex
->surface
.level
[level
].offset
+
124 box
->z
* rtex
->surface
.level
[level
].slice_size
+
125 box
->y
/ util_format_get_blockheight(format
) * rtex
->surface
.level
[level
].pitch_bytes
+
126 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
129 static int r600_init_surface(struct r600_common_screen
*rscreen
,
130 struct radeon_surface
*surface
,
131 const struct pipe_resource
*ptex
,
133 bool is_flushed_depth
)
135 const struct util_format_description
*desc
=
136 util_format_description(ptex
->format
);
137 bool is_depth
, is_stencil
;
139 is_depth
= util_format_has_depth(desc
);
140 is_stencil
= util_format_has_stencil(desc
);
142 surface
->npix_x
= ptex
->width0
;
143 surface
->npix_y
= ptex
->height0
;
144 surface
->npix_z
= ptex
->depth0
;
145 surface
->blk_w
= util_format_get_blockwidth(ptex
->format
);
146 surface
->blk_h
= util_format_get_blockheight(ptex
->format
);
148 surface
->array_size
= 1;
149 surface
->last_level
= ptex
->last_level
;
151 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
152 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
153 surface
->bpe
= 4; /* stencil is allocated separately on evergreen */
155 surface
->bpe
= util_format_get_blocksize(ptex
->format
);
156 /* align byte per element on dword */
157 if (surface
->bpe
== 3) {
162 surface
->nsamples
= ptex
->nr_samples
? ptex
->nr_samples
: 1;
163 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
165 switch (ptex
->target
) {
166 case PIPE_TEXTURE_1D
:
167 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
169 case PIPE_TEXTURE_RECT
:
170 case PIPE_TEXTURE_2D
:
171 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
173 case PIPE_TEXTURE_3D
:
174 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
176 case PIPE_TEXTURE_1D_ARRAY
:
177 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
178 surface
->array_size
= ptex
->array_size
;
180 case PIPE_TEXTURE_2D_ARRAY
:
181 case PIPE_TEXTURE_CUBE_ARRAY
: /* cube array layout like 2d array */
182 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
183 surface
->array_size
= ptex
->array_size
;
185 case PIPE_TEXTURE_CUBE
:
186 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP
, TYPE
);
192 if (ptex
->bind
& PIPE_BIND_SCANOUT
) {
193 surface
->flags
|= RADEON_SURF_SCANOUT
;
196 if (!is_flushed_depth
&& is_depth
) {
197 surface
->flags
|= RADEON_SURF_ZBUFFER
;
200 surface
->flags
|= RADEON_SURF_SBUFFER
|
201 RADEON_SURF_HAS_SBUFFER_MIPTREE
;
204 if (rscreen
->chip_class
>= SI
) {
205 surface
->flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
210 static int r600_setup_surface(struct pipe_screen
*screen
,
211 struct r600_texture
*rtex
,
212 unsigned pitch_in_bytes_override
)
214 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
217 r
= rscreen
->ws
->surface_init(rscreen
->ws
, &rtex
->surface
);
222 rtex
->size
= rtex
->surface
.bo_size
;
224 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= rtex
->surface
.level
[0].pitch_bytes
) {
225 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
228 rtex
->surface
.level
[0].nblk_x
= pitch_in_bytes_override
/ rtex
->surface
.bpe
;
229 rtex
->surface
.level
[0].pitch_bytes
= pitch_in_bytes_override
;
230 rtex
->surface
.level
[0].slice_size
= pitch_in_bytes_override
* rtex
->surface
.level
[0].nblk_y
;
231 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
232 rtex
->surface
.stencil_offset
=
233 rtex
->surface
.stencil_level
[0].offset
= rtex
->surface
.level
[0].slice_size
;
239 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
240 struct pipe_resource
*ptex
,
241 struct winsys_handle
*whandle
)
243 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
244 struct r600_resource
*resource
= &rtex
->resource
;
245 struct radeon_surface
*surface
= &rtex
->surface
;
246 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
248 rscreen
->ws
->buffer_set_tiling(resource
->buf
,
250 surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
251 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
252 surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
253 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
,
254 surface
->bankw
, surface
->bankh
,
256 surface
->stencil_tile_split
,
258 surface
->level
[0].pitch_bytes
,
259 (surface
->flags
& RADEON_SURF_SCANOUT
) != 0);
261 return rscreen
->ws
->buffer_get_handle(resource
->buf
,
262 surface
->level
[0].pitch_bytes
, whandle
);
265 static void r600_texture_destroy(struct pipe_screen
*screen
,
266 struct pipe_resource
*ptex
)
268 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
269 struct r600_resource
*resource
= &rtex
->resource
;
271 if (rtex
->flushed_depth_texture
)
272 pipe_resource_reference((struct pipe_resource
**)&rtex
->flushed_depth_texture
, NULL
);
274 pipe_resource_reference((struct pipe_resource
**)&rtex
->htile_buffer
, NULL
);
275 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
276 pipe_resource_reference((struct pipe_resource
**)&rtex
->cmask_buffer
, NULL
);
278 pb_reference(&resource
->buf
, NULL
);
282 static const struct u_resource_vtbl r600_texture_vtbl
;
284 /* The number of samples can be specified independently of the texture. */
285 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
286 struct r600_texture
*rtex
,
288 struct r600_fmask_info
*out
)
290 /* FMASK is allocated like an ordinary texture. */
291 struct radeon_surface fmask
= rtex
->surface
;
293 memset(out
, 0, sizeof(*out
));
295 fmask
.bo_alignment
= 0;
298 fmask
.flags
|= RADEON_SURF_FMASK
;
300 if (rscreen
->chip_class
>= SI
) {
301 fmask
.flags
|= RADEON_SURF_HAS_TILE_MODE_INDEX
;
304 switch (nr_samples
) {
308 if (rscreen
->chip_class
<= CAYMAN
) {
316 R600_ERR("Invalid sample count for FMASK allocation.\n");
320 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
321 * This can be fixed by writing a separate FMASK allocator specifically
322 * for R600-R700 asics. */
323 if (rscreen
->chip_class
<= R700
) {
327 if (rscreen
->ws
->surface_init(rscreen
->ws
, &fmask
)) {
328 R600_ERR("Got error in surface_init while allocating FMASK.\n");
332 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
334 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
335 if (out
->slice_tile_max
)
336 out
->slice_tile_max
-= 1;
338 out
->tile_mode_index
= fmask
.tiling_index
[0];
339 out
->pitch
= fmask
.level
[0].nblk_x
;
340 out
->bank_height
= fmask
.bankh
;
341 out
->alignment
= MAX2(256, fmask
.bo_alignment
);
342 out
->size
= fmask
.bo_size
;
345 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
346 struct r600_texture
*rtex
)
348 r600_texture_get_fmask_info(rscreen
, rtex
,
349 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
351 rtex
->fmask
.offset
= align(rtex
->size
, rtex
->fmask
.alignment
);
352 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
355 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
356 struct r600_texture
*rtex
,
357 struct r600_cmask_info
*out
)
359 unsigned cmask_tile_width
= 8;
360 unsigned cmask_tile_height
= 8;
361 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
362 unsigned element_bits
= 4;
363 unsigned cmask_cache_bits
= 1024;
364 unsigned num_pipes
= rscreen
->tiling_info
.num_channels
;
365 unsigned pipe_interleave_bytes
= rscreen
->tiling_info
.group_bytes
;
367 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
368 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
369 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
370 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
371 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
373 unsigned pitch_elements
= align(rtex
->surface
.npix_x
, macro_tile_width
);
374 unsigned height
= align(rtex
->surface
.npix_y
, macro_tile_height
);
376 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
377 unsigned slice_bytes
=
378 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
380 assert(macro_tile_width
% 128 == 0);
381 assert(macro_tile_height
% 128 == 0);
383 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
384 out
->alignment
= MAX2(256, base_align
);
385 out
->size
= rtex
->surface
.array_size
* align(slice_bytes
, base_align
);
388 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
389 struct r600_texture
*rtex
,
390 struct r600_cmask_info
*out
)
392 unsigned pipe_interleave_bytes
= rscreen
->tiling_info
.group_bytes
;
393 unsigned num_pipes
= rscreen
->tiling_info
.num_channels
;
394 unsigned cl_width
, cl_height
;
409 case 16: /* Hawaii */
418 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
420 unsigned width
= align(rtex
->surface
.npix_x
, cl_width
*8);
421 unsigned height
= align(rtex
->surface
.npix_y
, cl_height
*8);
422 unsigned slice_elements
= (width
* height
) / (8*8);
424 /* Each element of CMASK is a nibble. */
425 unsigned slice_bytes
= slice_elements
/ 2;
427 out
->slice_tile_max
= (width
* height
) / (128*128);
428 if (out
->slice_tile_max
)
429 out
->slice_tile_max
-= 1;
431 out
->alignment
= MAX2(256, base_align
);
432 out
->size
= rtex
->surface
.array_size
* align(slice_bytes
, base_align
);
435 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
436 struct r600_texture
*rtex
)
438 if (rscreen
->chip_class
>= SI
) {
439 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
441 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
444 rtex
->cmask
.offset
= align(rtex
->size
, rtex
->cmask
.alignment
);
445 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
447 if (rscreen
->chip_class
>= SI
)
448 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
450 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
453 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
454 struct r600_texture
*rtex
)
456 if (rtex
->cmask_buffer
)
459 assert(rtex
->cmask
.size
== 0);
461 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
463 rtex
->cmask_buffer
= (struct r600_resource
*)
464 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
465 PIPE_USAGE_DEFAULT
, rtex
->cmask
.size
);
466 if (rtex
->cmask_buffer
== NULL
) {
467 rtex
->cmask
.size
= 0;
471 /* update colorbuffer state bits */
472 rtex
->cmask
.base_address_reg
=
473 r600_resource_va(&rscreen
->b
, &rtex
->cmask_buffer
->b
.b
) >> 8;
475 if (rscreen
->chip_class
>= SI
)
476 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
478 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
481 static unsigned si_texture_htile_alloc_size(struct r600_common_screen
*rscreen
,
482 struct r600_texture
*rtex
)
484 unsigned cl_width
, cl_height
, width
, height
;
485 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
486 unsigned num_pipes
= rscreen
->tiling_info
.num_channels
;
488 /* HTILE doesn't work with 1D tiling (there's massive corruption
490 if (rtex
->surface
.level
[0].mode
!= RADEON_SURF_MODE_2D
)
515 width
= align(rtex
->surface
.npix_x
, cl_width
* 8);
516 height
= align(rtex
->surface
.npix_y
, cl_height
* 8);
518 slice_elements
= (width
* height
) / (8 * 8);
519 slice_bytes
= slice_elements
* 4;
521 pipe_interleave_bytes
= rscreen
->tiling_info
.group_bytes
;
522 base_align
= num_pipes
* pipe_interleave_bytes
;
524 return rtex
->surface
.array_size
* align(slice_bytes
, base_align
);
527 static unsigned r600_texture_htile_alloc_size(struct r600_common_screen
*rscreen
,
528 struct r600_texture
*rtex
)
530 unsigned sw
= rtex
->surface
.level
[0].nblk_x
* rtex
->surface
.blk_w
;
531 unsigned sh
= rtex
->surface
.level
[0].nblk_y
* rtex
->surface
.blk_h
;
532 unsigned npipes
= rscreen
->info
.r600_num_tile_pipes
;
535 /* XXX also use it for other texture targets */
536 if (rscreen
->info
.drm_minor
< 26 ||
537 rtex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
538 rtex
->surface
.level
[0].nblk_x
< 32 ||
539 rtex
->surface
.level
[0].nblk_y
< 32) {
543 /* this alignment and htile size only apply to linear htile buffer */
544 sw
= align(sw
, 16 << 3);
545 sh
= align(sh
, npipes
<< 3);
546 htile_size
= (sw
>> 3) * (sh
>> 3) * 4;
547 /* must be aligned with 2K * npipes */
548 htile_size
= align(htile_size
, (2 << 10) * npipes
);
552 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
553 struct r600_texture
*rtex
)
556 if (rscreen
->chip_class
>= SI
) {
557 htile_size
= si_texture_htile_alloc_size(rscreen
, rtex
);
559 htile_size
= r600_texture_htile_alloc_size(rscreen
, rtex
);
565 /* XXX don't allocate it separately */
566 rtex
->htile_buffer
= (struct r600_resource
*)
567 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
568 PIPE_USAGE_DEFAULT
, htile_size
);
569 if (rtex
->htile_buffer
== NULL
) {
570 /* this is not a fatal error as we can still keep rendering
571 * without htile buffer */
572 R600_ERR("Failed to create buffer object for htile buffer.\n");
574 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
, 0, htile_size
, 0);
578 /* Common processing for r600_texture_create and r600_texture_from_handle */
579 static struct r600_texture
*
580 r600_texture_create_object(struct pipe_screen
*screen
,
581 const struct pipe_resource
*base
,
582 unsigned pitch_in_bytes_override
,
583 struct pb_buffer
*buf
,
584 struct radeon_surface
*surface
)
586 struct r600_texture
*rtex
;
587 struct r600_resource
*resource
;
588 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
591 rtex
= CALLOC_STRUCT(r600_texture
);
595 resource
= &rtex
->resource
;
596 resource
->b
.b
= *base
;
597 resource
->b
.vtbl
= &r600_texture_vtbl
;
598 pipe_reference_init(&resource
->b
.b
.reference
, 1);
599 resource
->b
.b
.screen
= screen
;
600 rtex
->pitch_override
= pitch_in_bytes_override
;
602 /* don't include stencil-only formats which we don't support for rendering */
603 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
605 rtex
->surface
= *surface
;
606 if (r600_setup_surface(screen
, rtex
, pitch_in_bytes_override
)) {
611 /* Tiled depth textures utilize the non-displayable tile order.
612 * This must be done after r600_setup_surface.
613 * Applies to R600-Cayman. */
614 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
616 if (rtex
->is_depth
) {
617 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
618 R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) &&
619 (rscreen
->debug_flags
& DBG_HYPERZ
)) {
621 r600_texture_allocate_htile(rscreen
, rtex
);
624 if (base
->nr_samples
> 1) {
626 r600_texture_allocate_fmask(rscreen
, rtex
);
627 r600_texture_allocate_cmask(rscreen
, rtex
);
628 rtex
->cmask_buffer
= &rtex
->resource
;
630 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
637 /* Now create the backing buffer. */
639 if (!r600_init_resource(rscreen
, resource
, rtex
->size
,
640 rtex
->surface
.bo_alignment
, FALSE
)) {
646 resource
->cs_buf
= rscreen
->ws
->buffer_get_cs_handle(buf
);
647 resource
->domains
= RADEON_DOMAIN_GTT
| RADEON_DOMAIN_VRAM
;
650 if (rtex
->cmask
.size
) {
651 /* Initialize the cmask to 0xCC (= compressed state). */
652 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
653 rtex
->cmask
.offset
, rtex
->cmask
.size
, 0xCCCCCCCC);
656 /* Initialize the CMASK base register value. */
657 va
= r600_resource_va(&rscreen
->b
, &rtex
->resource
.b
.b
);
658 rtex
->cmask
.base_address_reg
= (va
+ rtex
->cmask
.offset
) >> 8;
660 if (rscreen
->debug_flags
& DBG_VM
) {
661 fprintf(stderr
, "VM start=0x%"PRIu64
" end=0x%"PRIu64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
662 r600_resource_va(screen
, &rtex
->resource
.b
.b
),
663 r600_resource_va(screen
, &rtex
->resource
.b
.b
) + rtex
->resource
.buf
->size
,
664 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
665 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
668 if (rscreen
->debug_flags
& DBG_TEX
||
669 (rtex
->resource
.b
.b
.last_level
> 0 && rscreen
->debug_flags
& DBG_TEXMIP
)) {
670 printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
671 "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
672 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
673 rtex
->surface
.npix_x
, rtex
->surface
.npix_y
,
674 rtex
->surface
.npix_z
, rtex
->surface
.blk_w
,
675 rtex
->surface
.blk_h
, rtex
->surface
.blk_d
,
676 rtex
->surface
.array_size
, rtex
->surface
.last_level
,
677 rtex
->surface
.bpe
, rtex
->surface
.nsamples
,
678 rtex
->surface
.flags
, util_format_short_name(base
->format
));
679 for (int i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
680 printf(" L %i: offset=%"PRIu64
", slice_size=%"PRIu64
", npix_x=%u, "
681 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
682 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
683 i
, rtex
->surface
.level
[i
].offset
,
684 rtex
->surface
.level
[i
].slice_size
,
685 u_minify(rtex
->resource
.b
.b
.width0
, i
),
686 u_minify(rtex
->resource
.b
.b
.height0
, i
),
687 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
688 rtex
->surface
.level
[i
].nblk_x
,
689 rtex
->surface
.level
[i
].nblk_y
,
690 rtex
->surface
.level
[i
].nblk_z
,
691 rtex
->surface
.level
[i
].pitch_bytes
,
692 rtex
->surface
.level
[i
].mode
);
694 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
695 for (int i
= 0; i
<= rtex
->surface
.last_level
; i
++) {
696 printf(" S %i: offset=%"PRIu64
", slice_size=%"PRIu64
", npix_x=%u, "
697 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
698 "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
699 i
, rtex
->surface
.stencil_level
[i
].offset
,
700 rtex
->surface
.stencil_level
[i
].slice_size
,
701 u_minify(rtex
->resource
.b
.b
.width0
, i
),
702 u_minify(rtex
->resource
.b
.b
.height0
, i
),
703 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
704 rtex
->surface
.stencil_level
[i
].nblk_x
,
705 rtex
->surface
.stencil_level
[i
].nblk_y
,
706 rtex
->surface
.stencil_level
[i
].nblk_z
,
707 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
708 rtex
->surface
.stencil_level
[i
].mode
);
715 static unsigned r600_choose_tiling(struct r600_common_screen
*rscreen
,
716 const struct pipe_resource
*templ
)
718 const struct util_format_description
*desc
= util_format_description(templ
->format
);
720 /* MSAA resources must be 2D tiled. */
721 if (templ
->nr_samples
> 1)
722 return RADEON_SURF_MODE_2D
;
724 /* Transfer resources should be linear. */
725 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
726 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
728 /* Handle common candidates for the linear mode.
729 * Compressed textures must always be tiled. */
730 if (!(templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
) &&
731 !util_format_is_compressed(templ
->format
)) {
732 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600-Cayman. */
733 if (rscreen
->chip_class
<= CAYMAN
&&
734 desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
735 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
737 /* Cursors are linear on SI.
738 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
739 if (rscreen
->chip_class
>= SI
&&
740 (templ
->bind
& PIPE_BIND_CURSOR
))
741 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
743 if (templ
->bind
& PIPE_BIND_LINEAR
)
744 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
746 /* Textures with a very small height are recommended to be linear. */
747 if (templ
->target
== PIPE_TEXTURE_1D
||
748 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
750 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
752 /* Textures likely to be mapped often. */
753 if (templ
->usage
== PIPE_USAGE_STAGING
||
754 templ
->usage
== PIPE_USAGE_STREAM
)
755 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
758 /* Make small textures 1D tiled. */
759 if (templ
->width0
<= 16 || templ
->height0
<= 16)
760 return RADEON_SURF_MODE_1D
;
762 /* The allocator will switch to 1D if needed. */
763 return RADEON_SURF_MODE_2D
;
766 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
767 const struct pipe_resource
*templ
)
769 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
770 struct radeon_surface surface
= {0};
773 r
= r600_init_surface(rscreen
, &surface
, templ
,
774 r600_choose_tiling(rscreen
, templ
),
775 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
779 r
= rscreen
->ws
->surface_best(rscreen
->ws
, &surface
);
783 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
787 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
788 const struct pipe_resource
*templ
,
789 struct winsys_handle
*whandle
)
791 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
792 struct pb_buffer
*buf
= NULL
;
795 enum radeon_bo_layout micro
, macro
;
796 struct radeon_surface surface
;
800 /* Support only 2D textures without mipmaps */
801 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
802 templ
->depth0
!= 1 || templ
->last_level
!= 0)
805 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
);
809 rscreen
->ws
->buffer_get_tiling(buf
, µ
, ¯o
,
810 &surface
.bankw
, &surface
.bankh
,
812 &surface
.stencil_tile_split
,
813 &surface
.mtilea
, &scanout
);
815 if (macro
== RADEON_LAYOUT_TILED
)
816 array_mode
= RADEON_SURF_MODE_2D
;
817 else if (micro
== RADEON_LAYOUT_TILED
)
818 array_mode
= RADEON_SURF_MODE_1D
;
820 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
822 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, false);
828 surface
.flags
|= RADEON_SURF_SCANOUT
;
830 return (struct pipe_resource
*)r600_texture_create_object(screen
, templ
,
831 stride
, buf
, &surface
);
834 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
835 struct pipe_resource
*texture
,
836 struct r600_texture
**staging
)
838 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
839 struct pipe_resource resource
;
840 struct r600_texture
**flushed_depth_texture
= staging
?
841 staging
: &rtex
->flushed_depth_texture
;
843 if (!staging
&& rtex
->flushed_depth_texture
)
844 return true; /* it's ready */
846 resource
.target
= texture
->target
;
847 resource
.format
= texture
->format
;
848 resource
.width0
= texture
->width0
;
849 resource
.height0
= texture
->height0
;
850 resource
.depth0
= texture
->depth0
;
851 resource
.array_size
= texture
->array_size
;
852 resource
.last_level
= texture
->last_level
;
853 resource
.nr_samples
= texture
->nr_samples
;
854 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
855 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
856 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
859 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
861 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
862 if (*flushed_depth_texture
== NULL
) {
863 R600_ERR("failed to create temporary texture to hold flushed depth\n");
867 (*flushed_depth_texture
)->is_flushing_texture
= TRUE
;
868 (*flushed_depth_texture
)->non_disp_tiling
= false;
873 * Initialize the pipe_resource descriptor to be of the same size as the box,
874 * which is supposed to hold a subregion of the texture "orig" at the given
877 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
878 struct pipe_resource
*orig
,
879 const struct pipe_box
*box
,
880 unsigned level
, unsigned flags
)
882 memset(res
, 0, sizeof(*res
));
883 res
->format
= orig
->format
;
884 res
->width0
= box
->width
;
885 res
->height0
= box
->height
;
888 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
891 /* We must set the correct texture target and dimensions for a 3D box. */
892 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0)
893 res
->target
= orig
->target
;
895 res
->target
= PIPE_TEXTURE_2D
;
897 switch (res
->target
) {
898 case PIPE_TEXTURE_1D_ARRAY
:
899 case PIPE_TEXTURE_2D_ARRAY
:
900 case PIPE_TEXTURE_CUBE_ARRAY
:
901 res
->array_size
= box
->depth
;
903 case PIPE_TEXTURE_3D
:
904 res
->depth0
= box
->depth
;
910 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
911 struct pipe_resource
*texture
,
914 const struct pipe_box
*box
,
915 struct pipe_transfer
**ptransfer
)
917 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
918 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
919 struct r600_transfer
*trans
;
920 boolean use_staging_texture
= FALSE
;
921 struct r600_resource
*buf
;
925 /* We cannot map a tiled texture directly because the data is
926 * in a different order, therefore we do detiling using a blit.
928 * Also, use a temporary in GTT memory for read transfers, as
929 * the CPU is much happier reading out of cached system memory
930 * than uncached VRAM.
932 if (rtex
->surface
.level
[level
].mode
>= RADEON_SURF_MODE_1D
)
933 use_staging_texture
= TRUE
;
935 /* Untiled buffers in VRAM, which is slow for CPU reads and writes */
936 if (!(usage
& PIPE_TRANSFER_MAP_DIRECTLY
) &&
937 (rtex
->resource
.domains
== RADEON_DOMAIN_VRAM
)) {
938 use_staging_texture
= TRUE
;
941 /* Use a staging texture for uploads if the underlying BO is busy. */
942 if (!(usage
& PIPE_TRANSFER_READ
) &&
943 (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.cs_buf
, RADEON_USAGE_READWRITE
) ||
944 rctx
->ws
->buffer_is_busy(rtex
->resource
.buf
, RADEON_USAGE_READWRITE
))) {
945 use_staging_texture
= TRUE
;
948 if (texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
) {
949 use_staging_texture
= FALSE
;
952 if (use_staging_texture
&& (usage
& PIPE_TRANSFER_MAP_DIRECTLY
)) {
956 trans
= CALLOC_STRUCT(r600_transfer
);
959 trans
->transfer
.resource
= texture
;
960 trans
->transfer
.level
= level
;
961 trans
->transfer
.usage
= usage
;
962 trans
->transfer
.box
= *box
;
964 if (rtex
->is_depth
) {
965 struct r600_texture
*staging_depth
;
967 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
968 /* MSAA depth buffers need to be converted to single sample buffers.
970 * Mapping MSAA depth buffers can occur if ReadPixels is called
971 * with a multisample GLX visual.
973 * First downsample the depth buffer to a temporary texture,
974 * then decompress the temporary one to staging.
976 * Only the region being mapped is transfered.
978 struct pipe_resource resource
;
980 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
982 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
983 R600_ERR("failed to create temporary texture to hold untiled copy\n");
988 if (usage
& PIPE_TRANSFER_READ
) {
989 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
991 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
992 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
993 0, 0, 0, box
->depth
, 0, 0);
994 pipe_resource_reference((struct pipe_resource
**)&temp
, NULL
);
998 /* XXX: only readback the rectangle which is being mapped? */
999 /* XXX: when discard is true, no need to read back from depth texture */
1000 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1001 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1006 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1008 box
->z
, box
->z
+ box
->depth
- 1,
1011 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1014 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
1015 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
1016 trans
->staging
= (struct r600_resource
*)staging_depth
;
1017 } else if (use_staging_texture
) {
1018 struct pipe_resource resource
;
1019 struct r600_texture
*staging
;
1021 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1022 R600_RESOURCE_FLAG_TRANSFER
);
1024 /* Create the temporary texture. */
1025 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1026 if (staging
== NULL
) {
1027 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1031 trans
->staging
= &staging
->resource
;
1032 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
1033 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1034 if (usage
& PIPE_TRANSFER_READ
) {
1035 r600_copy_to_staging_texture(ctx
, trans
);
1038 /* the resource is mapped directly */
1039 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
1040 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1041 offset
= r600_texture_get_offset(rtex
, level
, box
);
1044 if (trans
->staging
) {
1045 buf
= trans
->staging
;
1047 buf
= &rtex
->resource
;
1050 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1051 pipe_resource_reference((struct pipe_resource
**)&trans
->staging
, NULL
);
1056 *ptransfer
= &trans
->transfer
;
1057 return map
+ offset
;
1060 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1061 struct pipe_transfer
* transfer
)
1063 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1064 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1065 struct radeon_winsys_cs_handle
*buf
;
1066 struct pipe_resource
*texture
= transfer
->resource
;
1067 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1069 if (rtransfer
->staging
) {
1070 buf
= rtransfer
->staging
->cs_buf
;
1072 buf
= r600_resource(transfer
->resource
)->cs_buf
;
1074 rctx
->ws
->buffer_unmap(buf
);
1076 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1077 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1078 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1079 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1080 &rtransfer
->staging
->b
.b
, transfer
->level
,
1083 r600_copy_from_staging_texture(ctx
, rtransfer
);
1087 if (rtransfer
->staging
)
1088 pipe_resource_reference((struct pipe_resource
**)&rtransfer
->staging
, NULL
);
1093 static const struct u_resource_vtbl r600_texture_vtbl
=
1095 NULL
, /* get_handle */
1096 r600_texture_destroy
, /* resource_destroy */
1097 r600_texture_transfer_map
, /* transfer_map */
1098 NULL
, /* transfer_flush_region */
1099 r600_texture_transfer_unmap
, /* transfer_unmap */
1100 NULL
/* transfer_inline_write */
1103 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1104 struct pipe_resource
*texture
,
1105 const struct pipe_surface
*templ
,
1106 unsigned width
, unsigned height
)
1108 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1110 if (surface
== NULL
)
1113 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1114 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1116 pipe_reference_init(&surface
->base
.reference
, 1);
1117 pipe_resource_reference(&surface
->base
.texture
, texture
);
1118 surface
->base
.context
= pipe
;
1119 surface
->base
.format
= templ
->format
;
1120 surface
->base
.width
= width
;
1121 surface
->base
.height
= height
;
1122 surface
->base
.u
= templ
->u
;
1123 return &surface
->base
;
1126 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1127 struct pipe_resource
*tex
,
1128 const struct pipe_surface
*templ
)
1130 unsigned level
= templ
->u
.tex
.level
;
1132 return r600_create_surface_custom(pipe
, tex
, templ
,
1133 u_minify(tex
->width0
, level
),
1134 u_minify(tex
->height0
, level
));
1137 static void r600_surface_destroy(struct pipe_context
*pipe
,
1138 struct pipe_surface
*surface
)
1140 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1141 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_fmask
, NULL
);
1142 pipe_resource_reference((struct pipe_resource
**)&surf
->cb_buffer_cmask
, NULL
);
1143 pipe_resource_reference(&surface
->texture
, NULL
);
1147 unsigned r600_translate_colorswap(enum pipe_format format
)
1149 const struct util_format_description
*desc
= util_format_description(format
);
1151 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
1153 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1154 return V_0280A0_SWAP_STD
;
1156 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1159 switch (desc
->nr_channels
) {
1161 if (HAS_SWIZZLE(0,X
))
1162 return V_0280A0_SWAP_STD
; /* X___ */
1163 else if (HAS_SWIZZLE(3,X
))
1164 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1167 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1168 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1169 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1170 return V_0280A0_SWAP_STD
; /* XY__ */
1171 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1172 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1173 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1174 return V_0280A0_SWAP_STD_REV
; /* YX__ */
1175 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1176 return V_0280A0_SWAP_ALT
; /* X__Y */
1177 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1178 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1181 if (HAS_SWIZZLE(0,X
))
1182 return V_0280A0_SWAP_STD
; /* XYZ */
1183 else if (HAS_SWIZZLE(0,Z
))
1184 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1187 /* check the middle channels, the 1st and 4th channel can be NONE */
1188 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
))
1189 return V_0280A0_SWAP_STD
; /* XYZW */
1190 else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
))
1191 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1192 else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
))
1193 return V_0280A0_SWAP_ALT
; /* ZYXW */
1194 else if (HAS_SWIZZLE(1,X
) && HAS_SWIZZLE(2,Y
))
1195 return V_0280A0_SWAP_ALT_REV
; /* WXYZ */
1201 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
1202 enum pipe_format surface_format
,
1203 const union pipe_color_union
*color
)
1205 union util_color uc
;
1207 memset(&uc
, 0, sizeof(uc
));
1209 if (util_format_is_pure_uint(surface_format
)) {
1210 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
1211 } else if (util_format_is_pure_sint(surface_format
)) {
1212 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
1214 util_pack_color(color
->f
, surface_format
, &uc
);
1217 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
1220 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
1221 struct pipe_framebuffer_state
*fb
,
1222 struct r600_atom
*fb_state
,
1224 const union pipe_color_union
*color
)
1228 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
1229 struct r600_texture
*tex
;
1230 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
1235 /* if this colorbuffer is not being cleared */
1236 if (!(*buffers
& clear_bit
))
1239 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
1241 /* 128-bit formats are unusupported */
1242 if (util_format_get_blocksizebits(fb
->cbufs
[i
]->format
) > 64) {
1246 /* the clear is allowed if all layers are bound */
1247 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
1248 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
1252 /* cannot clear mipmapped textures */
1253 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
1257 /* only supported on tiled surfaces */
1258 if (tex
->surface
.level
[0].mode
< RADEON_SURF_MODE_1D
) {
1262 /* ensure CMASK is enabled */
1263 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
1264 if (tex
->cmask
.size
== 0) {
1268 /* Do the fast clear. */
1269 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
1270 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
1271 tex
->cmask
.offset
, tex
->cmask
.size
, 0);
1273 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
1274 fb_state
->dirty
= true;
1275 *buffers
&= ~clear_bit
;
1279 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
1281 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
1282 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
1285 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
1287 rctx
->b
.create_surface
= r600_create_surface
;
1288 rctx
->b
.surface_destroy
= r600_surface_destroy
;