2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_memory.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_surface.h"
34 #include "os/os_time.h"
38 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
39 struct r600_texture
*rtex
);
40 static enum radeon_surf_mode
41 r600_choose_tiling(struct r600_common_screen
*rscreen
,
42 const struct pipe_resource
*templ
);
45 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
46 struct r600_texture
*rdst
,
47 unsigned dst_level
, unsigned dstx
,
48 unsigned dsty
, unsigned dstz
,
49 struct r600_texture
*rsrc
,
51 const struct pipe_box
*src_box
)
56 if (util_format_get_blocksizebits(rdst
->resource
.b
.b
.format
) !=
57 util_format_get_blocksizebits(rsrc
->resource
.b
.b
.format
))
60 /* MSAA: Blits don't exist in the real world. */
61 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
62 rdst
->resource
.b
.b
.nr_samples
> 1)
65 /* Depth-stencil surfaces:
66 * When dst is linear, the DB->CB copy preserves HTILE.
67 * When dst is tiled, the 3D path must be used to update HTILE.
69 if (rsrc
->is_depth
|| rdst
->is_depth
)
73 * src: Use the 3D path. DCC decompression is expensive.
74 * dst: Use the 3D path to compress the pixels with DCC.
76 if ((rsrc
->dcc_offset
&& rsrc
->surface
.level
[src_level
].dcc_enabled
) ||
77 (rdst
->dcc_offset
&& rdst
->surface
.level
[dst_level
].dcc_enabled
))
81 * src: Both texture and SDMA paths need decompression. Use SDMA.
82 * dst: If overwriting the whole texture, discard CMASK and use
83 * SDMA. Otherwise, use the 3D path.
85 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
86 /* The CMASK clear is only enabled for the first level. */
87 assert(dst_level
== 0);
88 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
89 dstx
, dsty
, dstz
, src_box
->width
,
90 src_box
->height
, src_box
->depth
))
93 r600_texture_discard_cmask(rctx
->screen
, rdst
);
96 /* All requirements are met. Prepare textures for SDMA. */
97 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
98 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
100 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
101 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
106 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
107 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
108 struct pipe_resource
*dst
,
110 unsigned dstx
, unsigned dsty
, unsigned dstz
,
111 struct pipe_resource
*src
,
113 const struct pipe_box
*src_box
)
115 struct pipe_blit_info blit
;
117 memset(&blit
, 0, sizeof(blit
));
118 blit
.src
.resource
= src
;
119 blit
.src
.format
= src
->format
;
120 blit
.src
.level
= src_level
;
121 blit
.src
.box
= *src_box
;
122 blit
.dst
.resource
= dst
;
123 blit
.dst
.format
= dst
->format
;
124 blit
.dst
.level
= dst_level
;
125 blit
.dst
.box
.x
= dstx
;
126 blit
.dst
.box
.y
= dsty
;
127 blit
.dst
.box
.z
= dstz
;
128 blit
.dst
.box
.width
= src_box
->width
;
129 blit
.dst
.box
.height
= src_box
->height
;
130 blit
.dst
.box
.depth
= src_box
->depth
;
131 blit
.mask
= util_format_get_mask(src
->format
) &
132 util_format_get_mask(dst
->format
);
133 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
136 pipe
->blit(pipe
, &blit
);
140 /* Copy from a full GPU texture to a transfer's staging one. */
141 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
143 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
144 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
145 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
146 struct pipe_resource
*src
= transfer
->resource
;
148 if (src
->nr_samples
> 1) {
149 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
150 src
, transfer
->level
, &transfer
->box
);
154 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
158 /* Copy from a transfer's staging texture to a full GPU one. */
159 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
161 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
162 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
163 struct pipe_resource
*dst
= transfer
->resource
;
164 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
165 struct pipe_box sbox
;
167 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
169 if (dst
->nr_samples
> 1) {
170 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
171 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
176 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
177 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
181 static unsigned r600_texture_get_offset(struct r600_texture
*rtex
, unsigned level
,
182 const struct pipe_box
*box
)
184 enum pipe_format format
= rtex
->resource
.b
.b
.format
;
186 return rtex
->surface
.level
[level
].offset
+
187 box
->z
* rtex
->surface
.level
[level
].slice_size
+
188 box
->y
/ util_format_get_blockheight(format
) * rtex
->surface
.level
[level
].pitch_bytes
+
189 box
->x
/ util_format_get_blockwidth(format
) * util_format_get_blocksize(format
);
192 static int r600_init_surface(struct r600_common_screen
*rscreen
,
193 struct radeon_surf
*surface
,
194 const struct pipe_resource
*ptex
,
195 enum radeon_surf_mode array_mode
,
196 unsigned pitch_in_bytes_override
,
200 bool is_flushed_depth
,
201 bool tc_compatible_htile
)
203 const struct util_format_description
*desc
=
204 util_format_description(ptex
->format
);
205 bool is_depth
, is_stencil
;
207 unsigned i
, bpe
, flags
= 0;
209 is_depth
= util_format_has_depth(desc
);
210 is_stencil
= util_format_has_stencil(desc
);
212 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
213 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
214 bpe
= 4; /* stencil is allocated separately on evergreen */
216 bpe
= util_format_get_blocksize(ptex
->format
);
217 /* align byte per element on dword */
223 if (!is_flushed_depth
&& is_depth
) {
224 flags
|= RADEON_SURF_ZBUFFER
;
226 if (tc_compatible_htile
&&
227 array_mode
== RADEON_SURF_MODE_2D
) {
228 /* TC-compatible HTILE only supports Z32_FLOAT.
229 * Promote Z16 to Z32. DB->CB copies will convert
230 * the format for transfers.
233 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
237 flags
|= RADEON_SURF_SBUFFER
;
240 if (rscreen
->chip_class
>= VI
&&
241 (ptex
->flags
& R600_RESOURCE_FLAG_DISABLE_DCC
||
242 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
))
243 flags
|= RADEON_SURF_DISABLE_DCC
;
245 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
246 /* This should catch bugs in gallium users setting incorrect flags. */
247 assert(ptex
->nr_samples
<= 1 &&
248 ptex
->array_size
== 1 &&
250 ptex
->last_level
== 0 &&
251 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
253 flags
|= RADEON_SURF_SCANOUT
;
257 flags
|= RADEON_SURF_IMPORTED
;
259 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
, flags
, bpe
,
260 array_mode
, surface
);
265 if (pitch_in_bytes_override
&& pitch_in_bytes_override
!= surface
->level
[0].pitch_bytes
) {
266 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
269 surface
->level
[0].nblk_x
= pitch_in_bytes_override
/ bpe
;
270 surface
->level
[0].pitch_bytes
= pitch_in_bytes_override
;
271 surface
->level
[0].slice_size
= pitch_in_bytes_override
* surface
->level
[0].nblk_y
;
275 for (i
= 0; i
< ARRAY_SIZE(surface
->level
); ++i
)
276 surface
->level
[i
].offset
+= offset
;
281 static void r600_texture_init_metadata(struct r600_texture
*rtex
,
282 struct radeon_bo_metadata
*metadata
)
284 struct radeon_surf
*surface
= &rtex
->surface
;
286 memset(metadata
, 0, sizeof(*metadata
));
287 metadata
->microtile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_1D
?
288 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
289 metadata
->macrotile
= surface
->level
[0].mode
>= RADEON_SURF_MODE_2D
?
290 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
291 metadata
->pipe_config
= surface
->pipe_config
;
292 metadata
->bankw
= surface
->bankw
;
293 metadata
->bankh
= surface
->bankh
;
294 metadata
->tile_split
= surface
->tile_split
;
295 metadata
->mtilea
= surface
->mtilea
;
296 metadata
->num_banks
= surface
->num_banks
;
297 metadata
->stride
= surface
->level
[0].pitch_bytes
;
298 metadata
->scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
301 static void r600_dirty_all_framebuffer_states(struct r600_common_screen
*rscreen
)
303 p_atomic_inc(&rscreen
->dirty_fb_counter
);
306 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
307 struct r600_texture
*rtex
)
309 struct r600_common_screen
*rscreen
= rctx
->screen
;
310 struct pipe_context
*ctx
= &rctx
->b
;
312 if (ctx
== rscreen
->aux_context
)
313 pipe_mutex_lock(rscreen
->aux_context_lock
);
315 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
316 ctx
->flush(ctx
, NULL
, 0);
318 if (ctx
== rscreen
->aux_context
)
319 pipe_mutex_unlock(rscreen
->aux_context_lock
);
322 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
323 struct r600_texture
*rtex
)
325 if (!rtex
->cmask
.size
)
328 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
331 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
332 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
333 rtex
->dirty_level_mask
= 0;
335 if (rscreen
->chip_class
>= SI
)
336 rtex
->cb_color_info
&= ~SI_S_028C70_FAST_CLEAR(1);
338 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
340 if (rtex
->cmask_buffer
!= &rtex
->resource
)
341 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
343 /* Notify all contexts about the change. */
344 r600_dirty_all_framebuffer_states(rscreen
);
345 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
348 static bool r600_can_disable_dcc(struct r600_texture
*rtex
)
350 /* We can't disable DCC if it can be written by another process. */
351 return rtex
->dcc_offset
&&
352 (!rtex
->resource
.is_shared
||
353 !(rtex
->resource
.external_usage
& PIPE_HANDLE_USAGE_WRITE
));
356 static bool r600_texture_discard_dcc(struct r600_common_screen
*rscreen
,
357 struct r600_texture
*rtex
)
359 if (!r600_can_disable_dcc(rtex
))
362 assert(rtex
->dcc_separate_buffer
== NULL
);
365 rtex
->dcc_offset
= 0;
367 /* Notify all contexts about the change. */
368 r600_dirty_all_framebuffer_states(rscreen
);
373 * Disable DCC for the texture. (first decompress, then discard metadata).
375 * There is unresolved multi-context synchronization issue between
376 * screen::aux_context and the current context. If applications do this with
377 * multiple contexts, it's already undefined behavior for them and we don't
378 * have to worry about that. The scenario is:
380 * If context 1 disables DCC and context 2 has queued commands that write
381 * to the texture via CB with DCC enabled, and the order of operations is
383 * context 2 queues draw calls rendering to the texture, but doesn't flush
384 * context 1 disables DCC and flushes
385 * context 1 & 2 reset descriptors and FB state
386 * context 2 flushes (new compressed tiles written by the draw calls)
387 * context 1 & 2 read garbage, because DCC is disabled, yet there are
390 * \param rctx the current context if you have one, or rscreen->aux_context
393 bool r600_texture_disable_dcc(struct r600_common_context
*rctx
,
394 struct r600_texture
*rtex
)
396 struct r600_common_screen
*rscreen
= rctx
->screen
;
398 if (!r600_can_disable_dcc(rtex
))
401 if (&rctx
->b
== rscreen
->aux_context
)
402 pipe_mutex_lock(rscreen
->aux_context_lock
);
404 /* Decompress DCC. */
405 rctx
->decompress_dcc(&rctx
->b
, rtex
);
406 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
408 if (&rctx
->b
== rscreen
->aux_context
)
409 pipe_mutex_unlock(rscreen
->aux_context_lock
);
411 return r600_texture_discard_dcc(rscreen
, rtex
);
414 static void r600_degrade_tile_mode_to_linear(struct r600_common_context
*rctx
,
415 struct r600_texture
*rtex
,
416 bool invalidate_storage
)
418 struct pipe_screen
*screen
= rctx
->b
.screen
;
419 struct r600_texture
*new_tex
;
420 struct pipe_resource templ
= rtex
->resource
.b
.b
;
423 templ
.bind
|= PIPE_BIND_LINEAR
;
425 /* r600g doesn't react to dirty_tex_descriptor_counter */
426 if (rctx
->chip_class
< SI
)
429 if (rtex
->resource
.is_shared
||
430 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
)
433 /* This fails with MSAA, depth, and compressed textures. */
434 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
435 RADEON_SURF_MODE_LINEAR_ALIGNED
)
438 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
442 /* Copy the pixels to the new texture. */
443 if (!invalidate_storage
) {
444 for (i
= 0; i
<= templ
.last_level
; i
++) {
448 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
449 util_max_layer(&templ
, i
) + 1, &box
);
451 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
452 &rtex
->resource
.b
.b
, i
, &box
);
456 r600_texture_discard_cmask(rctx
->screen
, rtex
);
457 r600_texture_discard_dcc(rctx
->screen
, rtex
);
459 /* Replace the structure fields of rtex. */
460 rtex
->resource
.b
.b
.bind
= templ
.bind
;
461 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
462 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
463 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
464 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
465 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
466 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
467 rtex
->resource
.domains
= new_tex
->resource
.domains
;
468 rtex
->resource
.flags
= new_tex
->resource
.flags
;
469 rtex
->size
= new_tex
->size
;
470 rtex
->surface
= new_tex
->surface
;
471 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
472 rtex
->cb_color_info
= new_tex
->cb_color_info
;
473 rtex
->cmask
= new_tex
->cmask
; /* needed even without CMASK */
475 assert(!rtex
->htile_buffer
);
476 assert(!rtex
->cmask
.size
);
477 assert(!rtex
->fmask
.size
);
478 assert(!rtex
->dcc_offset
);
479 assert(!rtex
->is_depth
);
481 r600_texture_reference(&new_tex
, NULL
);
483 r600_dirty_all_framebuffer_states(rctx
->screen
);
484 p_atomic_inc(&rctx
->screen
->dirty_tex_descriptor_counter
);
487 static boolean
r600_texture_get_handle(struct pipe_screen
* screen
,
488 struct pipe_context
*ctx
,
489 struct pipe_resource
*resource
,
490 struct winsys_handle
*whandle
,
493 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
494 struct r600_common_context
*rctx
= (struct r600_common_context
*)
495 (ctx
? ctx
: rscreen
->aux_context
);
496 struct r600_resource
*res
= (struct r600_resource
*)resource
;
497 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
498 struct radeon_bo_metadata metadata
;
499 bool update_metadata
= false;
501 /* This is not supported now, but it might be required for OpenCL
502 * interop in the future.
504 if (resource
->target
!= PIPE_BUFFER
&&
505 (resource
->nr_samples
> 1 || rtex
->is_depth
))
508 if (resource
->target
!= PIPE_BUFFER
) {
509 /* Since shader image stores don't support DCC on VI,
510 * disable it for external clients that want write
513 if (usage
& PIPE_HANDLE_USAGE_WRITE
&& rtex
->dcc_offset
) {
514 if (r600_texture_disable_dcc(rctx
, rtex
))
515 update_metadata
= true;
518 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
519 (rtex
->cmask
.size
|| rtex
->dcc_offset
)) {
520 /* Eliminate fast clear (both CMASK and DCC) */
521 r600_eliminate_fast_color_clear(rctx
, rtex
);
523 /* Disable CMASK if flush_resource isn't going
526 if (rtex
->cmask
.size
)
527 r600_texture_discard_cmask(rscreen
, rtex
);
531 if (!res
->is_shared
|| update_metadata
) {
532 r600_texture_init_metadata(rtex
, &metadata
);
533 if (rscreen
->query_opaque_metadata
)
534 rscreen
->query_opaque_metadata(rscreen
, rtex
,
537 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
541 if (res
->is_shared
) {
542 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
545 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
546 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
547 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
549 res
->is_shared
= true;
550 res
->external_usage
= usage
;
553 return rscreen
->ws
->buffer_get_handle(res
->buf
,
554 rtex
->surface
.level
[0].pitch_bytes
,
555 rtex
->surface
.level
[0].offset
,
556 rtex
->surface
.level
[0].slice_size
,
560 static void r600_texture_destroy(struct pipe_screen
*screen
,
561 struct pipe_resource
*ptex
)
563 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
564 struct r600_resource
*resource
= &rtex
->resource
;
566 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
568 r600_resource_reference(&rtex
->htile_buffer
, NULL
);
569 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
570 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
572 pb_reference(&resource
->buf
, NULL
);
573 r600_resource_reference(&rtex
->dcc_separate_buffer
, NULL
);
574 r600_resource_reference(&rtex
->last_dcc_separate_buffer
, NULL
);
578 static const struct u_resource_vtbl r600_texture_vtbl
;
580 /* The number of samples can be specified independently of the texture. */
581 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
582 struct r600_texture
*rtex
,
584 struct r600_fmask_info
*out
)
586 /* FMASK is allocated like an ordinary texture. */
587 struct pipe_resource templ
= rtex
->resource
.b
.b
;
588 struct radeon_surf fmask
= {};
591 memset(out
, 0, sizeof(*out
));
593 templ
.nr_samples
= 1;
594 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
596 /* Use the same parameters and tile mode. */
597 fmask
.bankw
= rtex
->surface
.bankw
;
598 fmask
.bankh
= rtex
->surface
.bankh
;
599 fmask
.mtilea
= rtex
->surface
.mtilea
;
600 fmask
.tile_split
= rtex
->surface
.tile_split
;
602 switch (nr_samples
) {
606 if (rscreen
->chip_class
<= CAYMAN
) {
614 R600_ERR("Invalid sample count for FMASK allocation.\n");
618 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
619 * This can be fixed by writing a separate FMASK allocator specifically
620 * for R600-R700 asics. */
621 if (rscreen
->chip_class
<= R700
) {
625 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
, flags
, bpe
,
626 RADEON_SURF_MODE_2D
, &fmask
)) {
627 R600_ERR("Got error in surface_init while allocating FMASK.\n");
631 assert(fmask
.level
[0].mode
== RADEON_SURF_MODE_2D
);
633 out
->slice_tile_max
= (fmask
.level
[0].nblk_x
* fmask
.level
[0].nblk_y
) / 64;
634 if (out
->slice_tile_max
)
635 out
->slice_tile_max
-= 1;
637 out
->tile_mode_index
= fmask
.tiling_index
[0];
638 out
->pitch_in_pixels
= fmask
.level
[0].nblk_x
;
639 out
->bank_height
= fmask
.bankh
;
640 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
641 out
->size
= fmask
.surf_size
;
644 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
645 struct r600_texture
*rtex
)
647 r600_texture_get_fmask_info(rscreen
, rtex
,
648 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
650 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
651 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
654 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
655 struct r600_texture
*rtex
,
656 struct r600_cmask_info
*out
)
658 unsigned cmask_tile_width
= 8;
659 unsigned cmask_tile_height
= 8;
660 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
661 unsigned element_bits
= 4;
662 unsigned cmask_cache_bits
= 1024;
663 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
664 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
666 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
667 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
668 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
669 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
670 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
672 unsigned pitch_elements
= align(rtex
->resource
.b
.b
.width0
, macro_tile_width
);
673 unsigned height
= align(rtex
->resource
.b
.b
.height0
, macro_tile_height
);
675 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
676 unsigned slice_bytes
=
677 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
679 assert(macro_tile_width
% 128 == 0);
680 assert(macro_tile_height
% 128 == 0);
682 out
->pitch
= pitch_elements
;
683 out
->height
= height
;
684 out
->xalign
= macro_tile_width
;
685 out
->yalign
= macro_tile_height
;
686 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
687 out
->alignment
= MAX2(256, base_align
);
688 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
689 align(slice_bytes
, base_align
);
692 static void si_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
693 struct r600_texture
*rtex
,
694 struct r600_cmask_info
*out
)
696 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
697 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
698 unsigned cl_width
, cl_height
;
713 case 16: /* Hawaii */
722 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
724 unsigned width
= align(rtex
->resource
.b
.b
.width0
, cl_width
*8);
725 unsigned height
= align(rtex
->resource
.b
.b
.height0
, cl_height
*8);
726 unsigned slice_elements
= (width
* height
) / (8*8);
728 /* Each element of CMASK is a nibble. */
729 unsigned slice_bytes
= slice_elements
/ 2;
732 out
->height
= height
;
733 out
->xalign
= cl_width
* 8;
734 out
->yalign
= cl_height
* 8;
735 out
->slice_tile_max
= (width
* height
) / (128*128);
736 if (out
->slice_tile_max
)
737 out
->slice_tile_max
-= 1;
739 out
->alignment
= MAX2(256, base_align
);
740 out
->size
= (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
741 align(slice_bytes
, base_align
);
744 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
745 struct r600_texture
*rtex
)
747 if (rscreen
->chip_class
>= SI
) {
748 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
750 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
753 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
754 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
756 if (rscreen
->chip_class
>= SI
)
757 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
759 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
762 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
763 struct r600_texture
*rtex
)
765 if (rtex
->cmask_buffer
)
768 assert(rtex
->cmask
.size
== 0);
770 if (rscreen
->chip_class
>= SI
) {
771 si_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
773 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
776 rtex
->cmask_buffer
= (struct r600_resource
*)
777 r600_aligned_buffer_create(&rscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
779 rtex
->cmask
.alignment
);
780 if (rtex
->cmask_buffer
== NULL
) {
781 rtex
->cmask
.size
= 0;
785 /* update colorbuffer state bits */
786 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
788 if (rscreen
->chip_class
>= SI
)
789 rtex
->cb_color_info
|= SI_S_028C70_FAST_CLEAR(1);
791 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
793 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
796 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
797 struct r600_texture
*rtex
)
799 unsigned cl_width
, cl_height
, width
, height
;
800 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
801 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
803 rtex
->surface
.htile_size
= 0;
805 if (rscreen
->chip_class
<= EVERGREEN
&&
806 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 26)
809 /* HW bug on R6xx. */
810 if (rscreen
->chip_class
== R600
&&
811 (rtex
->resource
.b
.b
.width0
> 7680 ||
812 rtex
->resource
.b
.b
.height0
> 7680))
815 /* HTILE is broken with 1D tiling on old kernels and CIK. */
816 if (rscreen
->chip_class
>= CIK
&&
817 rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
818 rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
< 38)
821 /* Overalign HTILE on P2 configs to work around GPU hangs in
822 * piglit/depthstencil-render-miplevels 585.
824 * This has been confirmed to help Kabini & Stoney, where the hangs
825 * are always reproducible. I think I have seen the test hang
826 * on Carrizo too, though it was very rare there.
828 if (rscreen
->chip_class
>= CIK
&& num_pipes
< 4)
857 width
= align(rtex
->resource
.b
.b
.width0
, cl_width
* 8);
858 height
= align(rtex
->resource
.b
.b
.height0
, cl_height
* 8);
860 slice_elements
= (width
* height
) / (8 * 8);
861 slice_bytes
= slice_elements
* 4;
863 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
864 base_align
= num_pipes
* pipe_interleave_bytes
;
866 rtex
->surface
.htile_alignment
= base_align
;
867 rtex
->surface
.htile_size
=
868 (util_max_layer(&rtex
->resource
.b
.b
, 0) + 1) *
869 align(slice_bytes
, base_align
);
872 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
873 struct r600_texture
*rtex
)
875 uint32_t clear_value
;
877 if (rtex
->tc_compatible_htile
) {
878 clear_value
= 0x0000030F;
880 r600_texture_get_htile_size(rscreen
, rtex
);
884 if (!rtex
->surface
.htile_size
)
887 rtex
->htile_buffer
= (struct r600_resource
*)
888 r600_aligned_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
890 rtex
->surface
.htile_size
,
891 rtex
->surface
.htile_alignment
);
892 if (rtex
->htile_buffer
== NULL
) {
893 /* this is not a fatal error as we can still keep rendering
894 * without htile buffer */
895 R600_ERR("Failed to create buffer object for htile buffer.\n");
897 r600_screen_clear_buffer(rscreen
, &rtex
->htile_buffer
->b
.b
,
898 0, rtex
->surface
.htile_size
,
899 clear_value
, R600_COHERENCY_NONE
);
903 void r600_print_texture_info(struct r600_texture
*rtex
, FILE *f
)
907 fprintf(f
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
908 "blk_h=%u, array_size=%u, last_level=%u, "
909 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
910 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
911 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
913 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
914 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
915 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
917 fprintf(f
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
918 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
919 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.bankw
,
920 rtex
->surface
.bankh
, rtex
->surface
.num_banks
, rtex
->surface
.mtilea
,
921 rtex
->surface
.tile_split
, rtex
->surface
.pipe_config
,
922 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
924 if (rtex
->fmask
.size
)
925 fprintf(f
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
926 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
927 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
928 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
929 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
931 if (rtex
->cmask
.size
)
932 fprintf(f
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch=%u, "
933 "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
934 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
935 rtex
->cmask
.pitch
, rtex
->cmask
.height
, rtex
->cmask
.xalign
,
936 rtex
->cmask
.yalign
, rtex
->cmask
.slice_tile_max
);
938 if (rtex
->htile_buffer
)
939 fprintf(f
, " HTile: size=%u, alignment=%u, TC_compatible = %u\n",
940 rtex
->htile_buffer
->b
.b
.width0
,
941 rtex
->htile_buffer
->buf
->alignment
,
942 rtex
->tc_compatible_htile
);
944 if (rtex
->dcc_offset
) {
945 fprintf(f
, " DCC: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u\n",
946 rtex
->dcc_offset
, rtex
->surface
.dcc_size
,
947 rtex
->surface
.dcc_alignment
);
948 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
949 fprintf(f
, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64
", "
950 "fast_clear_size=%"PRIu64
"\n",
951 i
, rtex
->surface
.level
[i
].dcc_enabled
,
952 rtex
->surface
.level
[i
].dcc_offset
,
953 rtex
->surface
.level
[i
].dcc_fast_clear_size
);
956 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
957 fprintf(f
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
958 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
959 "pitch_bytes=%u, mode=%u\n",
960 i
, rtex
->surface
.level
[i
].offset
,
961 rtex
->surface
.level
[i
].slice_size
,
962 u_minify(rtex
->resource
.b
.b
.width0
, i
),
963 u_minify(rtex
->resource
.b
.b
.height0
, i
),
964 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
965 rtex
->surface
.level
[i
].nblk_x
,
966 rtex
->surface
.level
[i
].nblk_y
,
967 rtex
->surface
.level
[i
].pitch_bytes
,
968 rtex
->surface
.level
[i
].mode
);
970 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
971 fprintf(f
, " StencilLayout: tilesplit=%u\n",
972 rtex
->surface
.stencil_tile_split
);
973 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
974 fprintf(f
, " StencilLevel[%i]: offset=%"PRIu64
", "
975 "slice_size=%"PRIu64
", npix_x=%u, "
976 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
977 "pitch_bytes=%u, mode=%u\n",
978 i
, rtex
->surface
.stencil_level
[i
].offset
,
979 rtex
->surface
.stencil_level
[i
].slice_size
,
980 u_minify(rtex
->resource
.b
.b
.width0
, i
),
981 u_minify(rtex
->resource
.b
.b
.height0
, i
),
982 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
983 rtex
->surface
.stencil_level
[i
].nblk_x
,
984 rtex
->surface
.stencil_level
[i
].nblk_y
,
985 rtex
->surface
.stencil_level
[i
].pitch_bytes
,
986 rtex
->surface
.stencil_level
[i
].mode
);
991 /* Common processing for r600_texture_create and r600_texture_from_handle */
992 static struct r600_texture
*
993 r600_texture_create_object(struct pipe_screen
*screen
,
994 const struct pipe_resource
*base
,
995 struct pb_buffer
*buf
,
996 struct radeon_surf
*surface
)
998 struct r600_texture
*rtex
;
999 struct r600_resource
*resource
;
1000 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1002 rtex
= CALLOC_STRUCT(r600_texture
);
1006 resource
= &rtex
->resource
;
1007 resource
->b
.b
= *base
;
1008 resource
->b
.b
.next
= NULL
;
1009 resource
->b
.vtbl
= &r600_texture_vtbl
;
1010 pipe_reference_init(&resource
->b
.b
.reference
, 1);
1011 resource
->b
.b
.screen
= screen
;
1013 /* don't include stencil-only formats which we don't support for rendering */
1014 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
1016 rtex
->surface
= *surface
;
1017 rtex
->size
= rtex
->surface
.surf_size
;
1019 rtex
->tc_compatible_htile
= rtex
->surface
.htile_size
!= 0;
1020 assert(!!(rtex
->surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
) ==
1021 rtex
->tc_compatible_htile
);
1023 /* TC-compatible HTILE only supports Z32_FLOAT. */
1024 if (rtex
->tc_compatible_htile
)
1025 rtex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1027 rtex
->db_render_format
= base
->format
;
1029 /* Tiled depth textures utilize the non-displayable tile order.
1030 * This must be done after r600_setup_surface.
1031 * Applies to R600-Cayman. */
1032 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
1033 /* Applies to GCN. */
1034 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
1036 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1037 * between frames, so the only thing that can enable separate DCC
1038 * with DRI2 is multiple slow clears within a frame.
1040 rtex
->ps_draw_ratio
= 0;
1042 if (rtex
->is_depth
) {
1043 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1044 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
1045 rscreen
->chip_class
>= EVERGREEN
) {
1046 rtex
->can_sample_z
= !rtex
->surface
.depth_adjusted
;
1047 rtex
->can_sample_s
= !rtex
->surface
.stencil_adjusted
;
1049 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
1050 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
1051 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
1052 rtex
->can_sample_z
= true;
1055 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
1056 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
1057 rtex
->db_compatible
= true;
1059 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
1060 r600_texture_allocate_htile(rscreen
, rtex
);
1063 if (base
->nr_samples
> 1) {
1065 r600_texture_allocate_fmask(rscreen
, rtex
);
1066 r600_texture_allocate_cmask(rscreen
, rtex
);
1067 rtex
->cmask_buffer
= &rtex
->resource
;
1069 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
1075 /* Shared textures must always set up DCC here.
1076 * If it's not present, it will be disabled by
1077 * apply_opaque_metadata later.
1079 if (rtex
->surface
.dcc_size
&&
1080 (buf
|| !(rscreen
->debug_flags
& DBG_NO_DCC
)) &&
1081 !(rtex
->surface
.flags
& RADEON_SURF_SCANOUT
)) {
1082 /* Reserve space for the DCC buffer. */
1083 rtex
->dcc_offset
= align64(rtex
->size
, rtex
->surface
.dcc_alignment
);
1084 rtex
->size
= rtex
->dcc_offset
+ rtex
->surface
.dcc_size
;
1088 /* Now create the backing buffer. */
1090 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
1091 rtex
->surface
.surf_alignment
);
1093 resource
->flags
|= RADEON_FLAG_HANDLE
;
1095 if (!r600_alloc_resource(rscreen
, resource
)) {
1100 resource
->buf
= buf
;
1101 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1102 resource
->bo_size
= buf
->size
;
1103 resource
->bo_alignment
= buf
->alignment
;
1104 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1105 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1106 resource
->vram_usage
= buf
->size
;
1107 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1108 resource
->gart_usage
= buf
->size
;
1111 if (rtex
->cmask
.size
) {
1112 /* Initialize the cmask to 0xCC (= compressed state). */
1113 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
1114 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1115 0xCCCCCCCC, R600_COHERENCY_NONE
);
1118 /* Initialize DCC only if the texture is not being imported. */
1119 if (!buf
&& rtex
->dcc_offset
) {
1120 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1122 rtex
->surface
.dcc_size
,
1123 0xFFFFFFFF, R600_COHERENCY_NONE
);
1126 /* Initialize the CMASK base register value. */
1127 rtex
->cmask
.base_address_reg
=
1128 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1130 if (rscreen
->debug_flags
& DBG_VM
) {
1131 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1132 rtex
->resource
.gpu_address
,
1133 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1134 base
->width0
, base
->height0
, util_max_layer(base
, 0)+1, base
->last_level
+1,
1135 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1138 if (rscreen
->debug_flags
& DBG_TEX
) {
1140 r600_print_texture_info(rtex
, stdout
);
1147 static enum radeon_surf_mode
1148 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1149 const struct pipe_resource
*templ
)
1151 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1152 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1154 /* MSAA resources must be 2D tiled. */
1155 if (templ
->nr_samples
> 1)
1156 return RADEON_SURF_MODE_2D
;
1158 /* Transfer resources should be linear. */
1159 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1160 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1162 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1163 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1164 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1165 (templ
->target
== PIPE_TEXTURE_2D
||
1166 templ
->target
== PIPE_TEXTURE_3D
))
1167 force_tiling
= true;
1169 /* Handle common candidates for the linear mode.
1170 * Compressed textures and DB surfaces must always be tiled.
1172 if (!force_tiling
&& !util_format_is_compressed(templ
->format
) &&
1173 (!util_format_is_depth_or_stencil(templ
->format
) ||
1174 templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
)) {
1175 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1176 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1178 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1179 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1180 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1182 /* Cursors are linear on SI.
1183 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1184 if (rscreen
->chip_class
>= SI
&&
1185 (templ
->bind
& PIPE_BIND_CURSOR
))
1186 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1188 if (templ
->bind
& PIPE_BIND_LINEAR
)
1189 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1191 /* Textures with a very small height are recommended to be linear. */
1192 if (templ
->target
== PIPE_TEXTURE_1D
||
1193 templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1194 templ
->height0
<= 4)
1195 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1197 /* Textures likely to be mapped often. */
1198 if (templ
->usage
== PIPE_USAGE_STAGING
||
1199 templ
->usage
== PIPE_USAGE_STREAM
)
1200 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1203 /* Make small textures 1D tiled. */
1204 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1205 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1206 return RADEON_SURF_MODE_1D
;
1208 /* The allocator will switch to 1D if needed. */
1209 return RADEON_SURF_MODE_2D
;
1212 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1213 const struct pipe_resource
*templ
)
1215 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1216 struct radeon_surf surface
= {0};
1217 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1218 bool tc_compatible_htile
=
1219 rscreen
->chip_class
>= VI
&&
1220 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1221 !(rscreen
->debug_flags
& DBG_NO_HYPERZ
) &&
1222 !is_flushed_depth
&&
1223 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1224 util_format_is_depth_or_stencil(templ
->format
);
1228 r
= r600_init_surface(rscreen
, &surface
, templ
,
1229 r600_choose_tiling(rscreen
, templ
), 0, 0,
1230 false, false, is_flushed_depth
,
1231 tc_compatible_htile
);
1236 return (struct pipe_resource
*)
1237 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1240 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1241 const struct pipe_resource
*templ
,
1242 struct winsys_handle
*whandle
,
1245 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1246 struct pb_buffer
*buf
= NULL
;
1247 unsigned stride
= 0, offset
= 0;
1248 unsigned array_mode
;
1249 struct radeon_surf surface
;
1251 struct radeon_bo_metadata metadata
= {};
1252 struct r600_texture
*rtex
;
1254 /* Support only 2D textures without mipmaps */
1255 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1256 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1259 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
, &stride
, &offset
);
1263 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1265 surface
.pipe_config
= metadata
.pipe_config
;
1266 surface
.bankw
= metadata
.bankw
;
1267 surface
.bankh
= metadata
.bankh
;
1268 surface
.tile_split
= metadata
.tile_split
;
1269 surface
.mtilea
= metadata
.mtilea
;
1270 surface
.num_banks
= metadata
.num_banks
;
1272 if (metadata
.macrotile
== RADEON_LAYOUT_TILED
)
1273 array_mode
= RADEON_SURF_MODE_2D
;
1274 else if (metadata
.microtile
== RADEON_LAYOUT_TILED
)
1275 array_mode
= RADEON_SURF_MODE_1D
;
1277 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1279 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
, stride
,
1280 offset
, true, metadata
.scanout
, false, false);
1285 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1289 rtex
->resource
.is_shared
= true;
1290 rtex
->resource
.external_usage
= usage
;
1292 if (rscreen
->apply_opaque_metadata
)
1293 rscreen
->apply_opaque_metadata(rscreen
, rtex
, &metadata
);
1295 return &rtex
->resource
.b
.b
;
1298 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1299 struct pipe_resource
*texture
,
1300 struct r600_texture
**staging
)
1302 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1303 struct pipe_resource resource
;
1304 struct r600_texture
**flushed_depth_texture
= staging
?
1305 staging
: &rtex
->flushed_depth_texture
;
1306 enum pipe_format pipe_format
= texture
->format
;
1309 if (rtex
->flushed_depth_texture
)
1310 return true; /* it's ready */
1312 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1313 switch (pipe_format
) {
1314 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1315 /* Save memory by not allocating the S plane. */
1316 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1318 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1319 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1320 /* Save memory bandwidth by not copying the
1321 * stencil part during flush.
1323 * This potentially increases memory bandwidth
1324 * if an application uses both Z and S texturing
1325 * simultaneously (a flushed Z24S8 texture
1326 * would be stored compactly), but how often
1327 * does that really happen?
1329 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1333 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1334 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1336 /* DB->CB copies to an 8bpp surface don't work. */
1337 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1341 memset(&resource
, 0, sizeof(resource
));
1342 resource
.target
= texture
->target
;
1343 resource
.format
= pipe_format
;
1344 resource
.width0
= texture
->width0
;
1345 resource
.height0
= texture
->height0
;
1346 resource
.depth0
= texture
->depth0
;
1347 resource
.array_size
= texture
->array_size
;
1348 resource
.last_level
= texture
->last_level
;
1349 resource
.nr_samples
= texture
->nr_samples
;
1350 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1351 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1352 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1355 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1357 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1358 if (*flushed_depth_texture
== NULL
) {
1359 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1363 (*flushed_depth_texture
)->non_disp_tiling
= false;
1368 * Initialize the pipe_resource descriptor to be of the same size as the box,
1369 * which is supposed to hold a subregion of the texture "orig" at the given
1372 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1373 struct pipe_resource
*orig
,
1374 const struct pipe_box
*box
,
1375 unsigned level
, unsigned flags
)
1377 memset(res
, 0, sizeof(*res
));
1378 res
->format
= orig
->format
;
1379 res
->width0
= box
->width
;
1380 res
->height0
= box
->height
;
1382 res
->array_size
= 1;
1383 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1386 /* We must set the correct texture target and dimensions for a 3D box. */
1387 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1388 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1389 res
->array_size
= box
->depth
;
1391 res
->target
= PIPE_TEXTURE_2D
;
1395 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1396 struct r600_texture
*rtex
,
1397 unsigned transfer_usage
,
1398 const struct pipe_box
*box
)
1400 /* r600g doesn't react to dirty_tex_descriptor_counter */
1401 return rscreen
->chip_class
>= SI
&&
1402 !rtex
->resource
.is_shared
&&
1403 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1404 rtex
->resource
.b
.b
.last_level
== 0 &&
1405 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1406 box
->x
, box
->y
, box
->z
,
1407 box
->width
, box
->height
,
1411 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1412 struct r600_texture
*rtex
)
1414 struct r600_common_screen
*rscreen
= rctx
->screen
;
1416 /* There is no point in discarding depth and tiled buffers. */
1417 assert(!rtex
->is_depth
);
1418 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
);
1420 /* Reallocate the buffer in the same pipe_resource. */
1421 r600_alloc_resource(rscreen
, &rtex
->resource
);
1423 /* Initialize the CMASK base address (needed even without CMASK). */
1424 rtex
->cmask
.base_address_reg
=
1425 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1427 r600_dirty_all_framebuffer_states(rscreen
);
1428 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
1430 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1433 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1434 struct pipe_resource
*texture
,
1437 const struct pipe_box
*box
,
1438 struct pipe_transfer
**ptransfer
)
1440 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1441 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1442 struct r600_transfer
*trans
;
1443 struct r600_resource
*buf
;
1444 unsigned offset
= 0;
1446 bool use_staging_texture
= false;
1448 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1450 /* Depth textures use staging unconditionally. */
1451 if (!rtex
->is_depth
) {
1452 /* Degrade the tile mode if we get too many transfers on APUs.
1453 * On dGPUs, the staging texture is always faster.
1454 * Only count uploads that are at least 4x4 pixels large.
1456 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1458 box
->width
>= 4 && box
->height
>= 4 &&
1459 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1460 bool can_invalidate
=
1461 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1464 r600_degrade_tile_mode_to_linear(rctx
, rtex
,
1468 /* Tiled textures need to be converted into a linear texture for CPU
1469 * access. The staging texture is always linear and is placed in GART.
1471 * Reading from VRAM is slow, always use the staging texture in
1474 * Use the staging texture for uploads if the underlying BO
1477 if (rtex
->surface
.level
[0].mode
>= RADEON_SURF_MODE_1D
)
1478 use_staging_texture
= true;
1479 else if (usage
& PIPE_TRANSFER_READ
)
1480 use_staging_texture
= (rtex
->resource
.domains
&
1481 RADEON_DOMAIN_VRAM
) != 0;
1482 /* Write & linear only: */
1483 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1484 RADEON_USAGE_READWRITE
) ||
1485 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1486 RADEON_USAGE_READWRITE
)) {
1488 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1490 r600_texture_invalidate_storage(rctx
, rtex
);
1492 use_staging_texture
= true;
1496 trans
= CALLOC_STRUCT(r600_transfer
);
1499 trans
->transfer
.resource
= texture
;
1500 trans
->transfer
.level
= level
;
1501 trans
->transfer
.usage
= usage
;
1502 trans
->transfer
.box
= *box
;
1504 if (rtex
->is_depth
) {
1505 struct r600_texture
*staging_depth
;
1507 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1508 /* MSAA depth buffers need to be converted to single sample buffers.
1510 * Mapping MSAA depth buffers can occur if ReadPixels is called
1511 * with a multisample GLX visual.
1513 * First downsample the depth buffer to a temporary texture,
1514 * then decompress the temporary one to staging.
1516 * Only the region being mapped is transfered.
1518 struct pipe_resource resource
;
1520 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1522 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1523 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1528 if (usage
& PIPE_TRANSFER_READ
) {
1529 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1531 R600_ERR("failed to create a temporary depth texture\n");
1536 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1537 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1538 0, 0, 0, box
->depth
, 0, 0);
1539 pipe_resource_reference(&temp
, NULL
);
1543 /* XXX: only readback the rectangle which is being mapped? */
1544 /* XXX: when discard is true, no need to read back from depth texture */
1545 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1546 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1551 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1553 box
->z
, box
->z
+ box
->depth
- 1,
1556 offset
= r600_texture_get_offset(staging_depth
, level
, box
);
1559 trans
->transfer
.stride
= staging_depth
->surface
.level
[level
].pitch_bytes
;
1560 trans
->transfer
.layer_stride
= staging_depth
->surface
.level
[level
].slice_size
;
1561 trans
->staging
= (struct r600_resource
*)staging_depth
;
1562 buf
= trans
->staging
;
1563 } else if (use_staging_texture
) {
1564 struct pipe_resource resource
;
1565 struct r600_texture
*staging
;
1567 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1568 R600_RESOURCE_FLAG_TRANSFER
);
1569 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1570 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1572 /* Create the temporary texture. */
1573 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1575 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1579 trans
->staging
= &staging
->resource
;
1580 trans
->transfer
.stride
= staging
->surface
.level
[0].pitch_bytes
;
1581 trans
->transfer
.layer_stride
= staging
->surface
.level
[0].slice_size
;
1583 if (usage
& PIPE_TRANSFER_READ
)
1584 r600_copy_to_staging_texture(ctx
, trans
);
1586 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1588 buf
= trans
->staging
;
1590 /* the resource is mapped directly */
1591 trans
->transfer
.stride
= rtex
->surface
.level
[level
].pitch_bytes
;
1592 trans
->transfer
.layer_stride
= rtex
->surface
.level
[level
].slice_size
;
1593 offset
= r600_texture_get_offset(rtex
, level
, box
);
1594 buf
= &rtex
->resource
;
1597 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1598 r600_resource_reference(&trans
->staging
, NULL
);
1603 *ptransfer
= &trans
->transfer
;
1604 return map
+ offset
;
1607 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1608 struct pipe_transfer
* transfer
)
1610 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1611 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1612 struct pipe_resource
*texture
= transfer
->resource
;
1613 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1615 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1616 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1617 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1618 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1619 &rtransfer
->staging
->b
.b
, transfer
->level
,
1622 r600_copy_from_staging_texture(ctx
, rtransfer
);
1626 if (rtransfer
->staging
) {
1627 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1628 r600_resource_reference(&rtransfer
->staging
, NULL
);
1631 /* Heuristic for {upload, draw, upload, draw, ..}:
1633 * Flush the gfx IB if we've allocated too much texture storage.
1635 * The idea is that we don't want to build IBs that use too much
1636 * memory and put pressure on the kernel memory manager and we also
1637 * want to make temporary and invalidated buffers go idle ASAP to
1638 * decrease the total memory usage or make them reusable. The memory
1639 * usage will be slightly higher than given here because of the buffer
1640 * cache in the winsys.
1642 * The result is that the kernel memory manager is never a bottleneck.
1644 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1645 rctx
->gfx
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1646 rctx
->num_alloc_tex_transfer_bytes
= 0;
1652 static const struct u_resource_vtbl r600_texture_vtbl
=
1654 NULL
, /* get_handle */
1655 r600_texture_destroy
, /* resource_destroy */
1656 r600_texture_transfer_map
, /* transfer_map */
1657 u_default_transfer_flush_region
, /* transfer_flush_region */
1658 r600_texture_transfer_unmap
, /* transfer_unmap */
1661 /* DCC channel type categories within which formats can be reinterpreted
1662 * while keeping the same DCC encoding. The swizzle must also match. */
1663 enum dcc_channel_type
{
1664 dcc_channel_float32
,
1667 dcc_channel_float16
,
1670 dcc_channel_uint_10_10_10_2
,
1673 dcc_channel_incompatible
,
1676 /* Return the type of DCC encoding. */
1677 static enum dcc_channel_type
1678 vi_get_dcc_channel_type(const struct util_format_description
*desc
)
1682 /* Find the first non-void channel. */
1683 for (i
= 0; i
< desc
->nr_channels
; i
++)
1684 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
)
1686 if (i
== desc
->nr_channels
)
1687 return dcc_channel_incompatible
;
1689 switch (desc
->channel
[i
].size
) {
1691 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1692 return dcc_channel_float32
;
1693 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1694 return dcc_channel_uint32
;
1695 return dcc_channel_sint32
;
1697 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
)
1698 return dcc_channel_float16
;
1699 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1700 return dcc_channel_uint16
;
1701 return dcc_channel_sint16
;
1703 return dcc_channel_uint_10_10_10_2
;
1705 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
)
1706 return dcc_channel_uint8
;
1707 return dcc_channel_sint8
;
1709 return dcc_channel_incompatible
;
1713 /* Return if it's allowed to reinterpret one format as another with DCC enabled. */
1714 bool vi_dcc_formats_compatible(enum pipe_format format1
,
1715 enum pipe_format format2
)
1717 const struct util_format_description
*desc1
, *desc2
;
1718 enum dcc_channel_type type1
, type2
;
1721 if (format1
== format2
)
1724 desc1
= util_format_description(format1
);
1725 desc2
= util_format_description(format2
);
1727 if (desc1
->nr_channels
!= desc2
->nr_channels
)
1730 /* Swizzles must be the same. */
1731 for (i
= 0; i
< desc1
->nr_channels
; i
++)
1732 if (desc1
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1733 desc2
->swizzle
[i
] <= PIPE_SWIZZLE_W
&&
1734 desc1
->swizzle
[i
] != desc2
->swizzle
[i
])
1737 type1
= vi_get_dcc_channel_type(desc1
);
1738 type2
= vi_get_dcc_channel_type(desc2
);
1740 return type1
!= dcc_channel_incompatible
&&
1741 type2
!= dcc_channel_incompatible
&&
1745 void vi_dcc_disable_if_incompatible_format(struct r600_common_context
*rctx
,
1746 struct pipe_resource
*tex
,
1748 enum pipe_format view_format
)
1750 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1752 if (rtex
->dcc_offset
&&
1753 rtex
->surface
.level
[level
].dcc_enabled
&&
1754 !vi_dcc_formats_compatible(tex
->format
, view_format
))
1755 if (!r600_texture_disable_dcc(rctx
, (struct r600_texture
*)tex
))
1756 rctx
->decompress_dcc(&rctx
->b
, rtex
);
1759 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1760 struct pipe_resource
*texture
,
1761 const struct pipe_surface
*templ
,
1762 unsigned width
, unsigned height
)
1764 struct r600_common_context
*rctx
= (struct r600_common_context
*)pipe
;
1765 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1766 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1771 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1772 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1774 pipe_reference_init(&surface
->base
.reference
, 1);
1775 pipe_resource_reference(&surface
->base
.texture
, texture
);
1776 surface
->base
.context
= pipe
;
1777 surface
->base
.format
= templ
->format
;
1778 surface
->base
.width
= width
;
1779 surface
->base
.height
= height
;
1780 surface
->base
.u
= templ
->u
;
1781 surface
->level_info
= &rtex
->surface
.level
[templ
->u
.tex
.level
];
1783 if (texture
->target
!= PIPE_BUFFER
)
1784 vi_dcc_disable_if_incompatible_format(rctx
, texture
,
1788 return &surface
->base
;
1791 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1792 struct pipe_resource
*tex
,
1793 const struct pipe_surface
*templ
)
1795 unsigned level
= templ
->u
.tex
.level
;
1796 unsigned width
= u_minify(tex
->width0
, level
);
1797 unsigned height
= u_minify(tex
->height0
, level
);
1799 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1800 const struct util_format_description
*tex_desc
1801 = util_format_description(tex
->format
);
1802 const struct util_format_description
*templ_desc
1803 = util_format_description(templ
->format
);
1805 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1807 /* Adjust size of surface if and only if the block width or
1808 * height is changed. */
1809 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1810 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1811 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1812 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1814 width
= nblks_x
* templ_desc
->block
.width
;
1815 height
= nblks_y
* templ_desc
->block
.height
;
1819 return r600_create_surface_custom(pipe
, tex
, templ
, width
, height
);
1822 static void r600_surface_destroy(struct pipe_context
*pipe
,
1823 struct pipe_surface
*surface
)
1825 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1826 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1827 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1828 pipe_resource_reference(&surface
->texture
, NULL
);
1832 static void r600_clear_texture(struct pipe_context
*pipe
,
1833 struct pipe_resource
*tex
,
1835 const struct pipe_box
*box
,
1838 struct pipe_screen
*screen
= pipe
->screen
;
1839 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1840 struct pipe_surface tmpl
= {{0}};
1841 struct pipe_surface
*sf
;
1842 const struct util_format_description
*desc
=
1843 util_format_description(tex
->format
);
1845 tmpl
.format
= tex
->format
;
1846 tmpl
.u
.tex
.first_layer
= box
->z
;
1847 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
1848 tmpl
.u
.tex
.level
= level
;
1849 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
1853 if (rtex
->is_depth
) {
1856 uint8_t stencil
= 0;
1858 /* Depth is always present. */
1859 clear
= PIPE_CLEAR_DEPTH
;
1860 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
1862 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
1863 clear
|= PIPE_CLEAR_STENCIL
;
1864 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
1867 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
1869 box
->width
, box
->height
, false);
1871 union pipe_color_union color
;
1873 /* pipe_color_union requires the full vec4 representation. */
1874 if (util_format_is_pure_uint(tex
->format
))
1875 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
1876 else if (util_format_is_pure_sint(tex
->format
))
1877 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
1879 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
1881 if (screen
->is_format_supported(screen
, tex
->format
,
1883 PIPE_BIND_RENDER_TARGET
)) {
1884 pipe
->clear_render_target(pipe
, sf
, &color
,
1886 box
->width
, box
->height
, false);
1888 /* Software fallback - just for R9G9B9E5_FLOAT */
1889 util_clear_render_target(pipe
, sf
, &color
,
1891 box
->width
, box
->height
);
1894 pipe_surface_reference(&sf
, NULL
);
1897 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1899 const struct util_format_description
*desc
= util_format_description(format
);
1901 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1903 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1904 return V_0280A0_SWAP_STD
;
1906 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1909 switch (desc
->nr_channels
) {
1911 if (HAS_SWIZZLE(0,X
))
1912 return V_0280A0_SWAP_STD
; /* X___ */
1913 else if (HAS_SWIZZLE(3,X
))
1914 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1917 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1918 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1919 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1920 return V_0280A0_SWAP_STD
; /* XY__ */
1921 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1922 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1923 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1925 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
1926 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1927 return V_0280A0_SWAP_ALT
; /* X__Y */
1928 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1929 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1932 if (HAS_SWIZZLE(0,X
))
1933 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
1934 else if (HAS_SWIZZLE(0,Z
))
1935 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1938 /* check the middle channels, the 1st and 4th channel can be NONE */
1939 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
1940 return V_0280A0_SWAP_STD
; /* XYZW */
1941 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
1942 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1943 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
1944 return V_0280A0_SWAP_ALT
; /* ZYXW */
1945 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
1948 return V_0280A0_SWAP_ALT_REV
;
1950 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
1957 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
1959 static void vi_dcc_clean_up_context_slot(struct r600_common_context
*rctx
,
1964 if (rctx
->dcc_stats
[slot
].query_active
)
1965 vi_separate_dcc_stop_query(&rctx
->b
,
1966 rctx
->dcc_stats
[slot
].tex
);
1968 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
[slot
].ps_stats
); i
++)
1969 if (rctx
->dcc_stats
[slot
].ps_stats
[i
]) {
1970 rctx
->b
.destroy_query(&rctx
->b
,
1971 rctx
->dcc_stats
[slot
].ps_stats
[i
]);
1972 rctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
1975 r600_texture_reference(&rctx
->dcc_stats
[slot
].tex
, NULL
);
1979 * Return the per-context slot where DCC statistics queries for the texture live.
1981 static unsigned vi_get_context_dcc_stats_index(struct r600_common_context
*rctx
,
1982 struct r600_texture
*tex
)
1984 int i
, empty_slot
= -1;
1986 /* Remove zombie textures (textures kept alive by this array only). */
1987 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
1988 if (rctx
->dcc_stats
[i
].tex
&&
1989 rctx
->dcc_stats
[i
].tex
->resource
.b
.b
.reference
.count
== 1)
1990 vi_dcc_clean_up_context_slot(rctx
, i
);
1992 /* Find the texture. */
1993 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
1994 /* Return if found. */
1995 if (rctx
->dcc_stats
[i
].tex
== tex
) {
1996 rctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2000 /* Record the first seen empty slot. */
2001 if (empty_slot
== -1 && !rctx
->dcc_stats
[i
].tex
)
2005 /* Not found. Remove the oldest member to make space in the array. */
2006 if (empty_slot
== -1) {
2007 int oldest_slot
= 0;
2009 /* Find the oldest slot. */
2010 for (i
= 1; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++)
2011 if (rctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2012 rctx
->dcc_stats
[i
].last_use_timestamp
)
2015 /* Clean up the oldest slot. */
2016 vi_dcc_clean_up_context_slot(rctx
, oldest_slot
);
2017 empty_slot
= oldest_slot
;
2020 /* Add the texture to the new slot. */
2021 r600_texture_reference(&rctx
->dcc_stats
[empty_slot
].tex
, tex
);
2022 rctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2026 static struct pipe_query
*
2027 vi_create_resuming_pipestats_query(struct pipe_context
*ctx
)
2029 struct r600_query_hw
*query
= (struct r600_query_hw
*)
2030 ctx
->create_query(ctx
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2032 query
->flags
|= R600_QUERY_HW_FLAG_BEGIN_RESUMES
;
2033 return (struct pipe_query
*)query
;
2037 * Called when binding a color buffer.
2039 void vi_separate_dcc_start_query(struct pipe_context
*ctx
,
2040 struct r600_texture
*tex
)
2042 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2043 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2045 assert(!rctx
->dcc_stats
[i
].query_active
);
2047 if (!rctx
->dcc_stats
[i
].ps_stats
[0])
2048 rctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(ctx
);
2050 /* begin or resume the query */
2051 ctx
->begin_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2052 rctx
->dcc_stats
[i
].query_active
= true;
2056 * Called when unbinding a color buffer.
2058 void vi_separate_dcc_stop_query(struct pipe_context
*ctx
,
2059 struct r600_texture
*tex
)
2061 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2062 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2064 assert(rctx
->dcc_stats
[i
].query_active
);
2065 assert(rctx
->dcc_stats
[i
].ps_stats
[0]);
2067 /* pause or end the query */
2068 ctx
->end_query(ctx
, rctx
->dcc_stats
[i
].ps_stats
[0]);
2069 rctx
->dcc_stats
[i
].query_active
= false;
2072 static bool vi_should_enable_separate_dcc(struct r600_texture
*tex
)
2074 /* The minimum number of fullscreen draws per frame that is required
2076 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2079 /* Called by fast clear. */
2080 static void vi_separate_dcc_try_enable(struct r600_common_context
*rctx
,
2081 struct r600_texture
*tex
)
2083 /* The intent is to use this with shared displayable back buffers,
2084 * but it's not strictly limited only to them.
2086 if (!tex
->resource
.is_shared
||
2087 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2088 tex
->resource
.b
.b
.target
!= PIPE_TEXTURE_2D
||
2089 tex
->resource
.b
.b
.last_level
> 0 ||
2090 !tex
->surface
.dcc_size
)
2093 if (tex
->dcc_offset
)
2094 return; /* already enabled */
2096 /* Enable the DCC stat gathering. */
2097 if (!tex
->dcc_gather_statistics
) {
2098 tex
->dcc_gather_statistics
= true;
2099 vi_separate_dcc_start_query(&rctx
->b
, tex
);
2102 if (!vi_should_enable_separate_dcc(tex
))
2103 return; /* stats show that DCC decompression is too expensive */
2105 assert(tex
->surface
.level
[0].dcc_enabled
);
2106 assert(!tex
->dcc_separate_buffer
);
2108 r600_texture_discard_cmask(rctx
->screen
, tex
);
2110 /* Get a DCC buffer. */
2111 if (tex
->last_dcc_separate_buffer
) {
2112 assert(tex
->dcc_gather_statistics
);
2113 assert(!tex
->dcc_separate_buffer
);
2114 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2115 tex
->last_dcc_separate_buffer
= NULL
;
2117 tex
->dcc_separate_buffer
= (struct r600_resource
*)
2118 r600_aligned_buffer_create(rctx
->b
.screen
, 0,
2120 tex
->surface
.dcc_size
,
2121 tex
->surface
.dcc_alignment
);
2122 if (!tex
->dcc_separate_buffer
)
2126 /* dcc_offset is the absolute GPUVM address. */
2127 tex
->dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2129 /* no need to flag anything since this is called by fast clear that
2130 * flags framebuffer state
2135 * Called by pipe_context::flush_resource, the place where DCC decompression
2138 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
,
2139 struct r600_texture
*tex
)
2141 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
2142 struct pipe_query
*tmp
;
2143 unsigned i
= vi_get_context_dcc_stats_index(rctx
, tex
);
2144 bool query_active
= rctx
->dcc_stats
[i
].query_active
;
2145 bool disable
= false;
2147 if (rctx
->dcc_stats
[i
].ps_stats
[2]) {
2148 union pipe_query_result result
;
2150 /* Read the results. */
2151 ctx
->get_query_result(ctx
, rctx
->dcc_stats
[i
].ps_stats
[2],
2153 r600_query_hw_reset_buffers(rctx
,
2154 (struct r600_query_hw
*)
2155 rctx
->dcc_stats
[i
].ps_stats
[2]);
2157 /* Compute the approximate number of fullscreen draws. */
2158 tex
->ps_draw_ratio
=
2159 result
.pipeline_statistics
.ps_invocations
/
2160 (tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
);
2161 rctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2163 disable
= tex
->dcc_separate_buffer
&&
2164 !vi_should_enable_separate_dcc(tex
);
2167 tex
->num_slow_clears
= 0;
2169 /* stop the statistics query for ps_stats[0] */
2171 vi_separate_dcc_stop_query(ctx
, tex
);
2173 /* Move the queries in the queue by one. */
2174 tmp
= rctx
->dcc_stats
[i
].ps_stats
[2];
2175 rctx
->dcc_stats
[i
].ps_stats
[2] = rctx
->dcc_stats
[i
].ps_stats
[1];
2176 rctx
->dcc_stats
[i
].ps_stats
[1] = rctx
->dcc_stats
[i
].ps_stats
[0];
2177 rctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2179 /* create and start a new query as ps_stats[0] */
2181 vi_separate_dcc_start_query(ctx
, tex
);
2184 assert(!tex
->last_dcc_separate_buffer
);
2185 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2186 tex
->dcc_separate_buffer
= NULL
;
2187 tex
->dcc_offset
= 0;
2188 /* no need to flag anything since this is called after
2189 * decompression that re-sets framebuffer state
2194 /* FAST COLOR CLEAR */
2196 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
2197 enum pipe_format surface_format
,
2198 const union pipe_color_union
*color
)
2200 union util_color uc
;
2202 memset(&uc
, 0, sizeof(uc
));
2204 if (util_format_get_blocksizebits(surface_format
) == 128) {
2205 /* DCC fast clear only:
2206 * CLEAR_WORD0 = R = G = B
2209 assert(color
->ui
[0] == color
->ui
[1] &&
2210 color
->ui
[0] == color
->ui
[2]);
2211 uc
.ui
[0] = color
->ui
[0];
2212 uc
.ui
[1] = color
->ui
[3];
2213 } else if (util_format_is_pure_uint(surface_format
)) {
2214 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
2215 } else if (util_format_is_pure_sint(surface_format
)) {
2216 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
2218 util_pack_color(color
->f
, surface_format
, &uc
);
2221 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
2224 static bool vi_get_fast_clear_parameters(enum pipe_format surface_format
,
2225 const union pipe_color_union
*color
,
2226 uint32_t* reset_value
,
2227 bool* clear_words_needed
)
2229 bool values
[4] = {};
2231 bool main_value
= false;
2232 bool extra_value
= false;
2234 const struct util_format_description
*desc
= util_format_description(surface_format
);
2236 if (desc
->block
.bits
== 128 &&
2237 (color
->ui
[0] != color
->ui
[1] ||
2238 color
->ui
[0] != color
->ui
[2]))
2241 *clear_words_needed
= true;
2242 *reset_value
= 0x20202020U
;
2244 /* If we want to clear without needing a fast clear eliminate step, we
2245 * can set each channel to 0 or 1 (or 0/max for integer formats). We
2246 * have two sets of flags, one for the last or first channel(extra) and
2247 * one for the other channels(main).
2250 if (surface_format
== PIPE_FORMAT_R11G11B10_FLOAT
||
2251 surface_format
== PIPE_FORMAT_B5G6R5_UNORM
||
2252 surface_format
== PIPE_FORMAT_B5G6R5_SRGB
) {
2254 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_PLAIN
) {
2255 if(r600_translate_colorswap(surface_format
, false) <= 1)
2256 extra_channel
= desc
->nr_channels
- 1;
2262 for (i
= 0; i
< 4; ++i
) {
2263 int index
= desc
->swizzle
[i
] - PIPE_SWIZZLE_X
;
2265 if (desc
->swizzle
[i
] < PIPE_SWIZZLE_X
||
2266 desc
->swizzle
[i
] > PIPE_SWIZZLE_W
)
2269 if (desc
->channel
[i
].pure_integer
&&
2270 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2271 /* Use the maximum value for clamping the clear color. */
2272 int max
= u_bit_consecutive(0, desc
->channel
[i
].size
- 1);
2274 values
[i
] = color
->i
[i
] != 0;
2275 if (color
->i
[i
] != 0 && MIN2(color
->i
[i
], max
) != max
)
2277 } else if (desc
->channel
[i
].pure_integer
&&
2278 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2279 /* Use the maximum value for clamping the clear color. */
2280 unsigned max
= u_bit_consecutive(0, desc
->channel
[i
].size
);
2282 values
[i
] = color
->ui
[i
] != 0U;
2283 if (color
->ui
[i
] != 0U && MIN2(color
->ui
[i
], max
) != max
)
2286 values
[i
] = color
->f
[i
] != 0.0F
;
2287 if (color
->f
[i
] != 0.0F
&& color
->f
[i
] != 1.0F
)
2291 if (index
== extra_channel
)
2292 extra_value
= values
[i
];
2294 main_value
= values
[i
];
2297 for (int i
= 0; i
< 4; ++i
)
2298 if (values
[i
] != main_value
&&
2299 desc
->swizzle
[i
] - PIPE_SWIZZLE_X
!= extra_channel
&&
2300 desc
->swizzle
[i
] >= PIPE_SWIZZLE_X
&&
2301 desc
->swizzle
[i
] <= PIPE_SWIZZLE_W
)
2304 *clear_words_needed
= false;
2306 *reset_value
|= 0x80808080U
;
2309 *reset_value
|= 0x40404040U
;
2313 void vi_dcc_clear_level(struct r600_common_context
*rctx
,
2314 struct r600_texture
*rtex
,
2315 unsigned level
, unsigned clear_value
)
2317 struct pipe_resource
*dcc_buffer
;
2318 uint64_t dcc_offset
;
2320 assert(rtex
->dcc_offset
&& rtex
->surface
.level
[level
].dcc_enabled
);
2322 if (rtex
->dcc_separate_buffer
) {
2323 dcc_buffer
= &rtex
->dcc_separate_buffer
->b
.b
;
2326 dcc_buffer
= &rtex
->resource
.b
.b
;
2327 dcc_offset
= rtex
->dcc_offset
;
2330 dcc_offset
+= rtex
->surface
.level
[level
].dcc_offset
;
2332 rctx
->clear_buffer(&rctx
->b
, dcc_buffer
, dcc_offset
,
2333 rtex
->surface
.level
[level
].dcc_fast_clear_size
,
2334 clear_value
, R600_COHERENCY_CB_META
);
2337 /* Set the same micro tile mode as the destination of the last MSAA resolve.
2338 * This allows hitting the MSAA resolve fast path, which requires that both
2339 * src and dst micro tile modes match.
2341 static void si_set_optimal_micro_tile_mode(struct r600_common_screen
*rscreen
,
2342 struct r600_texture
*rtex
)
2344 if (rtex
->resource
.is_shared
||
2345 rtex
->resource
.b
.b
.nr_samples
<= 1 ||
2346 rtex
->surface
.micro_tile_mode
== rtex
->last_msaa_resolve_target_micro_mode
)
2349 assert(rtex
->surface
.level
[0].mode
== RADEON_SURF_MODE_2D
);
2350 assert(rtex
->resource
.b
.b
.last_level
== 0);
2352 /* These magic numbers were copied from addrlib. It doesn't use any
2353 * definitions for them either. They are all 2D_TILED_THIN1 modes with
2354 * different bpp and micro tile mode.
2356 if (rscreen
->chip_class
>= CIK
) {
2357 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2358 case 0: /* displayable */
2359 rtex
->surface
.tiling_index
[0] = 10;
2362 rtex
->surface
.tiling_index
[0] = 14;
2364 case 3: /* rotated */
2365 rtex
->surface
.tiling_index
[0] = 28;
2367 default: /* depth, thick */
2368 assert(!"unexpected micro mode");
2372 switch (rtex
->last_msaa_resolve_target_micro_mode
) {
2373 case 0: /* displayable */
2374 switch (rtex
->surface
.bpe
) {
2376 rtex
->surface
.tiling_index
[0] = 10;
2379 rtex
->surface
.tiling_index
[0] = 11;
2382 rtex
->surface
.tiling_index
[0] = 12;
2387 switch (rtex
->surface
.bpe
) {
2389 rtex
->surface
.tiling_index
[0] = 14;
2392 rtex
->surface
.tiling_index
[0] = 15;
2395 rtex
->surface
.tiling_index
[0] = 16;
2397 default: /* 8, 16 */
2398 rtex
->surface
.tiling_index
[0] = 17;
2402 default: /* depth, thick */
2403 assert(!"unexpected micro mode");
2408 rtex
->surface
.micro_tile_mode
= rtex
->last_msaa_resolve_target_micro_mode
;
2410 p_atomic_inc(&rscreen
->dirty_fb_counter
);
2411 p_atomic_inc(&rscreen
->dirty_tex_descriptor_counter
);
2414 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
2415 struct pipe_framebuffer_state
*fb
,
2416 struct r600_atom
*fb_state
,
2417 unsigned *buffers
, unsigned *dirty_cbufs
,
2418 const union pipe_color_union
*color
)
2422 /* This function is broken in BE, so just disable this path for now */
2423 #ifdef PIPE_ARCH_BIG_ENDIAN
2427 if (rctx
->render_cond
)
2430 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
2431 struct r600_texture
*tex
;
2432 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
2437 /* if this colorbuffer is not being cleared */
2438 if (!(*buffers
& clear_bit
))
2441 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
2443 /* the clear is allowed if all layers are bound */
2444 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
2445 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
2449 /* cannot clear mipmapped textures */
2450 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
2454 /* only supported on tiled surfaces */
2455 if (tex
->surface
.level
[0].mode
< RADEON_SURF_MODE_1D
) {
2459 /* shared textures can't use fast clear without an explicit flush,
2460 * because there is no way to communicate the clear color among
2463 if (tex
->resource
.is_shared
&&
2464 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
2467 /* fast color clear with 1D tiling doesn't work on old kernels and CIK */
2468 if (tex
->surface
.level
[0].mode
== RADEON_SURF_MODE_1D
&&
2469 rctx
->chip_class
>= CIK
&&
2470 rctx
->screen
->info
.drm_major
== 2 &&
2471 rctx
->screen
->info
.drm_minor
< 38) {
2475 /* Fast clear is the most appropriate place to enable DCC for
2476 * displayable surfaces.
2478 if (rctx
->chip_class
>= VI
&&
2479 !(rctx
->screen
->debug_flags
& DBG_NO_DCC_FB
)) {
2480 vi_separate_dcc_try_enable(rctx
, tex
);
2482 /* Stoney can't do a CMASK-based clear, so all clears are
2483 * considered to be hypothetically slow clears, which
2484 * is weighed when determining to enable separate DCC.
2486 if (tex
->dcc_gather_statistics
&&
2487 rctx
->family
== CHIP_STONEY
)
2488 tex
->num_slow_clears
++;
2491 /* Try to clear DCC first, otherwise try CMASK. */
2492 if (tex
->dcc_offset
&& tex
->surface
.level
[0].dcc_enabled
) {
2493 uint32_t reset_value
;
2494 bool clear_words_needed
;
2496 if (rctx
->screen
->debug_flags
& DBG_NO_DCC_CLEAR
)
2499 if (!vi_get_fast_clear_parameters(fb
->cbufs
[i
]->format
,
2500 color
, &reset_value
,
2501 &clear_words_needed
))
2504 vi_dcc_clear_level(rctx
, tex
, 0, reset_value
);
2506 if (clear_words_needed
)
2507 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2508 tex
->separate_dcc_dirty
= true;
2510 /* 128-bit formats are unusupported */
2511 if (util_format_get_blocksizebits(fb
->cbufs
[i
]->format
) > 64) {
2515 /* Stoney/RB+ doesn't work with CMASK fast clear. */
2516 if (rctx
->family
== CHIP_STONEY
)
2519 /* ensure CMASK is enabled */
2520 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
2521 if (tex
->cmask
.size
== 0) {
2525 /* Do the fast clear. */
2526 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
2527 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
2528 R600_COHERENCY_CB_META
);
2530 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
2533 /* We can change the micro tile mode before a full clear. */
2534 if (rctx
->screen
->chip_class
>= SI
)
2535 si_set_optimal_micro_tile_mode(rctx
->screen
, tex
);
2537 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
2540 *dirty_cbufs
|= 1 << i
;
2541 rctx
->set_atom_dirty(rctx
, fb_state
, true);
2542 *buffers
&= ~clear_bit
;
2546 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
2548 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
2549 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
2552 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
2554 rctx
->b
.create_surface
= r600_create_surface
;
2555 rctx
->b
.surface_destroy
= r600_surface_destroy
;
2556 rctx
->b
.clear_texture
= r600_clear_texture
;